TEXAS INSTRUMENTS SN54HC164 SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS handbook
Contents
1. 7 recommended operating conditions Voc Supply voltage vec ay V VIL Low level input voltage Input voltage Output voltage Input transition rise and fall time Operating free air temperature T If this device is used in the threshold region from Vj max 0 5 V to Vjymin 1 5 V there is a potential to go into the wrong state from induced grounding causing double clocking Operating with the inputs at tt 1000 ns and Vcc 2 V does not damage the device however functionally the CLK inputs are not ensured while in the shift count or toggle operating modes electrical characteristics over recommended operating free air temperature range unless otherwise noted Ta 25 C SN54HC164 SN74HC164 PARAMETER TEST CONDITIONS Vcc UNIT Icc Vi Vcc or 0 lo 0 PG eto a wj toto ki TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 SN54HC164 SN74HC164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS SCLS115B DECEMBER 1982 REVISED MAY 1997 timing requirements over recommended operating free air temperature range unless otherwise noted Ta 25 C SN54HC164 SN74HC164 Vcc UNIT MIN MAX MIN MAX MIN MAX Pav fo sf 0 a2 03 Setup time before CLKT ns Pav Pav poss Hold time data after CLKT SS E ns switching characteristics over recommended operating free air temperature range C 50 pF unless otherwise noted see Figure 1 P RAMETER FROM TO Ta 25 C SN54HC164 SN74HC164 UN2. IT NUT eC mm maaf m ma gt f operating characteristics T 25 C PARAMETER TEST CONDITIONS UNIT Cpd Power dissipation capacitance 135 eS wy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 o SN54HC164 SN74HC164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS SCLS115B DECEMBER 1982 REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION i CC High Level Pulse 20 30 ov From Output Test Under Test Point le tw aS lt C 50 pF i see Note A Low Level cc Pulse 50 50 oV LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Vcc Input 50 50 ov tPLH tPH gt V Vv Reference 50 cc In Phase de 90 90 R soe OH Input Output D7 o ov 10 f XOA VoL t i E tsu P4 th gt th gt eet lee y tPHL gt tPLH Data Vee OH Input ia 90 307 50 Out of Phase 90 X 50 50 72 90 10 10 OV Output o 2 Voi tf gt et gt lt t VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES NOTES A B moo CL includes probe and test fixture capacitance VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Phase relationships between waveforms were chosen arbitrarily All input pulses are supplied by generators having the following characteristics PRR lt 1 MHz Zo 50 Q tr 6 ns tf 6 ns For clock inputs fm
3. SN54HC164 SN74HC164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS SCLS115B DECEMBER 1982 REVISED MAY 1997 AND Gated Enable Disable Serial Inputs SN54HC164 JOR W PACKAGE Fully Buffered Clock and Serial Inputs B a TATARE Direct Clear Package Options Include Plastic Small Ouitline D and Ceramic Flat W Packages Ceramic Chip Carriers FK and Standard Plastic N and Ceramic J 300 mil DIPs description These 8 bit shift registers feature AND gated serial inputs and an asynchronous clear CLR SN54HC164 FK PACKAGE input The gated serial A and B inputs permit TOP VIEW complete control over incoming data a low at either input inhibits entry of the new data and resets the first flip flop to the low level at the next clock CLK pulse A high level input enables the other input which then determines the state of the first flip flop Data at the serial inputs can be changed while CLK is high or low provided the minimum setup time requirements are met Clocking occurs on the low to high level transition of CLK The SN54HC164 is characterized for operation over the full military temperature range of 55 C to 125 C The SN74HC164 is characterized for eS Ne Sna enaa operation from 40 C to 85 C FUNCTION TABLE OUTPUTS TET A B X X X X H H L X X L Qao QB0 QHo the level of Qa Qp or Qu respectively before the indicated steady state input conditions were establishe
4. TED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
5. ax is measured when the input duty cycle is 50 The outputs are measured one at a time with one input transition per measurement tPLH and tpHL are the same as tpg Figure 1 Load Circuit and Voltage Waveforms k TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRAN
6. aximum ratings over operating free air temperature ranget Supply voltage range VOC cvcsced cee eae ENOR eeu eee ee ee 0 5Vto7V Input clamp current lik Vj lt 0 or Vi gt Vcc see Note 1 eee 20 mA Output clamp current lox Vo lt 0 or Vg gt Vac see Note 1 0 eee eee 20 mA Continuous output current lo Vo O to VOC 2 6 eee 25 mA Continuous current through Vcc or GND 0 eee 50 mA Package thermal impedance j see Note 2 D package 00 eee 127 C W N package fiecc0 ct vid ee eee divas eek ovate 78 C W Storage temperature range Tyg 1 e eee eee eee eee 65 C to 150 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 The input and output voltage ratings may be exceeded if the input and output current ratings are observed 2 The package thermal impedance is calculated in accordance with JESD 51 except for through hole packages which use a trace length of zero vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 SN54HC164 SN74HC164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS SCLS115B DECEMBER 1982 REVISED MAY 199
7. d Qan QGn the level of Qa or QG before the most recent T transition of CLK indicates a 1 bit shift Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 1997 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments l standard warranty Production processing does not necessarily include testing of all parameters EXAS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 SN54HC164 SN74HC164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS SCLS115B DECEMBER 1982 REVISED MAY 1997 logic symbolt 9 CLR 8 CLK 1 A 2 B T This symbol is in accordance with ANSI IEEE Std 91 1984 and IEC Publication 617 12 Pin numbers shown are for the D J N and W packages logic diagram positive logic Qa QB Qc Qp QE QF QG QH Pin numbers shown are for the D J N and W packages ki TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS TEXAS 75265 SN54HC164 SN74HC164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS SCLS115B DECEMBER 1982 REVISED MAY 1997 typical clear shift and clear sequence Serial Inputs Outputs Clear Clear absolute m
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TEXAS INSTRUMENTS SN54HC164 SN74HC164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS handbook