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ANALOG DEVICES AD620 handbook

1. Table 1 AD620A AD620B AD620S Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit GAIN G 1 49 4 kO Ro Gain Range 1 10 000 1 10 000 1 10 000 Gain Error Vour 10 V G 1 0 03 0 10 0 01 0 02 0 03 0 10 G 10 0 15 0 30 0 10 0 15 0 15 0 30 G 100 0 15 0 30 0 10 0 15 0 15 0 30 G 1000 0 40 0 70 0 35 0 50 0 40 0 70 Nonlinearity 10Vto 10 V G 1 1000 10 10 40 10 40 10 40 ppm G 1 100 2 10 95 10 95 10 95 Gain vs Temperature G 1 10 10 10 ppm C Gain 1 50 50 50 ppm C VOLTAGE OFFSET Total RTI Error Vosi Voso G Input Offset Vos Vs 5V 30 125 15 50 30 125 uV to 15V Overtemperature Vs 5V 185 85 225 uV to 15V Average TC Vs 5V 0 3 1 0 0 1 0 6 0 3 1 0 15 Output Offset Voso Vs 15V 000 200 500 1000 uV 5V 500 1500 uV Overte r SEER5V 000 0 2000 uV to T5V Average TC Vs 5V 5 0 15 2 5 7 0 5 0 15 uV C to 15V Offset Referred to the Input vs Supply PSR Vs 2 3 V to 18 V G 1 80 100 80 100 80 100 dB G 10 95 120 100 120 95 120 dB G 100 110 140 120 140 110 140 dB 1000 110 140 120 140 110 140 INPUT CURRENT Input Bias Current 0 5 2 0 0 5 1 0 0 5 2 nA Overtemperature 2 5 15 4 nA Average TC 3 0 3 0 8 0 pA C Input Offset Current 0 3 1 0 03 0 5 0 3 1 0 nA Overtemperature 1 5 0 75 2 0 nA Average TC 1 5 1 5 8 0 pA C INPUT Input Impedance Differential 10 2 10 2 10 2 GO pF Common Mode 10 2 10 2 10 2 GO pF Input Volta
2. FREQUENCY Hz Figure 11 Current Noise Spectral Density vs Frequency RTI NOISE 2 0 VIDIV 00775 0 012 TIME 1 SECIDIV Figure 12 0 1 Hz to 10 Hz RTI Voltage Noise G 1 RTI NOISE 0 1uVIDIV 00775 0 013 TIME 1 SEC DIV Figure 13 0 1 Hz to 10 Hz RTI Voltage Noise G 1000 00775 0 011 100 000 a 10 000 gi i eo 2 FET INPUT o IN AMP 1000 TOTAL DRIF CMR dB Figure 16 Typical CMR vs Frequency RTI Zero to 1 Source Imbalance Rev G Page 8 of 20 00775 0 014 Figure 14 0 1 Hz to 10 Hz Current Noise 5 pA Div AD620A 1k 10k 100k 1M 10M SOURCE RESISTANCE Q Figure 15 Total Drift vs Source Resistance 160 140 0 1 1 10 100 1k 10k 100k 1M FREQUENCY Hz 00775 0 015 00775 0 016 0 1 1 10 100 1k 10k 100k 1M 180 160 FREQUENCY Hz Figure 17 Positive PSR vs Frequency RTI G 1 1000 0 1 100 1k 1000 100 10 GAIN VIV 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 18 Negative PSR vs Frequency RTI G 1 1000 FREQUENCY Hz Figure 19 Gain vs Frequency 00775 0 017 00775 0 018 00775 0 019 35 G 10 10
3. gt 1 27 0 0500 0 50 0 0196 o BSC 1 75 0 0688 0 25 0 0099 45 0 25 0 0098 1 35 0 0532 0 10 0 0040 tj S 0 51 0 0201 118 COPLANARITY 0 31 0 0122 0 25 0 0098 0 1 27 0 0500 0 10 SEATING 2 5771000G7 0 40 0 0157 PLANE 0 17 0 0067 40 0 COMPLIANT TO JEDEC STANDARDS MS 012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 52 8 Lead Standard Small Outline Package SOIC Narrow Body R 8 Dimensions shown in millimeters and inches C cond ADI Rev G Page 19 of 20 AD620 ORDERING GUIDE Model Temperature Range Package Option AD620AN 40 C 85 C N 8 AD620ANZ 40 C to 85 C N 8 AD620BN 40 C 85 C N 8 AD620BNZ 40 C to 85 C N 8 AD620AR 40 C 85 C R 8 AD620ARZ 40 C to 85 C R 8 AD620AR REEL 40 C to 85 C 13 REEL AD620ARZ REEL 40 C to 85 C 13 REEL AD620AR REEL7 40 C to 85 C 7 REEL AD620ARZ REEL7 40 C to 85 C 7 REEL AD620BR 40 C to 85 C R 8 AD620BRZ 40 C to 85 C R 8 AD620BR REEL 40 C to 85 C 13 REEL AD620BRZ RL 40 C to 85 C 13 REEL AD620BR REEL7 40 C to 85 C 7 REEL AD620BRZ R7 40 C to 85 C 7 REEL AD620ACHIPS 40 C to 85 C Die Form AD620SQ 883B 55 C to 125 C Q 8 1 N Plastic DIP Q CERDIP R SO
4. tuentur rate iS 15 Changes to RF Interference section see 15 Edit to Ground Returns for Input Bias Currents section 17 Added AD620CHIPS to Ordering 19 Input Ptotection eene petet ttes onte 16 RE Interference iiio Rhe 16 Common Mode Rejection seen 17 HP 17 Ground Returns for Input Bias 18 Outline Dimensions entente tentent entente 19 Ordering Guide ie e tete tette 20 7 03 Data Sheet changed from REV E to REV Editto EEATURES reget tere tei dette ie else eae egenos 1 Changes to SPECIFICATIONS rrenen 2 Removed AD620CHIPS from ORDERING GUIDE 4 Re Replaced Replaced zi LM eee E Rer ED 6 R placed tees 9 Replaced 31 and 32 teet 10 Replaced Pigtire 4th 10 Changes to Table 11 Changes to Figures 6 and 7 serere 12 Changes to Figure reticere tienes 13 Edited INPUT PROTECTION section 13 Added new ERR eee 13 Changes to RF INTERFACE section ssseeeeen 14 Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS Aei 15 Updated OUTLINE DIMENSIONS see 16 Rev G Page 2 of 20 SPECIFICATIONS Typical 25 C Vs 15 V and 2 unless otherwise noted AD620
5. e TYPICAL STANDARD BIPOLAR INPUT IN AMP 100 100 10 RTI VOLTAGE NOISE 0 1 10Hz uV AD620 SUPERBETA BIPOLAR INPUT IN AMP 1k 10k 100k 1M 10M 100M SOURCE RESISTANCE 00775 0 003 Figure 3 Total Voltage Noise vs Source Resistance One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved and offset drift of ata acquisition AD620 TABLE OF CONTENTS Sp cifications 3 Absolute Maximum Ratings eerte 5 ESD Caution oet ene eR HORRORE e Pe ie 5 Typical Performance Characteristics ee 7 Theory of Operation eerte entente entente 13 Gain Selections ae er Ee eee RD e RR ee 16 Input and Output Offset Voltage sss 16 Reference Terminal eerte 16 REVISION HISTORY 12 04 Rev F to Rev G Replaced Figure 15 oirin seen ietsaan eene nen e eH HP 7 Replaced Figure 33 2 hee 10 Replaced Figure 34 and Figure 35 sss 10 Replaced EFigure 37 15e t RR ete 10 Changes to Table 3 sie iei etta 13 Changes to Figure 41 and Figure 42 sse 14 Changes to Figure 43 ehe de 15 Change to Figure ens 17 Changes to Input Protection section sse 15 Deleted Figure9
6. 0 01 TO 0 1 SETTLING TIME us 00775 0 029 0 5 10 15 20 OUTPUT STEP SIZE V 00775 0 032 Figure 29 Small Signal Pulse Response G 100 2 100 pF Figure 32 Settling Time vs Step Size G 1 1000 100 2 z m E 8 A 8 1 10 100 1000 GAIN 8 Figure 30 Large Signal Response and Settling Time Figure 33 Settling Time to 0 01 vs Gain fora 10 V Step 1000 0 5 mV 0 01 Figure 31 Small Signal Pulse Response G 1000 2 C 100 pF Figure 34 Gain Nonlinearity 1 10 10 uV 1 ppm Rev G Page 11 of 20 10kQ 10T 10kQ 00775 0 035 00775 0 037 ALL RESISTORS 1 TOLERANCE Figure 35 Gain Nonlinearity 100 10 100 uV 10 ppm Figure 37 Settling Time Test Circuit com ADI 00775 0 036 Figure 36 Gain Nonlinearity 1000 10 1 mV 100 ppm Rev G Page 12 of 20 THEORY OF OPERATION 00775 0 038 Figure 38 Simplified Schematic of AD620 The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach Absolute value trimming allows the user to program gain accurately to 0 1596 at G 100 with only one resistor Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components thus ensuring the high level of performance inherent in this circuit www B
7. 0 1000 30 N o a OUTPUT VOLTAGE V p p 2 eo Vg 0 0 TO SUPPLY VOLTAGES f e a INPUT VOLTAGE LIMIT V e a 10k 100k 1M 00775 0 020 FREQUENCY Hz Figure 20 Large Signal Frequency Response 0 5 10 15 20 SUPPLY VOLTAGE Volts Figure 21 Input Voltage Range vs Supply Voltage G 1 Vs 0 0 1 5 1 0 OUTPUT VOLTAGE SWING V REFERRED TO SUPPLY VOLTAGES 0 5 Vs 0 0 0 5 10 15 20 SUPPLY VOLTAGE Volts Figure 22 Output Voltage Swing vs Supply Voltage G 10 Rev G Page 9 of 20 00775 0 021 00775 0 022 OUTPUT VOLTAGE SWING V p p 30 Vg 15V G 10 20 10 0 0 100 1k 10k LOAD RESISTANCE Q Figure 23 Output Voltage Swing vs Load Resistance 00775 0 024 Figure 24 Large Signal Pulse Response and Settling Time G 1 0 5 mV 0 01 00775 0 025 Figure 25 Small Signal Response G 1 2 C 100 pF 00775 0 023 00775 0 026 Figure 26 Large Signal Response and Settling Time G 10 0 5 mV 0 01 00775 0 027 Figure 27 Small Signal Response G 10 2 C 100 pF 00775 0 030 Figure 28 Large Signal Response and Settling Time G 100 0 5 mV 0 01 Rev G Page 10 of 20 AD620 TO
8. 3 9 13 nV VHz Output Voltage Noise eno 72 100 72 100 72 100 nV VHz RTI 0 1 Hz to 10 Hz G 1 3 0 3 0 6 0 3 0 6 0 uV p p G 10 0 55 0 55 0 8 0 55 0 8 uV 100 1000 0 28 028 0 4 0 28 04 uV Current Noise f 1kHz 100 100 100 fA VHz 0 1 Hz to 10 Hz 10 10 10 pA REFERENCE INPUT Rin 20 20 20 lin Vins Veer 50 60 50 60 50 60 pA Voltage Range Vs 1 6 Vs 1 6 Vs 1 6 Vs 1 6 Vs 1 6 Vs 1 6 V Gain to Output 1 0 0001 1 0 0001 1 0 0001 POWER SUPPLY Operating Range 2 3 18 2 3 18 2 3 18 V Quiescent Current Vs 2 3 V 0 9 1 3 0 9 1 3 0 9 1 3 to 18V Overtemperature 1 1 1 6 1 1 1 6 1 1 1 6 mA TEMPERATURE RANGE For Specified Performance 40 to 85 40 to 85 55 to 125 C 1 See Analog Devices military data sheet for 883B tested specifications Does not include effects of external resistor Re 3 One input grounded 1 4 This is defined as the same supply range that is used to specify PSR Rev G Page 4 of 20 ABSOLUTE MAXIMUM RATINGS AD620 Stresses above those listed under Absolute Maximum Ratings Table 2 Parameter Rating Supply Voltage 18V Internal Power Dissipation 650 mW Input Voltage Common Mode Vs Differential Input Voltage 25V Output Short Circuit Duration Indefinite Storage Temperature Range Q 65 C to 150 C Storage Temperature Range N R 65 C to 125 C Operating Temperature Range AD620 A B 40 C
9. 3ppm C TRACKING DISCRETE 1 RESISTOR 100ppm C TRACKING SUPPLY CURRENT 15mA MAX Figure 39 Make vs Buy 00775 0 041 E I imi uit ppm of Full Scale Error Sourc 0 Homebrew ABSOLUTE ACCUR at Ta 25 Input Offset Voltage uV 125 uV 20 mV 150 pV x 2 20 mV 6 250 10 607 Output Offset Voltage uV 1000 uV 100 mV 20 mV 150 uV x 2 100 20 mV 500 150 Input Offset Current nA 2 x350 0 20 mV 6 350 Q 20 mV 18 53 CMR dB 110 dB 3 16 ppm x5 V 20 mV 0 02 Match x 5 V 20 mV 100 791 500 Total Absolute Error 7 559 11 310 DRIFT TO 85 C Gain Drift ppm C 50 ppm 10 ppm x60 C 100 ppm C Track x 60 C 3 600 6 000 Input Offset Voltage Drift uV C 1 uV C x 60 C 20 mV 2 5 x J2 x 60 C 20 mV 3 000 10 607 Output Offset Voltage Drift uV C 15 uV C x 60 100 mV 20 mV 2 5 uV C x 2 x 60 C 100 mV 20 mV 450 150 Total Drift Error 7 050 16 757 RESOLUTION Gain Nonlinearity ppm of Full Scale 40 ppm 40 ppm 40 40 Typ 0 1 Hz to 10 Hz Voltage Noise uV 0 28 uV p p 20 mV 0 38 uV x 2 20 mV 14 27 Total Resolution Error 54 67 Grand Total Error 14 663 28 134 G 100 Vs 15V All errors are min max and referred to input Rev G Page 14 of 20 AD620 DIGITAL DATA OUTPUT Y 0 6mA MAX 00775 0 042 Figure 40 A Pressure Monitor Circuit that Operates on a 5 V Single Supply Pressure Measurement Although useful in many bridge appl
10. 80 7 11 0 250 6 35 0 240 6 10 0 325 8 26 17 74 0 310 7 87 0 100 2 54 9 300 7 62 BSC 0 060 a 4 0 195 4 95 029 0 130 3 30 0 150 3 Es i 0 38 uh Du 0 150 3 81 y 0 38 0 015 0 gl 0 130 3 30 m ae LANE 0 014 0 36 0 115 2 92 SEATING e 0 022 56 Le 0 005 0 13 0 430 10 92 0 018 0 46 0 014 0 36 0 070 1 78 0 060 1 52 0 045 1 14 COMPLIANT TO JEDEC STANDARDS MS 001 BA CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS Figure 50 8 Lead Plastic Dual In Line Package PDIP Narrow Body N 8 Dimensions shown in inches and millimeters 0 100 2 23 BSC 0 405 405 10 29 29 320 8 ar 1 9 960 1 52 90 7 37 0 200 5 08 0 015 0 38 MAX 0 200 5 08 0 150 3 81 0 125 3 18 MIN 0 023 0 58 al ls NIA 0 015 0 38 0 014 0 36 0 x ee 78 PLANE gt 0 008 0 20 0 030 0 76 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 51 8 Lead Ceramic Dual In Line Package CERDIP Q 8 Dimensions shown in inches and millimeters AD620 5 00 0 1968 MS 0 1890 E 4 00 0 1574 3 80 0 1497 a 5 80 0 2284
11. AL PERFORMANCE CHARACTERISTICS 25 C Vs 15 V 2 unless otherwise noted PERCENTAGE OF UNITS PERCENTAGE OF UNITS PERCENTAGE OF UNITS SAMPLE SIZE 360 INPUT OFFSET VOLTAGE uV Figure 5 Typical Distribution of Input Offset Voltage SAMPLE SIZE 850 1200 600 0 600 1200 INPUT BIAS CURRENT pA Figure 6 Typical Distribution of Input Bias Current SAMPLE SIZE 850 INPUT OFFSET CURRENT pA Figure 7 Typical Distribution of Input Offset Current 00775 0 005 00775 0 006 00775 0 007 INPUT BIAS CURRENT nA 75 25 25 75 125 175 TEMPERATURE C 00775 0 008 Figure 8 Input Bias Current vs Temperature 00775 0 009 WARM UP TIME Minutes Figure 9 Change in Input Offset Voltage vs Warm Up Time 1000 GAIN 1 f 100 gt M 10 o o Q 10 amp 9 GAIN 100 1 000 N GAIN 1000 BW LIMIT 1 1 10 100 1k 10k 100k 00775 0 010 FREQUENCY Hz Figure 10 Voltage Noise Spectral Density vs Frequency G 1 1000 Rev G Page 7 of 20
12. ANALOG DEVICES FEATURES Easy to use Gain set with one external resistor Gain range 1 to 10 000 Wide power supply range 2 3 V to 18 V Higher performance than 3 op amp designs Available in 8 lead DIP and SOIC packaging Low power 1 3 mA max supply current Excellent dc performance B grade 50 pV max input offset voltage 0 6 pV C max input offset drift 1 0 nA max input bias current 100 dB min common mode rejection ratio G 10 Low noise 9 nV 4Hz 1 kHz input voltage noise 0 28 V noise 0 1 Hz to 10 Hz Excellent ac specifications 120 kHz bandwidth G 100 15 us settling time to 0 0196 APPLICATI Transducer interface Data acquisition systems Industrial process controls Battery powered and portable equipment 30 000 25 000 20 000 15 000 AD620A L gt gt 10 000 gt 5 000 0 SUPPLY CURRENT mA TOTAL ERROR PPM OF FULL SCALE o m a 00775 0 002 Figure 2 Three Op Amp IA Designs vs AD620 Rev G Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and r
13. C where Cp 210Cc Cp affects the difference signal Cc affects the common mode signal Any mismatch in R x Cc will degrade the AD620 s CMRR To avoid inadvertently reducing CMRR bandwidth performance make sure that Cc is at least one magnitude smaller than C The effect of mismatched Ccs is reduced with a larger Cp Cc ratio Rev G Page 16 of 20 00775 0 045 Figure 43 Circuit to Attenuate RF Interference COMMON MODE REJECTION Instrumentation amplifiers such as the AD620 offer high CMR which is a measure of the change in output voltage when both inputs are changed by equal amounts These specifications are usually given for a full range input voltage change and a specified source imbalance For optimal CMR the reference terminal should be tied to a low impedance point and differences in capacitance and resistance should be kept to a minimum between the two inputs In many applications shielded cables are used to tive de shields thus minimizing the capacitance mismatch between the inputs AD620 00775 0 046 INPUT 00775 0 047 Figure 45 Common Mode Shield Driver GROUNDING Since the A d with respect to the e many pin to the appropriate local ground To isolate low level analog signals from a noisy digital environment many data acquisition components have separate analog and digital ground pins Figure 46 It would be convenient to use a single ground line
14. DTI AD620 The input transistors Q1 and Q2 provide a single differential pair bipolar input for high precision Figure 38 yet offer 10x lower input bias current thanks to Super6eta processing Feedback through the Q1 A1 RI loop and the Q2 A2 R2 loop maintains constant collector current of the input devices Q1 and Q2 thereby impressing the input voltage across the external gain setting resistor Rc This creates a differential gain from the inputs to the A1 A2 outputs given by R2 Rc 1 The unity gain subtractor A3 removes any common mode signal yielding a single ended output referred to the REF pin potential The value of Rc also determines the transconductance of the preamp stage As Rc is reduced for larger gains the transconductance increases asymptotically to that of the input transistors This has three important advantages a Open loop gain is boosted for increasing programmed gain thus reducing gain related errors b The gain bandwidth product determined by C1 and C2 and the preamp transconductance increases with programmed gain thus optimizing frequency response c The input voltage noise is reduced to a value of 9 nV VHz determined mainly by the collector current and base resistance of the input devices fimmed to an o be programmed The internal gain resistor abs 3 accuratel m i The gain equation is then 49 4kC G 1 49 4 Make vs Buy a Typic
15. IC n WA C O 2004 Analog Devices Inc All rights reserved Trademarks ANALOG and registered trademarks are the property of their respective owners www ana 0 0 com cansa DEVICES Rev G Page 20 of 20
16. al Bridge Application Error Budget The AD620 offers improved performance over homebrew three op amp IA designs along with smaller size fewer components and 10x lower supply current In the typical application shown in Figure 39 a gain of 100 is required to amplify a bridge output of 20 mV full scale over the industrial temperature range of 40 C to 85 C Table 3 shows how to calculate the effect various error sources have on circuit accuracy Rev G Page 13 of 20 AD620 Regardless of the system in which it is being used the AD620 provides greater accuracy at low power and price In simple systems absolute accuracy and drift errors are by far the most significant contributors to error In more complex systems with an intelligent processor an autogain autozero cycle will remove all absolute accuracy and drift errors leaving only the resolution errors of gain nonlinearity and noise thus allowing full 14 bit accuracy 10V 00775 0 039 PRECISION BRIDGE TRANSDUCER Table 3 Make vs Buy Error Budget AD620A MONOLITHIC INSTRUMENTATION AMPLIFIER G 100 SUPPLY CURRENT 1 3mA MAX 00775 0 040 Note that for the homebrew circuit the OP07 specifications for input voltage offset and noise have been multiplied by V2 This is because a three op amp type in amp has two op amps at its inputs both contributing to the overall input error HOMEBREW IN AMP G 100 0 02 RESISTOR MATCH
17. egistered trademarks are the property of their respective owners Low Cost Low Power Instrumentation Amplifier AD620 CONNECTION DIAGRAM 00775 0 001 TOP VIEW Figure 1 8 Lead PDIP N CERDIP Q and SOIC R Packages PRODUCT DESCRIPTION The AD620 is a low cost high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to 10 000 Furthermore the AD620 features 8 lead SOIC and DIP packaging that is smaller than discrete designs and offers lower power only 1 3 mA max supply current making it a good fit for battery powered portable or remote applications The AD620 with its high accuracy of 40 ppm maximum nonlinearity low offset voltage amp 50 0 6 ai side use i a isiti systems s weigh sales aig i Fur 0 olse input ent and low power interfaces of the AD620 make it well suited for medical applications such as ECG and noninvasive blood pressure monitors The low input bias current of 1 0 nA max is made possible with the use of Super6eta processing in the input stage The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV AHz at 1 kHz 0 28 uV in the 0 1 Hz to 10 Hz band and 0 1 pA VHz input current noise Also the AD620 is well suited for multiplexed applications with its settling time of 15 us to 0 0196 and its cost is low enough to enable designs with one in amp per channel 10 000 p e
18. ge Range Vs 2 3V Vs4 1 9 5 1 2 Vs 1 9 Vs 1 2 Vs 1 9 4Vs 1 2 V to 5 V Overtemperature Vs 2 1 TVs 1 3 Vs 2 1 TVs 1 3 Vs 2 1 Vs 1 3 V Vs 5V Vs 1 9 Vs 1 4 1 9 Vs 1 4 Vs 1 9 Vs 1 4 V to 18 V Overtemperature V 2 1 Vs 1 4 Vs 2 1 TVs 2 1 Vs 2 3 V 14 V Rev G Page 3 of 20 AD620 AD620A AD620B AD620S Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit Common Mode Rejection Ratio DC to 60 Hz with 1 Source Imbalance Vu O0Vto 10V G 1 73 90 80 90 73 90 dB G 10 93 110 100 110 93 110 dB G 100 110 130 120 130 110 130 dB G 1000 110 130 120 130 110 130 dB OUTPUT Output Swing 10 Vs 2 3V Vs 1 2 Vs 1 1 Vs 1 2 1 1 1V 1 2 V to 5V 1 1 Overtemperature Vs 1 4 TVs 1 3 Vs 1 4 Vs 1 3 Vs 1 6 Vs 1 3 V Vs 5V Vs 1 2 lt 1 4 Vs 1 2 5 1 4 1 2 Vs 1 4 V 18V Overtemperature Vs 1 6 TVs 1 5 Vs 1 6 4 Vs 1 5 Vs 2 3 Vs 1 5 V Short Circuit Current 18 18 18 mA DYNAMIC RESPONSE Small Signal 3 dB Bandwidth G 1 1000 1000 1000 kHz G 10 800 800 800 kHz G 100 120 120 120 kHz 1000 12 12 12 kHz Slew Rate 0 75 1 2 0 75 1 2 0 75 1 2 V us Settling Time to 0 0196 10 V Step G 1 100 15 5 us G 10 5 1 us NOISE Voltage Noise 1 kHz Total RTI Noise Vern e G Input Voltage Noise eni 9 13 9 1
19. however current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error Therefore separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground These ground returns must be tied together at some point usually best at the ADC package shown in Figure 46 ANALOG P S 15V C 15V DIGITAL DATA OUTPUT 00775 0 048 Figure 46 Basic Grounding Practice Rev G Page 17 of 20 AD620 GROUND RETURNS FOR INPUT BIAS CURRENTS Input bias currents are those currents necessary to bias the input transistors of an amplifier There must be a direct return path for these currents Therefore when amplifying floating input sources such as transformers or ac coupled sources there must be a dc path from each input to ground as shown in Figure 47 Figure 48 and Figure 49 Refer to A Designers Guide to Instrumentation Amplifiers free from Analog Devices for more information regarding in amp applications INPUT REFERENCE TO POWER SUPPLY GROUND 00775 0 050 Figure 48 Ground Returns for Bias Currents with Thermocouple Inputs INPUT REFERENCE O Vour TO POWER SUPPLY GROUND 00775 0 049 TO POWER SUPPLY GROUND 8 Figure 49 Ground Returns for Bias Currents with AC Coupled Inputs Rev G Page 18 of 20 OUTLINE DIMENSIONS 0 400 10 16 0 365 9 27 0 355 9 02 0 2
20. ications such as weigh scales the AD620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant Figure 40 shows a 3 pressure transducer bridge powered from 5 V In such a circuit the bridge consumes only 1 7 mA Adding the AD620 and a buffered voltage divider allows the signal to be conditioned for only 3 8 my voltage p re transduffers Site and drift it will also serve applications such as diagnostic noninvasive blood pressure measurement PATIENT CIRCUIT PROTECTION ISOLATION AD620A Medical ECG The low current noise of the AD620 allows its use in ECG monitors Figure 41 where high source resistances of 1 or higher are not uncommon The AD6205 low power low supply voltage requirements and space saving 8 lead mini DIP and SOIC package offerings make it an excellent choice for battery powered data recorders Furthermore the low bias currents and low current noise coupled with the low voltage noise of 20 improve the C rfo The ito osen in stability of the right leg drive loop Proper safeguards such as isolation must be added to this circuit to protect the patient from possible harm 3V OUTPUT 1VimV G 7 FILTER OUTPUT AMPLIFIER 00775 0 043 Figure 41 A Medical ECG Monitor Circuit Rev G Page 15 of 20 AD620 Precision V I Converter The AD620 along with another op amp and tw
21. inate at low gains The total Vos for a given gain is calculated as Total Error RTI input error output error G Total Error RTO input error x G output error REFERENCE TERMINAL The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system It provides a direct means of injecting a precise offset to the output with an allowable range of 2 V within the supply voltages Parasitic resistance should be kept to a minimum for optimum CMR INPUT PROTECTION The AD620 features 400 Q of series thin film resistance at its inputs and will safely withstand input overloads of up to 15 V or 60 mA for several hours This is true for all gains and power on and off which is particularly important since the signal source and jon may be powered separately For longer time n gb the supplies low leakage diode m vay ae as an bi will reduce the required resistance yielding lower noise RF INTERFERENCE All instrumentation amplifiers rectify small out of band signals The disturbance may appear as a small dc voltage offset High frequency signals can be filtered with a low pass R C network placed at the input of the instrumentation amplifier Figure 43 demonstrates such a configuration The filter limits the input signal according to the following relationship 1 FilterFre Ee TUE 2nR 2C 4C FilterFre Ed fen 2nR
22. o resistors makes a precision current source Figure 42 The op amp buffers the reference terminal to maintain good CMR The output voltage Vx of the AD620 appears across R1 which converts it to a current This current less only the input bias current of the op amp then flows out to the load Vine Vin Vx _ Vin Vin G h m m LOAD Figure 42 Precision Voltage to Current Converter Operates on 1 8 mA 3 V GAIN SELECTION precisely The AD62 resistors Ta Note that for G 1 the Rc pins are unconnected Re oo For any arbitrary gain Rc can be calculated by using the formula 49 4 kO G 1 n To minimize gain error avoid high parasitic resistance in series with Rc to minimize gain drift Rc should have a low TC less than 10 ppm C for the best performance Table 4 Required Values of Gain Resistors 1 Std Table Calculated 0 1 Std Table Calculated Value of R Q Gain Value of R Q Gain 49 9 k 1 990 49 3 k 2 002 12 4k 4 984 12 4k 4 984 5 49 k 9 998 5 49 k 9 998 2 61 k 19 93 2 61 k 19 93 1 00 k 50 40 1 01 k 49 91 499 100 0 499 100 0 249 199 4 249 199 4 100 495 0 98 8 501 0 49 9 991 0 49 3 1 003 0 INPUT AND OUTPUT OFFSET VOLTAGE The low errors of the AD620 are attributed to two sources input and output errors The output error is divided by G when referred to the input In practice the input errors dominate at high gains and the output errors dom
23. to 85 C AD620 S 55 C to 125 C Lead Temperature Range Soldering 10 seconds 300 C may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device in free air 8 Lead Plastic Package 95 C 8 Lead CERDIP Package 110 C 8 Lead SOIC Package 155 C 2NA BDOTLC cont A ESD electrostati h selisitive ost tic Charge as 4 n cum l te On the ct features human body and test equipment and can discharge without detection Although this produ proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING ST aa ESD SENSITIVE DEVICE Rev G Page 5 of 20 AD620 REFERENCE 0 0708 1 799 FOR CHIP APPLICATIONS THE PADS 1R AND 8Rg MUST BE CONNECTED IN PARALLEL TO THE EXTERNAL GAIN REGISTER Rg DO NOT CONNECT THEM IN SERIES TO Rg FOR UNITY GAIN APPLICATIONS WHERE Rg IS NOT REQUIRED THE PADS 1Rg MAY SIMPLY BE BONDED TOGETHER AS WELL AS THE PADS 8Rg Rev G Page 6 of 20 00775 0 004 AD620 TYPIC

ANALOG DEVICES AD620 handbook

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