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ANALOG DEVICES AD607 handbook

1. 40 35 30 25 8 20 3 QUADRATIC FIT OF I GAIN CORR IFF 15 10 5 0 17 17 2 17 4 17 6 17 8 18 18 2 18 4 18 6 18 8 0 0 2 04 06 08 10 12 14 16 18 20 DEMODULATOR GAIN dB BASEBAND FREQUENCY MHz Figure 29 Demodulator Gain Histogram Figure 26 Demodulator Gain vs Frequency T 25 C VPOS 3 V IF 10 7 MHz 20 14 9 I CORR i 18 T 17 10 CUBIC FIT OF I GAIN TEMP m 16 8 2 15 5 14 13 4 12 2 11 10 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100110 120 130 0 1 0 08 0 06 0 04 0 02 0 0 02 0 04 0 06 0 08 0 1 TEMPERATURE OUTPUT OFFSET Volts Figure 27 Demodulator Gain vs Temperature Figure 30 Demodulator Output Offset Voltage Histogram T 25 C VPOS 3 V IF 10 7 MHz 12 REV 0 AD607 40 2127 ms Timebase 5 00 us div 40 2377 ms 40 2627 ms Delay 40 2377 ms Memory 1 100 0 mVolts div Offset 154 0 mVolts Timebase 5 00 us div Delay 40 2377 ms Memory 2 60 00 mVolts div Offset 209 0 mVolts Timebase 5 00 us div Delay 40 2377 ms Delta T 15 7990 us Start 40 2327 ms Stop 40 2485 ms Trigger on External at Pos Edge at 40 0 mVolts Figure 31 Power Up Response Time to PLL Stable 15 10 SUPPLY CURRENT mA 0 0 5 1 15
2. D 607 H ANALOG DEVICES Low Power Mixer AGC RSSI 3 V Receiver IF Subsystem AD607 FEATURES Complete Receiver on a Chip Monoceiver Mixer 15 dBm 1 dB Compression Point 8 dBm Input Third Order Intercept 500 MHz RF and LO Bandwidths Linear IF Amplifier Linear in dB Gain Control MGC or AGC with RSSI Output Quadrature Demodulator On Board Phase Locked Quadrature Oscillator Demodulates IFs from 400 kHz to 12 MHz Can Also Demodulate AM CW SSB Low Power 25 mW at 3 CMOS Compatible Power Down Interfaces to AD7013 and AD7015 Baseband Converters APPLICATIONS GSM CDMA TDMA and TETRA Receivers Satellite Terminals Battery Powered Communications Receivers GENERAL DESCRIPTION The AD607 is 3 V low power receiver IF subsystem for opera tion at input frequencies as high as 500 MHz and IFs from 400 kHz to 12 MHz It consists of mixer IF amplifiers I and demodulators a phase locked quadrature oscillator AGC detector and a biasing system with external power down The AD607 s low noise high intercept mixer is a doubly balanced Gilbert cell type It has a nominal 15 dBm input referred 1 dB compression point and a 8 dBm input referred third order intercept The mixer section of the AD607 also includes a local oscillator LO preamplifier which lowers the required LO drive to 16 dBm The gain control input can serve as either a manual gain control MGC input or an automatic gain control AGC
3. 54mV MAX INPUT LOIP CONSTANT 16dBm 50mV TYPICAL IMPEDANCE MAX OUTPUT MAX INPUT E USING THE AD607 In this section we will focus on a few areas of special impor tance and include a few general application tips As is true of any wideband high gain component great care is needed in PC board layout The location of the particular grounding points must be considered with due regard to possibility of unwanted signal coupling particularly from IFOP to RFHI or IFHI or both The high sensitivity of the AD607 leads to the possibility that unwanted local EM signals may have an effect on the perfor mance During system development carefully shielded test as semblies should be used The best solution is to use a fully enclosed box enclosing all components with the minimum number of needed signal connectors RF LO I and Q outputs in miniature coax form The I and output leads can include small series resistors about 100 Q inside the shielded box without significant loss of performance provided the external loading during testing is light that is a resistive load of more than 20 kO and capaci tances of a few picofarads These help to keep unwanted RF emanations out of the interior The power supply should be connected via a through hole ca pacitor with a ferrite bead on both inside and outside leads Close to the IC pins two capacitors of different value should be used to decouple the main supply Vp a
4. 23 V the scale factor is 16 4 mV dB 80 dB corresponds to 1 312 change and the discharge time decreases to 290 us could also be expressed in dB with a scaling of 20 mV dB it works out to T C x P x 44 000 where P is the change in input power expressed in dB Thus using C 1 nF checking the time needed for 80 dB we get T 355 us For the case where the scaling is 16 4 mV dB T C x P x 36 000 The AD607 s AGC detector delivers only one brief charging pulse per cycle of the IF At a 10 7 MHz IF for example this is every 93 ns When the AGC system is in equilibrium this pulse REV 0 AD607 of current exactly balances the 4 5 uA discharge current It makes no difference what the actual value of Vg is at that point since the filter is an integrator Thus at 20 mV dB IT 5 E 5uAx 93 0 42 mV C 1nF Vrrppre This corresponds to 0 021 dB the ripple will modulate the gain by that amount over each cycle The effect of such modula tion on the signal is hard to quantify but it roughly translates to a 2 amplitude modulation Also the gain ripple depends on the scale factor For this example at GREF 1 23 and a 16 4 mV dB scale factor the gain ripple increases to 0 025 dB AGC Charge Time When the gain is too high the IF amplifier will be overdriven to produce a square wave output roughly of 560 mV If per fectly square and time and amplitude symmetric this would be s
5. BUS Figure 48 Evaluation Board Test Setup 22 REV 0 0 OUTLINE DIMENSIONS Dimensions shown in inches and mm 20 Pin Plastic SSOP RS 20 Y 20 11 0 212 5 38 0 205 5 207 0 311 7 9 PIN 1 0 301 7 64 1 O 10 0090 0 0 0 295 7 50 0 07 1 78 0 271 6 90 0 066 1 67 yh gt le e 007 094 0 008 0 203 0 0256 0 65 zl 0 022 0 559 0 002 0 050 BSC 6 005 0 127 1 LEAD NO 1 IDENTIFIED BY A DOT 2 LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL M 38510 REQUIREMENTS 23 AD607 96 1 01 1 0 2 5 NI GALNIYd 24
6. CMOS compatible power down completes the AD607 Mixer The mixer is an improved Gilbert cell design and can operate from low frequencies it is internally dc coupled up to an RF input of 500 MHz The dynamic range at the input of the mixer is determined at the upper end by the maximum input signal level of 56 mV between and up to which the mixer remains linear and at the lower end by the noise level It is customary to define the linearity of a mixer in terms of the 1 dB gain compression point and third order intercept which for the AD607 are 15 dBm and 8 dBm respectively in a 50 Q system O GAIN RSSI C GREF Figure 33 Functional Block Diagram REV 0 13 AD607 The mixer s input port is differential that is pin RELO is functionally identical to RFHI and these nodes are internally biased we will generally assume that is decoupled to ac ground The RF port can be modeled as a parallel RC circuit as shown in Figure 34 C1 2 7 L1 C1 C2 11 OPTIONAL MATCHING CIRCUIT 3 COUPLES RFLO AC GROUND Figure 34 Mixer Port Modeled as a Parallel RC Network an Optional Matching Network Is also Shown The local oscillator LO input is internally biased at Vp 2 via a nominal 1000 resistor internally connected from pin LOIP to VMID The LO interface includes a preamplifier which mini mizes the drive requirements thus simplifying the oscillator de si
7. Figure Max f 10 7 MHz 17 dB Input 1 dB Compression Point IF 10 7 MHz 15 dBm Output Third Order Intercept IF 10 7 MHz 18 dBm Maximum IF Output Voltage at IFOP Zr 6000 560 mV Output Resistance at IFOP From IFOP to VMID 15 Q Bandwidth 3 dB at IFOP Max Gain 45 MHz GAIN CONTROL See Figures 43 and 44 Gain Control Range Mixer IF Section GREF to 1 5 V 90 dB Gain Scaling GREF to 1 5 V 20 mV dB GREF to General Reference Voltage 75 dB V Gain Scaling Accuracy to 1 5 80 dB Span 1 Bias Current at GAIN RSSI 5 Bias Current GREF 1 Input Resistance at GAIN GREF 1 DEMODULATORS Required DC Bias at DMIP VPOS 2 V de Input Resistance at DMIP From DMIP to VMID 50 kQ Input Bias Current at DMIP 2 uA Maximum Input Voltage IF gt 3 MHz 2150 mV IF gt 3 MHz 75 mV Amplitude Balance 10 7 MHz Outputs at 600 mV 100 kHz 20 2 dB Quadrature Error 10 7 MHz Outputs at 600 mV 100 kHz 1 2 Degrees Phase Noise in Degrees 10 7 MHz 10 kHz 100 dBc Hz Demodulation Gain Sine Wave Input Baseband Output 18 dB Maximum Output Voltage 2 20 kQ 21 23 V Output Offset Voltage Measured from Qour to VMID 10 mV Output Bandwidth Sine Wave Input Baseband Output 1 5 MHz PLL Required DC Bias at FDIN VPOS 2 V dc Input Resistance at FDIN From FDIN to VMID 50 kQ Input Bias Current at FDIN 200 nA Frequency Range 0 4 to 12 MHz Required Input Drive
8. voltage based RSSI output In MGC operation the AD607 accepts an external gain control voltage input from an external AGC detec tor or a DAC In AGC operation an onboard detector and an external averaging capacitor form an AGC loop that holds the IF output level at 300 mV The voltage across this capacitor then provides an RSSI output REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices PIN CONFIGURATION 20 Lead SSOP RS Suffix FDIN 1 20 VPS1 comi 2 FLTR PRUP 3 IOUT LOIP 4 QOUT RFLO 5 607 VPS2 E s oue GREF IFOP MXOP 8 COM2 VMID 9 GAIN RS 10 IFLO The I and Q demodulators provide inphase and quadrature baseband outputs to interface with Analog Devices AD7013 1554 TETRA MSAT and AD7015 GSM baseband con verters quadrature phase locked to the IF drives the I and Q demodulators The I and Q demodulators can also de modulate AM when the AD607 s quadrature is phase locked to the received signal the in phase demodulator becomes a synchronous product detector for AM The VCO can also be phase locked to an external beat frequency oscill
9. vs Temperature VPOS 3 VGAIN 0 3 VREF 1 5 IF 10 7 MHz RF 250 MHz a lt 3 a o ui z 2 5 0 O 50 100 150 200 250 300 350 400 450 500 550 600 0 RADIO FREQUENCY MHz 2 4 2 6 28 3 3 2 3 4 3 6 38 4 4 2 4 4 4 6 4 8 5 5 2 5 4 5 6 5 8 6 SUPPLY Volts Figure 15 Mixer Conversion Gain vs Frequency Figure 18 Mixer Conversion Gain and IF Amplifier Gain T 25 VPOS 2 7 VREF 1 35 V IF 10 7 MHz vs Supply Voltage 25 C VGAIN 0 3 VREF 1 5 IF 10 7 MHz RF 250 MHz 10 0 0607 90 00 100 00 m 1 9 110 00 z m 5 7 2120 00 2 7 130 00 140 00 150 00 0 1 1 10 100 1 00 02 1 00 03 1 00 04 1 00 05 1 00 06 1 00 07 INTERMEDIATE FREQUENCY MHz CARRIER FREQUENCY OFFSET f fm Hz Figure 19 IF Amplifier Gain vs Frequency Figure 22 PLL Phase Noise L F vs Frequency T 25 C VPOS VREF 1 5 VPOS 0 1 uF IF 10
10. 00 5 0 2 5 30 00 33 33 0 667 3 333 5 5 2 75 27 27 36 67 0 733 3 667 NOTE Maximum gain occurs for gain control voltage 0 V 16 0 AD607 Bias System The AD607 operates from a single supply Vp usually of 3 V at a typical supply current of 8 5 mA at midgain and T 27 C corresponding to a power consumption of 25 mW Any voltage from 2 7 V to 5 5 V may be used The bias system includes a fast acting active high CMOS compatible power up switch allowing the part to idle at 550 JA when disabled Biasing is proportional to absolute temperature PTAT to ensure stable gain with temperature An independent regulator generates a voltage at the midpoint of the supply Vp 2 which appears at the VMID pin at a low im pedance This voltage does not shut down ensuring that the major signal interfaces e g mixer to IF and IF to demodula tors remain biased at all times thus minimizing transient dis turbances at power up and allowing the use of substantial decoupling capacitors on this node The quiescent consumption of this regulator is included in the idling current EXTERNAL FREQUENCY REFERENCE a Biasing FDIN from Supply when Using External Frequency Reference EXTERNAL FREQUENCY REFERENCE E 85 b Biasing FDIN from VMID when Using External Frequency Reference Figure 41 Suggested Methods for Biasing Pin FDIN at 2 1 3V 54mV MAX OUTPUT MAX MXOP IFHI
11. 2 2 5 GAIN VOLTAGE Volts Figure 32 Power Supply Current vs Gain Control Voltage GREF 1 5 MID POINT GENERATOR COM1 COM2 AGC BIAS GENERATOR BIAS a PRODUCT OVERVIEW The AD607 provides most of the active circuitry required to realize a complete low power single conversion superhetero dyne receiver or most of a double conversion receiver at input frequencies up to 500 MHz and with an IF of from 400 kHz to 12 MHz The internal I Q demodulators and their associated phase locked loop which can provide carrier recovery from the TF support a wide variety of modulation modes including n PSK n QAM and AM A single positive supply voltage of 3 V required 2 7 minimum 5 5 maximum at a typical sup ply current of 8 5 mA at midgain In the following discussion will be used to denote the power supply voltage which will be assumed to be 3 V Figure 33 shows the main sections of the AD607 It consists of a variable gain mixer and linear four stage IF strip which together provide a voltage controlled gain range of more than 90 dB followed by dual demodulators each comprising a multi plier followed by a 2 pole 2 MHz low pass filter and driven by a phase locked loop providing the inphase and quadrature clocks An internal AGC detector is included and the tempera ture stable gain control system provides an accurate RSSI capa bility A biasing system with
12. 21 AD607 In operation Figure 48 the AD607 evaluation board draws about 8 5 mA at midgain 59 dB Use high impedance probes to monitor signals from the demodulated and Q outputs and the IF output The MGC voltage should be set such that the signal level at DMIP does not exceed 150 signal levels above this will overload the and Q demodulators The inser tion loss between IFOP and DMIP typically 3 dB if a simple low pass filter R8 and C2 is used and higher if a reverse terminated bandpass filter is used HP 6632A If the AD607 s internal AGC detector is used then the GAIN RSSI Pin 12 becomes an output and the RSSI voltage appears across C12 which serves as an integrating capacitor This volt age must be monitored by a high impedance 100 minimum probe The internal AGC loop holds the IF voltage at IFOP Pin 14 at 300 mV in this application about 6 dB of attenua tion is needed between pins IFOP and DMIP to avoid overload ing the I and demodulators HP 3326 PROGRAMMABLE SYNTHESIZED POWER SUPPLY SIGNAL GENERATOR 2 7V 6V FLUKE 6082A SYNTHESIZED SIGNAL GENERATOR 240 MHz ZFSC 2 1 COMBINER HP 8656A SYNTHESIZED SIGNAL GENERATOR 240 02 MHz HP 9920 IEEE CONTROLLER 10 710 MHz TEKTRONIX 11402A OSCILLOSCOPE WITH 11A32 PLUGIN HP 8656A DATA PRECISION SYNTHESIZED DVC8200 HP9121 SIGNAL GENERATOR PROGRAMMABLE DISK DRIVE 229 3 MHz VOLTAGE SOURCE IEEE 488
13. 7 MHz 10 2 5 8 6 2 a 2 gos E 0 5 gt B gt E 4 6 8 10 1 5 0 02040608 1 12 1 4 1 6 18 2 22 24 26 28 3 0 1 1 10 100 GAIN VOLTAGE Volts PLL FREQUENCY MHz Figure 20 AD607 Gain Error vs Gain Control Voltage Figure 23 PLL Loop Voltage at FLTR Kyco vs Frequency Representative Part 8 7 6 5 54 3 996 200 us 1 00870 ms 1 02120 ms 2 Timebase 2 5 Delay 1 00870 ms Memory 1 100 0 mVolts div Offset 127 3 mVolts Timebase 2 50 us div Delay 1 00870 ms Memory 2 20 00 mVolts div Offset 155 2 mVolts 1 2 Timebase 2 50 Delay 1 00870 ms s 80 287 88 89 19009 9 22727794 22 Delta 16 5199 us QUADRATURE ANGLE Degrees Start 1 00048 ms Stop 1 01700 ms Trigger on External at Pos Edge at 134 0 mVolts Figure 24 Demodulator Quadrature Angle Histogram Figure 21 PLL Acquisition Time T 25 C VPOS IF 10 7 MHz REV 0 11 AD607 30 25 20 CUBIC FIT OF I GAIN CORR E 215 z 7 5 5 10 5 0 2 1 0 1 2 2 5 3 3 5 4 4 5 5 5 5 6 IQ GAIN BALANCE dB SUPPLY Volts Figure 25 Demodulator Gain Balance Histogram Figure 28 Demodulator Gain vs Supply Voltage 25 VPOS 3 IF 10 7 MHz
14. ECTION 20 Pin SSOP RS 20 FDIN 1 e 20 vPS1 com 2 19 FLTR PRUP 3 18 IOUT LOIP 4 QOUT RFLO 5 AD607 16 vps2 TOP VIEW RFHI 6 Not to Scale 15 DMIP GREF 14 IFOP MXOP 8 13 2 9 12 GAIN RS 10 IFLO REV 0 Typical Performance Characteristics AD607 HP8656B IEEE RF OUT SYNTHESIZER HP8656B IEEE RF OUT SYNTHESIZER HP8656B IEEE RF OUT SYNTHESIZER HP6633A P6205 TEK1105 X10 OUT IN1 OUT1 FET PROBE HP8594E IN2 OUT2 RF IN IEEE PROBE SUPPLY SPEC AN DP8200 Figure 1 Mixer Amplifier Test Set HP8720C PORT_1 IEEE 488 PORT 2 NETWORK AN CHARACTERIZATION BOARD HP87658 HP8765B HP346B HP8970A 28V NOISE IN 28V OUT NOISE SOURCE NOISE FIGURE METER HP8656B IEEE OUT SYNTHESIZER HP6633A DP8200 Figure 2 Mixer Noise Figure Test Set REV 0 5 AD607 CHARACTERIZATION BOARD HP346B P6205 TEK1103 HP8970A x10 OUT IN1 OUT RF IN 28V NOISE 28V OUT NOISE SOURCE NOISE FIGURE METER IN2 OUT2 PROBE SUPPLY HP6633A DP8200 Figure 3 IF Amp Noise Figure Test Set CHARACTERIZATION BOARD HP8656B IEEE RF OUT SYNTHESIZER HP3326A OUTPUT 1 P6205 1103 IEEE OUTPUT 2 A x10 OUT DUAL SYNTHESIZER O FET PROBE HP87658 87658 HP8694E P6205 RF IN IEEE SPEC AN HP6633A X10 OUT2 FET PROBE PROBE SUPPLY HP54120 CH1 CH2 CH3 DP8200 TRIG
15. High impedance input typically 1 5 V sets gain scaling 8 MXOP Mixer Output High impedance single sided current output 1 3 V max voltage output 6 mA max current output 9 VMID Midsupply Bias Voltage Output of the midsupply bias generator VMID VPOS 2 10 IF High Input AC coupled IF input 56 mV max input for linear operation 11 IFLO IF Low Voltage Reference node for IF input auto offset null 12 GAIN RSSI Gain Control Input RSSI Output High impedance input 0 V 2 V using 3 V supply max gain at 0 RSSI Output when using Internal Detector RSSI voltage is across AGC Capacitor connected to this pin 13 COM2 Common 2 Supply common for IF stages and demodulator 14 IFOP IF Output Low impedance single sided voltage output 5 dBm 560 mV max 15 DMIP Demodulator Input Signal input to I and demodulators 150 mV max input at IF gt 3 MHz for linear operation 75 mV max input at IF lt 3 MHz for linear operation Must be biased at Vp 2 16 VPS2 VPOS Supply 2 Supply to high level IF PLL and demodulators 17 QOUT Quadrature Output Low impedance baseband output 1 23 V full scale in 20 min load ac coupled 18 IOUT In Phase Output Low impedance I baseband output 1 23 V full scale in 20 min load ac coupled 19 FLTR PLL Loop Filter Series RC PLL Loop filter connected to ground 20 VPS1 VPOS Supply 1 Supply to mixer low level IF PLL and gain control PIN CONN
16. IEEE 488 DIGITAL OSCILLOSCOPE Figure 4 PLL Demodulator Test Set 0 CHARACTERIZATION BOARD HP6633A DP8200 Figure 5 GAIN Pin Bias Test Set CHARACTERIZATION BOARD HP6633A 8200 Figure 6 Demodulator Bias Test Set CHARACTERIZATION BOARD HP3325B IEEE RF OUT SYNTHESIZER HP6633A VPOS VNEG SPOS SNEG DCPS HP8594E RF IN IEEE SPEC AN HP6633A Figure 7 Power Up Threshold Test Set REV ES AD607 AD607 CHARACTERIZATION BOARD P6205 1103 HP54120 x10 OUT IN1 OUT1 CH1 FET PROBE CH2 P6205 CH3 x10 OUT IN2 OUT2 FLG082A FET PROBE PROBE SUPPLY TRIG IEEE 488 DIGITAL OSCILLOSCOPE HP6633A VPOS VNEG SPOS SNEG NOTE MUST BE 3 RESISTOR POWER DIVIDER DP8200 HP8112 IEEE PULSE OUT PULSE GENERATOR Figure 8 Power Up Test Set CHARACTERIZATION BOARD HP8656B P6205 1103 HP8594E IEEE RF OUT X10 ouT IN1 OUT IN IEEE SYNTHESIZER FET PROBE SPEC AN IN2 OUT2 PROBE SUPPLY HP6633A Figure 9 IF Output Impedance Test Set CHARACTERIZATION BOARD HP54120 P6205 1103 X10 OUT1 CH1 FET PROBE CH2 P6205 CH3 x10 OUT2 CH4 FET PROBE PROBE SUPPLY TRIG IEEE_488 DIGITAL OSCILLOSCOPE FL6082A RF OUT OUT HP6633A DP8200 Figure 10 PLL Settling Time Test Set 8 0 0607 CHARACTERIZATION BOARD HP3325B IEEE RF OUT SYNTHESIZER HP3326 DCFM OUTPUT 1 P6205 1103 IEEE OU
17. Level Sine Wave Input at Pin 1 400 mV Acquisition Time to 3 IF 10 7 MHz 16 5 us POWER DOWN INTERFACE Logical Threshold For Power Up on Logical High 2 V dc Input Current for Logical High 75 uA Turn On Response Time To PLL Locked 16 5 us Standby Current 550 uA POWER SUPPLY Supply Range 2 7 5 5 Supply Current Midgain IF 10 7 MHz 8 5 mA OPERATING TEMPERATURE to Tmax Operation to 2 7 V Minimum Supply Voltage 25 85 Operation to 4 5 Minimum Supply Voltage 40 85 Specifications subject to change without notice REV 0 AD607 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Supply Voltage VPS1 VPS2 to COM1 COM2 5 5 bn A que p Y 2 M Y Temperature Package Package Internal Power Dissipation 600 mW Tu Model Range Description Option 2 7 to 5 5 Operating Temperature Range EET 25 C to 85 AD607ARS 25 C to 85 20 Pin Plastic RS 20 4 5 V to 5 5 V Operating Temperature Range for2 7Vto5 5V SSOP EU EN EEREN 40 C to 85 C Operation 40 C Storage Temperature Range 65 to 150 85 for 4 5 V Lead Temperature Range Soldering 60 sec 300 to 5 5 Operation NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions ab
18. TPUT 2 10 OUT1 DUAL SYNTHESIZER FET PROBE HP8765B P6205 0 8694 OUT2 IEEE SPEC AN HP6633A x10 FET PROBE PROBE SUPPLY DP8200 Figure 11 Quadrature Test Set C M C M aout C M GAIN C M pmp NOTE CONNECTIONS MARKED ARE DC COUPLED Figure 12 AD607 Characterization Board REV 0 AD607 V IF 20 MHz 20 MHz SSB NF dB CONVERSION GAIN dB 7 VPOS 3V IF 10 MHz 50 70 90 110 130 150 170 190 210 230 250 0 1 1 10 100 RF FREQUENCY MHz INTERMEDIATE FREQUENCY MHz Figure 13 Mixer Noise Figure vs Frequency Figure 16 Mixer Conversion Gain vs IF 25 VPOS 3 VREF 1 5 V 4500 4 0 4000 3 5 3500 1 RE 0 C FIT OF IF GAIN TEMP 3000 5 9 25 6 2500 6 m 2 2 0 2 5 E 2000 5 2 x 5 15 4 3 tt 1500 5 FIT OF GAI SHUNT COMPONENT 1 0 1000 6 0 5 0 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY MHz 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 TEMPERATURE Figure 14 Mixer Input Impedance Frequency VPOS V V GAIN 0 8 V Figure 17 Mixer Conversion Gain and IF Amplifier Gain
19. and FM detection via the and Q de modulators respectively Table lists the AD607 Evaluation Board s I O Connectors and their functions Table AD607 Evaluation Board Input and Output Connections Reference Connector Approximate Designation Type Description Coupling Signal Level Comments 5 Frequency DC 400 mV This pin needs to be biased at VMID Detector Input and ac coupled when driven by an external signal generator J2 SMA Power Up DC CMOS Logic Tied to Positive Supply by Jumper J10 Level Input SMA LO Input AC 16 dBm Input is terminated in 50 Q 250 mV J4 SMA RF Input AC 15 dBm max Input is terminated in 50 Q 54 mV J5 SMA MGC Input DC 0 4 V to 2 0 V Jumper is set for Manual Gain Control or 3 V Supply Input See Table I for Control Voltage RSSI Output GREF VMID Values J6 SMA IF Output AC NA This signal level depends on the AD607 s gain setting J7 SMA Q Output AC NA This signal level depends on the AD607 s gain setting 18 SMA I Output AC NA This signal level depends on the AD607 s gain setting Jo Jumper Ties GREF NA NA Sets gain control Scale Factor SF to VMID SF 75 VMID in dB V where VMID VPOS 2 J10 Jumper Ties Power Up NA NA Remove to test Power Up Down to Positive Supply 1 Terminal Pin Power Supply DC DC 2 7 V to 5 5 V Positive Input Draws 8 5 mA at VPS1 VPS2 midgain connection T2 Terminal Pin Power Supply DC Return GND 0
20. as gain span of 25 dB for the nominal AGC voltage range Thus in conjunction with the mixer s variable gain the total gain exceeds 90 dB The final IF stage has a fixed gain of 20 dB and it also provides differential to single ended conversion The IF input is differential at IFHI noninverting relative to the output IFOP and IFLO inverting Figure 36 shows a simpli fied schematic of the IF interface The offset voltage of this stage would cause a large dc output error at high gain so it is nulled by low pass feedback path from the IF output also shown in Figure 25 Unlike the mixer output the signal at IFOP is low impedance single sided voltage centered at Vp 2 by the DC feedback loop It may be loaded by a resistance as low as 50 Q which will normally be connected to VMID OFFSET FEEDBACK LOOP Figure 36 Simplified Schematic of the IF Interface REV 0 0607 The IF s small signal bandwidth is approximately 45 MHz from IFHI and IFLO through IFOP The peak output at IFOP is 560 mV at Vp 3 and 400 mV at the minimum of 2 7 This allows some headroom at the demodulator inputs pin DMIP which accept a maximum input of 150 mV for IFs gt 3 MHz and 75 mV IFs lt 3 MHz at IFs gt 3 MHz the drive to the demodulators must be reduced to avoid saturat ing the output amplifiers with higher order mixing products that are no longer removed by the onboard low pass filters If the interna
21. ator BFO and the demodulator serves as product detector for CW or SSB reception Finally the AD607 can be used to demodulate BPSK using an external Costas Loop for carrier recovery O Analog Devices Inc 1995 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD607 SPEC 0 25 C Supply 3 0 V IF 10 7 MHz unless otherwise noted Model AD607ARS Conditions Min Typ Max Units DYNAMIC PERFORMANCE MIXER Maximum RF and LO Frequency Range For Conversion Gain gt 20 dB 500 MHz Maximum Mixer Input Voltage For Linear Operation Between RFHI and RFLO 54 mV Input 1 dB Compression Point RF Input Terminated in 50 Q 15 dBm Input Third Order Intercept RF Input Terminated in 50 Q 5 dBm Noise Figure Matched Input Max f 83 MHz IF 10 7 MHz 14 dB Matched Input Max f 144 MHz IF 10 7 MHz 12 dB Maximum Output Voltage at MXOP Zip 165 Q at Input Compression 21 3 V Mixer Output Bandwidth at 3 dB 1650 45 MHz LO Drive Level Mixer LO Input Terminated in 50 Q 16 dBm LO Input Impedance LOIP to VMID 1 Isolation RE to IF RF 240 MHz IF 10 7 MHz LO 229 3 MHz 30 dB Isolation LO to IF RF 240 MHz IF 10 7 MHz LO 229 3 MHz 20 dB Isolation LO to RF RF 240 MHz IF 10 7 MHz LO 229 3 MHz 40 dB Isolation IF to RF 240 MHz IF 10 7 MHz LO 229 3 MHz 70 dB IF AMPLIFIERS Noise
22. e The objective should be that the gain should not vary by more than the amount required to introduce say 1 THD distortion at the lowest modulation frequency say 300 Hz Note that in AM applications it is the modulation bandwidth that determines the required AGC filter capaci tor not the IF 4 In some applications even slower AGC may be desired than that required to prevent modulation tracking AD607 EVALUATION BOARD The AD607 evaluation board Figures 46 and 47 consists of an AD607 ground plane I O connectors and a 10 7 MHz band pass filter The RF and LO ports are terminated in 50 Q to provide broadband match to external signal generators to al low choice of RF and LO input frequencies The IF filter is at 10 7 MHz and has 330 Q input and output terminations the board is laid out to allow the user to substitute other filters for other IFs R11 VPOS FDIN VMID MOD FOR DC COUPLED INPUT Figure 46 Evaluation Board REV 0 19 AD607 or 2 y ANALOG A DEVICES C8 EVALUATION BOARD REU A Figure 47 Evaluation Board Layout 20 0 AD607 The board provides SMA connectors for the RF and LO port inputs the demodulated I and outputs the manual gain con trol MGC input the PLL input and the power up input In addition the IF output is also available at an SMA connector this may be connected to the PLL input for carrier recovery to realize synchronous AM
23. e internal AGC detector is used REV 0 The gain control scaling is proportional to the reference voltage applied to the pin GREF When this pin is tied to the midpoint of the supply VMID the scale is nominally 20 mV dB 50 dB V for Vp 3 V Under these conditions the lower 80 dB of gain range mixer plus IF corresponds to a control voltage of 0 4 V lt 2 0 V The final centering of this 1 6 V range de pends on the insertion losses of the IF filters used More gener ally the gain scaling using these connections is Vp 150 volts per dB so becomes 33 3 mV dB 30 dB V using a 5 V supply with a proportional change in the range to 0 33 lt Vg 3 V Table II lists gain control voltages and scale factors for power supply voltages from 2 7 V to 5 5 V Alternatively pin GREF can be tied to an external voltage reference Vg provided for example by an AD1582 2 5 V or AD1580 1 21 V voltage reference to provide supply independent gain scaling of Vp 75 volts per dB When using the Analog Devices AD7013 and AD7015 baseband converters the external reference may also be provided by the reference output of the baseband converter Figure 38 For example the AD7015 baseband converter provides of 1 23 V when connected to GREF the gain scaling is 16 4 mV dB 60 dB V An auxiliary DAC in the AD7015 can be used to generate the voltage Since it uses the same reference voltage the nu merical inp
24. erates from 400 kHz to 12 MHz and is con trolled by the voltage between VPOS and FLTR In normal op eration a series RC network forming the PLL loop filter is connected from FLTR to ground The use of an integral sample hold system ensures that the frequency control voltage on pin FLTR remains held during power down so reacquisition 1 pole RC filter with its corner above the modulation bandwidth of the carrier typically occurs in 16 5 is sufficient to attenuate undesired outputs Phase Locked Loop In practice the probability of a phase mismatch at power up is high so the worst case linear settling period to full lock needs The demodulators are driven by quadrature signals that are to be considered in making filter choices This is typically 16 5 us vided by a variable frequency quadrature oscillator VFQO phase locked to a reference signal applied to pin FDIN When this signal is at the IF inphase and quadrature baseband out puts are generated at IOUT and QOUT respectively The at an IF of 10 7 MHz for a 100 mV signal at and FDIN Table II AD607 Gain and Manual Gain Control Voltage vs Power Supply Voltage Power Supply GREF Gain Control Voltage VMID Scale Factor Scale Factor Voltage Input Range V V dB V mVIdB V 2 7 1 35 55 56 18 00 0 360 1 800 3 0 1 5 50 00 20 00 0 400 2 000 3 5 1 75 42 86 23 33 0 467 2 333 4 0 2 0 37 50 26 67 0 533 2 667 4 5 2 25 33 33 30 00 0 600 3 0
25. gn and reducing LO leakage from the RF port Internally this single sided input is actually differential the noninverting input is referenced to pin VMID The LO requires a single sided drive of 50 mV or 16 dBm in a 50 Q system The mixer s output passes through both a low pass filter and a buffer which provides an internal differential to single ended signal conversion with a bandwidth of approximately 45 MHz Its output at pin MXOP is in the form of a single ended current This approach eliminates the 6 dB voltage loss of the usual se ries termination by replacing it with shunt terminations at the both the input and the output of the filter The nominal conver sion gain is specified for operation into a total IF bandpass filter BPF load of 165 Q that is a 330 Q filter doubly terminated as shown in Figure 33 Note that these loads are connected to bias point VMID which is always at the midpoint of the supply that is Vp 2 The conversion gain is measured between the mixer input and the input of this filter and varies between 1 5 dB and 26 5 dB for a 165 Q load impedance Using filters of higher impedance the conversion gain can always be maintained at its specified value or made even higher for filters of lower impedance of say Zo the conversion gain will be lowered by 10 log 0 165 Zo Thus the use of a 50 Q filter will result in a conversion gain that is 5 2 dB lower Figure 35 shows filter matching networks and Table
26. l AGC detector is used the IF output will be at an amplitude of Vp 10 that is 300 mV for Vp 3 V This 300 mV level requires the insertion of 6 dB of post IF filter loss be tween IFOP and DMIP to avoid overloading demodulators often a simple RC low pass filter with its corner frequency at the IF will suffice Since there is no band limiting in the IF strip the output referred noise can be quite high in a typical application and at a gain of 75 dB it is about 100 mV rms making post IF filtering desirable IFOP may be also used as an IF output for driving an A D converter external demodulator or external AGC detector Figure 37 shows methods of matching the optional second IF filter a Biasing DMIP from Power Supply Assumes BPF AC Coupled Internally 7 CBvPAsS b Biasing DMIP from VMID Assumes BPF AC Coupled Internally Figure 37 Input and Output Matching of the Optional Second IF Filter Gain Scaling and RSSI The AD607 s overall gain expressed in decibels is linear in dB with respect to the AGC voltage Vg at pin GAIN RSSI The gain of all sections is maximum when is zero and reduces progressively up to 2 2 V for Vp 3 V in general up to a limit 0 8 V The gain of all stages changes in parallel The AD607 features temperature compensation of the gain scaling Note that GAIN RSSI pin is either an MGC input when the gain is controlled by some external means or an RSSI output when th
27. lanced by the pull down current and the charging ceases It will be apparent that the loop filter is essentially a perfect integrator This simple system can be used because the input impedance of the gain control system also internally tied to the GAIN RSSI pin is several megohms and its bias current is small The volt age Vg may be used as an RSSI output however if it is to be heavily loaded a buffer amplifier must be used Note that unlike post demodulation detector via DSP this scheme responds to signal plus noise Thus when operating at high gains the AGC loop will see a substantial output at the IFOP node even though a filter may be added by the user between the pins IFOP and DMIP This will trick the loop into lowering the gain until the composite output signal IF plus noise reaches the reference level and satisfies the average current requirement In these circumstances the wanted signal will be smaller than expected Thus the internal AGC system will result in a slight compression of the demodulated output for very small signal levels Discharge Time The discharge current is approximately 4 5 uA thus to restore gain in the event rapid drop out requires time of T C x Vg 4 5 uA Using 1 nF capacitor and noting that an 80 dB gain change corresponds to 1 6 V the discharge time is 355 us Note however that when GREF is tied to a different value the scaling changes For GREF 1
28. liced at the 300 mV level to generate a current of 76 2 or 38 yA After subtracting the 4 5 UA we should have about 33 In fact the maximum ramp up current is about 20 uA because the waveform is not a crisp square wave and as the loop ap proaches equilibrium it is more nearly sinusoidal Thus the ramp up rate is 20 4 5 4 4 times faster than the discharge rate In our example a 1 6 V change will require about 1 5 ms using Applications Hints Do not place a resistor from Pin 12 to Ground The resistor converts the integrator ideal for AGC into a low pass filter An integrator needs no input to sustain a given output a low JUMPER R10 AD607 EVALUATION BOARD AS RECEIVED VPOS VMID MOD FOR LARGE MAGNITUDE AC COUPLED INPUT 4 99kQ OPEN LOIP pass filter does This input is an INCREASED AMPLITUDE required at IFOP The AGC loop thus does not level the output at IFOP Reasons for Using a Larger AGC Capacitor 1 In applications where gain modulation may be troublesome raise the capacitor from 1 nF to 2 7 nF the 80 dB slew time at 20 mV dB is now close to 1 ms 2 As the IF is lowered the capacitor must be increased accord ingly if gain ripple is to be avoided Thus to achieve the same ripple at 455 kHz requires the 1 nF capacitor to be in creased to 0 022 3 In AM applications the AGC loop must not track the modu lation envelop
29. lists resistor values Figure 35 Suggested IF Filter Matching Network The Values of R1 and R2 Are Selected to Keep the Impedance at Pin MXOP at 165 Q 14 Table AD607 Filter Termination Resistor Values for Common IFs Filter Filter Termination Resistor IF Impedance Values for 24 dB of Mixer Gain Ri R2 R3 450 kHz 1500 Q 1740 13300 15000 455 kHz 1500 Q 1740 13300 15000 6 5 MHz 10000 2150 7870 1000 Q 10 7 MHz 3300 3300 00 3300 NOTES Resistor values were calculated such that R1 R2 and R2 Zen rer 165 Q The maximum permissible signal level at MXOP is determined by both voltage and current limitations Using a 3 V supply and VMID at 1 5 V the maximum swing is about 1 3 V To attain a voltage swing of 1 V in the standard IF filter load of 165 Q load requires peak drive current of about 6 mA which is well within the linear capability of the mixer However these upper limits for voltage and current should not be confused with issues related to the mixer gain already discussed In an operational system the AGC voltage will determine the mixer gain and hence the signal level at the input pin it will always be less than 56 mV 15 dBm into 50 which is the limit of the IF amplifier s linear range IF Amplifier Most of the gain in the AD607 arises in the IF amplifier strip which comprises four stages The first three are fully differential and each h
30. nd the midpoint supply pin VMID Guidance on these matters is also generally in cluded in applications schematics Gain Distribution As in all receivers the most critical decisions in effectively using the AD607 relate to the partitioning of gain between the various subsections Mixer IF Amplifier Demodulators and the place ment of filters so as to achieve the highest overall signal to noise ratio and lowest intermodulation distortion Figure 42 shows the main signal path at maximum and minimum signal levels 1 23V MAX OUTPUT 560mV 154mV FOP DMIP LOCATION OF OPTIONAL SECOND IF FILTER Figure 42 Signal Levels for Minimum and Maximum Gain REV 0 17 AD607 As noted earlier the gain in dB is reduced linearly with the volt age on the GAIN pin Figure 43 shows how the mixer and IF strip gains vary with when GREF 15 connected to VMID 1 5 V and a supply voltage of 3 V is used Figure 44 shows how these vary when GREF is connected to 1 23 reference 90dB 80dB 70dB 60dB 50dB IF GAIN 40dB 30dB on MIXER GAIN 10dB 0dB 0 1 18V 22 24 NORMAL OPERATING RANGE Vg Figure 43 Gain Distribution for GREF 1 5 90dB 80dB 70dB 67 5dB 60dB 50dB 40dB 30dB 21 54 20dB MIXER GAIN 10dB 7 5dB 1 5dB 0dB 0 0 328V 1V 1 64V 2V NORMAL OPERATING RANGE gt Fig
31. ove those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics 20 lead SSOP Package 6j 126 C W CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection WARNING lt Although the AD607 features proprietary ESD protection circuitry permanent damage may a occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE REV 0 3 0607 PIN DESCRIPTION Pin Mnemonic Reads Function 1 FDIN Frequency Detector Input PLL input for demodulator quadrature oscillator 400 mV drive required from external oscillator Must be biased at Vp 2 2 Common 1 Supply common for RF front end and main bias 3 PRUP Power Up Input 3 V 5 V CMOS compatible power up control logical high powered up max input level VPS1 VPS2 4 LOIP Local Oscillator Input LO input ac coupled 54 mV LO input required 16 dBm for 50 Q input termination 5 RFLO RF Low Input Usually connected to ac ground 6 High Input AC coupled 56 mV max input for linear operation 7 GREF Gain Reference Input
32. ted Methods for Biasing Pin DMIP at Vy2 For IFs lt 3 MHz the on chip low pass filters 2 MHz cutoff do not attenuate the IF or feedthrough products thus the maxi mum input voltage at DMIP must be limited to 75 mV to al low sufficient headroom at the and Q outputs for not only the desired baseband signal but also the unattenuated higher order demodulation products These products can be removed by an external low pass filter In the case of 1854 applications using a 455 kHz IF and the AD7013 baseband converter a simple quadrature accuracy of this VFQO is typically 1 2 at 10 7 MHz The PLL uses a sequential phase detector that comprises low power emitter coupled logic and charge pump Figure 40 I CLOCK F SEQUENTIAL FREQUENCY PSP PHASE Runde QUADRATURE 190 OSCILLATOR SMA d Q CLOCK i5 ECL OUTPUTS REFERENCE CARRIER FDIN AFTER LIMITING Figure 40 Simplified Schematic of the PLL and Quadrature VCO The reference signal may be provided from an external source in the form of a high level clock typically a low level signal 400 mV since there is an input amplifier between FDIN and the loop s phase detector For example the IF output itself can be used by connecting DMIP to FDIN which will then pro vide automatic carrier recover for synchronous AM detection and take advantage of any post IF filtering Pin FDIN must be biased at Vp 2 Figure 41 shows suggested methods The VFQO op
33. ure 44 Gain Distribution for GREF 1 23 V Using the Internal AGC Detector The AD607 includes a detector cell at the output of the IF am plifier that allows it to provide its own AGC and output leveling function in receiver applications where DSP support is not needed It is only necessary to connect a filter capacitor between the GAIN pin and ground to invoke this feature The voltage appearing on this pin may then be used as an RSSI output with the scaling discussed earlier note particularly that the voltage on GRFF continues to determine this scaling Figure 45 shows a simplified schematic of the detector Transis tor Q2 remains cut off by a 300 mV bias when Vp 3 V in gen eral Vp 10 until the positive tip of the IF waveform causes it to briefly conduct charging the AGC filter capacitor Cagc in a positive direction The voltage across this capacitor is Vg 18 LAST IF STAGE 1 5V 316mV TO INTERNAL GAIN CONTROL IF OUTPUT AVERAGE OF IC2 IS FORCED 4 5 BY INTEGRATION IN CAGC COMM Figure 45 Simplified Schematic of AGC Detector Acting against this is an internally generated 4 5 pull down current which operates to within a few millivolts of ground As the voltage at the GAIN RSSI pin rises the gain falls so re ducing the amplitude of the IF output and reducing the ampli tude of the current spike in Q2 eventually a point is reached where its average collector current is ba
34. ut to this DAC provides an accurate RSSI value in digital form no longer requiring the reference voltage to have high absolute accuracy AD7013 OR AD7015 Figure 38 Interfacing the AD607 to the AD7013 or AD7015 Baseband Converters I Q Demodulators Both demodulators I and Q receive their inputs at pin DMIP Internally this single sided input is actually differential the noninverting input is referenced to pin VMID Each demodula tor comprises a full wave synchronous detector followed by a 2 MHz two pole low pass filter producing single sided outputs at pins IOUT and QOT Using the I and Q demodulators for IFs above 12 MHz is precluded by the 400 kHz to 12 MHz response of the PLL used in the demodulator section Pin DMIP requires an external bias source at 2 Figure 39 shows sug gested methods Outputs IOUT and are centered at Vp 2 and can swing up to 1 23 V even at the low supply voltage of 2 7 V They can therefore directly drive the RX ADCs in the AD7015 baseband converter which require an amplitude of 1 23 V to fully load them when driven by a single sided signal The con version gain of the I and Q demodulators is 18 dB X8 requir ing a maximum input amplitude at DMIP of 150 mV for IFs gt 3 MHz 15 AD607 a Biasing DMIP from Power Supply Assumes BPF AC Coupled Internally 85 b Biasing from VMID Assumes Coupled Internally Figure 39 Sugges

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