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NEC MC-4564EC727 handbook

1. Vcc Vss REGE NC Data Sheet 14461 2 00500 SDRAM Bank Select Data Inputs Outputs Clock Input Clock Enable Input Write Protect Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQ Mask Enable Address Input for EEPROM Serial Data I O for PD Clock Input for PD Power Supply Ground Register Buffer Enable No Connection 4564 727 Block Diagram 1 2 RCS10 I 50 o 1 RDQMBO RDQMB4 DQ3 0 00 DQM DQM CS DQ20 O 1 O 1 O 2 O 2 O 3 O 3 D27 O0 DQM CS CS YOO DQM CS O 1 O 1 O 2 O 2 O 3 O 3 D28 O0 DQM CS O0 DQM CS O 1 O 1 O 2 O 2 4 O 3 CS O0 DQM CS O 1 O 1 O 2 O 2 u O 3 CS O0 DQM CS DQM ICS O 1 O 1 10 2 D22 10 2 D31 O 3 O 3 D29 D4 RCS3 RCS2 o RDQMB2 DQ19o Wyv O0 DQM YOO DQM CS 00180 O 1 O 1 O 2 O 2 032 O 3 O 3 O0 DQM CS CS DQM CS O 1 1 jo 024 jo 033 O 3 O 3 O0 DQM CS DQM CS O 1 O 1 10 2 D25 10 2 D34 DOM TCS DOM TCS yo2 026 02 D35 D18 09 D27 CLK D1 D19 D10 D28 100 CLK D2 D20 011 029 CLK1 CLK3 P CLK D3 D21 D12 D30 CLKO O PLL CLK D4 D22 D13 D31 gt CLK 05 023 014 032 CLK 06 024 015 033
2. CLK 07 025 016 034 D8 026 017 035 REGISTER1 REGISTERS 12 pF SERIAL PD SDA SCLO WP Vcc O 4 D0 035 REGISTER REGISTERS PLL 47 _ Vss DO 035 REGISTER REGISTERS PLL SAO 1 SA2 4 Data Sheet M14461EJ2V0DS00 10 ko REGE Register 1 Register 2 A110 BA1 CKEO Register 3 CS2 CS3 DQMB2 DQMB3 o DQMB6 o DQMB7 Remarks 1 The value of all resistors of DQs is 10 2 DO 035 uPD45128441 8 M words x 4 bits x 4 banks 3 REGE lt Buffer mode REGE gt Register mode 4 Register SN74AVC16834DGG PLL HD74CDCF2510B IDTCSP2510C Data Sheet 14461 2 00500 MC 4564EC727 R1A1 DO D4 D9 D12 D18 D22 D27 D30 R2A1 D5 D8 013 017 023 026 031 035 R1A3 00 04 09 012 018 022 027 030 R2A3 05 08 013 017 023 026 031 035 R1A5 00 04 09 012 018 022 027 030 R2A5 05 08 013 017 023 026 031 035 R1A7 00 04 09 012 018 022 027 030 R2A7 05 08 013 017 023 026 031 035 R1A9 00 04 09 012 018 022 027 030 R2A9 05 08 013 017 023 026 031 035 R1RAS 00 04 09 012 018 022 027 030 R2RAS 05 08 013 017 023 026 031 035 R1CAS 00 04 09 012 018 022 027 030 R2CAS 05 08 013 017 023 026 031 035 R1BAO0 00 04 09 012 018 022 027 030 RCS1 RDQMB4 RDQMB5 R1A0 DO D4 D9 D12 D18 D22 D27 D30 R2A0 D5 D8 D13 D17 D23 D26 D31 D35 R1A2 DO D4 D9 D
3. one time during 30 ns IccaNS gt Vin Input signals are stable Operating current Icca tck gt lo CAS latency 2 Burst mode CAS latency 3 CBR Auto Refresh current 1665 tac gt tre MIN CAS latency 2 CAS latency 3 Vi 0 to 3 6 V All other pins not under test 0 V 2 830 mA 3 gt 3 83 3 460 5 08 5 260 Self refresh current lecce lt 0 2 lw Input leakage current Input leakage current CKEO Input leakage current CS0 CS3 DQMB0 DQMB7 Output leakage current Vo c 01938 el vt BETIS Notes 1 1 depends on output loading and cycle rates Specified values are obtained with the output open low High level output voltage Vou VoL Low level output voltage In addition to this Icc is measured on condition that addresses are changed only one time during MIN 2 depends on output loading and cycle rates Specified values are obtained with the output open In addition to this is measured on condition that addresses are changed only one time during MN 3 5 is measured on condition that addresses are changed only one time during MIN Data Sheet M14461EJ2VODS00 7 4564 727 Characteristics Recommended Operating Conditions Unless Otherwi
4. repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance M7 98 8
5. 12 D18 D22 D27 D30 R2A2 D5 D8 D13 D17 D23 D26 D31 D35 R1A4 DO D4 D9 D12 D18 D22 D27 D30 R2A4 D5 D8 013 017 023 026 D31 D35 R1A6 DO D4 D9 D12 D18 D22 D27 D30 R2A6 D5 D8 D13 D17 D23 D26 D31 D35 R1A8 DO D4 D9 D12 D18 D22 D27 D30 R2A8 D5 D8 D13 D17 D23 D26 D31 D35 R1A10 00 04 09 012 D18 D22 027 030 R2A10 05 08 013 017 023 026 031 035 R1WE 00 04 09 012 018 022 027 030 R2WE 05 08 013 017 023 026 031 035 R2BAO0 05 08 013 017 023 026 031 035 RCSO RDQMB4 RDQMB5 R1A11 D0 D4 D9 D12 D18 D22 D27 D30 R2A11 D5 D8 D13 D17 D23 D26 D31 D35 R1BA1 D0 D4 D9 D12 D18 D22 D27 D30 R2BA1 D5 D8 D13 D17 D23 D26 D31 D35 R1CKE0 D0 D2 09 010 D18 D20 027 028 2 D5 D6 D14 D15 023 024 032 033 D3 D4 D11 D13 021 022 029 031 R4CKEO D7 D8 D16 D17 D23 D24 034 035 RCS2 RCS3 RDQMB2 RDQMB3 RDQMB6 RDQMB7 2 2 4564 727 Electrical Specifications All voltages are referenced to Vss GND e After power up wait more than 1 ms and then execute power on sequence and CBR Auto refresh before proper device operation is achieved Absolute Maximum Ratings Casas w es iid Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage The device is not meant to be operated under conditions outside the limits described in the
6. 2518 C 4564EC T274E RV RS DATA SHEET MOS INTEGRATED CIRCUIT MC 4564EC727 64M WORD BY 72 BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE Description The MC 4564EC727 is a 67 108 864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of 128 M SDRAM uPD45128441 are assembled This module provides high density and large quantities of memory in a small space without utilizing the surface mounting technology on the printed circuit board Decoupling capacitors are mounted on power supply line for noise reduction Features 67 108 864 words by 72 bits organization ECC type Clock frequency and access time from CLK MC 4564EC727EF A75 133 MHz PC133 Registered DIMM Fully Synchronous Dynamic RAM with all signals referenced to a positive clock edge Pulsed interface Possible to assert random column address in every cycle Quad internal banks controlled by BAO and BA1 Bank Select Programmable burst length 1 2 4 8 and Full Page Programmable wrap sequence Sequential Interleave Programmable CAS latency 2 3 Automatic precharge and controlled precharge CBR Auto refresh and self refresh All DQs have 10 Q 10 of series resistor Single 3 3 V 0 3 V power supply e LVTTL compatible 4 096 refresh cycles 64 ms Burst termination by Burst Stop command and Precharge command 168 pin dual in line memory module Pin pitch 2 1 27 mm Registered type Serial
7. 4 0 0 10 3 0 1 27 0 1 4 0 MIN 0 2 0 15 1 0 0 05 2 54 0 10 8 0 MIN 3 0 MIN M168S 50A111 detail of part detail of part D2 N lt gt x lt zu oO o z z z x lt Data Sheet M14461EJ2V0DS00 13 4564 727 MEMO 14 Data Sheet 14461 2 00500 4564 727 NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT
8. PD Stacked monolithic technology The information in this document is subject to change without notice Before using this document please confirm that this is the latest version Not all devices types available in every country Please check with local NEC representative for availability and additional information Document No 14461 02 00500 2nd edition mark shows major revised points NEC Corporation 1999 Date Published February 2000 NS CP K Printed in Japan 4564 727 Ordering Information Clock 4564EC727PF A75 Edge connector Gold plated 36 pieces of uPD45128441G5 Rev P 43 18 mm height 10 16mm 400 TSOP Il MC 4564EC727EF A75 E Tm 168 pin Dual In line Memory Module 36 pieces of uPD45128441G5 Rev E Socket Type 10 16mm 400 TSOP 1 2 Data Sheet 14461 2 00500 Pin Configuration 168 pin Dual In line Memory Module Socket Type Edge connector Gold plated 9 13 A11 Vcc O CLK1 O NC O Vss O CKEO CS3 DQMB6 DQMB7 O NC O Vcc O NC O NC O CB6 O CB7 O Vss O DQ48 O DQ49 10 BA1 A12 O Vcc O 1 2 3 4 5 6 7 8 9 1 MC 4564EC727 indicates active low signal A0 A11 Address Inputs Row A0 A11 Column A0 A9 A11 BAO A13 BA1 A12 000 DQ63 7 CLKO CLK3 CKEO WP CS0 CS3 RAS CAS DQMBO DOMB7 SA0 SA2 SDA SCL
9. PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Inputlevels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels settings or contents of registers Device is not initialized until the reset signal 1 received Reset operation must be executed immediately after power on for devices having reset function Data Sheet M14461EJ2VODS00 15 4564 727 CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules be sure not to touch any components on the modules such as the memory IC chip capacitors and chip
10. ny losses incurred by the customer or third parties arising from the use of these circuits software and information While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible
11. o 25 o o soram o 1 2 banks 72 bits ofo ofi lm 1 1 1 2 4 8 o EEA po jo pa fo 4564 727 2 2 32 and address signal input 15H 0 1 1 1 1 5 ns setup time 33 and address signal input 08H 0 1 0 0 8 ns hold time as Data C me vee Dos mss _ Assen 127 Intel specification CAS latency A75 85H support E E Es Ex ES E ES ER Timing Chart Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information M13348E 12 Data Sheet 14461 2 00500 0 0 0 0 1 1 1 0 0 0 1 po up 0255 4564 727 Package Drawing 168 PIN DUAL IN LINE MODULE SOCKET TYPE A AREA B M1 AREA B 2 ITEM MILLIMETERS 133 35 133 35 0 13 11 43 36 83 D 6 35 D1 2 0 D2 3 125 54 61 6 35 1 27 8 89 24 495 42 18 17 78 43 18 0 13 1 23 40 2 19 78 6 35 MAX 1 0 R2 0
12. ommand wo m ACT one to ACT another command period 16 PY go __ Datainto ACT REF command OASlaeny 3 tw aefa period Auto precharge CASlteny 2 tw 100620 d es 3 om __ m Mode register set cycle time trsc Refresh time 4 096 refresh cycles we Note This device can satisfy the spec of 1CLK 20 ns for up to and including 125 MHz operation 10 Data Sheet M14461EJ2VODS00 Serial PD MC 4564EC727 1 2 Notes serial PD memory 1 Total number of bytes of seal PD memory 08H o 2 04H 3 Number ofrows ocu o 4 Number of columns 0 5 module banks oH o Data width 48H 7 Data width continued oH 8 jVotapimefae OTH _ 9 azs o oL sAccesstime azs sam o 11 DIMM configurationtype fo 12 Refresh rate type 1 SDRAMwidh 15 Minimum clock delay 01H 4 6 7 8 9 0 1 EA 19 _ CS latency supported om o 20 E H H 2 SDRAM device attributes General OH o 27 TRP MIN 14H 29 mew A oF o 9 __ azs 30 TRAS MIN 2DH 51 jModuebankdensty 40H o 1 1 1 1 2 2 2 2 04 06 E 0 Data Sheet M14461EJ2VODS00 128 bytes
13. operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Recommended Operating Conditions wa o p pss 38 e v s v o gt Capacitance TA 25 C f 1 MHz Input capacitance Cn A0 A11 BAO A13 BA1 A12 pF wu 5 e je jemxm wo reo mo 6 Data Sheet 14461 92 00800 f F f f f 4564 727 DC Characteristics Recommended Operating Conditions unless otherwise noted Operating current Burst length 1 ICAS latency 2 a75 2 740 mA 1 gt trc MIN lo 0 mA ICAS 3 a75 2 830 0 Precharge standby current IccaN CKE gt 15 ns CS gt Vin MIN 7 3 gt non power down mode Input signals are changed one time during 30 ns IccaNS CKE gt tck Input signals are stable Active standby current in CKE lt 15 ns power down mode 5 CKE lt Active standby current in lccsoN gt 15 CS gt 3 4 3 o 2 1 330 non power down mode Input signals are changed
14. resistors It is necessary to avoid undue mechanical stress on these components to prevent damaging them When re packing memory modules be sure the modules are NOT touching each other Modules in contact with other modules may cause excessive mechanical stress which may damage the modules The information in this document is subject to change without notice Before using this document please confirm that this is the latest version No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer NEC Corporation assumes no responsibility for a
15. se Noted Test Conditions AC high level input voltage low level input voltage 2 4 0 4 EE CLK Input tac Output 8 Data Sheet 14461 92 00800 4564 727 Synchronous Characteristics dii Clock time BE DM 2 we 10 n Access time from CLK 3 us sae 1 2 uc jinputclock _ 0 9 m wj O muctKduygde 486 5 i weoumodime tm 20 0 Data out low impedance time Data outhigh impedance time 0 8 2 so 54 m 2 so 60 f m 1 Address setuptime jej j JOKE setuptime 0 CKE setup time Power down exit Command 50 CS3 RAS CAS WE DQMBO DQMB7 setup time Command 50 CS3 RAS CAS DQMBO DQMB7 hold time Note 1 Output load Output Remark These specifications are applied to the monolithic device Data Sheet M14461EJ2VODS00 9 4564 727 Asynchronous Characteristics dii a REF to command period ees es ACT to PRE command period 5 1 000 command period e m Delay time ACT to READWRITE c

NEC MC-4564EC727 handbook

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