MAXIM DS1330Y/AB handbook
Contents
1. 100 1005 Package Type P 34 pin PowerCap Module Vcc Tolerance 5 Y 10 8 of 11 DS1330Y AB DS1330Y AB NONVOLATILE SRAM 34 PIN POWERCAP MODULE TOP VIEW SIDE VIEW gt gt gt c c c BOTTOM VIEW REFERENCE ONLY COMPONENTS AND PLACEMENTS MAY DIFFER FROM THOSE SHOWN 9 of 11 DS1330Y AB DS1330Y AB NONVOLATILE SRAM 34 PIN POWERCAP MODULE WITH POWERCAP INCHES N B IER ire COL 1000000000001 COMPONENTS PLACEMENTS MAY DIFFER FROM THOSE SHOWN BOTTOM VIEW REFERENCE ONLY ASSEMBLY AND USE Reflow soldering Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented label side up live bug Hand soldering and touch up Do not touch soldering iron to leads for more than 3 seconds To solder apply flux to the pad heat the lead frame pad and apply solder To remove part apply flux heat pad until solder reflows and use a solder wick LPM replacement in a socket To replace a Low Profile Module in a 68 pin PLCC socket attach a DS9034PC PowerCap to a module base then insert the complete module into the socket one row of leads at a time pushing only on the corners of the cap Never apply force to the center of the device To remove from a socket use a PLCC extraction tool and ens2. DC ELECTRICAL Vcc 5V 5 for DS1330AB CHARACTERISTICS ta See Note 10 Vcc 5V 10 for DS1330Y PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current In 0 1 0 T O Leakage Current CE gt Vin lt 1 0 1 0 Output Current 2 4 Tou 1 0 mA 14 Output Current 0 4V 2 0 14 Standby Current CE 2 2V Iccsi 200 600 Standby Current Vcc 0 5V Iccs2 50 150 Operating Current Iccoi 85 mA Write Protection Voltage DS1330AB 4 50 4 62 4 75 Write Protection Voltage 05 1330 Vrp 4 25 4 37 4 5 3 of 11 DS1330Y AB CAPACITANCE t4 25 C PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance Cin 5 10 pF Input Output Capacitance 5 10 AC ELECTRICAL Voc 5V 5 for DS1330AB CHARACTERISTICS ta See Note 10 Vcc 5V 10 for DS1330Y DS1330AB 70 DS1330AB 100 DS1330Y 70 DS1330Y 100 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Read Cycle Time tre 70 100 ns Access Time tacc 70 100 ns OE to Output Valid tog 45 50 ns CE to Output Valid tco 70 100 ns OE or CE to Output Active 5 5 ns 5 Output High Z from Deselection top 25 35 ns 5 Output Hold from Address toH 5 5 ns Change Write Cycle Time twc 70 100 ns Write Pulse Width twp 55 75
3. 15 Each DS1330 has a built in switch that disconnects the lithium source until the user first applies Vcc The expected tpr is defined as accumulative time in the absence of Vcc starting from the time power is first applied by the user This parameter is assured by component selection process control and design It is not measured directly during production testing All AC and DC electrical characteristics are valid over the full operating temperature range For commercial products this range is 0 C to 70 C For industrial products IND this range is 40 C to 85 In power down condition the voltage on any pin may not exceed the voltage on twri and are measured from WE going high twr2 and tpm are measured from CE going high RST and BW are open drain outputs and cannot source current External pull up resistors should be connected to these pins for proper operation Both pins will sink 10mA DS1330 modules are recognized by Underwriters Laboratory U L under file E99151 DC TEST CONDITIONS Outputs Open Cycle 200ns for operating current All voltages are referenced to ground AC TEST CONDITIONS Output Load 100 pF 1TTL Gate Input Pulse Levels 0 3 0V Timing Measurement Reference Levels Input 1 5V Output 1 5V Input pulse Rise and Fall Times 5ns ORDERING INFORMATION DS1330 TTP 555 III Operating Temperature Range blank 0 to 70 IND 40 to 85 C Access Speed 70 700
4. 2578 D SI265Y DS1330Y AB f DALLAS AX 256k Nonvolatile SRAM with Battery Monitor RES PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Power supply monitor resets processor when Vcc power loss occurs and holds processor in reset during Vcc ramp up Battery monitor checks remaining capacity daily Read and write access times as fast as 70ns Unlimited write cycle endurance Typical standby current 50LA 1 2 3 4 5 6 7 8 9 34 Pin POWERCAP MODULE PCM Upgrade for 32k x 8 SRAM EEPROM or USES DS9034PC POWERCAP Flash Lithium battery is electrically disconnected to retain freshness until power is applied for the PIN DESCRIPTION first time 0 14 Address Inputs Full 10 Vcc operating range DS1330Y DQ0 DQ7 E Data In Data Out or optional 5 Vcc operating range CE Chip Enable DS1330AB WE Write Enable Optional industrial temperature range of OE Output Enable 40 C to 85 C designated IND RST Reset Output PONE Module PCM package BW Battery Warning Directly surface mountable module Vcc Power 45V Replaceable snap on PowerCap provides GND Ground lithium backup battery NC No Connect Standardized pinout for all nonvolatile NV SRAM products Detachment feature on PowerCap allows easy removal using a regular screwdriver DESCRIPTION The DS1330 256k NV S
5. RAMs 262 144 bit fully static SRAMs organized as 32 768 words by 8 bits Each NV SRAM has a self contained lithium energy source and control circuitry which constantly monitors Vcc for an out of tolerance condition When such a condition occurs the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption Additionally the DS1330 devices have dedicated circuitry for monitoring the status of Vcc and the status of the internal lithium battery DS1330 devices in the PowerCap module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete NV SRAM module The devices can be used in place of 32k x 8 SRAM EEPROM or Flash components 1 of 11 032904 DS1330Y AB READ MODE The DS1330 devices execute a read cycle whenever WE Write Enable is inactive high and CE Chip Enable and OE Output Enable are active low The unique address specified by the 15 address inputs Ao defines which of the 32 768 bytes of data is to be accessed Valid data will be available to the eight data output drivers within tacc Access Time after the last address input signal is stable providing that CE and Output Enable access times are also satisfied If and CE access times are not satisfied then data access must be measured from the later occurring signal CE or OE and the limiting parameter is either tco for CE or to
6. g for OE rather than address access WRITE MODE The DS1330 devices execute a write cycle whenever the WE and CE signals are in the active low state after address inputs are stable The later occurring falling edge of CE or WE will determine the start of the write cycle The write cycle is terminated by the earlier rising edge of CE or WE All address inputs must be kept valid throughout the write cycle WE must return to the high state for a minimum recovery time twr before another cycle can be initiated The OE control signal should be kept inactive high during write cycles to avoid bus contention However if the output drivers are enabled CE and OE active then WE will disable the outputs in topw from its falling edge DATA RETENTION MODE The DS1330AB provides full functional capability for Vcc greater than 4 75V and write protects by 4 5V The DS1330Y provides full functional capability for Vcc greater than 4 5V and write protects by 4 25V Data is maintained in the absence of Vcc without any additional support circuitry The NV SRAMs constantly monitor Vcc Should the supply voltage decay the NV SRAMs automatically write protect themselves all inputs become don t care and all outputs become high impedance As Vcc falls below approximately 2 7V the power switching circuit connects the lithium energy source to RAM to retain data During power up when Vcc rises above approximately 2 7V the power switching circuit connects externa
7. l Vcc to the RAM and disconnects the lithium energy source Normal RAM operation can resume after Vcc exceeds 4 75V for the DS1330AB and 4 5V for the DS1330Y SYSTEM POWER MONITORING DS1330 devices have the ability to monitor the external Vcc power supply When an out of tolerance power supply condition is detected the NV SRAMs warn a processor based system of impending power failure by asserting RST On power up RSTis held active for 200ms nominal to prevent system operation during power on transients and to allow tggc to elapse RST has an open drain output driver BATTERY MONITORING The DS1330 devices automatically perform periodic battery voltage monitoring on a 24 hour time interval Such monitoring begins within after Vcc rises above Vrp and is suspended when power failure occurs After each 24 hour period has elapsed the battery is connected to an internal IMQ test resistor for one second During this one second if battery voltage falls below the battery voltage trip point 2 6V the battery warning output BW is asserted Once asserted BW remains active until the module is replaced The battery is still retested after each Vcc power up however even if BW is active If the battery voltage is found to be higher than 2 6V during such testing BW is de asserted and regular 24 hour testing resumes BW has an open drain output driver 2 of 11 DS1330Y AB PACKAGES The 34 pin PowerCap module integrates SRAM memory and NV c
8. ms 14 Vcc Valid to BW Valid tBPU 1 5 14 BATTERY WARNING TIMING ta See Note 10 PARAMETER SYMBOL MIN MAX UNITS NOTES Battery Test Cycle 24 hr Battery Test Pulse Width tBTPW 1 S Battery Test to BW Active tew 1 8 ta 25 C PARAMETER SYMBOL MIN MAX UNITS NOTES Expected Data Retention Time 10 years 9 WARNING Under no circumstance are negative undershoots of any amplitude allowed when device is in battery backup mode NOTES 1 WE is high for a Read Cycle 2 OE Vm or Vu If OE Vy during write cycle the output buffers remain in a high impedance state 3 twp is specified as the logical AND of CE and WE twp is measured from the latter of CE or WE going low to the earlier of CE or WE going high 4 tpsis measured from the earlier of CE or WE going high 5 These parameters are sampled with a 5pF load and are not 100 tested 6 If the CE low transition occurs simultaneously with or latter than the WE low transition the output buffers remain in a high impedance state during this period 7 the CE high transition occurs prior to or simultaneously with the WE high transition the output buffers remain in high impedance state during this period 8 If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition the output buffers remain in a high impedance state during this period 7 of 11 DS1330Y AB 10 11 12 13 14
9. ns 3 Address Setup Time taw 0 ns Write Recovery Time 5 5 ns 12 twR2 12 12 13 Output High Z from WE topw 25 33 ns 5 Output Active from WE togw 5 5 ns Data Setup Time tps 30 40 ns 4 Data Hold Time 0 0 ns 12 tpH2 7 7 13 READ CYCLE ADDRESSES Dour SEE NOTE 1 DS1330Y AB WRITE CYCLE 1 oes ee tw dur SC em 75757 575 LY tos V Ow DATA IN STABLE Vi Vi SEE NOTES 2 3 4 6 7 8 and 12 L WRITE CYCLE 2 ADDRESSES V M r LN Din DATAINSTABLE gt V SEE NOTES 2 3 4 6 7 8 and 13 5 of 11 DS1330Y AB POWER DOWN POWER UP CONDITION Voc VTP tor 2 7 BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY RST SLEWS WITH Lc BW SEE NOTES 11 AND 14 BATTERY WARNING DETECTION SEE NOTE 14 6of 11 DS1330Y AB POWER DOWN POWER UP TIMING ta See Note 10 PARAMETER SYMBOL MIN MAX UNITS NOTES Vcc Fail Detect to CE and WE Inactive tpp 1 5 us 11 slew from Vrp to 0V tF 150 us Vcc Fail Detect to RST Active 15 us 14 Vcc slew from OV to Vrp tg 150 us Vcc Valid to CE and WE Inactive tpu 2 ms Valid to End of Write Protection tREC 125 ms Vcc Valid to RST Inactive trpu 150 200 350
10. ontrol along with contacts for connection to the lithium battery in the DS9034PC PowerCap The PowerCap module package design allows a DS1330 PCM device to be surface mounted without subjecting its lithium backup battery to destructive high temperature reflow soldering After a DS1330 PCM is reflow soldered a DS9034PC is snapped on top of the PCM to form a complete NV SRAM module The DS9034PC is keyed to prevent improper attachment DS1330 PowerCap modules and DS9034PC PowerCaps are ordered separately and shipped in separate containers See the DS9034PC data sheet for further information ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground 0 3V to 6 0V Operating Temperature Range Storage Temperature Range Soldering Temperature 0 C to 70 C 40 C to 85 C for IND parts 40 C to 70 C 40 C to 85 C for IND parts 260 C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods of time may affect reliability RECOMMENDED DC OPERATING CONDITIONS ta See Note 10 PARAMETER SYMBOL MIN MAX UNITS NOTES DS1330AB Power Supply Voltage 4 75 5 0 5 25 V DS1330Y Power Supply Voltage 4 5 5 0 229 Logic 1 Vin 22 Logic 0 0 0 0 8
11. ure that it does not hit or damage any of the module IC components Do not use any other tool for extraction 10 of 11 DS1330Y AB RECOMMENDED POWERCAP MODULE LAND PATTERN E AE RECOMMENDED POWERCAP MODULE SOLDER STENCIL P roe 1 5 00000000000000000 11 of 11
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MAXIM DS1330Y/AB handbook