ANALOG DEVICES Low Power High Speed Rail-to-Rail Input/Output Amplifier AD8029/AD8030/AD8040 handbook
Contents
1. 1000 1 _ 100 2 4 a 10 m 5 a E 2 O 1 0 1 1k 10k 100k 1M 10M 100M 1G FREQUENCY Hz INPUT ERROR VOLTAGE mV Rev A Page 13 of 20 Figure 45 Output Impedance vs Frequency Enabled 0 2 5 2 0 1 5 10 05 0 0 5 OUTPUT VOLTAGE V 10 15 20 03679 0 072 Figure 46 Input Error Voltage vs Output Voltage AD8029 AD8030 AD8040 DISABLE 0 5V TO 2V OUTPUT DISABLED OUTPUT AMPLITUDE V G 1 Rf 1kO 250 300 03679 A 020 0 50 100 150 TIME ns 200 Figure 47 AD8029 DISABLE Turn Off Timing OUTPUT ENABLED OUTPUT AMPLITUDE V Vs 2 5V G 1 Rf 1kO 0 50 100 150 200 250 300 ns 03679 A 021 Figure 48 AD8029 DISABLE Turn On Timing 350 350 Rev A Page 14 of 20 DISABLE PIN CURRENT uA 1 2 7 0 08 1 12 2 3 DISABLE PIN VOLTAGE V 03679 A 022 Figure 49 AD8029 DISABLE Pin Current vs DISABLE Pin Voltage THEORY OF OPERATION DISABLEO TO DISABLE CIRCUITRY AD8029 ONLY IN AD8029 AD8030 AD8040 O Vout Vs 03679 0 051 Figure 50 Simplified Schematic The AD8029 single AD2. ADS023 0 0 ANALOG Low Power High Speed DEVICES Rail to Rail Input Output Amplifier AD8029 AD8030 AD8040 FEATURES CONNECTION DIAGRAMS Low power 1 8 DISABLE 2 Vout 1 6 1 3 mA supply current amplifier 2 Vs High speed IN 3 6 Vour vs S DISABLE 125 MHz 3 dB bandwidth G 1 Vs 5 NC 60 V us slew rate NC NO CONNECT at Lk IN 80 ns settling time to 0 196 Rail to rail input and output Figure 1 SOIC 8 R Figure 2 5C70 6 KS No phase reversal inputs 200 mV beyond rails Wide supply range 2 7 V to 12V Offset voltage 6 mV max Low input bias current 0 7 pA to 1 5 pA Small packaging SOIC 8 SC70 6 SOT23 8 SOIC 14 TSSOP 14 03679 A 004 03679 A 002 APPLICATIONS 8 3 Battery powered instrumentation 5 E Filters D A to D drivers Figure 3 SOIC 8 R and Figure 4 SOIC 14 R and Buffering SOT23 8 RJ TSSOP 14 RU GENERAL DESCRIPTION The AD8029 single AD8030 dual and AD8040 quad are powered systems with large bandwidth requirements to high rail to rail input and output high speed amplifiers with a speed systems where component density requires lower power quiescent current of only 1 3 mA per amplifier Despite their dissipation low power consumption the amplifiers provide excellent performance with 125 MHz small signal bandwidth and 60 V us slew rate ADTs proprietary XFCB process enables high speed and high performance on low power The AD8029
3. Figure 40 Input Offset Voltage vs Input Common Mode Voltage INPUT OFFSET VOLTAGE mV FREQUENCY Rev A Page 12 of 20 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 41 Input Offset Voltage vs Temperature 120 COUNT 1088 MEAN 0 44mV STDEV 1 05mV 100 80 60 40 20 5 4 3 2 1 0 1 2 3 4 5 INPUT OFFSET VOLTAGE mV 03679 0 064 Figure 42 Input Offset Voltage Distribution 03679 A 006 OUTPUT SATURATION VOLTAGE V OUTPUT SATURATION VOLTAGE mV OUTPUT IMPEDANCE DISABLE LOW FREQUENCY Hz 03679 0 061 Figure 43 AD8029 Output Impedance vs Frequency Disabled LOAD RESISTANCE TIED TO MIDSUPPLY 1000 LOAD RESISTANCE Figure 44 Output Saturation Voltage vs Load Resistance 1kQ TIED TO MIDSUPPLY SOLID LINE Vs VOH DASHED LINE VOL Vs 20 35 50 65 80 TEMPERATURE 125 03679 0 066 Figure 42 Output Saturation Voltage vs Temperature AD8029 AD8030 AD8040
4. Vs R In single supply operation with R referenced to Vs worst case is Vour Vs 2 Airflow will increase heat dissipation effectively reducing 9a Also more metal directly in contact with the package leads from metal traces through holes ground and power planes will reduce the Care must be taken to minimize parasitic capaci tances at the input leads of high speed op amps as discussed in the PCB Layout section Figure 6 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC 8 125 C W SOT23 8 160 C W SOIC 14 90 C W TSSOP 14 120 C W and SC70 6 208 C W packages on a standard 4 layer board values are approximations MAXIMUM POWER DISSIPATION W 0 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100110120 AMBIENT TEMPERATURE 03679 018 Figure 6 Maximum Power Dissipation Output Short Circuit Shorting the output to ground or drawing excessive current from the AD8029 AD8030 AD8040 could cause catastrophic failure Rev A Page 6 of 20 TYPICAL PERFORMANCE CHARACTERISTICS AD8029 AD8030 AD8040 Default Conditions Vs 5 V Ta 25 Ri 1 tied to midsupply unless otherwise noted 0 Gz 1 gt Rp Rg 1kQ NORMALIZED CLOSED LOOP GAIN dB Vo 0 1V
5. 0 1 1 10 100 1000 FREQUENCY MHz 03679 0 004 Figure 7 Small Signal Frequency Response for Various Gains G 1 3 Vo 0 1V 2 5V 1 5 5 2 z S 3 a O 4 7 1 45V 1 o 5 1 9 y O 6 Y 7 H 8 i 1 10 100 1000 FREQUENCY MHz 03679 0 005 Figure 8 Small Signal Frequency Response for Various Supplies CLOSED LOOP GAIN dB 100 03679 0 006 FREQUENCY MHz Figure 9 Large Signal Frequency Response for Various Supplies 0 2 DASHED LINES 2V 1kQ 0 1 SOLID LINES Vour 0 1V 0 z IN 0 1 n 2 4 6 1 8 02 1 51 03 3x 5 I a a G 2 0 5 1 1 i 5 06 L z 07 1 1 po 0 8 1 10 100 FREQUENCY MHz E REA Figure 10 0 1 dB Flatness Frequency Response G 2 Vo 0 1V p p NORMALIZED CLOSED LOOP GAIN dB 1 10 100 FREQUENCY MHz 03679 A 012 Figure 11 Small Signal Frequency Response for Various Supplies NORMALIZED CLOSED LOOP GAIN dB 1 10 100 FREQUENCY MHz 03679 A 013 Figure 12 Large Signal Frequency Response for Various Supplies Rev A Page 7 of 20 AD8029 AD8030
6. 3 of 20 AD8029 AD8030 AD8040 SPECIFICATIONS WITH 5 V SUPPLY Table 2 Vs 5 V Ta 25 G 1 1 to midsupply unless otherwise noted specifications are per amplifier Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vo 0 1 V p p 80 120 MHz G 1 Vo 2Vp p 13 18 MHz Bandwidth for 0 1 dB Flatness G 2 Vo 0 1 V p p 6 MHz Slew Rate G 1 Vo 2 V Step 55 V us G 1 Vo 2V Step 60 V us Settling Time to 0 196 G 2 Vo 2 V Step 82 ns NOISE DISTORTION PERFORMANCE Spurious Free Dynamic Range SFDR fc 1 MHz Vo 2 V p p 73 dBc fc 5 MHz Vo 2 V p p 55 dBc Input Voltage Noise f 100 kHz 16 5 nv VHz Input Current Noise f 100 kHz 1 1 pA VHz Crosstalk AD8030 AD8040 5 MHz Vn 2 V p p 79 dB DC PERFORMANCE Input Offset Voltage PNP Active Vem 2 5 V 1 4 5 mV NPN Active Vem 4 5 V 1 8 6 mV Input Offset Voltage Drift to Tmax 25 Input Bias Current NPN Active 4 5 V 0 8 1 2 Tmn to Tmax 1 PNP Active Vem 2 5 V 1 8 28 Tmin to Tmax 2 Input Offset Current 0 1 0 9 Open Loop Vo 1Vto4V 65 74 dB INPUT CHARACTERISTICS Input Resistance 6 MQ Input Capacitance 2 pF Input Common Mode Voltage Range 0 2 to 5 2 V Common Mode Rejection Ratio 0 25 V to 2 V R 10 kO 80 90 dB DISABLE PIN AD8029 DISABLE Low Voltage Vs 0 8 V DISABLE Low Current 6 5 DISABLE High Volt
7. 72 dBc 5 MHz Vo 2 V 60 dBc Input Voltage Noise 100 kHz 16 5 nV JHz Input Current Noise 100 2 1 1 pA VHz Crosstalk AD8030 AD8040 5 MHz Vn 2 V p p 80 dB DC PERFORMANCE Input Offset Voltage PNP Active Vem 1 5 V 1 1 5 mV NPN Active Vem 2 5 V 1 6 mV Input Offset Voltage Drift Tmnto Tmax 24 uV C Input Bias Current NPN Active 2 5 V 0 7 1 2 to Tmax 1 Input Bias Current PNP Active Va 1 5 V 1 5 2 5 to Tmax 1 6 Input Offset Current 0 1 0 9 Open Loop Gain Vo 0 5 V to 2 5 V 64 73 dB INPUT CHARACTERISTICS Input Resistance 6 MO Input Capacitance 2 pF Input Common Mode Voltage Range 0 2 to 43 2 V Common Mode Rejection Ratio 0 25 V to 1 25 V 10 78 88 dB DISABLE PIN AD8029 DISABLE Low Voltage Vs 0 8 V DISABLE Low Current 6 5 DISABLE High Voltage Vs 1 2 V DISABLE High Current 0 2 Turn Off Time 5096 of DISABLE to 1096 of Final Vo 165 ns Vn 1V G 1 Turn On Time 50 of DISABLE to lt 10 of Final Vo 95 ns Vn 1V G 1 OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Rising Falling Edge Vin 1Vto 4V G 1 75 100 ns Output Voltage Swing 1 Vs 0 09 Vs 0 09 V 2 10 kO Vs 0 04 Vs 0 04 V Short Circuit Current Sinking and Sourcing 80 40 mA Off Isolation AD8029 Vin 0 1 V p p f 1 MHz DISABLE Low 55 dB Capacitive Load Drive 3096 Overshoot 10 pF POWER SUPPLY Operating Range 2 7
8. AD8030 are the only low power rail to rail input and output high speed amplifiers available in SOT23 and SC70 micro packages The amplifiers are rated over the extended industrial temperature range 40 C to 125 This family of amplifiers exhibits true single supply operation with rail to rail input and output performance for supply voltages ranging from 2 7 V to 12 V The input voltage range extends 200 mV beyond each rail without phase reversal The dynamic range of the output extends to within 40 mV of each rail The AD8029 AD8030 AD8040 provide excellent signal quality with minimal power dissipation At 1 SFDR is 72 dBc at 1 MHz and settling time to 0 196 is only 80 ns Low distortion and fast settling performance make these amplifiers suitable drivers for single supply A D converters VOLTAGE V G 1 The versatility of the AD8029 AD8030 AD8040 allows the user to operate the amplifiers on a wide range of supplies while consuming less than 6 5 mW of power These features extend the operation time in applications ranging from battery Figure 5 Rail to Rail Response R 1kQ TIED TO MIDSUPPLY TIME us 03679 A 010 Rev Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use
9. Small Signal Frequency Response vs Temperature FREQUENCY MHz 03679 0 015 Figure 18 Large Signal Frequency Response vs Temperature AD8029 AD8030 AD8040 35 G 1 1 Vour 2V Vout 2V 45 Ry 1kO SECOND HARMONIC SOLID LINE SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE THIRD HARMONIC DASHED LINE m _ 5 5 i z j 65 e Vs NW 2 e 5L T H gt a 9 z z Q s5 2 Vs 45V a lt b Vg 5V 95 105 0 01 01 1 10 0 01 0 1 1 10 FREQUENCY MHz 08679 0046 FREQUENCY MHz Figure 19 Harmonic Distortion vs Frequency and Supply Voltage Figure 22 Harmonic Distortion vs Frequency and Load G 2 T 1 FREQ 1MHz 45 Rp 1kQ Vout 2V p p FREQ 1MHz 50 8 Vg 3 Vg 5V z _6 z E 4 pM a ug Li 8 M 80 4 vr T KA q lt 1 lt I 1 90
10. Specifications subject to change without notice No license is granted by implication One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A or otherwise under any patent or patent rights of Analog Devices Trademarks and Tel 781 329 4700 www analog com registered trademarks are the property of their respective owners Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD8029 AD8030 AD8040 TABLE OF CONTENTS Specificationsu n t HERI e a a iya EORR 3 Applications a re e aq 16 Specifications with 5 V Supply sse 3 Wideband Operation sse 16 Specifications with 5 V Supply sse 4 Output Loading sensitivity seen 16 Specifications with 3 V Supply sss 5 Disable PIE 17 Absolute Maximum Ratings eene 6 Circuit Considerations seen 18 Maximum Power Dissipation senten 6 Design Tools and Technical Support sss 18 Typical Performance Characteristics sse 7 Outline Dimiensions iet ettet 19 Theory of Operation n n a a 15 Ordering Gilde eser eH ERR uqa 20 Input NECI 15 ESD iot quas 20 Qutput Stage co eee eere Re It N 15 REVISION HISTORY Revision A 11 03 Data Sheet Changed from Rev 0 to Rev A Change Page Added AD8040 20 2 2 22 0 Universal Change to Figure ayau upa saq
11. than 1 in noninverting configurations the feedback Ber id m 19 network represents an additional current load at the amplifier FREQUENCY MHz 8 output The feedback network Rr Re is in parallel with Figure 54 Gain of 2 Distortion which lowers the effective resistance at the output of the amplifier The lower effective resistance causes the amplifier to supply more current at the output Lower values of feedback resistance increase the current draw thus increasing the amplifiers power dissipation Rev A Page 16 of 20 Table 5 Effect of Load on Performance AD8029 AD8030 AD8040 Noninverting Rr Rc Rioap 3 dB BW Peaking 2 at 1 MHz HD3at1MHz Output Noise Gain ko ko MHz dB 2 V p p dB 2 V p p dB nV VHz 1 0 N A 1 120 0 02 80 72 16 5 1 0 N A 2 130 0 6 84 83 16 5 1 0 N A 5 139 1 87 5 92 5 16 5 2 1 1 1 36 0 72 60 33 5 2 2 5 2 5 2 5 44 5 0 2 79 72 5 344 2 5 5 5 43 2 84 86 36 1 1 1 1 40 0 01 68 57 33 6 1 2 5 2 5 2 5 40 0 05 74 68 34 1 5 5 5 34 1 78 80 36 The feedback resistance Rr Rc combines with the input DISABLE PIN capacitance to form a pole in the amplifier s loop response This can cause peaking and ringing in the amplifier s response if the RC time constant is too low Figure 55 illustrates this effect Peaking can be reduced by adding a small capacitor 1 pF 4 pF across the feedback resistor The best way to find
12. 0 1k 10k 100k 1M 10M 100M 1G 1k 10k 100k 1M 10M 100M 1G FREQUENCY Hz FREQUENCY Hz Figure 32 Common Mode Rejection Ratio vs Frequency Figure 35 PSRR vs Frequency 1 n 1 DRIVE DISABLE LOW 500 TOR Vin 0 1V 50 60 LISTEN TN Vour 8 8 70 x amp 80 t5 CROSSTALK 20log E AD8030 o 2 90 AMP 2 DRIVE x AMP 1 LISTEN 100 110 AD8040 120 AMP 4 DRIVE AMP 1 LISTEN 130 0 01 0 1 1 0 10 100 1000 FREQUENCY MHz os FREQUENCY MHz 8 Figure 33 AD8029 Off Isolation vs Frequency Figure 36 AD8030 AD8040 Crosstalk vs Frequency Rev A Page 11 of 20 AD8029 AD8030 AD8040 INPUT BIAS CURRENT PNP ACTIVE uA INPUT BIAS CURRENT uA 1 0 1 2 3 4 5 6 7 8 9 10 11 INPUT COMMON MODE VOLTAGE V 03679 0 074 Figure 37 Input Bias Current vs Input Common Mode Voltage SUPPLY CURRENT mA 0 35 50 65 80 95 110 125 TEMPERATURE 03679 0 073 Figure 38 Input Bias Current vs Temperature TEMPERATURE 03679 0 067 Figure 39 Quiescent Supply Current vs Temperature INPUT BIAS CURRENT NPN ACTIVE pA INPUT OFFSET VOLTAGE mV 1kO TO MIDSUPPLY Vs 3 A 0 1 2 3 4 5 6 7 8 9 10 11 INPUT COMMON MODE VOLTAGE V 03679 A 017
13. 12 V Quiescent Current Amplifier 1 3 1 4 mA Quiescent Current Disabled DISABLE Low 145 200 Power Supply Rejection Ratio Vs 1V 70 76 dB 1 Plus or no sign indicates current into pin minus indicates current out of pin Rev A Page 5 of 20 AD8029 AD8030 AD8040 ABSOLUTE MAXIMUM RATINGS Table 4 AD8029 AD8030 AD8040 Stress Ratings Parameter Rating Supply Voltage 12 6V Power Dissipation See Figure 6 Common Mode Input Voltage Vs 0 5V Differential Input Voltage 1 8 V Storage Temperature 65 C to 125 C Operating Temperature Range 40 C to 125 C Lead Temperature Range 300 C Soldering 10 sec Junction Temperature 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8029 AD8030 AD8040 package is limited by the associated rise in junction temperature on the die The plastic encapsulating the die locally reaches the junction temperature At approximately 150 C which is the glass transition temperature the plastic changes its properties Even temporarily exceedi
14. 4 Lead SOIC R 14 AD8040ARU 1 40 C to 125 14 Lead TSSOP RU 14 AD8040ARU REEL 2500 40 C to 125 C 14 Lead TSSOP RU 14 AD8040ARU REEL7 1000 40 C to 125 C 14 Lead TSSOP RU 14 ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although WARNING e this product features proprietary ESD protection circuitry permanent damage may occur on devices Rp subjected to high energy electrostatic discharges Therefore proper ESD precautions are der recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE 2003 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www ana 0 0 com S269 DEVICES Rev A Page 20 of 20
15. 8030 dual and AD8040 quad are rail to rail input and output amplifiers fabricated using Analog Devices XFCB process The XFCB process enables the AD8029 AD8030 AD8040 to operate on 2 7 V to 12 V supplies with a 120 MHz bandwidth and a 60 V us slew rate A simplified sche matic of the AD8029 AD8030 AD8040 is shown in Figure 50 INPUT STAGE For input common mode voltages less than a set threshold 1 2 V below Vcc the resistor degenerated PNP differential pair comprising Q toQ carries the entire Iran current allowing the input voltage to go 200 mV below Vs Conversely input common mode voltages exceeding the same threshold cause Iran to be routed away from the PNP differential pair and into the NPN differential pair through transistor Qs Under this condition the input common mode voltage is allowed to rise 200 mV above Vs while still maintaining linear amplifier behavior The transition between these two modes of operation leads to a sudden temporary shift in input stage transconduc tance gm and dc parameters such as the input offset voltage Vos which in turn adversely affect the distortion performance The SPD block shortens the duration of this transition thus improving the distortion performance As shown in Figure 50 the input differential pair is protected by a pair of two series diodes connected in anti parallel which clamp the differential input voltage to approximately 1 5 V OUTPUT STAGE The currents de
16. AD8040 OPEN LOOP GAIN dB NORMALIZED CLOSED LOOP GAIN dB 6 G 1 5 Vo 0 1V p p 20pF 4 10pF R 3 rik 2 s 5pF PE 3 0 _ Q 7 o 4 o 5 6 1 7 1 8 1 1 10 100 1000 FREQUENCY MHz Figure 13 Small Signal Frequency Response for Various 1 10 100 FREQUENCY MHz ex Figure 14 Frequency Response for Various Output Amplitudes 0 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY Hz 03679 0 054 Figure 15 Open Loop Gain and Phase vs Frequency OPEN LOOP PHASE Degrees CLOSED LOOP GAIN dB CLOSED LOOP GAIN dB CLOSED LOOP GAIN dB Rev A Page 8 of 20 2 1 1 0 Vo 0 1V Vs 0 2V Vicm 0V Vicm Vs 0 2V 10 100 FREQUENCY MHz 1000 03679 0 013 Figure 16 Small Signal Frequency Response for Various Input Common Mode Voltages 100 G 1 125 C Vo 0 1V p p 85 C 25 40 10 FREQUENCY MHz Figure 17
17. Active 0 V 1 6 5 mV NPN Active 4 5 V 2 mV Input Offset Voltage Drift Tmax 30 uV C Input Bias Current NPN Active 4 5 V 0 7 1 3 to Tmax 1 PNP Active 0 V 1 7 2 8 to Tmax 2 Input Offset Current 0 1 0 9 Open Loop Gain Vo 4 0 V 65 74 dB INPUT CHARACTERISTICS Input Resistance 6 MO Input Capacitance 2 pF Input Common Mode Voltage Range 5 2 to 45 2 V Common Mode Rejection Ratio Vem 4 5 V to 3 10 80 90 dB DISABLE PIN AD8029 DISABLE Low Voltage Vs 0 8 V DISABLE Low Current 6 5 DISABLE High Voltage Vs 1 2 V DISABLE High Current 0 2 Turn Off Time 5096 of DISABLE to 1096 of Final Vo 150 ns Vn 1V G 1 Turn On Time 50 of DISABLE to lt 10 of Final Vo 85 ns Vn 1V G 1 OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Rising Falling Edge Vn 6 Vto 6V G 1 55 45 ns Output Voltage Swing 1kO Vs 0 22 5 0 22 V 10 Vs 0 05 Vs 0 05 V Short Circuit Current Sinking and Sourcing 170 160 mA Off Isolation AD8029 Vin 0 1 V p p f 1 MHz DISABLE Low 55 dB Capacitive Load Drive 3096 Overshoot 20 pF POWER SUPPLY Operating Range 2 12 V Quiescent Current Amplifier 1 4 1 5 mA Quiescent Current Disabled DISABLE Low 150 200 Power Supply Rejection Ratio Vs 1V 73 80 dB Plus or no sign indicates current into pin minus indicates current out of pin Rev A Page
18. E 0 17 0 0067 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 56 8 Lead Standard Small Outline Package Narrow Body SOIC R 8 Dimensions shown in millimeters and inches 2 00 BSC gt CERE p pin i7 E 0 65 BSC 1 30 BSC 1 00 0 90 110 MAX 0 70 922 008 3 0 46 8 0 36 0 10 eei 030 SEATING T 0 26 PLANE 0 0 10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO 203AB Figure 57 6 Lead Plastic Surface Mount Package SC70 KS 6 Dimensions shown in millimeters gerere 0 65 BSC 1 95 1 30 5 1 15 0 90 pi 45MAX 022 0 08 4 E 8 0 60 0 15 0 38 gt e 0 45 022 sEATING 47 0 30 PLANE 0 COMPLIANT TO JEDEC STANDARDS MO 178BA Figure 58 8 Lead Small Outline Transistor Package SOT23 RJ 8 Dimensions shown in millimeters 1 75 0 0689 0 50 0 0197 45 0 25 0 0098 pump 0 0098 9 0 10 0 0039 d ae 0 51 0 0201 SEATING 0 25 0 0098 v r4 27 0 0500 0 31 0 0122 PLANE 0 17 0 0067 0 40 0 0157 COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MS 012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS
19. INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 59 14 Lead Standard Small Outline Package SOIC R 14 Dimensions shown in millimeters and inches p 05 1 00 aao 0 20 1 1 20 120 34 h 0 75 gt e 1 8 gt 0 60 E 0 30 0 0 45 SEATING PLANE COPLANARITY COMPLIANT TO JEDEC STANDARDS MO 153AB 1 Figure 60 14 Lead Thin Shrink Small Outline Package TSSOP RU 14 Dimensions shown in millimeters Rev A Page 19 of 20 AD8029 AD8030 AD8040 ORDERING GUIDE Model Branding AD8029AR 40 C to 125 C 8 Lead SOIC AD8029AR REEL N 40 C to 125 C 8 Lead SOIC R 8 AD8029AR REEL7 1 000 40 C to 125 C 8 Lead SOIC R 8 AD8029AKS R2 250 40 C to 125 C 6 Lead SC70 KS 6 H6B AD8029AKS REEL 10 000 40 C to 125 C 6 Lead SC70 KS 6 H6B AD8029AKS REEL7 3 000 40 C to 125 6 Lead SC70 KS 6 H6B AD8030AR 1 40 C to 125 C 8 Lead SOIC R 8 AD8030AR REEL 2 500 40 to 125 8 Lead SOIC R 8 AD8030AR REEL7 1 000 40 C to 125 C 8 Lead SOIC R 8 AD8030ARJ R2 250 40 C to 125 C 8 Lead SOT23 8 RJ 8 H7B AD8030ARJ REEL 10 000 40 C to 125 C 8 Lead SOT23 8 RJ 8 H7B AD8030ARJ REEL7 3 000 40 C to 125 C 8 Lead SOT23 8 RJ 8 H7B AD8040AR 1 40 C to 125 C 14 Lead SOIC R 14 AD8040AR REEL 2500 40 C to 125 14 Lead SOIC R 14 AD8040AR REEL7 1000 40 C to 125 1
20. T 1 0 1 5 1 2 0 z 1kQ TIED TO MIDSUPPLY 0 5V DIV 25ns DIV L 9 SU SS TIME Seconds 03679 0 059 03679 A 023 TIME ns Figure 29 Rail to Rail Response G 1 Figure 26 Large Signal Transient Response G 1 1 1kO Vs 32 5V OUTPUT VOLTAGE V OUTPUT VOLTAGE V 1V DIV L 200ns DIV 1V DIV 200ns DIV TIME ns 03679 0 024 TIME ns 03679 0 027 Figure 27 Output Overdrive Recovery Figure 30 Input Overdrive Recovery Rev A Page 10 of 20 AD8029 AD8030 AD8040 Vin 250mV DIV Vout 500mV DIV 0 1 2Vin 0 1 DIV Vout 2Vin 0 1 DI 0 1 0 1 Vout 500mV DIV 20ns DIV 03679 0 062 03679 0 063 Figure 31 Long Term Settling Time Figure 34 0 1 Short Term Settling Time 0 10 z 20 2 PSRR 30 40 g e E a 50 5 60 70 PSRR 80 90 100 10
21. age Vs 1 2 V DISABLE High Current 0 2 Turn Off Time 50 of DISABLE to lt 10 of Final Vo 155 ns Vin 1V G 1 Turn On Time 50 of DISABLE to lt 10 of Final Vo 90 ns Vn 1V G 1 OUTPUT CHARACTERISTICS Overdrive Recovery Time Rising Falling Edge Vin 1V to 6 1 45 50 ns Output Voltage Swing 1 Vs 0 17 Vs 0 17 V 10 kO Vs 0 04 Vs 0 04 V Short Circuit Current Sinking and Sourcing 95 60 mA Off Isolation AD8029 Vin 0 1 V p p f 1 MHz DISABLE Low 55 dB Capacitive Load Drive 3096 Overshoot 15 pF POWER SUPPLY Operating Range 2 7 12 V Quiescent Current Amplifier 1 3 1 5 mA Quiescent Current Disabled DISABLE Low 140 200 Power Supply Rejection Ratio Vs 1V 73 80 dB 1 Plus or no sign indicates current into pin minus indicates current out of pin Rev A Page 4 of 20 SPECIFICATIONS WITH 3 V SUPPLY Table 3 Vs 3 9 Ta 25 G 1 1 to midsupply unless otherwise noted All specifications are per amplifier AD8029 AD8030 AD8040 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vo 0 1 V p p 80 112 MHz G 1 Vo 2 2V p p 13 18 MHz Bandwidth for 0 1 dB Flatness G 2 Vo 0 1 Vp p 6 MHz Slew Rate G 41 Vo 2V Step 55 V us G 1 Vo 2V Step 57 V us Settling Time to 0 1 G 42 Vo 2V Step 110 ns NOISE DISTORTION PERFORMANCE Spurious Free Dynamic Range SFDR fc 1 MHz Vo 2 V
22. e 54 illustrate effective output loading and distortion performance Increasing the resistance of the feedback network can reduce the current consumption but has other implications R1 10uF 40 y Vout 2 0 5 03679 0 052 50 SECOND HARMONIC SOLID LINES THIRD HARMONIC DOTTED LINES Figure 51 Wideband Non inverting Gain Configuration Rr HARMONIC DISTORTION dBc b 7 O Vour DISABLE 255 R1 0 01 10 2 FREQUENCY MHz 8 R1 Figure 53 Gain of 1 Distortion 40 Vs 03679 0 053 Vs 5V 50 SECOND HARMONIC SOLID LINES Figure 52 Wideband Inverting Gain Configuration THIRD HARMONIC DOTTED LINES p gt a 4 8 60 1k Ry 1kQ IM LM OUTPUT LOADING SENSITIVITY Z AL A To achieve maximum performance and low power dissipation 7 ANI the designer needs to consider the loading at the output of 9 I pz 2 F Rp Ry 5kO AD8029 AD8030 AD8040 Table 5 shows the effects of output 90 lt os loading and performance 9 AK 100 lt 2477 ae m F Rr 2 5 When operating at unity gain the effective load at the amplifier S FL output is the resistance Ri being driven by the amplifier For gains other
23. gh speed circuit design The length of the current path is directly proportional to the magnitude of the parasitic inductances and thus the high frequency impedance of the path Fast current changes in an inductive ground return will create unwanted noise and ringing The length of the high frequency bypass capacitor pads and traces is critical A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor Because load currents flow from supplies as well as from ground the load should be placed at the same physical location as the bypass capacitor ground For large values of capacitors which are intended to be effective at lower frequencies the current return path length is less critical Power Supply Bypassing Power supply pins are actually inputs to the op amp Care must be taken to provide the op amp with a clean low noise dc voltage source Power supply bypassing is employed to provide a low imped ance path to ground for noise and undesired signals at all frequencies This cannot be achieved with a single capacitor type but with a variety of capacitors in parallel the bandwidth of power supply bypassing can be greatly extended The bypass capacitors have two functions 1 Provide a low impedance path for noise and undesired signals from the supply pins to ground 2 Provide local stored charge for fast switching conditions and minimize the voltage drop at the supply pins during
24. isabled 0 V to lt 0 8 V 0 V to lt 0 8 V 5 V to 4 2V High Enabled 1 2Vto3V 1 2Vto 5V 3 8Vto 5 V Rev A Page 17 of 20 AD8029 AD8030 AD8040 CIRCUIT CONSIDERATIONS PCB Layout High speed op amps require careful attention to PCB layout to achieve optimum performance Particular care must be exercised to minimize lead lengths of the bypass capacitors Excess lead inductance can influence the frequency response and even cause high frequency oscillations Using a multilayer board with an internal ground plane can help reduce ground noise and enable a more compact layout To achieve the shortest possible trace length at the inverting input the feedback resistor Rr should be located the shortest distance from the output pin to the input pin The return node of the resistor Rc should be situated as close as possible to the return node of the negative supply bypass capacitor On multilayer boards all layers beneath the op amp should be cleared of metal to avoid creating parasitic capacitive elements This is especially true at the summing junction i e the inver ting input IN Extra capacitance at the summing junction can cause increased peaking in the frequency response and lower phase margin Grounding To minimize parasitic inductances and ground loops in high speed densely populated boards a ground plane layer is critical Understanding where the current flows in a circuit is critical in the implementation of hi
25. ng this temperature limit may change the stresses that the package exerts on the die permanently shifting the parametric performance of the AD8029 AD8030 AD8040 Exceeding a junction temperature of 175 C for an extended period can result in changes in silicon devices potentially causing failure The still air thermal properties of the package and ambient temperature T4 and the total power dissipated in the package determine the junction temperature of the die The junction temperature can be calculated as Pp x The power dissipated the package Pp is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs The quiescent power is the voltage between the supply pins Vs times the quiescent current Is Assuming the load Rr is referenced to midsupply the total drive power is Vs 2 x Iovr some of which is dissipated in the package and some in the load Vour x The difference between the total drive power and the load power is the drive power dissipated in the package Pp Quiescent Power Total Drive Power Load Power Vs V Moor m L L RMS output voltages should be considered If R is referenced to Vs as in single supply operation then the total drive power is Vs x Tour If the rms signal levels are indeterminate consider the worst case when Vour Vs 4 for R to midsupply Py
26. nn SECOND HARMONIC SOLID LINE F ili SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE THIRD HARMONIC DASHED LINE 100 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 5 OUTPUT AMPLITUDE V p p 1 0 1 5 2 0 2 5 3 0 3 5 4 0 INPUT COMMON MODE VOLTAGE V 56790 02 Figure 20 Harmonic Distortion vs Output Amplitude Figure 23 Harmonic Distortion vs Input Common Mode Voltage 30 100 Vs 45V 7 Vour 2 0 40 RL 1kQ E 1 A 50 s G 2 1 a 10 z d a ES S 60 G 1 a 5 ibi 2 9 70 o o 2 2 2 i 80 x lt 9 2 2 3 at S gt lt 4 y G 1 100 SECOND HARMONIC SOLID LINE iio THIRD HARMONIC DASHED LINE 1 0 1 7 001 01 1 10 10 100 1k 10k 100k 1M 10M FREQUENCY MHz FREQUENCY Hz 03679 0 069 03679 A 016 Figure 21 Harmonic Distortion vs Frequency and Gain Figure 24 Voltage ghe dient Noise vs Frequeney Rev A Page 9 of 20 AD8029 AD8030 AD8040 OUTPUT VOLTAGE V 75 V 100 100 5 TIME ns 03679 0 025 1 N m OUTPUT VOLTAGE mV OUTPUT VOLTAGE mV a Figure 25 Small Signal Transient Response Figure 28 Small Signal Transient Response with Capacitive Load 2 5 G 1 4V 2 0 Vs 2 5V 1 5 1 0 2V p p 0 5 gt 0 2 E 0 5 mM
27. rived from the PNP and input differential pairs are injected into the current mirrors and thus establishing a common mode signal voltage at the input of the output buffer The output buffer performs three functions l It buffers and applies the desired signal voltage to the output devices and Qu 2 senses the common mode current level in the output devices 3 It regulates the output common mode current by establishing a common mode feedback loop The output devices Qio and Qu work in a common emitter configuration and are Miller compensated by internal capacitors Cur and Cus The output voltage compliance is set by the output devices collector resistance Rc about 25 and by the required load current L For instance a light equivalent load 5 allows the output voltage to swing to within 40 mV of either rail while heavier loads cause this figure to deteriorate as Rc x L Rev A Page 15 of 20 AD8029 AD8030 AD8040 APPLICATIONS WIDEBAND OPERATION Rr For example if using the values shown in Table 5 for a gain of 2 with resistor values of 2 5 the effective load at the output is 1 67 For inverting configurations only the feedback resistor is in parallel with the output load If the load is greater than that specified in the data sheet the amplifier can introduce nonlinearities in its open loop response which increases distortion Figure 53 and Figur
28. sa 1 Changes to Specifications a 3 Changes to Figures 10 12 7 Change to Figure V4 8 Changes to Figures 20 and 21 sss 9 Inserted new Figure e a EHE 11 Change to Figure 40 12 Inserted new Figure 41 estet 12 Added Output Loading Sensitivity section 16 Changes to Table Dinniy s kA E E 17 Changes to Power Supply Bypassing section 18 Changes to Ordering Guide sss 20 Rev A Page 2 of 20 SPECIFICATIONS SPECIFICATIONS WITH 5 V SUPPLY Table 1 5 V Ta 25 G 1 1 to ground unless otherwise noted All specifications are per amplifier AD8029 AD8030 AD8040 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vo 0 1 V p p 80 125 MHz G 41 Vo 2 V p p 14 19 MHz Bandwidth for 0 1 dB Flatness 2 Vo 0 1 V p p 6 MHz Slew Rate 1 Vo 2 V Step 62 V us 1 Vo 2VStep 63 V us Settling Time to 0 196 2 Vo 2V Step 80 ns NOISE DISTORTION PERFORMANCE Spurious Free Dynamic Range SFDR fc 1 MHz Vo 2 V p p 74 dBc fc 5 MHz Vo 2 V p p 56 dBc Input Voltage Noise 100 kHz 16 5 nV JHz Input Current Noise f 100 kHz 1 1 pA VHz Crosstalk AD8030 AD8040 f25MHz Vn 2 V p p 79 dB DC PERFORMANCE Input Offset Voltage PNP
29. the optimal value of capacitor is to empirically try it in your circuit Another factor of higher resistance values is the impact it has on noise performance Higher resistor values generate more noise Each application is unique and therefore a balance must be reached between distortion peaking and noise performance Table 5 outlines the trade offs that different loads have on distortion peaking and noise performance In gains of 1 2 and 10 equivalent loads of 1 2 and 5 are shown With increasing load resistance the distortion and 3 dB bandwidth improve while the noise and peaking degrade slightly NORMALIZED CLOSED LOOP GAIN dB 03679 A 007 FREQUENCY MHz Figure 55 Frequency Response for Various Feedback Load Resistances The AD8029 disable pin allows the amplifier to be shut down for power conservation or multiplexing applications When in the disable mode the amplifier draws only 150 uA of quiescent current The disable pin control voltage is referenced to the negative supply The amplifier enters power down mode any time the disable pin is tied to the most negative supply or within 0 8 V of the negative supply If left open the amplifier will operate normally For switching levels refer to Table 6 Table 6 Disable Pin Control Voltage Disable Pin Supply Voltage Voltage 3V 5V 5V Low D
30. transients This is typically achieved with large electrolytic capacitors Good quality ceramic chip capacitors should be used and always kept as close as possible to the amplifier package A parallel combination of a 0 1 uF ceramic and a 10 uF electrolytic covers a wide range of rejection for unwanted noise The 10 uF capacitor is less critical for high frequency bypassing and in most cases one per supply line is sufficient The values of capacitors are circuit dependant and should be determined by the system s requirements DESIGN TOOLS AND TECHNICAL SUPPORT Analog Devices is committed to the design process by providing technical support and online design tools ADI offers technical support via free evaluation boards sample ICs Spice models interactive evaluation tools application notes phone and email support all available at www analog com Rev A Page 18 of 20 AD8029 AD8030 AD8040 OUTLINE DIMENSIONS 8 75 0 3445 5 00 0 1968 m 0 1 M 4 00 0 1574 AM 5 6 20 0 2440 4 5 80 0 2284 3 80 0 1497 yen 0 25 0 0098 gt je 1 27 0 0500 0 50 0 0196 BSC 175 0 0688 0 25 0 0099 1 35 0 0532 4 00 0 1575 3 80 0 1496 iyi F 1 27 0 0500 8 55 03369 HR 6 20 0 2441 5 80 0 2283 0 10 0 0040 0 51 0 0201 s COPLANARITY SEATING 0 31 0 0122 0 25 0 0098 0 1 27 0 0500 0 10 PLAN
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