intersil X5168 X5169 handbook
Contents
1. PART NUMBER PART NUMBER RESET PART RESET PART Vcc RANGE Vrgp RANGE TEMP RANGE ACTIVE LOW MARKING ACTIVE HIGH MARKING V V C PACKAGE X5168P 4 5A X5168P AL X5169P 4 5A X5169P AL 4 5 5 5 4 5 4 75 0 to 70 8 Ld PDIP X5169PZ 4 5A 8 Ld PDIP X5168Pl 4 5A X5169PI 4 5A 40 to 85 8 Ld PDIP X5169PIZ 4 5A X5169P Z AM 8 Ld PDIP X5168S8 4 5A X5168 AL X5169S8 4 5A X5169 AL 0 to 70 8 Ld SOIC X5168S8Z 4 5A X5168Z AL X5169S8Z 4 5A X5169 Z AL 8 Ld SOIC X5168881 4 5A X5168 AM X5169S8I 4 5A X5169 AM 40 to 85 8 Ld SOIC X5168S8IZ 4 5A X5168 ZAM X5169S8IZ 4 5A X5169 Z AM 8 Ld SOIC X5168V14 4 5A X5169V14 4 5A 0 to 70 14 Ld TSSOP X5168V141 4 5A X5169V141 4 5A 40 to 85 14 Ld TSSOP X5168P X5168P X5169P X5169P 4 5 5 5 4 25 4 5 0 to 70 8 Ld PDIP X5169PZ X5169P Z 8 Ld PDIP X5168PI X5168P X5169PI X5169P 40 to 85 8 Ld PDIP X5169PIZ X5169P ZI 8 Ld PDIP X5168S8 X5168 X5169S8 X5169 0 to 70 8 Ld SOIC X5168S8Z X5168 Z X5169S8Z X5169 Z 8 Ld SOIC X5168S8l X5168 X5169S8l X5169 I 40 to 85 8 Ld SOIC X5168S8IZ X5168 Z X5169S8IZ X5169 Z 8 Ld SOIC X5168V14 X5168V X5169V14 X5169V 0 to 70 14 Ld TSSOP X5168V14I X5169V14I 40 to 85 14 Ld TSSOP X5168P 2 7A X5169P 2 7A 2 7 5 5 2 85 3 0 0 to 70 8 Ld PDIP X5169PZ 2 7A X5169P Z AN 8 Ld PDIP X5168PI 2 7A X5169PI 2 7A 40 to 85 8 Ld PDIP X5169PIZ 2 7A X5169P Z AP 8 Ld PDIP X5168S8 2 7A X5168 AN X516988 2 7A X51692. Input rise time 100 ns te 9 Input fall time 100 ns tes CS deselect time 500 ns two Write cycle time 10 ms 12 intersil FN8130 1 September 16 2005 X5168 X5169 Serial Input Timing lcs cs I ap SCK YY VV VV VVV VYY VVV VV VY VV V sa AAA MSBIN KKK AAA AA AA tsa N XXX SO High Impedance Serial Output Timing 2 7 5 5N SYMBOL PARAMETER MIN MAX UNIT fsck Clock frequency 0 2 MHz tpis Output disable time 250 ns ty Output valid from clock low 200 ns tuo Output hold time 0 ns tro Output rise time 100 ns tgo Output fall time 100 ns Notes 3 This parameter is periodically sampled and not 100 tested 4 twc is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self timed internal nonvolatile write cycle Serial Output Timing NN bau liac SCK TC twL gt lt ipis si ADDR S LSBIN TIS TITTY II h JIII I IIIi i3 interi FN8130 1 intersil September 16 2005 X5168 X5169 Power Up and Power Down Timing Voc 0 Volts RESET X5168 RESET X5169 RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT VTRIP Reset trip point voltage X5168 4 5A X5168 4 5A 4 5 4 63 4 75 V Reset trip point voltage X5168 X5169 4 25 4 38 4 5 Reset trip point voltage X5168 2 7A X5169 2 7A 2 85 2 93 3 0 Reset trip point voltage X5168 2 7 X5169 2 7 2 55 2 63 2 7 Viu Vrt
3. 1 while an internal write cycle to the status register is in progress will not stop this write operation but the operation disables subsequent write attempts to the status register When WP is HIGH all functions including nonvolatile writes to the status register operate normally Setting the WPEN bit in the status register to 0 blocks the WP pin function allowing writes to the status register when WP is HIGH or LOW Setting the WPEN bit to 1 while the WP pin is LOW activates the programmable ROM mode thus requiring a change in the WP pin prior to subsequent status register changes This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the status register Manufacturing can then load configuration data manufacturing time and other parameters into the EEPROM then set the portion of memory to be protected by setting the block lock bits and finally set the OTP mode by setting the WPEN bit Data changes now require a hardware change 20 21 22 23 24 25 26 27 28 29 30 16 Bit Address GEAR Ge E AE EE Data Out s C ASASA ASA A An MSB FIGURE 5 READ EEPROM ARRAY SEQUENCE 7 intersil FN8130 1 September 16 2005 X5168 X5169 Read Sequence When reading from the EEPROM memory array CS is first pulled low to select the device The 8 bit READ instruction is transmitted to the device followed by the 16 bit address After the READ opcode and address ar
4. AN 0 to 70 8 Ld SOIC X5168S8Z 2 7A Note X5168 ZAN X5169S8Z 2 7A X5169 Z AN 8 Ld SOIC Tape and Reel Pb free X5168S8I 2 7A X5169S8I 2 7A 40 to 85 8 Ld SOIC X5168S81Z 2 7A X5168 Z AP X5169S8IZ 2 7A X5169 Z AP 8 Ld SOIC X5168V14 2 7A X5169V14 2 7A 0 to 70 14 Ld TSSOP X5168V141 2 7A X5169VI14 2 7A 40 to 85 14 Ld TSSOP X5168P 2 7 X5169P 2 7 2 7 5 5 2 55 2 7 0 to 70 8 Ld PDIP X5169PZ 2 7 X5169PZF 8 Ld PDIP X5168PI 2 7 X5169PI 2 7 40 to 85 8 Ld PDIP X5169PIZ 2 7 X5169P Z G 8 Ld PDIP X5168S8 2 7 X5168 F X5169S8 2 7 X5169 F 0 to 70 8 Ld SOIC X5168S8Z 2 7 X5168 Z F X5169S8Z 2 7 X5169 Z F 8 Ld SOIC X5168S8I 2 7 X5168 G X5169S8I 2 7 X5169 G 40 to 85 8 Ld SOIC X5168S8I1Z 2 7 X5168ZG X5169S8IZ 2 7 X5169 Z G 8 Ld SOIC X5168V14 2 7 X5169V14 2 7 0 to 70 14 Ld TSSOP X5168V141 2 7 X5169V141 2 7 40 to 85 14 Ld TSSOP NOTE Intersil Pb free plus anneal products employ special Pb free material sets molding compounds die attach materials and 10096 matte tin plate termination finish which are RoHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 Add T1 suffix for tape and reel 2 intersil FN8130 1 SE September 16 2005 X5168 X5169 Pin Configuration 8 LD SOIC PDIP X5168 69 Pin Description 14 LD TSSO
5. Vcc returns and exceeds Vru for 200ms Vcc Threshold Reset Procedure The X5168 X5169 has a standard Ve threshold Vrgip voltage This value will not change over normal operating and storage conditions However in applications where the standard Vom is not exactly right or for higher precision in the Vrpip value the X5168 X5169 threshold may be adjusted Setting the Vrgjp Voltage This procedure sets the Vro to a higher voltage value For example if the current Vru is 4 4V and the new Vru is 4 6V this procedure directly makes the change If the new setting is lower than the current setting then it is necessary to reset the trip point before setting the new value To set the new Vru voltage apply the desired Vtpip threshold to the Vcc pin and tie the CS pin and the WP pin HIGH RESET RESET and SO pins are left unconnected Then apply the programming voltage Vp to both SCK and SI and pulse CS LOW then HIGH Remove Vp and the sequence is complete FIGURE 1 SET Van VOLTAGE Resetting the Vrgjp Voltage This procedure sets the Vro to a native voltage level For example if the current Vrgip is 4 4V and the Vo is reset the new Vru is something less than 1 7V This procedure must be used to set the voltage to a lower value To reset the Vrgip voltage apply a voltage between 2 7 and 5 5V to the Vcc pin Tie the CS pin the WP pin and the SCK pin HIGH RESET RESET and SO pins are left unconnected Then apply th
6. 00 C Recommended Operating Conditions Temperature Range Commercial ra ERU oa 6 eee eer d 0 C to 70 C Industrial 2 222 ak tese e Landa deg 40 C to 85 C Supply Voltage Limits 2 7 OF 2 7A eee eae 2 7V to 5 5V Blank or A 54 4 5V 5 5V CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability DC Electrical Specifications Over the recommended operating conditions unless otherwise specified LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT lcc4 Voc write current active SCK Vcc x 0 1 Vcc x 0 9 2MHz 5 mA SO Open lcc2 Vcc read current active SCK Vcc x 0 1 Vcc x 0 9 2MHz 0 4 mA SO Open Isp Vcc standby current WDT OFF CS Vec Vin Vss OF Vec 1 yA Voc 5 5V lu Input leakage current Vin Vss to Vee 0 1 10 pA lio Output leakage current Vout Vss to Vec 0 1 10 pA Vu Input LOW voltage 0 5 Vec x 0 3 V NOTE 1 Vin Input HIGH voltage Voc x 0 7 Vcc 0 5 V NOTE 1 Vout Output LOW voltage Vec gt 3 3V lo 2 1mA 0 4 V Voi2 Output LOW voltage 2V lt Vec x 3 3
7. AS TAK 5165V 14Z fH pv mg e Data Sheet CPU Supervisor with 16Kbit SP EEPROM These devices combine three popular functions Power on Reset Control Supply Voltage Supervision and Block Lock Protect Serial EEPROM Memory in one package This combination lowers system cost reduces board space requirements and increases reliability Applying power to the device activates the power on reset circuit which holds RESET RESET active for a period of time This allows the power supply and oscillator to stabilize before the processor can execute code The device s low Vcc detection circuitry protects the user s system from low voltage conditions by holding RESET RESET active when Vcc falls below a minimum Vcc trip point RESET RESET remains asserted until Vcc returns to proper operating level and stabilizes Five industry standard Vru thresholds are available however Intersil s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine tune the threshold in applications requiring higher precision September 16 2005 X5168 X5169 Replaces X25268 X25169 FN8130 1 Features Low Vcc Detection and Reset Assertion Five standard reset threshold voltages Re program low Vcc reset threshold voltage using special programming sequence Reset signal valid to Veg 1V Long Battery Life with Low Power Consumption lt 50yuA max standby current watchdog on 1pA max standby c
8. ESET is an active LOW HIGH open drain output which goes active RESET whenever Vcg falls below the minimum Vcg sense level It will remain active until Vcc rises above the minimum Voc sense level for 200ms RESET RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period A falling edge of CS will reset the watchdog timer RESET RESET goes active on power up at about 1V and remains active for 200ms after the power supply stabilizes 3 5 10 12 NC No internal connections 3 i FN8130 1 intersil September 16 2005 X5168 X5169 Principles of Operation Power on Reset Application of power to the X5168 X5169 activates a power on reset circuit This circuit goes active at about 1V and pulls the RESET RESET pin active This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator When Vcc exceeds the device Vru value for 200ms nominal the circuit releases RESET RESET allowing the processor to begin executing code Low Voltage Monitoring During operation the X5168 X5169 monitors the Vcc level and asserts RESET RESET if supply voltage falls below a preset minimum Vrgip The RESET RESET signal prevents the microprocessor from operating in a power fail or brownout condition The RESET RESET signal remains active until the voltage drops below 1V It also remains active until
9. P ES X5168 69 CS Vcc Vcc So RESET RESET ER NC NC RESET RESET NC NC SCK NC Se si WP SCK Vss si PIN SOIC PDIP PIN TSSOP NAME FUNCTION 1 1 CS Chip Select Input CS HIGH deselects the device and the SO output pin is at a high impedance state Unless a nonvolatile write cycle is underway the device will be in the standby power mode CS LOW enables the device placing it in the active power mode Prior to the start of any operation after power up a HIGH to LOW transition on CS is required 2 2 SO Serial Output SO is a push pull serial data output pin A read cycle shifts data out on this pin The falling edge of the serial clock SCK clocks the data out 5 8 SI Serial Input SI is a serial data input pin Input all opcodes byte addresses and memory data on this pin The rising edge of the serial clock SCK latches the input data Send all opcodes Table 1 addresses and data MSB first 6 9 SCK Serial Clock The serial clock controls the serial bus timing for data input and output The rising edge of SCK latches in the opcode address or data bits present on the SI pin The falling edge of SCK changes the data output on the SO pin 3 6 WP Write Protect The WP pin works in conjunction with a nonvolatile WPEN bit to lock the setting of the watchdog timer control and the memory write protect bits 4 7 Vss Ground 8 14 Vec Supply Voltage 7 13 RESET Reset Output RESET R
10. Small Outline Gull Wing Package Type S Pin 1 Index 0 020 0 50 X 49 lt 0 050 Typical Y Kk 0 050 P 8 A009 Y 0 0075 0 19 JL 0 010 0 25 0 016 0 410 0 037 0 TN Typical FOOTPRINT 8 Places NOTE ALL DIMENSIONS IN INCHES IN PARENTHESES IN MILLIMETERS 18 intersil FN8130 1 c September 16 2005 X5168 X5169 Packaging Information 14 Lead Plastic TSSOP Package Type V 025 65 BSC 252 6 4 BSC p 010 25 Gage Plane 0 8 i Seating Plane 019 50 029 75 Detail A 20X Eg 031 80 041 1 05 See Detail a A NOTE ALL DIMENSIONS IN INCHES IN PARENTHESES IN MILLIMETERS All Intersil U S products are manufactured assembled and tested utilizing ISO9000 quality systems v Intersil Corporation s quality certifications can be viewed at www intersil com design quality XICOR Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assu
11. V lg 1mA 0 4 V Vois Output LOW voltage Vec lt 2V lo 0 5mA 0 4 V Vout Output HIGH voltage Vec gt 3 3V lop 1 0mA Vcc 0 8 V Vou2 Output HIGH voltage 2V lt Vec lt 3 3V lop 0 4mA Voc 0 4 V Vous Output HIGH voltage Vec lt 2V lop 0 25mA Vcc 0 2 V Vois Reset output LOW voltage loi 1mA 0 4 V Capacitance T4 25 C f 1MHz Voc 5V SYMBOL TEST CONDITIONS MAX UNIT Cour Output capacitance SO RESET RESET Vout 0V 8 pF NOTE 2 C n NOTE 2 Input capacitance SCK SI CS WP Vin OV 6 pF NOTES 1 Mu min and Vu max are for reference only and are not tested 2 This parameter is periodically sampled and not 100 tested 11 intersil FN8130 1 September 16 2005 X5168 X5169 Equivalent A C Load Circuit at 5V Vcc A C Test Conditions Input pulse levels Vee x 0 1 to Vec x 0 9 SVL 5V Input rise and fall times 10ns 2 06kQ 4 6kQ Input and output timing level Voc x 0 5 Output 9 34 RESET RESET 3 03kQ SE 30pF AC Electrical Specifications Over recommended operating conditions unless otherwise specified 2 7 5 5V SYMBOL PARAMETER MIN MAX UNIT SERIAL INPUT TIMING fsck Clock frequency 0 2 MHz teyc Cycle time 500 ns ti EAD CS lead time 250 ns Lan CS lag time 250 ns twu Clock HIGH time 200 ns twL Clock LOW time 200 ns tsu Data setup time 50 ns tH Data hold time 50 ns Lal
12. e specified to be O s The WRITE operation minimally takes 32 clocks CS must go low and remain low for the duration of the operation If the address counter reaches the end of a page and the clock continues the counter will roll back to the first address of the page and overwrite any data that may have been previously written For the page write operation byte or page write to be completed CS can only be brought HIGH after bit O of the last data byte to be written is clocked in If itis brought HIGH at any other time the write operation will not be completed Figure 4 To write to the status register the WRSR instruction is followed by the data to be written Figure 5 Data bits 0 and 1 must be 0 While the write is in progress following a status register or EEPROM sequence the status register may be read to check the WIP bit During this time the WIP bit will be high Operational Notes The device powers up in the following state The device is in the low power standby state A HIGH to LOW transition on CS is required to enter an active state and receive an instruction SO pin is high impedance The write enable latch is reset The flag bit is reset Reset signal is active for tpyrst Data Protection The following circuitry has been included to prevent inadvertent writes e AWREN instruction must be issued to set the write enable latch CS must come HIGH at the proper clock count in order t
13. e programming voltage Vp to the SI pin ONLY and pulse CS LOW then HIGH Remove Vp and the sequence is complete FIGURE 2 RESET Ven VOLTAGE 4 intersil FN8130 1 September 16 2005 X5168 X5169 Vrnip Programming Execute Reset VTRIP Sequence Set Voc Vec Applied Desired Vrom New Voc Applied Execute Old Voc Applied Error Set Vrnip Sequence Apply 5V to Voc New Vcc Applied Old Vcc Applied Error Execute Reset VTRIP Sequence Decrement Vec Vec Vec SS 10mV RESET pin goes active Error Emax Error 2 Emax Measured Vun Desired Vrom Emax Maximum Desired Error FIGURE 3 V r ip PROGRAMMING SEQUENCE FLOW CHART e Vp 4 7K 4 7K NC i9 cipes e eo RESET 2 NC NC VrRIP Adj mui e o Program o a e e1 o R R V eset Vrgip 10K 10K Test Vrnip e Set VTRIP FIGURE 4 SAMPLE Ve RESET CIRCUIT 5 intersil FN8130 1 September 16 2005 X5168 X5169 SPI Serial Memory The memory portion of the device is a CMOS serial EEPROM array with Intersil s block lock protection The array is internally organized as x 8 The device features a Serial Peripheral Interface SPI and software protocol allowing operation on a simple four wire bus The device utilizes Intersil s proprietary Direct Write cell providing a m
14. e sent the data stored in the memory at the selected address is shifted out on the SO line The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses The address is automatically incremented to the next higher address after each byte of data is shifted out When the highest address is reached the address counter rolls over to address 0000 allowing the read cycle to be continued indefinitely The read operation is terminated by taking CS high Refer to the read EEPROM array sequence Figure 1 To read the status register the CS line is first pulled low to select the device followed by the 8 bit RDSR instruction After the RDSR opcode is sent the contents of the status register are shifted out on the SO line Refer to the read status register sequence Figure 2 Write Sequence Prior to any attempt to write data into the device the Write Enable Latch WEL must first be set by issuing the WREN instruction Figure 3 CS is first taken LOW then the WREN instruction is clocked into the device After all eight bits of the instruction are transmitted CS must then be taken HIGH If the user continues the write operation without taking CS HIGH after issuing the WREN instruction the write operation will be ignored To write data to the EEPROM memory array the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written Any unused address bits ar
15. inimum endurance of 100 000 cycles and a minimum data retention of 100 years The device is designed to interface directly with the synchronous Serial Peripheral Interface SPI of many popular microcontroller families It contains an 8 bit instruction register that is accessed via the SI input with data being clocked in on the rising edge of SCK CS must be LOW during the entire operation All instructions Table 1 addresses and data are transferred MSB first Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW Data is output on the SO line by the falling edge of SCK SCK is static allowing the user to stop the clock and then start it again to resume operations where left off Write Enable Latch The device contains a write enable latch This latch must be SET before a write operation is initiated The WREN instruction will set the latch and the WRDI instruction will reset the latch Figure 3 This latch is automatically reset upon a power up condition and after the completion of a valid write cycle Status Register The RDSR instruction provides access to the status register The status register may be read at any time even during a write cycle The status register is formatted as follows 7 6 5 4 3 2 1 0 WPEN FLB 0 0 BL1 BLO WEL WIP The Write In Progress WIP bit is a volatile read only bit and indicates whether the device is busy with an internal no
16. ion and can be reset by the WRDS instruction The block lock bits BLO and BL 1 set the level of block lock protection These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter one half all or none of the EEPROM array Any portion of the array that is block lock protected can be read but not written It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory STATUS REGISTER BITS ARRAY ADDRESSES PROTECTED BL1 BLO X5168 X5169 0 0 None 0 1 0600 07FF 1 0 0400 07FF 1 1 0000 07FF The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions The flag bit is automatically reset upon power up The nonvolatile WPEN bit is programmed using the WRSR instruction This bit works in conjunction with the WP pin to provide an in circuit programmable ROM function Table 2 SCK Instruction Sl High Impedance SO WP is LOW and WPEN bit programmed HIGH disables all status register write operations In Circuit Programmable ROM Mode This mechanism protects the block lock and watchdog bits from inadvertent corruption In the locked state programmable ROM mode the WP pin is LOW and the nonvolatile bit WPEN is 1 This mode disables nonvolatile writes to the device s status register Setting the WP pin LOW while WPEN is a
17. med at 25 C 25 25 mV Viv Vrrip Program variation after programming 0 75 C programmed at 25 C 25 25 mV Vanip programming parameters are periodically sampled and are not 100 tested 15 intersil FN8130 1 SE September 16 2005 X5168 X5169 Typical Performance Vcc Supply Current vs Temperature lsg 18 16 Watchdog Timer On Vcc 5V 14 12 Watchdog Timer On Vcc DN 10 g Voc E a 8 2 6 4 2 Watchdog Timer Off Vcc 3V 5V 0 LE 40C 25C Temp C Vtrip VS Temperature programmed at 25 C 5 025 5 000 4 975 3 525 3 500 VTniP 3 5V Voltage 3 475 2 525 2 500 2 475 Vrnip 2 5V 0 25 Temperature 85 tpurst VS Temperature 205 200 40 25 90 Degrees C 16 intersil FN8130 1 September 16 2005 X5168 X5169 Packaging Information 8 Lead Plastic Dual In Line Package Type P 0 360 9 14 0 430 10 92 Pin 1 Index 0 300 7 62 Ref Half Shoulder Width On All End Pins Optional 0 145 3 Seating 0 128 3 Plane 0 150 3 CT 0 025 0 64 0 125 3 18 0 015 0 38 A 0 065 1 65 0 045 1 14 0 110 2 I 0 020 0 51 0 090 2 2 0 016 0 41 073 1 84 Max Typ 0 010 0 25 NOTE 1 ALL DIMENSIONS IN INCHES IN PARENTHESES IN MILLIMETERS 2 PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 17 intersil FN8130 1 September 16 2005 X5168 X5169 Packaging Information 8 Lead Plastic
18. med by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 19 intersil FN8130 1 c September 16 2005
19. nvolatile write operation The WIP bit is read using the RDSR instruction When set to a 1 a nonvolatile write operation is in progress When set to a O no write is in progress TABLE 1 INSTRUCTION SET INSTRUCTION NAME INSTRUCTION FORMAT OPERATION WREN 0000 0110 Set the write enable latch enable write operations SFLB 0000 0000 Set flag bit WRDI RFLB 0000 0100 Reset the write enable latch reset flag bit RSDR 0000 0101 Read status register WRSR 0000 0001 Write status register watchdog block lock WPEN amp flag bits READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address Note Instructions are shown MSB in leftmost position Instructions are transferred MSB first TABLE 2 BLOCK PROTECT MATRIX WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER WPEN BLO BL1 WDO WEL WPEN WP PROTECTED BLOCK UNPROTECTED BLOCK WD1 0 X X Protected Protected Protected 1 1 0 Protected Writable Protected 1 0 X Protected Writable Writable 1 X 1 Protected Writable Writable 6 intersil FN8130 1 September 16 2005 X5168 X5169 The Write Enable Latch WEL bit indicates the status of the write enable latch When WEL 1 the latch is set HIGH and when WEL 0 the latch is reset LOW The WEL bit is a volatile read only bit It can be set by the WREN instruct
20. o start a nonvolatile write cycle 8 intersil FN8130 1 September 16 2005 X5168 X5169 cs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK Instruction Sl High Impedance Data Out so Homne CHEN ENSCH MSB FIGURE 6 READ STATUS REGISTER SEQUENCE sx UUUUUUUL High Impedance SO FIGURE 7 WRITE ENABLE LATCH SEQUENCE 20 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16 Bit Address Data Byte 1 si MS 3 K2K TXOK TX SX SX AX3X2X 1X0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 cen gl UU UUL Data Byte 2 Data Byte 3 Data Byte N KZXEXEXEXSEKZXIKOMZKEK SKS X8 A2 X1 KO KEK SKI AAA X0 FIGURE 8 WRITE SEQUENCE n 9 intersil FN8130 1 c September 16 2005 X5168 X5169 CS 9 10 11 12 13 14 15 SCK Instruction Data Byte SI SO High Impedance FIGURE 9 STATUS REGISTER WRITE SEQUENCE Symbol Table WAVEFORM INPUTS OUTPUTS Must be Will be steady steady May change Will change LY from LOW from LOW to HIGH to HIGH May change Will change NM from HIGH from HIGH to LOW to LOW Don t Care Changing XXX Changes State Not Allowed Known N A Center Line Impedance 10 intersil FN8130 1 September 16 2005 X5168 X5169 Absolute Maximum Ratings Temperature Under Dias 65 C to 135 C Storage Temperature 65 C to 150 C Voltage on any Pin with Respect to Vss 1 0V to 7V DC Output Current elles 5mA Lead Temperature Soldering je 3
21. rip hysteresis HIGH to LOW vs LOW to HIGH Vom voltage 20 mV tpursT Power up reset time out 100 200 280 ms tgpp Vcc detect to reset output 500 ns te 9 Vcc fall time 100 us tal Voc rise time 100 us VRVALID Reset valid Vcc 1 V Note 5 This parameter is periodically sampled and not 100 tested Vrgip Set Conditions SI tvpo 14 intersil FN8130 1 September 16 2005 X5168 X5169 Vrgip Reset Conditions Voc SCK Ve tvpo SI Vcc gt Programmed Vru V r p Programming Specifications Vec 1 7 5 5V Temperature 0 C to 70 C PARAMETER DESCRIPTION MIN MAX UNIT pe SCK Vo program voltage setup time 1 Hs pu SCK Mr program voltage hold time 1 US tp Mr program pulse width 1 Hus trsu VrRip level setup time 10 HS trup Ve level hold stable time 10 ms twc Vtrip write cycle time 10 ms trp Vip program cycle recovery period between successive programming cycles 10 ms typo SCK Mr program voltage off time before next cycle 0 ms Vp Programming voltage 15 18 VITRAN V gip programed voltage range 1 7 5 0 Viat Initial Vrgip program voltage accuracy Vcc applied Vzgip programmed at 25 C 0 1 0 4 Via2 Subsequent Vrgip program voltage accuracy Vcc applied V 44 Vrgp programmed at 25 C 25 25 mV Vir Vanip program voltage repeatability successive program operations program
22. urrent watchdog off lt 400yA max active current during read 16Kbits of EEPROM Built in Inadvertent Write Protection Power up power down protection circuitry Protect 0 1 4 1 2 or all of EEPROM array with Block Lock protection n circuit programmable ROM mode 2MHz SPI Interface Modes 0 0 amp 1 1 Minimize EEPROM Programming Time 32 byte page write mode Self timed write cycle 5ms write cycle time typical 2 7V to 5 5V and 4 5V to 5 5V Power Supply Operation Available Packages 14 Ld TSSOP 8 Ld SOIC 8 Ld PDIP Pb Free Plus Anneal Available ROHS Compliant Protect Logic Status Register 4Kbits 4Kbits EEPROM Array Reset Timebase gt Power on and Block Diagram WP SI Data SO Register Command SCK Decode amp m Control CS Logic Voc Low Voltage Reset Generation RESET RESET X5168 RESET X5169 RESET CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Intersil and design is a registered trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2005 All Rights Reserved All other trademarks mentioned are the property of their respective owners X5168 X5169 Ordering Information
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