TEXAS INSTRUMENTS UCC27221/UCC27222 handbook
Contents
1. os Se 25 SE Zu T 8 as Se C r BEE Bc s xxI IZ as wgp B el gs 22 Z V V gt X A o s s e2 35 oe L m 3 EE S ag 52 z AWN Ss 58 rir TE x EP E SE E es ta zB oe 25 zo o5 z2 r HH IS 33 RS z S DE Hp gt sl 15 ag d s 5 SE gt 5 5 LII Be So 4 25 g SS n JE e P ANN x s8 56 8 5 o T S El ANN L 7 Us Latt s rua gt ANN Es E os E TT gs 35 A gt 10K Ct 8200pF ei Figure 17 Typical Application Diagram da TEXAS INSTRUMENTS www ti com 19 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 TYPICAL CHARACTERISTICS BIAS CURRENT UVLO THRESHOLD vs vs TEMPERATURE NO LOAD TEMPERATURE 16 4 2 14 4 1 lt 4 0 10 E 3 2 o o 8 8 Ipp VDD 8 5 V Static I gt 6 a a A FREE 9 Q IvLo VLO 12 V Static 5 V Only Systems 3 35 Ba l 3 4 2 3 3 0 3 2 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TA Temperature C TA2. Exposed Pad Not to Scale NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities refer to Technical Brief PowerPAD Thermally Enhanced Package Texas Instruments Literature No SLMA002 and Application Brief PowerPAD Made Easy Texas Instruments Literature No SLMAO04 Both documents are available at www ti com PowerPAD is a trademark of Texas Instruments da TEXAS INSTRUMENTS www ti com 25 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 MECHANICAL DATA PWP R PDSO G PowerPAD PLASTIC SMALL OUTLINE 20 PINS SHOWN Thermal Pad See Note F 0 15 NOM i T Gage Plane 4 Emmm i Seating Plane 0 1 20 MAX 015 zx 0 10 4 PINS DIM A MAX A MIN 4073225 F 10 98 All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusions The package thermal performance may be e
3. Temperature C Figure 18 Figure 19 VLO LINE REGULATION VLO LOAD REGULATION vs vs TEMPERATURE NO LOAD IVLO 0 mA TEMPERATURE 6 8 6 8 6 7 6 7 gt I 66 7 66 E VDD 20 V 5 IvLO 0 mA o 6 5 9 6 5 EES VDD 12 V z IvLO 100 mA I o 6 4 164 gt 6 3 6 3 6 2 6 2 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TA Temperature C TA Temperature C Figure 20 Figure 21 3 TEXAS INSTRUMENTS 20 www ti com Vpp Dropout Voltage V VLo Short Circuit Current mA UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 TYPICAL CHARACTERISTICS DROPOUT VOLTAGE VDD AT VLO 6 175 V vs OUTPUT CURENT 8 6 8 6 84 qu gt 8 2 8 2 o go 8 0 9 5 7 8 7 8 a 7 6 e 7 6 a gt 74 54 72 7 2 7 0 7 0 0 50 100 IVLO VLO Output Current mA Figure 22 VLO SHORT CIRCUIT CURRENT vs TEMPERATURE 300 4 0 290 45 280 3 0 270 gt lt 250 20 X 240 15 E 230 1 0 220 210 0 5 200 0 0 50 25 0 25 50 75 100 125 TA Temperature C Figure 24 An TEXAS INSTRUMENTS www ti com DROPOUT VOLTAGE VDD AT VLO 6 175 V vs TEMPERATURE lyLo 100 mA 50 25 0 25 50 75 100 125 TA Temperature C Figure 23 INPUT THRESHOLD vs TEMPERATURE VDD 10 V TO 20 V I I Inp
4. 89 x 0 8 9 7 88 PTIVE i s x 88 s 86 86 E E 060 9 0 6 84 DELTA POWER 2 8 5 5 DISSIPATION 2 E 82 82 194 s 04 80 E 80 a 78 0 2 78 0 2 Vin 5V 76 VouT 1 8V 76 DELTA POWER fsw 500 kHz DISSIPATION 74 I 0 0 74 0 0 0 5 10 15 20 0 5 10 15 20 louT Output Current A louT Output Current A Figure 14 Figure 15 i Ai TEXAS INSTRUMENTS e UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 LAYOUT CONSIDERATIONS packaging The UCC27221 2 are only available in Tl s thermally enhanced 14 pin PowerPad package This package offers exceptional thermal impedance with a junction to case rating of 2 C W Shown as the crosshatched region in Figure 16 PowerPad includes an exposed leadframe die pad located on the bottom side of the package Exposed pad dimensions for the PowerPad TSSOP 14 pin package are 69 mils x 56 mils 1 8 mm x 1 4 mm However the exposed pad tolerances can be 41 2 mils 1 05 05 mm due to position and mold flow variation Effectively removing the heat from the PowerPAD package requires a thermal land area shown as the shaded gray region in Figure 16 designed into the PCB directly beneath the package A minimum thermal land area of 5 mm by 3 4 mm is recommended as illustrated in Figure 16 Any tolerance variances of the exposed PowerPad falls well within the thermal land area when the recommended minimum land area is included on the printed circuit bo
5. Sink resistance SW 0V VHI 6V IN 0V G1 05V 03 09 1 5 Source resistance 2 SW 0V VHI 6V IN 65V G1 55V 10 25 45 S Source current 1 2 SW 0V VHI 6V IN 65V G1 30V 3 33 Sink current 1 2 SW 0V VHI 6V IN 0V G1 30V 3 3 3 Rise time C 2 2 nF from G1 to SW Vpp 20 V 17 25 Fall time C 22 nF from G1 to SW Vpp 20 V 137 5 G2 SR output PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Sink resistance 2 PVLO 6 5V IN 65V G1 0 25 V 5 15 30 Source resistance 2 PVLO 65V IN 0V G2 60V 10 20 35 H Source current 1 2 PVLO 6 5V IN 0V G2 325V 3 3 3 Sink current 1 2 PVLO 6 5V IN 65V G2 325V 3 3 3 A Rise time 2 C 2 2 nF from G2 to PGND Vpp 20 V 17 25 Fall time C 22 nF from G2 to PGND Vpp 20 V an al P deadtime delay PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tOFF G2 IN to G2 falling 60 80 100 tOFF G1 IN to G1 falling 55 80 110 Delay Step Resolution 3 5 4 1 4 7 ton G1 minimum 15 ns tON G1 maximum 48 tON G2 minimum 21 tON G2 maximum 38 NOTE 1 2 Ensured by design Not production tested The pullup pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel The peak output current rating is the combined current from the bipolar and MOSFET transistors The output resistance is the RDS ON of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor OFF G1 l It 3H gt UDG 0
6. bias current at VLO ON 5 V applications only VLO 4 5 V VDD no connect 3 6 4 7 5 8 VDD 8 5 V 5 5 7 1 8 5 mA MDB bias current fin 500 kHz No load on G1 G2 55 10 20 input command IN PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High level input voltage 10 V lt VDD lt 20 V 3 3 3 6 3 9 Low level input voltage 10 V lt VDD lt 20V 2 2 2 5 2 8 X Input bias current Vpp 15V 1 uA input SWS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High level input threshold voltage Ls ie ON G2 maximum 44 on ze fin 500 kHz tON G2 Minimum 0 7 1 0 13 d Low level input threshold voltage G2s 0 0 V fin 500 kHz ton G1 minimum 100 300 500 mV Input bias current SWS 0 0 V 0 9 1 2 1 5 mA input G2S PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High level input voltage Lie ON G2maximum 4 on 26 V Low level input voltage Lom us TON G2 minimum 0 7 1 0 1 3 Input bias current G28 0V 370 470 570 uA NOTE 1 Ensured by design Not production tested 35 TEXAS INSTRUMENTS UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 ELECTRICAL CHARACTERISTICS VDD 12 V 1 uF capacitor from VDD to GND 1 uF capacitor from VHI to SW 0 1 uF and 2 2 uF capacitor from PVLO to PGND PVLO tied to VLO TA 40 C to 105 C for the UCC2722x TA Ty unless otherwise noted G1 main output PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
7. for powering the gate drives This system provides the 6 5 V gate drive to both MOSFETs while the power stage operates off the 3 3 V or 5 V bus 3 3 V or 5V Figure 5 System Application 3 3 V or 5 V Power Input with 12 V Available for Gate Drive Note that the series resistor R1 may be needed to slowdown the turn on of the main forward switch to limit the dV dt which can inadvertently turn on the synchronous rectifier switch The dV dt considerations and the selection of R1 are discussed in the previous section da TEXAS INSTRUMENTS 10 www ti com UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION systems with 5 V input only The circuit pictured in Figure 6 starts up from a 5 V input bus and provides a 6 5 V gate drive to the power MOSFETs This circuit uses a charge pump consisting of Dz D4 and Cs to effectively double the input voltage and apply this to the input of the linear regulator The regulator then regulates the doubled input voltage to the 6 5 V nominal for VLO D3 5V O DN Vout PWM o Cout Input GND O O GND Figure 6 System Application 5 V Only Power Input with 6 5 V Gate Drive Using Charge Pump Circuit da TEXAS INSTRUMENTS www ti com 11 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION selecting Do D3 and D4 Selection of suitable diodes is based upon the conducted peak and average currents D2 simply provi
8. in Figure 4 the minimum capacitance required to maintain a 3 peak to peak ripple voltage can be calculated to be 172 nF so a 180 nF or a 220 nF capacitor could be used The maximum peak to peak C1 ripple must be kept below 0 4 V for proper operation da TEXAS INSTRUMENTS 8 www ti com UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION selection of MOSFETs The peak current rating of a driver imposes a limit on the maximum gate charge of the external power MOSFET driven by it The limit is based on the amount of time needed to deliver or remove the required charge to achieve the desired switching speed during turn on and turn off of the external transistor Hence there are the families of gate driver circuits with different current ratings To demonstrate this assume a constant time interval for the switching transition and a fixed gate drive amplitude A larger MOSFET with more gate charge will require higher current capability from the driver to turn on or turn off the device in the same amount of time Accordingly there is a practical upper limit on gate charge which can be driven by the UCC27222 family of drivers Considering the current capability of the TrueDrive output stage and the available dynamic range delay adjust range of the Predictive Gate Drive circuitry this limit is approximately 120 nC of gate charge Some higher current applications require several MOSFETS to be connecte
9. switching frequency k is the percent ripple on C3 and Vrpo is the forward drop of D3 selection of bypass capacitor C4 The bypass capacitor C4 needs to be sized to take the peak current from the charge pump diode D4 The capacitor is sized based on allowable ripple voltage lagg X 1 D Foy X k x 2 x VIN Veps Vepa Cmn 8 where Vep3 and Vfp4 are the forward voltages of D3 and D4 and k is the percent ripple allowed on C4 da TEXAS INSTRUMENTS www ti com UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION synchronous rectification and predictive delay In a normal buck converter when the main switch turns off current is flowing to the load in the inductor This current cannot be stopped immediately without using infinite voltage For the current path to flow and maintain voltage levels at a safe level a rectifier or catch device is used This device can be either a conventional diode or it can be a controlled active device if a control signal is available to drive it The UCC27222 provides a signal to drive an N channel MOSFET as a rectifier This control signal is carefully coordinated with the drive signal for the main switch so that there is minimum delay from the time that the rectifier MOSFET turns off and the main switch turns on and minimum delay from when the main switch turns off and the rectifier MOSFET turns on This scheme Predictive Gate Drive delay uses infor
10. zEIguCcc2721fNg83 d TEXAS INSTRUMENTS UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 HIGH EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER FEATURES APPLICATIONS e Maximizes Efficiency by Minimizing Non Isolated Single or Multi phased Body Diode Conduction and Reverse DC to DC Converters for Processor Power Recovery Losses General Computer Telecom and Datacom Transparent Synchronous Buck Gate Drive Applications Operation From the Single Ended PWM Input DESCRIPTION Signal 12 V or 5 V Input Operation The UCC27221 and UCC27222 are high speed 3 3 V Input Operation With Availability of synchronous buck drivers for today s 12 V Bus Bias high efficiency lower output voltage designs Using Predictive Gate Drive PGD control e 5 i E On Board b s Gale Drive Regulator technology these drivers reduce diode e 3 3 A TrueDrive Gate Drives for High conduction and reverse recovery losses in the Current Delivery at MOSFET Miller synchronous rectifier MOSFET s The Thresholds UCC27221 has an inverted PWM input while the Automatically Adjusts for Changing UCC27222 has a non inverting PWM input Operating Conditions Predictive Gate Drive technology uses control Thermally Enhanced 14 Pin PowerPAD loops which are stabilized internally and are HTSSOP Package Minimizes Board Area and therefore transparent to the user These loops use Junction Temperature Rise no external components so
11. 03 APPLICATION INFORMATION selection of bypass capacitor C1 Bypass capacitors should be selected based upon allowable ripple voltage usually expressed as a percent of the regulated power supply rail to be bypassed In all of the UCC27222 application circuits shown herein C1 provides the bypass for the main high side gate driver Every time Q1 is switched on a packet of charge is removed from C1 to charge Q1 s gate to approximately 6 0 V The charge delivered to the gate of Q1 can be found in the manufacturer s datasheet curves An example of a gate charge curve is shown in Figure 4 GATE TO SOURCE VOLTAGE vs TOTAL GATE CHARGE 8 gt 6 I o S 9 4 o g Z 2 i 31nC E gt 0 0 10 20 30 40 Q6 Total Gate Charge nC Figure 4 As shown in Figure 4 31 nC of gate charge is required in order for Q1 s gate to be charged to 6 0 V relative to its source The minimum bypass capacitor value can be found using the following calculation Qc k x VHI Vey Cl vin 1 where k is the percent ripple on C1 Q is the total gate charge required to drive the gate of Q1 from zero to the final value of VHI VSW In this example gate charge curve the value of the quantity VHI VSW is taken to be 6 0 V This value represents the nominal VLO regulator output voltage minus the forward voltage drop of the external Schottky diode D1 For the MOSFET with the gate charge described
12. 1042 Figure 1 Predictive Gate Drive Timing Diagram da TEXAS INSTRUMENTS www ti com UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 TERMINAL FUNCTIONS TERMINAL lo DESCRIPTION NAME NO AGND 6 Analog ground for all internal logic circuitry AGND and PGND should be tied to the PCB ground plane with vias G1 13 O High side gate driver output that swings between SW and VHI G2 9 O Low side gate driver output that swings between PGND and PVLO G2S 10 I Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate deadtime IN 7 I Digital input command pin A logic high forces on the main switch and forces off the synchronous rectifier PGND 8 _ Ground return for the G2 driver Connect PGND to PCB ground plane with several vias PVLO 5 l PVLO supplies the G2 driver Connect PVLO to VLO and bypass on the PCB SW 12 G1 driver return connection Sws 11 Used by the predictive controller to sense SR body diode conduction Connect to SR MOSFET drain close to the MOSFET package VDD 3 I Input to the internal VLO regulator Nominal VDD range is from 8 5 V to 20 V Bypass with at least 0 1 uF of capacitance Floating G1 driver supply pin VHI is fed by an external Schottky diode during the SR MOSFET on time VHI 14 l Bypass VHI to SW with an external capacitor VLO 4 o Output of the VLO regulator and supply input for the
13. 221 3 25 V IN 3 25 V UCC37222 toFF G2 toN G1 toN G2 l La gt al EM G1 G2 90 f 10 Figure 2 Predictive Gate Drive Timing Diagram da TEXAS INSTRUMENTS 6 www ti com UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION A typical application circuit for systems with 8 5 V to 20 V input is shown in Figure 3 VIN Figure 3 System Application 8 5 V to 20 V Input selection of VHI series resistor R1 dV dt Considerations The series resistor R1 may be needed to slowdown the turn on of the main forward switch to limit the dV dt which can inadvertently turn on the synchronous rectifier switch In nominal 12 V input designs a R1 value of 4 Q to 10 Q can be used depending on the type of MOSFET used and the high side low side MOSFET ratio In 5 V or lower input applications however R1 is not needed When the drain source voltage of a MOSFET quickly rises inadvertent dV dt induced turn on of the device is possible This can especially be a problem for input voltages of 12 V or greater As Q1 rapidly turns on the drain to source voltage of Q2 rises sharply resulting in a dV dt voltage spike appearing on the gate signal of Q2 If the dV dt induced voltage spike were to exceed the given threshold voltage the MOSFET may briefly turn on when it should otherwise be commanded off Obviously this undesired event would have a negative impa
14. EVISED JULY 2003 PWP PACKAGE TOP VIEW N C N C VDD VLO PVLO AGND IN N C No internal connection AVAILABLE OPTIONS PACKAGED DEVICES PowerPAD HTSSOP 14 PWP TThe PWP package is available taped and reeled Add R suffix to device type e g UCC27221PWPR to order quantities of 2 000 devices per reel and 90 units per tube absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage range VDD 0 3 to 20 V Input voltage VA 2 d NEE E EEN Ret RR ERR RIVE RSEN RI RERRSNG ee eR RE s kaqa EE Supply current Ipp including gate drive current sacos at R Eege EE e Pads 100 mA Sink current peak pulsed G1 G2 Source current peak pulsed G1 G2 nent hen 4 0A Analog inp t IN sisse err aa 3 0 V to Vpp 0 3 V not to exceed 15 V Power Dissipation at TA 25 C PWP package sssssss II Operating junction temperature range TJ 06 I 55 C to 115 C Storage temperature range Tei osse xd erga dace ns d EA Ee 65 C to 150 C Lead temperature soldering 1 6 mm 1 16 inch from case for 10 seconds 300 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any oth
15. ION DRIVE PACKAGE TPS2830 1 Fast synchronous buck MOSFET drivers with dead time control 2 4A PowerPAD HTSSOP 14 SOIC 14 TPS2832 3 Fast synchronous buck MOSFET drivers with dead time control 24A SOIC 8 TPS2834 5 Synchronous buck MOSFET drivers with dead time control t2 4A PowerPAD HTSSOP 14 SOIC 14 TPS2836 7 Synchronous buck MOSFET drivers with dead time control 24A SOIC 8 TPS2838 9 Synchronous buck MOSFET drivers with drive regulator t4A PowerPAD HTSSOP 16 TPS2848 9 Synchronous buck MOSFET drivers with drive regulator t4A PowerPAD HTSSOP 14 TPS40000 1 2 3 Low input voltage mode synchronous buck controller with predictive t1A PowerPAD MSOP 10 gate drive REFERENCES 1 Power Supply Design Seminar SEM 1400 Topic 2 Design and Application Guide for High Speed MOSFET Gate Drive Circuits by Laszlo Balogh Texas Instruments Literature Number SLUP169 2 Power Supply Design Seminar SEM 1400 Topic 7 Implication of Synchronous Rectifiers in Isolated Single Ended Forward Converters by Christopher Bridge Texas Instruments Literature Number SLUP175 3 12Vto 1 8 V 20 A High Efficiency Synchronous Buck Converter Using UCC27222 With Predictive Gate Drive Technology TI Literature Number SLUU140 24 da TEXAS INSTRUMENTS www ti com UCC27221 1 7 7 EPHANICAL DATA UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 PWP R PDSO G14 PowerPAD PLASTIC SMALL OUTLINE Top View
16. RISTICS G1 RISE AND FALL TIMES G2 RISE AND FALL TIMES vs vs TEMPERATURE 2 2 nF TEMPERATURE 2 2 nF 30 30 25 25 20 20 Fall Time o o E E I I e15 e 15 A Rise Time o Fall Time S 10 10 5 5 0 0 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TA Temperature C TA Temperature C Figure 30 Figure 31 G1 SINK RESISTANCE G1 SOURCE RESISTANCE vs vs TEMPERATURE Rps on TEMPERATURE 1 5 40 1 4 35 1 3 30 1 2 G a 1 14 PES S S o 1 0 3 20 5 2 O 0 9 5 15 0 8 10 0 7 0 6 0 5 0 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TA Temperature C TA Temperature G Figure 32 Figure 33 3 TEXAS INSTRUMENTS www ti com 23 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 TYPICAL CHARACTERISTICS G2 SINK RESISTANCE G2 SOURCE RESISTANCE vs vs TEMPERATURE Rps on TEMPERATURE 40 40 35 35 30 30 G 1 25 S 25 u x tt 20 z 2 g 29 3 x 2 N 15 O 15 O 10 10 5 5 0 0 50 25 0 2 50 75 100 125 SB em O 25 5 73 100 125 TA Temperature C TA Ambient Temperature C Figure 34 Figure 35 RELATED PRODUCTS PART GATE NUMBER DESCRIPT
17. ard In addition a 2 by 3 array of 13 mil thermal vias is required within the exposed PowerPad area as shown in Figure 16 If additional heat sinking capability is required larger 25 mil vias can be added to the thermal land area i 3 4mm i Required Vias on PowerPad Area I I 0 1339 I 2x3 Array 0 65mm 0 0256 I 0 33mm 13 mil dia Vias CH EE Red 5 0mm owerPa E 1 8mm 0 069 9 1958 pue ness a ETA I Jl 0 3mm pl On 0 0118 0 0413 Exposed PowerPad 1 4mm 0 056 Optional Vias on Thermal Land Area 0 635mm 25 mil dia Vias Figure 16 TSSOP 14PWP Package Outline and Minimum PowerPAD PCB Thermal Land da TEXAS INSTRUMENTS www ti com UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 REFERENCE DESIGN AND EVALUATION MODULE A reference design is discussed in 12 V to 1 8 V 20 A High Efficiency Synchronous Buck Converter Using the UCC27222 with Predictive Gate Drive TI Literature Number SLUU140 and accompanying evaluation module EVM SLUP192 The design highlights UCC27222 and its Predictive Gate Drive synchronous buck operation using a simple single ended PWM controller The schematic is shown in Figure 17 N 3 CES z 51 C29 bad C28
18. ct on overall efficiency Minimizing the dV dt effect on Q2 can be accomplished by proper MOSFET selection and careful layout techniques The details of how to select a MOSFET to minimize dV dt susceptibility are outlined in SEM 1400 Topic 2 Appendix A Section A5 Secondly the switch node connecting Q1 Q2 and L1 should be laid out as tight as possible minimizing any parasitic inductance which might worsen the dV dt problem If the dV dt induced voltage spike is still present on the gate Q2 a 4W to 10W value of R1 is recommended to minimize the possibility of inadvertently turning on Q2 The addition of R1 slows the turn on of Q1 limiting the dV dt rate appearing on the drain to source of Q2 Slowing down the turn on of Q1 will result in slightly higher switching loss for that device only but the efficiency gained by preventing dV dt turn on of Q2 will far outweigh the negligible effect of adding R1 When Q2 is optimally selected for dV dt robustness and careful attention is paid to the PCB layout of the switch node R1 may not be needed at all and can therefore be replaced with a 0 O jumper to maintain high efficiency The goal of the designer should not be to completely eliminate the dV dt turn on spike but to assure that the maximum amplitude is less than the MOSFET gate to source turn on threshold voltage under all operating conditions da TEXAS INSTRUMENTS www ti com l UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 20
19. d parallel and driven by the same gate drive signal If their combined gate charge exceeds 120 nC the rise and fall times of the gate drive signals will extend and limit the delay adjust range of the PGD circuit in the UCC27222 This may limit the benefits of the PGD technology under certain operating conditions Note that there are additional considerations in the gate drive circuit design which influence the maximum gate charge of the external MOSFETs The most significant of these is the operating frequency which together with the amount of gate charge will define the power dissipation in the driver The allowable power dissipation is a function of the maximum junction and operating temperatures thermal and reliability considerations selection of bypass capacitor C2 C2 supplies the peak current required to turn on the Q2 synchronous rectifier MOSFET as well as the peak current to charge the C1 capacitor through the bootstrap diode Since the synchronous MOSFET is turned on with O V across its drain to source there is no Miller or gate to drain charge Therefore the synchronous MOSFET gate can be modeled as a simple linear capacitance The value of this capacitance can be found from the datasheet s gate charge curve Referring to Figure 5 the slope of the curve past the Miller plateau indicates the equivalent gate capacitance Because the Y axis is described in volts the capacitance is actually the inverse of the slope of the curve For exampl
20. des a path to charge C2 at converter power up Virtually any one of the common BAT54 series of Schottky diodes can be used To select D3 and D4 the peak currents of these two diodes need to be taken into account First the average current flowing in both D3 and D4 is the same as the regulator current described in equation 3 The peak currents in D3 and D4 are described as _ REG D3PK 1 D 5 IREG D4PK D 6 For most UCC27222 applications the duty cycle is much less than 5096 and the peak current in D3 is quite reasonable However the peak current in D4 is quite high This high peak current requires using a diode with a higher current rating for D4 To maintain a reasonable charge pump efficiency BAT54 type diodes can be used for applications where the peak currents are below approximately 40 mA For applications where the peak current is greater than 40 mA a 350 mA or 500 mA diode should be used A typical 350 mA diode is SD103CW SOD 123 package manufactured by Diodes Inc A typical 500 mA diode is the ZHCS500 SOT 23 package available from Zetex Inc selection of the flying capacitor C3 The flying capacitor is subjected to large peak currents and to keep the peak to peak ripple voltage low this capacitor has to be larger than C1 and C2 Selection of C3 should be done based on allowable peak to peak ripple on C3 IREG Fow X k x VIN Veps C3min 7 where Ingq is the regulator output current Fsw is the
21. e the curve in Figure 4 has a slope of approximately 2 V 12 nC over the gate charge range of 10 nC to 40 nC The equivalent capacitance is 12 nC 2 V 6 nF With the equivalent capacitance the minimum bypass capacitor value can be calculated as C2min cn 2 where e CeEq is the equivalent gate capacitance kisthe voltage ripple on C2 expressed as a percentage For a peak to peak ripple of 396 the minimum C2 capacitor value is calculated to be 200 nF A 220 nF capacitor would be used in this case da TEXAS INSTRUMENTS www ti com 3 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION regulator current and power dissipation The regulator current can be calculated from the dc or average current required by the two gate drivers This current can be expressed as neg Faw Cao x VLO Q 3 Assuming all the power dissipation is internal to the device and the internal bias current is negligible the power dissipated by the device is Pos Few X Cea X VLO Qg x VDD 4 For a 500 kHz design using MOSFETS with the gate charge characteristics shown in Figure 4 for both Q1 and Q2 the average regulator current would be 35 mA and when operated from a 12 V input rail the resulting power dissipation is calculated to be 420 mW systems using 3 3 V or 5 V power input and 12 V gate drive Figure 5 shows a schematic for systems where the power bus input is 5 V and 12 V is available
22. er conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability t AI voltages are with respect to AGND and PGND Currents are positive into negative out of the specified terminal da TEXAS INSTRUMENTS 2 www ti com UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 ELECTRICAL CHARACTERISTICS VDD 12 V 1 uF capacitor from VDD to GND 1 uF capacitor from VHI to SW 0 1 uF and 2 2 uF capacitor from PVLO to PGND PVLO tied to VLO TA 40 C to 105 C for the UCC2722x TA Ty unless otherwise noted VLO regulator www ti com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vpp 12 V IVLO 0 mA 6 2 6 5 6 8 Regulator output voltage Vpp 20 V IVLO 0 mA 6 2 6 5 6 8 V VDD 8 5 V IVLO 100 mA 6 1 6 5 6 9 Line Regulation Vpp 12V to 20 V 2 10 Load Regulation lyLO 0 mA to 100 mA 15 40 ny Short circuit current 1 VDD 8 5 V 220 mA Dropout voltage VDD at 5 VLO drop VLO 6 175 V IVLO 100 mA 7 1 7 8 8 5 V undervoltage lockout PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Start threshold voltage Measured at VLO 330 382 440 Minimum operating voltage after start 345 370 4 25 V Hysteresis 007 0 12 0 20 bias currents PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vi o
23. h 2V div Adaptive Drive Predictive Drive 100 ns div 100 ns div Figure 9 Adaptive vs Predictive Switching Waveforms da TEXAS INSTRUMENTS www ti com 15 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION Complementary Gate Drive Waveforms 2V div VDS of SR MOSFET Switch 2 V div Adaptive Drive Predictive Drive 20 ns div 20 ns div Figure 10 Close Up Turn Off of Synchronous Rectifier Switch to Turn On of Main Switch Complementary Gate Drive Waveforms 2 V div VDS of SR MOSFET Switch 2 V div Adaptive Drive Predictive Drive 20 ns div 20 ns div Figure 11 Close Up Turn Off of Main Switch to Turn On of Synchronous Rectifier Switch efficiency comparison Figures 12 through 15 show a series of efficiency measurements taken at two output voltages 0 9 V and 1 8 V and two switching frequencies 250 kHz and 500 kHz for both predictive and adaptive delay techniques The efficiency gain using the predictive technique is 1 for a Vour level of 1 8 V and at a switching frequency of 250 kHz Figure 12 Figures 13 and 14 show the efficiency gain approximately doubles when Vour is lowered by a factor of two to 0 9 V or when the switching frequency is doubled to 500 kHz With both doubled frequency and one half of the output voltage the efficiency gain of predictive technology i
24. he disadvantages include the body diode conduction time intervals caused by delays in the cross coupling loops and the inability to compensate for the delay to charge the MOSFET gates to the threshold levels Additionally it is difficult to determine whether the synchronous MOSFET channel is off by solely monitoring the SR MOSFET gate voltage Some devices actually add a programmable delay between the turn off of the synchronous rectifier and the turn on of the main MOSFET via an external capacitor This added delay directly affects the power stage efficiency through additional body diode conduction losses Since these losses are centralized in the synchronous MOSFET the stress and temperature rise in this component becomes a major design headache The third generation predictive control technique is different from the adaptive technique in that it uses information from the previous switching cycle to set the deadtime for the current cycle The adaptive technique on the other hand uses the current state information to set the delay times The inherent feedback loop propagation delays cause body diode conduction da TEXAS INSTRUMENTS www ti com UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION adaptive vs predictive waveforms Figures 9 through 11 illustrate the adaptive left vs predictive right switching waveforms Key comparison regions are denoted with A B C D and E for the adapt
25. ications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitation
26. ive control waveforms and A B C D and E for the predictive control waveforms Figures 10 and 11 are close ups of each transition edge At A the propagation delay from sensing the synchronous rectifier gate going low to the high side gate going high results in approximately 60 ns of body diode conduction shown at B With the predictive drive as soon as the body diode conduction of the SR MOSFET B is sensed the high side turn on delay is adjusted to minimize the body diode conduction time B At A the high side gate to source voltage is increasing while the synchronous rectifier gate to source voltage is decreasing A natural result of the precise timing of the high side MOSFET turn on is shown at C and C The overshoot and ringing for the predictive drive C has much smaller amplitude than the adaptive drive C due a reduction in reverse recovery in the SR MOSFET body diode This reduction in reverse recovery is only possible with the extremely precise gate timing used in the predictive drive technique At D the propagation delay from the synchronous rectifier drain to source voltage falling to the gate to source voltage rising causes the body diode of the SR MOSFET to conduct for approximately 60 ns E When the predictive drive is enabled D the inherent delay is eliminated and virtually no body diode conduction is shown at E Complementary Gate Drive Waveforms 2V div VDS of SR MOSFET Switc
27. logic and control circuitry Connect VLO to PVLO and bypass on the PCB SIMPLIFIED BLOCK DIAGRAM PREDICTIVE DELAY CONTROLLER UDG 01030 da TEXAS INSTRUMENTS www ti com 2 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION predictive gate drive technique The Predictive Gate Drive technology utilizes a digital feedback system to detect body diode conduction and then adjusts the deadtime delays to minimize it This system virtually eliminates the body diode conduction time intervals for the synchronous MOSFET while adjusting for different MOSFETs characteristics propagation and load dependent delays Maximum power stage efficiency is the end result Two internal feedback loops in the predictive delay controller continuously adjusts the turn on delays for the two MOSFET gate drives G1 and G2 As shown in Figure 2 ton G1 and toN G2 are varied to provide minimum body diode conduction in the synchronous rectifier MOSFET Qo The turn off delay for both G1 and G2 torE a1 and torr co are fixed by propagation delays internal to the device The predictive delay controller is implemented using a digital control technique and the time delays are therefore discrete The turn on delays ton Gi and ton G2 are changed by a single step typically 3 ns every switching cycle The minimum and maximum turn on delays for G1 and G2 are specified in the electrical characteristics table UCC27
28. mation from the current switching cycle to adjust the delays that are to be used in the next cycle Figure 7 shows the switch node voltage waveform for a synchronously rectified buck converter Illustrated are the relative effects of a fixed delay drive scheme constant pre set delays for the turnoff to turn on intervals an adaptive delay drive scheme variable delays based upon voltages sensed on the current switching cycle and the predictive delay drive scheme Note that the longer the time spent in body diode conduction during the rectifier conduction period the lower the efficiency Also not described in Figure 7 is the fact that the predictive delay circuit can prevent the body diode from becoming forward biased at all while at the same time avoiding cross conduction or shoot through This results in a significant power savings when the main MOSFET turns on and minimizes reverse recovery loss in the body diode of the rectifier MOSFET The power dissipation on the main forward MOSFET is reduced as well although that savings is not as significant as the savings in the rectifier MOSFET During reverse recovery the body diode is still forward biased thus the reverse recovery current goes through the forward MOSFET while the drain source voltage is still high causing additional switching losses Without PGD during this switching transition Vds Vin and Ids lload Irr in the main MOSFET With PGD however Vds Vin and lds lload The red
29. nhanced by attaching an external heat sink to the thermal pad This pad is electrically and thermally connected to the backside of the die Falls within JEDEC MO 153 The PowerPAD is not directly connected to any leads of the package However it is electrically and thermally connected to the substrate which is the ground of the device The exposed pad dimension is 1 4 mm x 1 8 mm However the tolerances can be 1 05 0 05 mm 41 2 mils due to position and mold flow variation For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instrument s Literature No SLMA002 and Application Brief PowerPad Made Easy Texas Instruments Literature No SLMA004 Both documents are available at www ti com 26 da TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subjectto TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specif
30. no additional design is needed to take advantage of the higher FUNCTIONAL APPLICATION DIAGRAM efficiency of these drivers VIN This closed loop feedback system detects body diode conduction and adjusts deadtime delays to minimize the conduction time interval This virtually eliminates body diode conduction while adjusting for temperature load dependent PWM delays and for different MOSFETs Precise gate timing at the nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET body diode reducing reverse recovery VOUT losses seen in the main high side MOSFET The lower junction temperature in the low side MOSFET increases product reliability Since the power dissipation is minimized a higher switching frequency can also be used allowing for smaller component sizes O The UCC27221 and UCC27222 are offered in the GNDIN GNDouT thermally enhanced 14 pin PowerPAD package Note 12 V input system shown For 5 V input only systems see Figure 6 with 2 C W Ojc Predictive Gate Drive and PowerPAD are trademarks of Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date Copyright O 2002 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include t testing of all parameters EXAS INSTRUMENTS www ti com l UCC27221 UCC27222 SLUS486B AUGUST 2001 R
31. s and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2003 Texas Instruments Incorporated
32. s about 496 over the adaptive technology Figure 15 Therefore as the switching frequency increases and output voltages are lowered the efficiency gains are higher This results in lower operational temperatures for increased reliability as well as smaller size designs for increased frequencies da TEXAS INSTRUMENTS 16 www ti com APPLICATION INFORMATION UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 www ti com EFFICIENCY EFFICIENCY vs vs OUTPUT CURRENT OUTPUT CURRENT 96 0 5 96 0 5 di VIN 25V PREDICTIVE 94 VouT 0 9 V b fsw 250 kHz 04 PREDICTIVE 0 4 90 90 E APTIVE S i 03 amp o 88 i a 2 E 0 3 5 2 gt 86 ADAPTIVE 8 9 a 2 S 9 84 5 7 02 3 0 25 o q kz 82 ao o 82 D 80 DELTA POWER S i DISSIPATION ES S i 49 40 12 78 VIN 5V 78 DELTA POWER E 76 VouT 18V y 76 DISSIPATION fsw 250 kHz 74 0 0 74 0 0 0 5 10 15 20 0 5 10 15 20 louT Output Current A louT Output Current A Figure 12 Figure 13 EFFICIENCY EFFICIENCY vs vs OUTPUT CURRENT OUTPUT CURRENT 96 1 2 96 1 2 VIN 5 V 94 94 vour 0 9 V e PREDICTIVE 10 go fSW 500 kHz 1 0 90 i 90 PREDICTIVE d e
33. uction in current accounts for additional power savings in the main MOSFET lc s IL Fixed Delay Adaptive Del Predictive De UDG 02175 Figure 7 Switch Node Waveforms for Synchronous Buck Converter da TEXAS INSTRUMENTS www ti com 13 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 APPLICATION INFORMATION comparison between predictive and adaptive gate drive techniques The first synchronous rectifier controllers had a fixed turn on delay between the two gate drivers The advantage of this well known technique is its simplicity The drawbacks include the need to make the delay times long enough to cover the entire application of the device and the temperature and lot to lot variation of the time delay Since the body diode of the synchronous rectifier conducts during this deadtime the efficiency of this technique varies with different MOSFETs ambient temperature and with the lot to lot variation of the deadtime delay To combat the variability of the internal time delays second generation controllers used state information from the power stage to control the turn on of the two gate drivers This technique is usually referred to as adaptive gate drive technique and is pictured in Flgure 8 Vin Vout UDG 01031 Figure 8 Adaptive Gate Drive Technique The main advantage of the adaptive technique is the on the fly delay adjustment for different MOSFETs and temperature variable time delays T
34. ut Threshold Rising A Input Threshold Falling a O Input Threshold Hyst M d I 50 25 0 25 50 75 100 125 TA Temperature C Figure 25 21 UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 TYPICAL CHARACTERISTICS PREDICTIVE DELAY BIT WEIGHT PROPAGATION DELAYS 22 www ti com vs vs TEMPERATURE TEMPERATURE 4 7 120 4 5 a 100 c i opt G2 2 I 5 4 3 80 5 9 41 S 60 tc o 2 9 2 a o I o 3 9 o 40 g 2 a 3 7 20 3 5 0 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TA Temperature C TA Temperature C Figure 26 Figure 27 PREDICTIVE DELAY RANGE PREDICTIVE DELAY RANGE vs vs 60 TEMPERATURE TEMPERATURE 60 50 ee ton G1 Max Ld 40 L S o 40 ton G2 Max c c 1 39 L 30 o o S S 20 tt 20 gt gt E s 10 A 10 N O o I 0 O ton G1 Min o ton G2 Min 10 i om 10 m O 30 30 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TA Temperature C TA Temperature C Figure 28 Figure 29 35 TEXAS INSTRUMENTS UCC27221 UCC27222 SLUS486B AUGUST 2001 REVISED JULY 2003 TYPICAL CHARACTE
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