ANALOG DEVICES AD8021 Low Noise High Speed Amplifier for 16-Bit Systems handbook
Contents
1. G 2 Rp 1kO 9 9 Re Re 4990 8 8 7 7 Rp 2500 6 m 6 z 5 2 5 4 4 A4 4 Rp 1500 3 3 2 2 Re 750 1 1 Rp 1kO AND 2 2pF 0 0 0 1M 1M 10M 100M 1G 0 1M 1M 10M 100M 1G FREQUENCY Hz FREQUENCY Hz TPC 7 Large Signal Frequency Response vs TPC 10 Small Signal Frequency Response vs Frequency and Load Noninverting See Test Frequency and Noninverting Vout 50 mV Circuit 2 See Test Circuit 1 9 15 G 2 85 C 8 12 25 C 7 9 6 6 m 5 40 C Vout o 3 T 85 C 50mV p p m z 4 2 0 4 V 4 3 2V pp 3 2 6 425 C 1 9 40 C 12 1 15 1M 10M 100M 1G 0 1M 1M 10M 100M FREQUENCY Hz FREQUENCY Hz TPC 8 Frequency Response vs Frequency TPC 11 Small Signal Frequency Response vs Temperature Noninverting Frequency and Rs Noninverting Vour 50 mV See Test Circuit 1 See Test Circuit 1 18 G 2 50pF 15 30pF 20 p 9 10 m 6 3 5 1 3 2 I2. 100 Ii E M i I gt EWIDTH 120ns i Hh 7 E o g z E 10 E i SH i o 5 M o ll Es 2 i Li a 2 1 4 8 12 16 20 24 28 32 10 100 1k 10k 100k 1M 10M TIME us FREQUENCY Hz TPC 31 Long Term Settling 0 V to 5 V Vs 12 V G 13 TPC 34 Input Current Noise vs Frequency 0 48 0 44 gt E 0 40 gt Pe 1 5 0 36 8 H 0 32 Q 0 28 0 24 50 25 0 25 50 75 100 TIME ns TEMPERATURE TPC 32 Small Signal Transient Response TPC 35 Vos vs Temperature Vo 50 mV p p G 1 See Test Circuit 1 100 8 4 8 0 N g 4 gt E 7 6 1 tr 2 s 10 3 7 2 5 5 68 9 a 2 6 4 1 6 0 10 100 1k 10k 100k 1M 10M 50 25 0 25 50 75 100 FREQUENCY Hz TEMPERATURE TPC 33 Input Voltage Noise vs Frequency TPC 36 Input Bias Current vs Temperature REV D 11 AD8021
3. G 1 Vg 2 5V 21 2 S 38 10 1 Rg 1000 1 5V Rix 1000 OpF 15 0 5 Rp 1kO Rg 2000 Vg 12 1 m 12 p 66 50 Cc 1 5 E 1 z 9 z 2 4 4 6 3 2 Rp 4990 Rg 2490 3 63 40 Cc 4pF 4 0 5 G 1 Rp 4990 Rg 4990 Vg 2 5V 3 Riy 56 20 7pF 6 sd LLL 41N E 0 1M 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY Hz TPC 2 Small Signal Frequency Response vs Frequency and Gain Voyr 50 mV Inverting See Test Circuit 1 GAIN dB 10M FREQUENCY Hz TPC 3 Small Signal Frequency Response vs Frequency and Compensation Capacitor Vout 50 mV See Test Circuit 1 FREQUENCY Hz TPC 5 Small Signal Frequency Response vs Frequency and Supply Voy 50 mV p p Inverting See Test Circuit 3 Vour 0 1V AND 50mV p p GAIN dB A Vout 4V 1V p p 1M 10M 100M 1G FREQUENCY Hz TPC 6 Frequency Response vs Frequency and Vout Noninverting See Test Circuit 1 REV AD8021
4. 20 0 30 10 40 20 a 50 1 30 m 60 E 40 3 70 o 90 80 60 l a 90 2 70 a 100 80 110 90 120 100 10k 100k 1M 10M 100M 0 1M 1M 10M 100M 1G FREQUENCY Hz FREQUENCY Hz TPC 37 CMRR vs Frequency See Test Circuit 4 TPC 40 Input to Output Isolation Chip Disabled See Test Circuit 7 o OUTPUT IMPEDANCE 30 10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G FREQUENCY Hz FREQUENCY Hz TPC 38 Output Impedance vs Frequency Chip TPC 41 Output Impedance vs Frequency Chip Enabled See Test Circuit 5 Disabled See Test Circuit 8 20 PSRR PSRR dB d Vs 5V 0 100 200 300 400 500 10 100 1M 10M 100M 500M TIME ns FREQUENCY Hz TPC 39 Enable tgy Disable 1 Time vs Vout TPC 42 PSRR vs Frequency and Supply Voltage See Test Circuit 6 See Test Circuits 9 and 10 REV D 12 AD8021 8 5 SUPPLY CURRENT mA 50
5. S o 3 9 z a 3 5 6 9 12 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G FREQUENCY Hz FREQUENCY Hz TPC 9 Small Signal Frequency Response vs TPC 12 Open Loop Gain and Phase vs Frequency and Capacitive Load Noninverting Frequency Rg 2100 Re 1 976 Vout 50 mV See Test Circuit 2 and Figure 16 Rp 53 6 Cc 0 pF See Test Circuit 3 REV D 7 AD8021 6 4 20 G 2 30 6 2 40 Vg 2 5V f f 50 Af 0 2MHz Pout 6 0 60 m 9760 1 ii 1 d 70 5 5 53603 1 500 5 8 80 12V 1 90 5 6 100 110 5 4 120 1M 10M 100M 9 5 9 7 10 0 10 3 10 5 FREQUENCY Hz FREQUENCY MHz TPC 13 0 1 dB Flatness vs Frequency and TPC 16 Intermodulation Distortion vs Frequency Supply Vour 1 V 150 Noninverting See Test Circuit 2 30 40 E 5 50 SECOND i a _60 IN Ir 2 70 2 R 1000 E 80 c ENS R 1KO B a 100 110 E 120 THIRD 130 0 1M 1M 10M 20M 0 5 10 15 20 FREQUENCY Hz FREQUENCY MHz TPC 14 Second and Third Harmonic Distortion TPC 17 Third Order Intercept vs Frequency and vs Frequency and Supply Voltage DISTORTION
6. 0 OO ANALOG DEVICES Low Noise High Speed Amplifier for 16 Bit Systems AD8021 FEATURES Low Noise 2 1 nV VHz Input Voltage Noise 2 1 pA VHz Input Current Noise Custom Compensation Constant Bandwidth from G 1 G 10 High Speed 200 MHz G 1 190 MHz G 10 Low Power 34 mW or 6 7 mA Typ for 5 V Supply Output Disable Feature 1 3 mA Low Distortion 93 dB Second Harmonic f 1 MHz 108 dB Third Harmonic fc 1 MHz DC Precision 1 mV Max Input Offset Voltage 0 5 pV C Input Offset Voltage Drift Wide Supply Range 5 V to 24 V Low Price Small Packaging Available in SOIC 8 and MSOP 8 APPLICATIONS ADC Preamp and Driver Instrumentation Preamp Active Filters Portable Instrumentation Line Receivers Precision Instruments Ultrasound Signal Processing High Gain Circuits PRODUCT DESCRIPTION The AD8021 is a very high performance high speed voltage feedback amplifier that can be used in 16 bit resolution systems It is designed to have low voltage and current noise 2 1 nV VHz typ and 2 1 pA VHz typ while operating at the lowest quiescent supply current 7 mA 5 V among today s high speed low noise op amps The AD8021 operates over a wide range of supply voltages from 2 5 V to 12 V as well as from single 5 V supplies making it ideal for high speed low power instru ments n output disable pin allows further reduction of the quiescent supply current to 1 3 mA REV D I
7. 25 0 25 50 75 100 TEMPERATURE C TPC 43 Quiescent Supply Current vs Temperature HP8753D NETWORK ANALYZER Test Circuits 500 CABLE R 5 Test Circuit 1 Noninverting Gain Test Circuit 4 CMRR EEL 08021 HP8753D PROBE Vs NETWORK o ANALYZER 500 CABLE Test Circuit 2 Noninverting Gain with FET Probe Test Circuit 5 Output Impedance Chip Enabled AD8021 500 CABLE 1 49 90 V V 8 4v 49 90 i 4990 Test Circuit 3 Inverting Gain Test Circuit 6 Enable Disable REV D 13 AD8021 HP8753D NETWORK ANALYZER 500 CABLE AD8021 FET Test Circuit 7 Input to Output Isolation Chip Disabled HP8753D NETWORK ANALYZER Test Circuit 8 Output Impedance Chip Disabled 14 HP8753D NETWORK ANALYZER 500 CABLE HP8753D NETWORK ANALYZER 500 CABLE Test Circuit 10 Negative PSRR REV D AD8021 APPLICATIONS The typical voltage feedback op amp is frequency stabilized with a fixed internal capacitor Cwrernar using dominant pole compen sation To a first order approximation voltage feedback op amps have a fixed gain bandwidth product For example if its 3 dB bandwidth for G 1 is 200 MHz at a gain of G 10 its bandwidth will be only about 20 MHz The AD8021 is a voltage 19 feedback op amp with a minimal Cpyrernar of about 1 5 pF By 9 adding an external compensation capacitor Cc the user can circumvent the fixed gai
8. Disabled Leakage Current Logic Ref 0 4 V 30 uA DISABLE 0 4 V 33 uA POWER SUPPLY Operating Range 2 25 5 12 0 V Quiescent Current Output Enabled 6 7 7 5 Output Disabled 1 2 1 5 Power Supply Rejection Ratio 4 5 V to 5 5 Ve 0 V 74 82 dB Power Supply Rejection Ratio 5 V Ver 0 5 V to 0 5 V 76 84 dB Specifications subject to change without notice REV 0 AD8021 ABSOLUTE MAXIMUM RATINGS Supply Voltage sca ds E vrac RU eae aed 26 4 V Power Dissipation Observed Power Derating Curves Input Voltage Common Mode tVst1V Differential Input Voltage 0 8 V Differential Input Current 10 mA Output Short Circuit Duration rm Observed Power Derating Curves Storage Temperature 65 C to 125 C Operating Temperature Range 40 C to 85 C Lead Temperature Range Soldering 10 sec 300 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability The AD8021 inputs are protected by diodes Current limiting resistors are not
9. HD2 Vo 2 V p p 93 dBc HD3 Vo 2 V p p 108 dBc f 5 MHz HD2 Vo 2 V p p 70 dBc HD3 Vo 2 V p p 80 dBc Input Voltage Noise f 50 kHz 2 1 2 6 nV VHz Input Current Noise f 50 kHz 2 1 pA VHz Differential Gain Error NTSC 150 Q 0 03 Differential Phase Error NTSC Ry 150 Q 0 04 Degrees DC PERFORMANCE Input Offset Voltage 0 4 1 0 mV Input Offset Voltage Drift Tmn to Tmax 0 5 uV C Input Bias Current Input or Input 7 5 10 5 uA Input Bias Current Drift 10 nA C Input Offset Current 0 1 0 5 tuA Open Loop Gain 82 86 dB INPUT CHARACTERISTICS Input Resistance 10 MQ Common Mode Input Capacitance 1 pF Input Common Mode Voltage Range 4 to 4 6 V Common Mode Rejection Ratio Vom 7 4 V 86 98 dB OUTPUT CHARACTERISTICS Output Voltage Swing 3 5 to 3 2 3 8 to 3 4 V Linear Output Current 60 mA Short Circuit Current 75 mA Capacitive Load Drive for 30 Overshoot Vo 50 mV p p 1 V p p 15 120 pF DISABLE CHARACTERISTICS Off Isolation f 10 MHz 40 dB Turn On Time Vo 0 V to 2 V 50 Logic to 50 Output 45 ns Turn Off Time Vo 0 V to 2 V 50 Logic to 50 Output 50 ns DISABLE Voltage Off On VDISABLE Viocic REFERENCE 1 75 1 90 V Enabled Leakage Current Logic Ref 0 4 V 70 uA DISABLE 4 0 V 2 uA Disabled Leakage Current Logic Ref 0 4 V 30 uA DISABLE 0 4 V 33 uA POWER SUPPLY Operating Range 2 25 5 12 0 V Quiescent Current Output Enabled 7 0 7 7 mA Output Disabled 1 3 1 6 mA Power Supply Rejection Ratio Vec
10. used in order to preserve the low noise If a differential input exceeds 0 8 V the input current should be limited to 10 mA MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8021 is limited by the associated rise in junction temperature The maxi mum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction tempera ture of 175 C for an extended period can result in device failure While the AD8021 is internally short circuit protected this may not be sufficient to guarantee that the maximum junction tem perature 150 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves PIN CONFIGURATION LOGIC AD8021 REFERENCE 1 DISABLE IN 2 Vs NENNEN 1 5 8 LEAD SOIC 1 0 A 8 LEAD MSOP 0 5 0 01 BEEN 55 45 35 25 15 5 5 15 25 35 45 55 65 75 85 AMBIENT TEMPERATURE C MAXIMUM POWER DISSIPATION mW Figure 2 Maximum Power Dissipation vs Temperature Specification is for device in free air 8 Lead SOIC Oy 125 C W 8 Lead MSOP 145 C W PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Function 1 LOGIC REFERENCE Referen
11. 0 05 V p p 95 130 MHz Slew Rate 1 V Step 1 Cc 10 pF 80 110 V us G 2 Cc 7 pF 110 140 V us G 5 Cc 2 pF 210 280 V us G 10 Cc 0 pF 290 390 V us Settling Time to 0 0196 Vo 1 V Step Ry 5000 28 ns Overload Recovery 50 0 V to 2 5 V Input Step G 2 40 ns DISTORTION NOISE PERFORMANCE f 1 MHz HD2 Vo 2 V p p 84 dBc HD3 Vo 2 V p p 91 dBc f 5 MHz HD2 Vo 2 V p p 68 dBc HD3 Vo 2 V p p 81 dBc Input Voltage Noise f 50 kHz 2 1 2 6 nV VHz Input Current Noise f 50 kHz 2 1 pA VHz DC PERFORMANCE Input Offset Voltage 0 4 1 0 mV Input Offset Voltage Drift Tmn to Tmax 0 8 uV C Input Bias Current Input or Input 7 5 10 3 uA Input Bias Current Drift 10 nA C Input Offset Current 0 1 0 5 tuA Open Loop Gain 72 76 dB INPUT CHARACTERISTICS Input Resistance 10 MQ Common Mode Input Capacitance 1 pF Input Common Mode Voltage Range 0 9 to 4 6 V Common Mode Rejection Ratio 1 5 3 5 V 84 98 dB OUTPUT CHARACTERISTICS Output Voltage Swing 1 25 to 3 38 1 10 to 3 60 V Linear Output Current 30 mA Short Circuit Current 50 mA Capacitive Load Drive for 30 Overshoot Vo 50 mV p p 1 V p p 10 120 pF DISABLE CHARACTERISTICS Off Isolation f 10 MHz 40 dB Turn On Time Vo 0 V to 1 V 50 Logic to 50 Output 45 ns Turn Off Time Vo 0 V to 1 V 50 Logic to 50 Output 50 ns DISABLE Voltage Off On VDISABLE Viocic REFERENCE 1 55 1 70 V Enabled Leakage Current Logic Ref 0 4 V 70 uA DISABLE 4 0 V 2 uA
12. RM 8 Dimensions shown in millimeters iti PIN 1 0 65 BSC 3 1 10 MAX 0 80 FER aT gt lt 0 60 0 22 0 08 0 40 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO 187AA Revision History Location Page 10 03 Data Sheet changed from REV C to REV D Edits to SPECIFICATIONS heading o Seba we Wade e E PT ERRARE WE ee AR UR EE EAR ees 3 Changes to ORDERING GUIDE deat Ra UR poet ao rep eb eR o eB t E oap eR EN 5 7103 Data Sheet changed from REV to REV C Deleted all references to evaluation board de RARE eR Xe de wis E EE S Universal Replaced EE 5 Updated OUTLINE DIMENSIONS i 22 9 9R Eee Re ee ORR URP AGERE TOME eL ESTATE Ge EN ES 20 2 03 Data Sheet changed from REV A to REV B Edits to Evaluation Board Applications rr her ed RR RR RE y Id weak died ed ed ruo d d 20 Edits to Eigute 20 6 02 Data Sheet changed from REV 0 to REV A Edits to SPECIFICA TIONS x er a ade egre RU S na des BUR dee do dp at UR I EUR 2 20 REV D C01888 0 10 03 D
13. determine the value of Rswnus that maintains 2 dB of peaking in the frequency response Note however that using attenuates the low frequency output by a factor of Rroap Rsnug 0 S 0 5 10 15 20 25 30 35 40 45 50 CAPACITIVE LOAD pF Figure 16 Relationship of Rsnug vs for 2 dB Peaking at a Gain of 2 GAIN dB 0 1 1 0 10 100 1000 FREQUENCY MHz Figure 15 Peaking vs Rsyug and for 33 pF REV D 19 AD8021 OUTLINE DIMENSIONS 8 Lead Standard Small Outline Package SOIC R 8 Dimensions shown in millimeters and inches 5 00 0 1968 018907 8 5 4 00 0 1574 6 20 0 2440 3 80 0 1497 1 4 5 80 0 2284 d d 1 27 0 0500 0 50 0 0196 BSC 1 75 0 0688 0 25 0 0099 0 25 0 0099 0 25 0 0098 1 35 0 0532 0 10 0 0040 Y y 0 51 0 0201 8 gt je COPLANARITY cS 0 0201 31 0 0122 0 25 ha 05 1 27 0 0500 0 10 SEATING 0 40 0 0157 PLANE 0 17 0 0067 COMPLIANT TO JEDEC STANDARDS MS 012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8 Lead Mini Small Outline Package MSOP
14. 4 V to 6 V Veg 5 V 86 95 dB Power Supply Rejection Ratio Vee 5 V Ver 6 V to 4 V 86 95 dB Specifications subject to change without notice 2 REV D AD8021 Vs 1 2 Vie Ta 25 C 1 Gain 2 unless otherwise noted AD8021AR AD8021ARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Cc 10 pF Vo 0 05 V p p 520 560 MHz G 2 Cc 7 pF Vo 0 05 V p p 175 220 MHz G 5 Cc 2 pF Vo 0 05 V p p 170 200 MHz G 10 Cc 0 pF Vo 0 05 V p p 125 165 MHz Slew Rate 1 V Step 1 Cc 10 pF 105 130 V us G 2 Cc 7 pF 140 170 V us G 5 Cc 2 pF 265 340 V us G 10 Cc 0 pF 400 460 V us Settling Time to 0 01 Vo 1 V Step Ry 500 Q 21 ns Overload Recovery 50 6 V Input Step G 2 90 ns DISTORTION NOISE PERFORMANCE f 1 MHz HD2 Vo 2 V p p 95 HD3 Vo 2 V p p 116 dBc f 5 MHz HD2 Vo 2 V p p 71 dBc HD3 Vo 2 V p p 83 dBc Input Voltage Noise f 50 kHz 2 1 2 6 nV VHz Input Current Noise f 50 kHz 2 1 pAVHz Differential Gain Error NTSC 150 Q 0 03 Differential Phase Error NTSC R 150 Q 0 04 Degrees DC PERFORMANCE Input Offset Voltage 0 4 1 0 mV Input Offset Voltage Drift Tmn to Tmax 0 2 uV C Input Bias Current Input or Input 8 11 3 uA Input Bias Current Drift 10 nA C Input Offset Current 0 1 0 5 tuA Open Loop Gain 84 88 dB INPUT CHARACTERISTICS Input Resi
15. NP transistors The folded cascode and current mirror provide a differential to single ended conversion of signal current This current then drives the high impedance node Pin 5 where the Cc external capacitor is connected The output stage preserves this high impedance with a current gain of 5 000 so that the AD8021 can maintain a high open loop gain even when driving heavy loads Two internal diode clamps across the inputs Pins 2 and 3 protect the input transistors from large voltages that could otherwise cause emitter base breakdown which would result in degradation of offset voltage and input bias current Vs OUTPUT Figure 6 Simplified Schematic PCB LAYOUT CONSIDERATIONS As with all high speed op amps achieving optimum performance from the AD8021 requires careful attention to PC board layout Particular care must be exercised to minimize lead lengths between the ground leads of the bypass capacitors and between the compensation capacitor and the negative supply Otherwise lead inductance can influence the frequency response and even cause high frequency oscillations Use of a multilayer printed circuit board with an internal ground plane will reduce ground noise and enable a compact component arrangement Due to the relatively high impedance of Pin 5 and low values of the compensation capacitor a guard ring is recommended The guard ring is simply a PC trace that encircles Pin 5 and is connected to the output Pi
16. arges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8021 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING ESD SENSITIVE DEVICE REV D AD8021 Typical Performance Characteristics T 256 Vs 5 V 6 2 Rr 499 49 9 Ro 976 Rp 53 6 Ce 7pF C 0 0 Vout 2 V p p Freq 1 MHz unless otherwise noted G 2 8 Vg 2 5 5V 7 5 1 6 z x m 8 ih a 3 12V 9 2 Vg 2 5V 1 0 1 10M 1M 10M 100M 1G FREQUENCY Hz TPC 1 Small Signal Frequency Response vs Frequency and Gain Voy 50 mV Noninverting See Test Circuit 1 24 FREQUENCY Hz TPC 4 Small Signal Frequency Response vs Frequency and Supply Voy 50 mV Noninverting See Test Circuit 1
17. ce for Pin 8 Voltage Level Connect to logic low supply 2 IN Inverting Input 3 TIN Noninverting Input 4 Vs Negative Supply Voltage 5 Compensation Capacitor Tie to Vs See the Applications section for value 6 Vout Output 7 Positive Supply Voltage 8 DISABLE Disable Active Low When Pin 8 DISABLE is about 2 V or more higher than Pin 1 LOGIC REFERENCE the part is enabled When Pin 8 is brought down to within about 1 5 V of Pin 1 the part is disabled See the Specification tables for exact disable and enable voltage levels If the disable feature is not going to be used Pin 8 can be tied to Vs or a logic high source and Pin 1 can be tied to ground or logic low Alterna tively if Pin 1 and Pin 8 are not connected the part will be in an enabled state ORDERING GUIDE Model Temperature Range Package Description Package Outline Branding AD8021AR 40 to 85 C 8 Lead SOIC R 8 AD8021AR REEL 40 to 85 C 8 Lead SOIC R 8 AD8021AR REEL7 40 C to 85 C 8 Lead SOIC R 8 AD8021ARM 40 C to 85 C 8 Lead MSOP RM 8 HNA AD8021ARM REEL 40 C to 85 C 8 Lead MSOP RM 8 HNA AD8021ARM REEL7 40 to 85 C 8 Lead MSOP RM 8 HNA AD8021ARZ 40 C to 85 C 8 Lead SOIC R 8 AD8021ARZ REEL 40 C to 85 C 8 Lead SOIC R 8 AD8021ARZ REEL7 40 C to 85 C 8 Lead SOIC R 8 Z Lead Free CAUTION ESD electrostatic discharge sensitive device Electrostatic ch
18. dBc DISTORTION dBc FREQUENCY Hz V TPC 15 Second and Third Harmonic Distortion TPC 18 Second and Third Harmonic Distortion vs Frequency and Vs vs Vour and REV D 08021 LLLLLLLLLL 3 1 gt POSITIVE OUTPUT gt o a o 9 z E E o 2 2 E a a tr 5 5 E 3 3 a E 5 Z NEGATIVE OUTPUT 3 8 0 400 800 1200 1600 2000 Vout V P P LOAD O TPC 19 Second and Third Harmonic Distortion TPC 22 DC Output Voltage vs Load See Test vs Voyr and Fundamental Frequency fc G 2 Circuit 1 120 e eo DISTORTION dBc A SHORT CIRCUIT CURRENT o o 20 50 30 10 10 30 50 70 90 110 Vour V P P TEMPERATURE C TPC 20 Second and Third Harmonic Distortion TPC 23 Short Circuit Current to Ground vs vs Vour and Fundamental Frequency fc G 10 Temperature 40 80 30 20 o tn 7 90 gt 10 5 T E 5 5 5 P 100 10 5 e 20 110 30 40 120 50 0 200 400 600 800 1000 0 40 80 120 160 200 FEEDBACK RESISTANCE TIME ns TPC 21 Second and Third Harmonic Distortion TPC 24 Small Signal Tra
19. e offs can be made to fine tune its dynamic performance Sometimes more bandwidth or slew rate is needed at a particular gain Reducing the compensation capacitance as illustrated in TPC 3 will increase the bandwidth and peaking due to a decrease in phase margin On the other hand if more stability is needed increasing the compensation cap will decrease the bandwidth while increasing the phase margin As with all high speed amplifiers parasitic capacitance and induc tance around the amplifier can affect its dynamic response Often the input capacitance due to the op amp itself as well as the PC board could have a significant effect The feedback resistance together with the input capacitance may contribute to a loss of phase margin thereby affecting the high frequency response as shown in TPC 10 Furthermore a capacitor Cg in parallel with the feedback resistor can compensate for this phase loss Additionally any resistance in series with the source will create a pole with the input capacitance as well as dampen high fre quency resonance due to package and board inductance and capacitance the effect of which is shown in TPC 11 It must also be noted that increasing resistor values will increase the overall noise of the amplifier and that reducing the feedback resistor value will increase the load on the output stage thus increasing distortion TPC 18 Using the Disable Feature When Pin 8 DISABLE is approximately 2 V
20. ematic of a 2 pole low pass active filter and Table IV lists typical component values for filters having a Bessel type response with gains of 2 and 5 Figure 14 is a network analyzer plot of this filter s performance Figure 13 Schematic of a Second Order Low Pass Active Filter Table IV Typical Component Values for Second Order Low Pass Filter of Figure 13 Gain R1 Q R2 Q Re Q Rs C2 Ce 2 71 5 215 499 499 10 nF 10 nF 7 pF 5 44 2 365 90 9 365 10 nF 10 nF 2 pF GAIN dB 1k 10k 100k 1M 10M FREQUENCY Hz Figure 14 Frequency Response of the Filter Circuit of Figure 13 for Two Different Gains REV D 18 AD8021 Driving Capacitive Loads 20 When the AD8021 drives a capacitive load the high frequency 18 response may show excessive peaking before it rolls off Two techniques can be used to improve stability at high frequency and reduce peaking The first technique is to increase the compensa tion capacitor Cc which reduces the peaking while maintaining gain flatness at low frequencies The second technique is to add a resistor in series between the output pin of the AD8021 and the capacitive load Figure 15 shows the response of the AD8021 when both Cc and Rgnup are used to reduce peaking 6 For a given Figure 16 can be used to
21. industrial temperature range of 40 C to 85 C 24 Vout 50mV p p 21 i G 10 1kO Rg 1000 ih Riy 1000 OpF T 15 G 5 1kO Rg 2000 Riy 66 50 1 5pF n 9 H o 1 6 ul 2 Rp 4990 Rg 2490 95 Ry 63 40 4pF o 0 1 Rp 4990 Rg 4990 3 Riy 56 20 Cc 7pF 6 0 1M 1M 10M 100M 1G FREQUENCY Hz Figure 1 Small Signal Frequency Response One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD8021 SPECIFICATIONS Vs 5 T 25 C V 5 V 1 Gain 2 unless otherwise noted AD8021AR AD8021ARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth 1 Cc 10 pF Vo 0 05 V 355 490 MHz G 2 Cc 7 pF Vo 0 05 V p p 160 205 MHz G 5 Cc 2 pF Vo 0 05 V p p 150 185 MHz G 10 Cc 0 pF Vo 0 05 V p p 110 150 MHz Slew Rate 1 V Step G 1 Cc 10 pF 95 120 V us G 2 Cc 7 pF 120 150 V us G 5 Cc 2 pF 250 300 V us G 10 Cc 0 pF 380 420 V us Settling Time to 0 01 Vo 1 V Step Ry 5000 23 ns Overload Recovery 50 2 5 V Input Step G 2 50 ns DISTORTION NOISE PERFORMANCE f 1 MHz
22. n 6 which is at the same potential as Pin 5 This serves two functions It shields Pin 5 from any local circuit noise generated by surrounding circuitry It also mini mizes stray capacitance which would tend to otherwise reduce the bandwidth An example of a guard ring layout may be seen in Figure 7 Also shown in Figure 7 the compensation capacitor is located immediately adjacent to the edge of the AD8021 package spanning Pin 4 and Pin 5 This capacitor must be a high quality surface mount COG or NPO ceramic The use of leaded capacitors is not recommended The high frequency bypass capacitor s should be located immediately adjacent to the supplies Pins 4 and 7 To achieve the shortest possible lead length at the inverting input the feedback resistor Rg is located beneath the board and just spans the distance from the output Pin 6 to inverting input Pin 2 The return node of resistor Rg should be situated as closely as possible to the return node of the negative supply bypass capacitor connected to Pin 4 REV D 16 AD8021 TOP VIEW BYPASS CAPACITOR GROUND PLANE BYPASS CAPACITOR COMPENSATION CAPACITOR GROUND PLANE Figure 7 Recommended Location of Critical Components and Guard Ring DRIVING 16 BIT ADCS Low noise and adjustable compensation make the AD8021 especially suitable as a buffer driver for high resolution analog to digital converters As seen in TPC 15 the harmonic distortion i
23. n bandwidth limitation of other voltage feedback op amps bandwidth is degraded to about 20 MHz and the phase margin increases to 90 Arrow B However by reducing to zero the bandwidth and phase margin return to about 200 MHz and 60 Arrow C respectively In addition the slew rate is dra matically increased as it roughly varies with the inverse of Cc 8 7 Unlike the typical op amp with fixed compensation the AD8021 allows the user to 1 Maximize the amplifier bandwidth for closed loop gains between 1 and 10 avoiding the usual loss of bandwidth and slew rate COMPENSATION CAPACITANCE pF a 2 Optimize the trade off between bandwidth and phase margin for a particular application 0 O 3 Match bandwidth in gain blocks with different noise gains 1 2 3 4 5 6 7 8 9 10 11 such as when designing differential amplifiers as shown in NOISEGAINVIV Figure 10 Figure 4 Suggested Compensation Capacitance vs Gain for Maintaining 1 dB Peaking Table I and Figure 4 provide recommended values of compensa tion capacitance at various gains and the corresponding slew rate bandwidth and noise Note that the value of the compensation capacitor depends on the circuit noise gain not the voltage gain As shown in Figure 5 the noise gain Gy of an op amp gain block is equal to its noninverting voltage gain regardless of whether it is actually used for inverting or nonin
24. nformation furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners CONNECTION DIAGRAM SOIC 8 R 8 MSOP 8 RM 8 LOGIC REFERENCE The AD8021 allows the user to choose the gain bandwidth product that best suits the application With a single capacitor the user can compensate the AD8021 for the desired gain with little trade off in bandwidth The AD8021 is a very well behaved amplifier that settles to 0 0196 in 23 ns for a 1 V step It has a fast overload recovery of 50 ns The AD8021 is stable over temperature with low input offset voltage drift and input bias current drift 0 5 uV C and 10 nA C respectively The AD8021 is also capable of driving a 75 Q line with 3 V video signals The AD8021 is not only technically superior but also priced considerably less than comparable amps drawing much higher quiescent current The AD8021 is a high speed general purpose amplifier ideal for a wide variety of gain configurations and can be used throughout a signal processing chain and in control loops The AD8021 is available in both standard 8 lead SOIC and MSOP packages in the
25. ng ac responses of driver halves Vin 49 90 GAIN dB 100k 1M 10M 100M 1G FREQUENCY Hz Figure 11 AC Response of Two Identically Compensated High Speed Op Amps Configured for Gains of 2 and 2 12 9 6 3 G 2 m 0 o 2 3 lt 9 6 9 12 15 18 100k 1M 10M 100M 1G FREQUENCY Hz Figure12 AC Response of Two Dissimilarly Compensated AD8021 Op Amps Figure 11 Configured for Gains of 2 and 2 Note the Close Gain Match USING THE AD8021 IN ACTIVE FILTERS The low noise and high gain bandwidth of the AD8021 make it an excellent choice in active filter circuits Most active filter litera ture provides resistor and capacitor values for various filters but neglects the effect of the op amp s finite bandwidth on filter performance ideal filter response with infinite loop gain is implied Unfortunately real filters do not behave in this manner Instead they exhibit finite limits of attenuation depending on the gain bandwidth of the active device Good low pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies and low noise and high dc gain for low frequency pass band performance Figure 13 shows the sch
26. nsient Response vs R vs Feedback Resistor Rp Vo 50 mV p p See Test Circuit 2 Noninverting REV D 9 AD8021 Vo 2V 20 F G 2 1 0 gt 1 8 Vg 2 5V 1 0 Vg 5V 2 0 0 40 80 120 160 200 0 40 80 120 160 200 TIME ns TIME ns TPC 25 Large Signal Transient Response vs R TPC 28 Large Signal Transient Response vs Vs See Test Circuit 2 Noninverting See Test Circuit 1 Vin 3V Vo 4V p p G 42 4 677 1V DIV 2V DIV Vin 2 1 p EI 9o 4 1 Vour4 2 3 4 5 0 100 200 300 400 500 0 50 100 150 200 250 TIME ns TPC 29 Overdrive Recovery vs R See Test Circuit 2 TPC 26 Large Signal Transient Response See Test Circuit 3 Inverting Vg 4V 9 G 2 eo 2 0 01 5 E 2 2 _0 01 3 25ns VERT 0 2mV DIV HOR 5ns DIV 0 40 80 120 160 200 TIME ns H H 9 j TPC 27 Large Signal Transient Response vs TPC 30 0 01 Settling Time 2 V Step See Test Circuit 1 REV D 10 AD8021
27. or more higher than Pin 1 LOGIC REFERENCE the part is enabled When Pin 8 is brought down to within about 1 5 V of Pin 1 the part is dis abled See the Specification tables for exact disable and enable voltage levels If the disable feature is not going to be used Pin 8 can be tied to Vs or a logic high source and Pin 1 can be tied to ground or logic low Alternatively if Pin 1 and Pin 8 are not connected the part will be in an enabled state THEORY OF OPERATION The AD8021 is fabricated on the second generation of Analog Devices proprietary High Voltage eXtra Fast Complementary Bipolar XFCB process which enables the construction of PNP and NPN transistors with similar frs in the 3 GHz region The transistors are dielectrically isolated from the substrate and each other eliminating the parasitic and latch up problems caused by junction isolation It also reduces nonlinear capacitance a source of distortion and allows a higher transistor fr for given quiescent current The supply current is trimmed which results in less part to part variation of bandwidth slew rate distortion and settling time As shown in Figure 6 the AD8021 input stage consists of an NPN differential pair in which each transistor operates at 0 8 mA collec tor current This allows the input devices a high transconductance thus AD8021 has a low input noise of 2 1 nVA Hz 50 kHz The input stage drives a folded cascode that consists of a pair of P
28. s tested with a noninverting gain of 10 1 and an output voltage of approximately 20 V p p for optimum resolution and noise per formance No filtering was used An FFT was performed using Analog Devices evaluation software for the AD7665 16 bit converter The results are listed in Table III DIFFERENTIAL DRIVER The AD8021 is uniquely suited as a low noise differential driver for many ADCs balanced lines and other applications requiring differential drive If pairs of internally compensated op amps are configured as inverter and follower the noise gain of the inverter will be higher than that of the follower section resulting in an imbalance in the frequency response see Figure 11 A better solution takes advantage of the external compensation feature of the AD8021 By reducing the value of the inverter its bandwidth may be increased to match that of the follower avoiding compromises in gain bandwidth and phase delay The inverting and noninverting bandwidths can be closely matched using the compensation feature thus minimizing distortion 177 AD8021 Figure 10 illustrates an inverter follower driver circuit operating at a gain of 2 using individually compensated AD8021s The values of feedback and load resistors were selected to provide a total load of less than 1 kQ and the equivalent resistances seen at each op amp s inputs were matched to minimize offset volt age and drift Figure 12 is a plot of the resulti
29. s better than 90 dB at frequencies between 100 kHz and 1 MHz This is a real advantage for complex waveforms that contain high frequency information as the phase and gain integrity of the sampled waveform can be preserved throughout the conversion process The increase in loop gain results in improved output regulation and lower noise when the converter input changes state during a sample This advantage is particularly apparent when using 16 bit high resolu tion ADCs with high sampling rates Figure 8 shows a typical ADC driver configuration The AD8021 is in an inverting gain of 7 5 is 65 kHz and its output voltage is 10 V p p The results are listed in Table II 12V AD7665 570kSPS 6 BITS Figure 8 Inverting ADC Driver Gain 7 5 fc 65 kHz REV D Table II Summary of ADC Driver Performance fc 65 kHz Vout 10V p p Parameter Measurement Unit Second Harmonic Distortion 101 3 dB Third Harmonic Distortion 109 5 THD 100 0 dB SFDR 100 3 dB AD7665 570kSPS 16 BITS Le d Ee T OPTIONAL Figure 9 Noninverting ADC Driver Gain 10 100 kHz Table III Summary of ADC Driver Performance fc 100 kHz Vour 20V p p Parameter Measurement Unit Second Harmonic Distortion 92 6 Third Harmonic Distortion 86 4 THD 84 4 SFDR 5 4 dB Figure 9 shows another ADC driver connection The circuit wa
30. stance 10 MQ Common Mode Input Capacitance 1 pF Input Common Mode Voltage Range 11 1 to 11 6 V Common Mode Rejection Ratio Vom 7 10V 86 96 dB OUTPUT CHARACTERISTICS Output Voltage Swing 10 2 to 9 8 10 6 to 10 2 V Linear Output Current 70 mA Short Circuit Current 115 mA Capacitive Load Drive for 30 Overshoot Vo 50 mV p p 1 V p p 15 120 pF DISABLE CHARACTERISTICS Off Isolation f 10 MHz 40 dB Turn On Time Vo 0 V to 2 V 50 Logic to 50 Output 45 ns Turn Off Time Vo 0 V to 2 V 50 Logic to 50 Output 50 ns DISABLE Voltage Off On VDISABLE Viocic REFERENCE 1 80 1 95 V Enabled Leakage Current Logic Ref 0 4 V 70 uA DISABLE 4 0 V 2 uA Disabled Leakage Current Logic Ref 0 4 V 30 uA DISABLE 0 4 V 33 uA POWER SUPPLY Operating Range t2 25 5 12 0 V Quiescent Current Output Enabled 7 8 8 6 mA Output Disabled 1 7 2 0 mA Power Supply Rejection Ratio Vec 11 V to 13 V Veg 12 V 86 96 dB Power Supply Rejection Ratio Vec 12 V Vez 13 V to 11 V 86 100 dB Specifications subject to change without notice REV D AD8021 Vs 5 V 9 T 25 C 1 KO Gain 2 unless otherwise noted AD8021AR AD8021ARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Cc 10 pF Vo 0 05 V p p 270 305 MHz G 2 Cc 7 pF Vo 0 05 V p p 155 190 MHz G 5 Cc 2 pF Vo 0 05 V p p 135 165 MHz G 10 Cc 0 pF Vo
31. verting gain Thus PHASE Degrees Noninverting Gy Rp Rg 1 Inverting Gy Rp Rg 1 OPEN LOOP GAIN dB 1k 10k 100k 1M 10M FREQUENCY Hz 100M 1G 10G Figure 3 Simplified Diagram of Open Loop Gain and Phase Response Figure 3 is the AD8021 gain and phase plot that has been sim plified for instructional purposes If the desired closed loop gain is G 1 and Cc 10 pF is chosen Arrow A of the figure shows that the bandwidth is about 200 MHz and the phase margin is about 60 If the gain is changed to G 10 and Cc is fixed at 10 pF then as expected for a typical op amp the G Gy 5 Ccomp NONINVERTING Figure 5 The Noise Gain of Both Is 5 INVERTING Table I Recommended Component Values See Test Circuit 2 Cp 0 Ry 1 Ryy 49 9 Q Noise Gain Slew 3 dB Output Noise Output Noise Noninverting Rs Re Rg Rate SS BW AD8021 Only AD8021 with Resistors Gain Q Q V s MHz nVINHz nVINHz 1 75 75 NA 10 120 490 2 1 2 8 2 49 9 499 499 7 150 205 4 3 8 2 5 49 9 1k 249 2 300 185 10 7 15 5 10 49 9 1k 110 0 420 150 21 2 27 9 20 49 9 lk 52 3 0 200 42 42 2 52 7 100 49 9 1k 10 0 34 6 211 1 264 1 REV D 15 AD8021 With the AD8021 a variety of trad
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