ANALOG DEVICES AD8018 5 V Rail-to-Rail High-Output Current xDSL Line Drive Amplifier handbook
Contents
1. 0 01 0 1 1 10 100 1k FREQUENCY MHz TPC 5 Output Impedance vs Frequency for Full Power Standby and Shutdown Modes 40 196 2 0 10 20 30 40 50 60 70 80 90 100 TIME ns TPC 6 0 1 Settling Time 4 REV 0 Bo It N a lt OUTPUT VOLTAGE dBv 25 10 100k 1M 10M 100M 1G FREQUENCY Hz TPC 7 Output Voltage vs Frequency 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 OUTPUT SWING Volts 1 7 1 6 1 5 1 10 100 1000 10k LOAD RESISTANCE Q TPC 8 Output Swing vs PSRR dB PSRR 100k 1M 10M 100M FREQUENCY Hz TPC 9 PSRR vs Frequency REV 0 OUTPUT VOLTAGE dBv CMRR dB NORMALIZED GAIN dB 1 e AD8018 Bo a aie 25 10k 100k 1M 10M 100M 1G FREQUENCY Hz TPC 10 Outp2. 1 AMP 555154 1 MOD JACK SHIELDED 6 6 ADS 12 20 5 Pl 2 3 pin gold male header Waldom D K WM 2723 ND ADS 12 3 80 JP3 4 2 3 pin gold male locking header Waldom WM 2701 ND ADS 12 3 79 P3 4 1 AD8018ARU ADSL Driver hybrid ADS AD8018ARU U1 D U T 1 4 4 4 40 x 1 2 threaded alum standoffs ADS 30 16 2 18 REV 0 AD8018 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead SOIC 14 Lead TSSOP SO 8 RU 14 0 1968 5 00 0 201 5 10 0 1890 am 0 197 5 00 A 0 193 4 90 0 1574 4 00 0 2440 6 20 0 1497 3 80 0 2284 5 80 0 177 4 50 a by 0 0196 0 50 mE 0 0500 1 27 3 0 169 4 30 BSC 0 0099 0 25 49 0 0688 1 75 025 Foose 8 i 0 0040 0 10 4 4 lle e PINT Bb bi SEATING 0 020 0 51 0 0098 0 25 0 0 050 1 27 0 0256 0 65 0 047 1 2 PLANE 0 013 0 33 0 0075 0 19 2 016 0 40 0 059 1 50 BSC MAX CONTROLLING DIMENSIONS ARE IN MILLIMETERS 0 093 1 00 h GHHEHHHPE vy ALL DIMENSIONS PER JEDEC STANDARDS MS 012 AA 0 031 0 80 F ie 8 e 0 006 0 15 0 0118 0 30 SEATING 0 008 0 20 0 0 030 0 75 0 002 0 05 0 0075 0 19 PLANE 0 004 0 09 0 024 0 60 0 018 0 45 CONTROLLING DIMENSIONS ARE IN MILLIMETERS REV 0 19 01519 4 5 7 00 0 PRINTED IN U S A
3. 8 Lead TSSOP Package 115 C W ORDERING GUIDE Temperature Package Package Model Range Description Option AD8018AR 40 C to 85 C 8 Lead Plastic SO 8 SOIC AD8018AR REEL 40 C to 85 C 8 Lead SOIC SO 8 AD8018ARU 409 to 85 14 Lead Plastic RU 14 TSSOP AD8018ARU REEL 40 C to 85 14 Lead Plastic RU 14 TSSOP AD8018ARU EVAL Evaluation Board RU 14 CAUTION MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8018 is limited by the associated rise in junction temperature The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in device failure While the AD8018 is internally short circuit protected this may not be sufficient to guarantee that the maximum junction tempera ture 150 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves Ty 150 C IC PACKAGE D TSSOP PACKAGE MAXIMUM POWER DISSIPATION Watts 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE C Figure 3 Plot
4. 5V 100 G 4 fo 100kHz PWDN 1 0 1 0 or 0 1 Vg 2 5V 30 G 4 fo 100kHz PWDN 1 0 1 1 3RD HARMONIC 2ND HARMONIC 2ND HARMONIC 3RD HARMONIC DIFFERENTIAL DISTORTION dBc DIFFERENTIAL DISTORTION dBc 100 110 200 300 400 500 600 700 800 PEAK OUTPUT CURRENT mA OUTPUT VOLTAGE Volts TPC 15 Differential Distortion vs Peak Output Current TPC 18 Differential Distortion vs Peak to Peak Output Voltage 6 REV 0 08018 16 15 14 Vg 5 25 a 1 13 Vg 5 00 a Vg 4 75 12 11 10 30 32 34 36 38 40 42 44 46 48 30 32 34 36 38 40 42 44 46 48 TRANSFORMER TURNS RATIO TRANSFORMER TURNS RATIO TPC 19 Line Power vs Turns Ratio MTPR 65 dBc TPC 22 Line Power vs Turns Ratio 75 dBc Out of Band f 43 kHz SFDR f 361 kHz Vg 5V Rune 1000 f 93kHz a o 2 o 13dBm 13 5dBm NT E 14dBm lt 2 12 5dBm lt P 12dBm E 1k 10k 100k 1M 10M 100M 1G TRANSFORMER TURNS RATIO N FREQUENCY Hz TPC 20 vs Turns Ratio TPC 23 Open Loop Transimpedance and Phase 30 Vg 5V Rune 1000 f 361kHz DECREASING 0 5 5 P 12
5. 5dBm m I P 13dBm 60 P 13 5dBm LR P 14dBm gt amp z 70 lt 80 P 12dBm 90 3 4 5 0 86 0 88 0 90 0 92 0 94 0 96 0 98 1 00 1 02 TRANSFORMER TURNS RATIO N POWER DOWN VOLTAGE Volts TPC 21 Out of Band SFDR vs Turns Ratio for Various TPC 24 Power Up Down Threshold Voltage Line Power REV 0 7 AD8018 10 Vin 2V p p 20 Vg 2 5 50 30 SIDE DRIVEN 50 5 SIDE DRIVEN 1 50 a E 60 8 70 RL 1000 SIDE DRIVEN 80 90 N RL 1000 100 SIDE DRIVEN 110 100k 1M 10M 100M 1G FREQUENCY Hz TPC 25 Crosstalk vs Frequency THEORY OF OPERATION The AD8018 is composed of two current feedback amplifiers capable of delivering 400 mA of output current while swinging to within 0 5 V of either power supply and maintaining low distortion A differential line driver using the AD8018 can provide CPE performance on a single 5 V supply This performance is enabled by Analog Device s XFCB process and a novel two stage current feedback architecture featuring a patent pending rail to rail output stage A simplified schematic is shown in Figure 4 Emitter followers buffer the positive input Vp to provide low input current and current noise The low impedance current feedback summing
6. Free Dynamic Range SFDR the AD8018 circuit should be supplied with a well regulated 5 V supply The 5 V supplied at the USB port may be poorly regu lated Improving the quality of the 5 V supply will optimize the performance of the AD8018 in a USB supplied CPE ADSL modem This can be accomplished through the use of a step up dc to dc converter or switching power supply followed by a low dropout LDO regulator such as the ADP3331 see Figure 6 Setting R1 to be 953 and R2 to be 301 will result in a Vout of 5 V Careful attention must be paid to decoupling the power supply pins at the output of the dc to dc converter the output of the LDO regulator and the supply pins of the AD8018 High quality capacitors with low equivalent series resistance ESR such as multilayer ceramic capacitors MLCCs should be used to mini mize supply voltage ripple and power dissipation A large usually tantalum 10 UF to 47 UF capacitor located in proximity to the AD8018 is required to provide good decoupling for lower fre quency signals In addition 0 1 uF MLCC decoupling capacitors should be located as close to each of the power supply pins as is physically possible no more than 1 8 inch away An additional large 4 7 uF to 10 tantalum capacitor should be placed on the board near the supply terminals to supply current for fast large signal changes at the AD8018 outputs REV 0 Figure 6 ADP3331 LDO METHOD FOR GENERATING A MIDSUPP
7. Tax 50 dB REV 0 AD8018 Parameter Conditions Min Typ Max Unit LOGIC INPUTS PWDNI 0 Logic 1 Voltage 2 0 V Logic 0 Voltage 0 8 V Logic Input Bias Current 240 Standby Recovery Time 10 Q G 2 Is 90 of Typical 500 ns Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply 8V Internal Power Dissipation Small Outline Package R 650 mW TSSOP Package RU 565 mW Input Voltage Common Mode tVs Logic Voltage 1 tVs Differential Input Voltage 1 6V Output Short Circuit Duration vr Sel een Are Oa Reefs Observe Power Derating Curves Storage Temperature Range 65 C to 125 C Operating Temperature Range 409 to 85 C Lead Temperature Range Soldering 10 sec 300 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for the device in free air 8 Lead SOIC Package 0 a 100 C W
8. covering all unused portions of the component side of the board to provide a low impedance return path Removing the ground plane on all layers from the area near the input and output pins will reduce stray capacitance particularly in the area of the inverting inputs Signal lines connecting the feedback and gain resistors should be as short as possible to minimize the inductance and stray capacitance associated with these traces Termination resistors and loads should be located as close as possible to their respective inputs and outputs Input and output traces should be kept as far apart as possible to minimize coupling crosstalk though the board Adherence to stripline design techniques for long signal traces greater than about 1 inch is recommended REV 0 AD8018 Following these generic guidelines will improve the performance of the AD8018 in all applications To optimize the AD8018 s performance as an ADSL differential line driver locate the transformer hybrid near the AD8018 drivers and as close to the RJ11 jack as possible Maintain differential circuit symmetry into the differential driver and from the output of the drivers through the transformer coupled output of the bridge circuit as much as possible CPE ADSL Application The low cost high output current dual AD8018 xDSL driver amplifiers have been specifically designed to drive high fidelity xDSL signals to within 0 5 V of the power rails the performance needed to p
9. excess phase Table I shows the recommended resistor values for use in a variety shift The optimum value for Rr depends on the gain and the of gain settings for the test circuit in TPC 1 These values are amount of peaking tolerable in the application intended to be a starting point when designing for any application g REV 0 AD8018 Table I Resistor Selection Guide Gain Rg 0 Rg Q 1 681 681 1 2 750 750 3 511 256 4 340 113 5 230 59 POWER DOWN FEATURES Two digitally programmable logic pins PWDNI1 and PWDNO are available on the TSSOP 14 package to select among three different modes of operation full power standby and shutdown The DGND pin is the logic ground reference The logic thresh old voltage is established 1 V above DGND In a typical 5 V single supply application the DGND pin is connected to analog ground If PWDN1 PWDNO DGND are left unconnected the AD8018 will operate at full power Table II Power Down Features and Truth Table Supply Output PWDNO PWDNI State Current Impedance High High Full Power 18 mA Low Low High Standby 9 mA Low High Low Standby 9 mA Low Low Low Disabled 300 uA High POWER SUPPLY AND DECOUPLING The AD8018 can be powered with a good quality i e low noise supply anywhere in the range from 3 3 V to 8 V However in order to optimize the ADSL upstream drive capability to 13 dBm and maintain the best Spurious
10. junction is at the negative input Vy The output stage is another high gain amplifier used as an integrator to provide frequency compensation The complementary common emitter output provides the extended output swing A current feedback amplifier s dynamic and distortion performance is relatively insensitive to its closed loop signal gain which is a distinct advantage over a voltage feedback architecture Figure 5 shows a simplified model of a current feedback amplifier The feedback signal is a current into the inverting node Ry is inversely proportional to the transconductance of the amplifier s input stage Emi Circuit analysis of the pictured follower with gain yields Tzs Tzs Rr GX Rin where G 1 IRo Rr TL EAR T 1 sCr Rr Figure 5 Model of Current Feedback Amplifier RIN l gyi 1250 Xn sui FEEDBACK RESISTOR SELECTION Recognizing that X lt and that the 3 dB point 15 51 In current feedback amplifiers selection of the feedback and gain when Tz Rr one can see that the amplifier s bandwidth resistors will impact on the MTPR performance bandwidth depends primarily on the feedback resistor There is a value of noise and gain flatness Care should be exercised in the selection Ry below which the amplifier will be unstable as an actual ampli of these resistors so that the optimum performance is achieved fier will have additional poles that will contribute
11. 12 Input Control Circuit REV 0 13 AD8018 C24 R25 JP1 R27 d res UCC ETC RR es morno C25 R26 JP2 R28 DEVICES o _ o AD8818 TssaP ir 25 9 NON INUERTING REU B P Figure 13 Assembly Primary Side nai C24 R25 R27 Tee O DODO ANALOG en E38 10 DEVICES 55 OU E ne 8p8018 TSSOP 17 25 Cope O NON INUERTING REU B Z ALL oo C14 JP4 S CTI 23 TPS 24 GND 53 C23 R TP17 JO 103 C20 CU Ome m R12 mL MH2 carr R6 R9 Figure 14 Silk Screen Primary Side 14 REV 08018 LAYER 1 Figure 15 Layer 1 Primary Side Figure 16 Layer 2 Ground Plane REV 0 15 AD8018 Figure 17 Layer 3 Power Plane Figure 18 Layer 4 Secondary Side 16 REV 0 08018 Figure 19 Assembly Secondary Side REV 0 17 AD8018 EVALUATION BOARD BILL OF MATERIALS AD8018 TSSOPIT Non Inverting REV A Evaluation PC board 4 40 x 1 4 panhead ss machine screw DCS ADS 30 1 1 Eval PC Board Qty Description Vendor Ref Desc 2 1 000 pF 50 V 1206 ceramic chip capacitor ADS 4 5 20 C22 27 2 0 01 uF 50 V 1206 ceramic chip capacitor ADS 4 5 19 C15 23 5 0 1 uF 50 V 1206 size ceramic chip capacitor ADS 4 5 18 C5 20 24 26 2 1 0 uF 16 V 1206 size ceramic chip capacitor Newark 83F6841 C8 10 4 26 red solid wire jump
12. LY VOLTAGE To operate an amplifier on a single voltage supply a voltage midway between the supply and ground must be generated to properly bias the inputs and the outputs A voltage divider can be created with two equal value resistors Figure 7 There is a trade off between the power consumed by the divider and the voltage drop across these resistors due to the positive input bias currents Selecting 2 5 for and R2 will create a voltage divider that draws only 1 mA from a 5 V supply The voltage generated with this topology can vary due to the temperature coefficient TC of resistance Resistors that are closely matched and have a low TC will minimize variations in the voltage reference due to temperature One should also be sure to use a decoupling capacitor 0 1 uF at the node where Veer is generated 5V R1 2 5kQ R2 2 5 T Figure 7 Midsupply Reference DIFFERENTIAL TESTING The test circuit shown in TPC 13 is used for measuring the dif ferential distortion of the AD8018 A single ended test signal is applied to the inverting input of the AD8138 differential driver with the noninverting input grounded Applying the differential output of the AD8138 through 100 Q resistors serves to isolate the inputs of the AD8018 differential driver and provide a well balanced low distortion input signal The differential load Rr of the AD8018 can be set to the equivalent of the line imped ance reflected through a transfor
13. Out of Band 144 kHz to 500 kHz 12 5 Q Pime 13 dBm 82 dBc Input Noise Voltage f 100 kHz 4 5 5 nVVHz Input Noise Current f 100 kHz Inputs 1 pANHz 100 kHz Inputs 10 pANHz Crosstalk f 1 MHz G 2 74 DC PERFORMANCE Input Offset Voltage 1 15 mV Tin to Tax 17 mV Input Offset Voltage Match 0 1 2 6 mV Transimpedance Vout 2 V p p RL 5 Q 830 2000 kQ Tyan to Tax 700 kQ INPUT CHARACTERISTICS Input Resistance Input 10 Input 125 Q Input Capacitance Input 1 pF Input Bias Current 0 3 8 pA Tin to Tax 14 pA Input Bias Current Match 0 1 5 5 pA Tmn to Tmax 8 pA Input Bias Current 1 1 5 Tin to Tax 2 5 pA Input Bias Current Match 0 1 0 5 pA Tmn to Tmax 1 pA CMRR Vw 2V to 4V 51 54 dB Input CM Voltage Range 1 2 3 8 V OUTPUT CHARACTERISTICS Cap Load 30 Overshoot 1000 pF Output Resistance Frequency 100 kHz PWDNI PWDNO 1 0 2 Q Output Voltage Swing 100Q 0 16 to 4 87 V Rr 50 0 5 to 4 5 V Linear Output Current SFDR lt 85 dBc f 100 kHz 10 Q 350 400 mA Short Circuit Current 1000 mA POWER SUPPLY Supply Current Amp PWDNI 1 PWDNO 1 9 10 mA Tyan to Tax 11 4 mA STBY Supply Current Amp PWDNI 0 PWDNO 1 or 4 5 5 1 mA PWDNI 1 PWDNO 0 4 5 5 1 mA SHUTDOWN Supply Current Amp PWDNI 0 PWDNO 0 0 3 0 55 mA Operating Range Single Supply 3 3 8 V Power Supply Rejection Ratio AVs t1V 60 66 dB Tin to Tax 56 dB Power Supply Rejection Ratio 1V 52 55 dB Tyan to
14. er ADS 10 14 3 C4 6 7 9 3 10 uF 16 V size Tantalum chip capacitor ADS 4 7 6 C14 17 19 1 Ferrite bead with 22 wire ADS 48 1 1 L5 1 10 Q 5 3 0 W metal oxide power resistor D K P10W 3BK ND 6 0 5 1 8 W 1206 size chip resistor ADS 3 18 88 C11 12 R20 21 30 31 2 10 0 Q 1 1 8 W 1206 size chip resistor ADS 3 18 120 R3 4 2 49 9 1 1 8 W 1206 size chip resistor ADS 3 14 26 R11 15 5 100 01 1 8 W 1206 size chip resistor ADS 3 18 40 R 8 14 25 26 32 2 2 49 KQ 1 1 8 W 1206 size chip resistor ADS 3 18 71 R16 17 3 750 Q 1 1 8 W 1206 size chip resistor ADS 3 18 8 R2 18 19 2 10 0 0 1 0805 size chip resistor ADS 3 36 5 R33 34 2 10 0 1 1 8 W 1206 size chip resistor ADS 3 18 119 R24 and 29 4 Test Point Black GND ADS 12 18 44 TP23 26 GND 2 Test Point Brown ADS 12 18 59 TP4 5 3 Test Point Red ADS 12 18 43 17 19 4 Test Point Orange ADS 12 18 60 1 2 10 11 1 Test Point Yellow ADS 12 18 32 TP3 2 Test Point Blue ADS 12 18 62 TP6 8 2 Test Point Green ADS 12 18 61 TP7 9 1 2 x 5 pin strips 1 4 of a 20 pin Samtek SIP strip socket ADS 11 2 14 T1 1 2 Pos GRAY term blk 25 161 0253 Newark 51F4106 ADS 12 19 10 TBI 2 4 0 1 inch ctr shunt Berg 65474 001 ADS 11 2 38 JP1 4 2 2 pin gold male header 0 1 inch ctr Berg 69157 102 ADS 11 2 37 JP1 2 4 50 Q BNC pc mount Telegartner JO1001A1944 ADS 12 6 22 53 6
15. for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices PIN CONFIGURATIONS 8 Lead SOIC Thermal Coastline 14 Lead TSSOP NC AD8018AR Vs OUT2 IN2 IN2 PWDNO DGND NC NC NO CONNECT PRODUCT DESCRIPTION The AD8018 is intended for use in single supply 5 V xDSL modems where high output current and low distortion are essential to achieve maximum reach The dual high speed amplifiers are capable of driving low distortion signals to within 0 5 V of the power supply rail Each amplifier can drive 400 mA of current into 10 Q differential while maintaining 82 dBc out of band SFDR The AD8018 is available with flexible standby and shutdown modes Two digital logic bits PWDNI and PWDNO may be used to put the AD8018 into one of three modes full power standby outputs low impedance and shutdown outputs high impedance Fabricated with ADI s high speed XFCB eXtra Fast Comple mentary Bipolar process the high bandwidth and fast slew rate of the AD8018 keep distortion to a minimum while dissipat ing a minimum of power The quiescent current of the AD8018 is low 9 mA amplifier The AD8018 drive capability comes compact 8 lead Thermal Coastline SOIC and 14 lead TSSOP packages Low distortion rail to rail output voltage and high current drive in smal
16. jacent subband or harmonics of other subbands Conventional methods of expressing the output signal integrity of line drivers such as single tone harmonic distortion or THD two tone InterModulation Distortion IMD and third order intercept IP3 become significantly less meaningful when amplifiers are required to process DMT and other heavily modulated waveforms A typical ADSL upstream DMT signal can contain as many as 27 carriers subbands or tones of QAM signals MultiTone Power Ratio MTPR is the relative difference between the measured power in a typical subband at one tone or carrier versus the power at another subband spe cifically selected to contain no QAM data In other words a selected subband or tone remains open or void of intentional power without a QAM signal yielding an empty frequency bin MTPR sometimes referred to as the empty bin test is typically expressed in dBc similar to expressing the relative difference between single tone fundamentals and second or third harmonic distortion components Measurements of MTPR are typically made on the line side or secondary side of the transformer 11 AD8018 POWER dBm 0 50 100 150 FREQUENCY kHz Figure 9 DMT Waveform in the Frequency Domain MTPR versus transformer turns ratio is depicted in TPC 21 and covers a variety of line power ranging from 12 dBm to 14 dBm As the turns ratio increases the driver hybrid can deliver more undistor
17. l packages make the AD8018 ideal for use in low cost USB PCMCIA and PCI Customer Premise Equip ment for ADSL SDSL VDSL and proprietary xDSL systems Both models will operate over the temperature range 40 C to 85 C 0 01 Figure 2 Single Supply Voltage Differential Drive Circuit for xDSL Applications One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2000 AD801 8 SPEC CATI 0 NS 25 C V 5 V 100 Rr Rg 750 unless otherwise noted Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vour lt 0 4 V p p Rp 5 Q 40 50 MHz G 1 Vour lt 0 4 V p p Ry 1000 100 130 MHz G 2 Vout lt 0 4V p p RL 50 35 40 MHz G 2 Vour lt 0 4 V p p Rp 1000 80 100 MHz 0 1 dB Bandwidth Vour 0 4 V p p 1000 10 MHz Large Signal Bandwidth Vout 4 V p p G 2 80 MHz Slew Rate Noninverting Vour 4 V p p 300 V ps Rise and Fall Time Noninverting Vour 2 V p p 5 5 ns Settling Time 0 1 Vour 2 V p p Rz 1000 25 ns NOISE HARMONIC PERFORMANCE Distortion Vout 6 V p p Differential Second Harmonic 100 kHz Ry 10 Q 89 94 500 kHz 10 Q 61 63 dBc Third Harmonic 100 kHz R 10 Q 86 89 500 kHz 10 Q 74 77 dBc MTPR In Band 25 kHz to 138 kHz 12 5 Q Pime 13 dBm 70 dBc SFDR
18. ly and deliver ing a total of 16 dBm 13 dBm to the line and 3 dBm to the matching network into 12 5 Q 100 Q reflected back through a 1 4 0 transformer plus back termination the power is 261 mW 40 mW 301 mW Using these calculations and a of 115 C W for the TSSOP package and 100 C W for the SOIC Tables III and IV show junction temperature versus power delivered to the line for sev eral supply voltages Table III Junction Temperature vs Line Power and Operating Voltage for TSSOP 85 C VsUPPLY Pune 5 6 7 8 13 115 122 129 136 14 117 125 132 140 15 119 127 136 144 16 121 130 139 148 17 123 133 143 153 18 125 136 147 158 Table IV Junction Temperature vs Line Power Operating Voltage for SOIC Tamg 85 C VsupPLY PLINE dBm 5 6 7 8 13 111 117 123 129 14 113 119 126 133 15 115 122 129 136 16 116 124 132 140 17 118 127 136 144 18 120 130 139 149 Running the AD8018 at voltages near 8 V can produce junction temperatures that exceed the thermal rating of the TSSOP pack ages and should be avoided The shaded areas indicate junction temperatures greater than 150 C LAYOUT CONSIDERATIONS As is the case with all high speed applications careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic Proper RF design technique is mandatory The PCB should have a ground plane
19. mer The AD9632 converts the differential output voltage back to a single ended signal The differential to single ended converter using the AD9632 has an attenuation of 26 dB and is wired with precision resis tors to optimize the balance of differential input signal The resulting smaller output signal can be easily measured using a 50 Q spectrum analyzer AD8018 This circuit requires significant power supply bypassing The AD8018 operates a split supply in this circuit The bypassing technique shown in TPC 13 utilizes a 220 UF tantalum capacitor and a 0 1 uF ceramic chip capacitor in parallel connected from the positive to negative supply and a 10 UF tantalum and 0 1 uF ceramic chip capacitor in parallel connected from each supply to ground The capacitors connected between the power supplies serve to minimize any voltage ripples that might appear at the supplies while sourcing or sinking any large differential current The large capacitor has a pool of charge instantly available for the AD8018 to draw from thus preventing any erroneous dis tortion results POWER DISSIPATION It is important to consider the total power dissipation of the AD8018 in order to properly size the heat sink area of an application Figure 8 is a simple representation of a differential driver With some simplifying assumptions we can estimate the total power dissipated in this circuit If the output current is large compared to the quiescent current comp
20. ne line Assuming that the maximum low distortion output swing available from the AD8018 line driver on a 5 V supply is 4 V and taking into account the power lost due to the termination resistance a step up transformer with turns ratio of 4 0 or greater is needed In the simplified differential drive circuit shown in Figure 2 the AD8018 is coupled to the phone line through a step up trans former with a 1 4 turns ratio R1 and R2 back termination or line matching resistors each 3 1 100 Q 2 42 where 100 Q is the approximate phone line impedance The total dif ferential load for the AD8018 including the termination resistors is 12 5 Even under these conditions the AD8018 provides low distortion signals to within 0 5 V of the power rails REV 0 Stability Enhancements The CPE bridge hybrid circuit presents a complex impedance to the drive amplifiers particularly when transformer parasitics are factored in To ensure stable operation under the full range of load conditions a series R C network Zoebel Network should be connected between each amplifier s output and ground The recommended values are 10 Q for the resistor and 1 nF for the capacitor to create a low impedance path to ground at frequen cies above 16 MHz see Figure 2 R33 and R34 are added to improve common mode stability Receive Channel Considerations A transformer used at the output of the differential line driver to step up the differential out
21. o voltage clipping of the signal TxDAC is a trademark of Analog Devices Inc a 2 VOLTS 3 0 25 02 15 1 0 0 05 0 0 05 10 15 02 TIME ms Figure 10 DMT Signal in the Time Domain Generating DMT Signals At this time DMT modulated waveforms are not typically menu selectable items contained within AWGs Even using AWG software to generate DMT signals AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the D A converters and output drivers used by AWG manufacturers Similar to evaluating single tone distortion performance of an amplifier MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver under evaluation Generating DMT signals can be accom plished using a Tektronics AWG 2021 equipped with Option 4 12 24 bit TTL Digital Data Out digitally coupled to Analog Devices AD9754 a 14 bit TxDAC buffered by an AD8002 amplifier configured as a differential driver Note that the DMT waveforms available on the Analog Devices website http www analog com or similar WFM files are needed to produce the digital data required to drive the TxDAC from the optional TTL Digital Data output of the AWG2021 REV 0 AD8018 TP23 TP24 TP25 TP26 U2 DECOUPLING DNI DO NOT INSTALL R13 DNI Figure 11 EVAL Board Schematic Figure
22. of Maximum Power Dissipation vs Temperature ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8018 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING r ESD SENSITIVE DEVICE REV 0 AD8018 Typical Performance Characteristics 7500 7500 150 100 50 OUTPUT VOLTAGE mV 100 VSO 10 V TPC 1 Single Ended Test Circuit 50 100 150 200 250 300 350 400 450 500 TIME ns TPC 2 Small Signal Step Response OUTPUT VOLTAGE V o 2 3 50 100 150 200 250 300 350 400 450 500 TIME ns TPC 3 Large Signal Step Response NV VHz RTI INoisE PA VHz 10 100 1k 10k 100k 1M FREQUENCY Hz TPC 4 Inoise and Vnoise vs Frequency 3k 2 5k 2k 0 0 1 5k OUTPUT IMPEDANCE 1 0 500 1 1
23. put voltage to the line has the inverse effect on signals received from the line A voltage reduction or attenuation equal to the inverse of the turns ratio is realized in the receive channel of a typical bridge hybrid The turns ratio of the transformer may also be dictated by the ability of the receive circuitry to resolve low level signals in the noisy twisted pair tele phone plant Higher turns ratio transformers effectively reduce the received signal to noise ratio due to the reduction in the received signal strength The AD8022 a dual amplifier with typical RTI voltage noise of only 2 5 nV VHz and a low supply current of 4 mA amplifier is recommended for the receive channel DMT Modulation MultiTone Power Ratio MTPR and Out of Band SFDR ADSL systems rely on DMT modulation to carry digital data over phone lines DMT modulation appears in the frequency domain as power contained in several individual frequency subbands sometimes referred to as tones or bins each of which is uniformly separated in frequency A uniquely encoded Quadra ture Amplitude Modulation QAM like signal occurs at the center frequency of each subband or tone See Figure 9 for an example of a DMT waveform in the frequency domain and Figure 10 for a time domain waveform Difficulties will exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal s from other subbands regardless of whether the corruption comes from an ad
24. rovide CPE ADSL on a single 5 V supply The AD8018 may be used in transformer coupled bridge hybrid cir cuits to drive modulated signals including Discrete MultiTone DMT upstream to the central office Evaluation Board The AD8018ARU EVAL evaluation board circuit in Figure 12 offers the ability to evaluate the AD8018 in a typical xDSL bridge hybrid circuit The receiver circuit on these boards is typically unpopulated Requesting samples of the AD8022AR with the AD8018ARU EVAL board will provide the capability to evaluate the AD8018ARU along with other Analog Devices products in a typi cal transceiver circuit The evaluation circuits have been designed to replicate the CPE side analog transceiver hybrid circuits The circuit mentioned above is designed using a one transformer transceiver topology including a line receiver line driver line matching network an RJ11 jack for interfacing to line simulators and transformer coupled inputs for single ended to differential input conversion AC coupling capacitors of 0 01 uF C8 and C10 in combina tion with 10 resistors R24 and R25 will form a zero frequency at 1 6 KHz Transformer Selection Customer premise ADSL requires the transmission of a 13 dBm 20 mW DMT signal The DMT signal can have a crest factor as high as 5 3 requiring the line driver to provide peak line power of 27 5 dBm 560 mW 27 5 dBm peak line power translates into a 7 5 V peak voltage on the 100 Q telepho
25. ted power due to higher output current capability Significant degradation of MTPR will occur if the output of the driver swings to the rails causing clipping at the DMT voltage peaks Driving DMT signals to such extremes not only compro mises in band MTPR but will also produce spurs that exist outside of the frequency spectrum containing the desired DMT power Out of band spurious free dynamic range SFDR can be defined as the relative difference in amplitude between these spurs and a tone in one of the upstream bins Compromising out of band SFDR is equivalent to increasing near end cross talk NEXT Regardless of terminology maintaining out of band SFDR while reducing NEXT will improve the overall performance of the modems connected at either end of the twisted pair TPC 21 shows how SFDR varies versus transformer turns ratio for line power ranging from 12 dBm to 14 dBm As line power increases or turns ratio decreases SFDR degrades The power contained in the spurs can be measured relative to the power contained in a typical upstream carrier and is expressed in dBc as SFDR similar to MTPR The supply voltage of the driver can also affect SFDR As the supply voltage is increased voltage swing is increased as well resulting in the ability to deliver more power to the line with out sacrificing performance This can be seen in TPC 22 Less undistorted power is available when lower turns ratio transform ers are used due t
26. ut Voltage vs Frequency 12 7500 7500 6 Vour 500 L N 15 18 100k 1M 10M 100M 1G FREQUENCY Hz TPC 11 Small Signal Frequency Response 10 20 30 STANDBY 1 0 or 0 1 40 50 1 1 FULL POWER 60 G Vg 2 5V 1000 70 100k 1M 10M 100M 1G FREQUENCY Hz TPC 12 CMRR vs Frequency Full Power and Standby Mode AD8018 60 E Vg 2 5V 7 96kQ 4020 G 4 70 fo 100kHz V 6V z OUT 80 VSIGIN 5000 p 2ND HARMONIC 500 A 3 90 E In ec 3RD HARMONIC E i 100 Ve T 110 5 10 100 LOAD RESISTANCE TPC 13 Differential Test Circuit TPC 16 Differential Distortion vs RLoap Vout 6V p p 100 Mg PWDN 1 0 1 1 Vg 2 5V 100 G 4 fg 100kHz PWDN 1 0 1 1 2ND HARMONIC 3RD HARMONIC DIFFERENTIAL DISTORTION dBc DIFFERENTIAL DISTORTION dBc 0 01 0 1 1 0 FREQUENCY MHz OUTPUT VOLTAGE Volts TPC 14 Differential Distortion vs Frequency TPC 17 Differential Distortion vs Peak to Peak Output Voltage Vg 2
27. uting the dissipa tion in the output devices and adding it to the quiescent power dissipation will give a close approximation of the total power dissipation in the package A factor 0 6 1 corrects for the slight error due to the Class A B operation of the output stage It can be estimated by subtracting the quiescent current in the output stage from the total quiescent current and ratioing that to the total quiescent current For the AD8018 0 833 Vs Vs Figure 8 Simplified Differential Driver Remembering that each output device dissipates for only half the time gives a simple integral that computes the power for each device 1 2Vo MIL Vox L total supply power can then be computed as 4 vs Wo Vor PU a Io Vs Pour L In this differential driver Vo is the voltage at the output of one amplifier so 2 Vo is the voltage across Rz which is the total impedance seen by the differential driver including back ter mination Now with two observations the integrals are easily evaluated First the integral of Vo is simply the square of the rms value of Vo Second the integral of Vo is equal to the average rectified value of Vo sometimes called the Mean Aver age Deviation or MAD It can be shown that for a DMT signal the MAD value is equal to 0 8 times the rms value 10 1 Pror 4 0 8 Vo rms Vs Vo rms xX 2 0 Vs Pour E For the AD8018 operating on a single 5 V supp
28. zi8gAD8018fithv ANALOG DEVICES 9 V Rail to Rail High Output Current XDSL Line Drive Amplifier AD8018 FEATURES Ideal xDSL Line Drive Amplifier for USB PCMCIA or PCI Based Customer Premise Equipment CPE The AD8018 provides maximum reach on 5 V supply driving 16 dBm of power into a back terminated transformer coupled 100 O while maintaining 82 dBc of out of band SFDR Rail to Rail Output Voltage and High Output Current Drive 400 mA Output Current into Differential Load of 10 Q 8 V p p Low Single Tone Distortion 86 dBc Worst Harmonic 6 V p p into Differential 10 100 kHz Low Noise 4 5 nV Hz Voltage Noise Density 100 kHz Out of Band SFDR 82 dBc 144 kHz to 500 kHz Rioap 12 5 O Pune 13 dBm Low Power Operation 3 3 V to 8 V Power Supply Range Two Logic Bits for Standby and Shutdown Low Supply Current of 9 mA Amplifier Typ Current Feedback Amplifiers High Speed 130 MHz Bandwidth 3 dB 300 V ps Slew Rate APPLICATIONS xDSL USB PCI PCMCIA Cards Consumer DSL Modems Twisted Pair Line Driver SFDR dBc 4 6 8 10 12 14 16 18 Pune dBm Figure 1 Out of Band SFDR vs ADSL Upstream Line Power Vs 5 V N 4 Turns 144 kHz to 500 kHz See Evaluation Board Schematics in Figure 11 REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor
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