National MF10 Universal Monolithic Dual Switched Capacitor Filter handbook
Contents
1. e n A 4 PLANE 0 004 0 014 0 009 0 013 TET ay a 0 050 0 014 0 020 0 102 gt 0 076 0 050_ 0 356 1 I M e STP 0 229 0 330 ALL LEAD TIPS 10 406 1 270 1 270 0 356 0 508 TYP ALL LEADS TYP ALL LEADS TYP 0 008 typ 0 203 M20B REV A Molded Package Small Outline M Order Number MF10ACWM or MF10CCWM NS Package Number M20B 19 MF 10 Universal Monolithic Dual Switched Capacitor Filter Physical Dimensions inches millimeters Continued 1 013 1 040 25 73 28 42 0 092 X 0 030 2 337 X 0762 0 032 0 005 MAX DP 0 813 0 127 En RAD PIN NO 1 IDENT 0 260 10 005 8 604 0 127 PIN NO 1 uud aes OPTION 1 n mum m EE MIN 0 300 0 320 OPTION 2 7 620 8 128 NOM E 0 060 LEE ee MI 0130 0 005 dd 3302 0 127 1 851 Iz 4 0 145 0 200 gt 3683 5080 95 5 0 009 0 015 90 0 004 a 0221 0385 25 0308 t 0n 0 100 0 010 Dainiai i es 0 125 0 140 0 508 aoso 0 005 251020254 0 018 0 003 gos 3a MIN ops 0 00 1 524 0 127 0 457 0 076 0 015 1016 ase ass 108 N20A REV G 20 Lead Molded Dual In Line Package N Order Number MF10ACN or MF10CCN NS Package Number N20A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CO2. a Hop Honp 0 707 Hopp GAIN V V fe fp fi to fu f LOG SCALE TL H 10399 6 b fo f LOG SCALE TL H 10399 8 b PHASE DEG I E es i Veo emn f LOG SCALE TL H 10399 9 a H 2 Hup s x s2 220 wo fe fo X 1 fp fo x t l Hop Hopp X FIGURE 3 2nd Order High Pass Response 1 HM EUR Q 402 wO Hoer g S Hpp s sod s2 og Q o fo fo ttf mq fo 7 un 1 12 fL folza Mag 1 1 12 tto a5 JG 1 wo 2rfo tto V 1 gi A e 202 202 1 Hop Holp X 4 J x us av to t LOG SCALE b TL H 10399 10 1 0 Definitions of Terms continued GAIN V V How s oo Hn s 90 s2 390 4 wo Hon amp 4S 3 0 707 Hon uon ano se SWR x fu fL 45 i e t fi fo fh fu fo fy LEA TTC 2Q f LOG SCALE f LOG SCALE TL H 10399 11 TL H 10399 12 fh fo zs x 4 a b FIGURE 4 2nd Order Notch Response i _ a Hap e5 E a Hoe s 222 oc z 2 180 Hap s os REM RE ES s2 a eo 360 fo fo f LOG SCALE 1 LOG SCALE TL H 10399 13 TL H 10399 14 a b FIGURE 5 2nd Order All Pass Response a Bandpass b Low Pass c High Pass 20 20 0 9 0 10 10 10 EEES 0 i
3. Hopp Q Hoi p Hong VHon1 Hon2 TL H 10399 18 TL H 10399 19 In Mode 3 the feedback loop is closed around the input summing amplifier the finite GBW product of this op amp causes a slight Q enhancement If this is a problem connect a small capacitor 10 pF 100 pF across R4 to provide some phase lead FIGURE 10 MODE 3 10 2 0 Modes of Operation continued MODE 3a HP BP LP and Notch with External Op Amp See Figure 11 f R2 f R2 fo CLK x or CLK x 100 R4 50 R4 R3 R2 c OE a R4 R2 R2 Horr 7g R3 HoBP TR R4 HoLP RI fork Rh NAT f notch frequency 4 or n note ITequency 7 100 VR so VR Hon gain of notch at R R f fo Q H 9H JI Oo s OLP Rh OHP Rg Hni gain of notch asf 0 R X HoLp l ta 2 E s 3 gain of notch asi ll R 9 x H Bh OHP MODE 4 Allpass Bandpass Lowpass Outputs See Figure 12 fo center frequency fork _ CLK AORTA 100 50 f center frequency of the complex zero fo fo R3 9 BwW Rz R3 Qz quality factor of complex zero pair AT For AP output make R1 R2 f R2 Hoap Allpass gain ao f fa Ho_p Lowpass gain as f 0 ll m N VL ll N R1 Hopp Bandpass gain at f fo R3 a amp 1 2 R2 R1 R2 Circuit Dynamics Hopp Hoip X Q Hoap 1 Q Due to the sampled data nature
4. R2 CONUM Hoip Lowpass gain asf 0 um Q R2 R3 Hote 1 HoLP peak Q X Hop for high Q s Hopp Bandpass gain at f fo R3 R1 HopPi p3 H Notch output gainas 9 aR ON put g f gt foK 2 Ri HogPz 1 Non Inverting Circuit Dynamics Hogp1 Q Note Vy should be driven from a low impedance lt 1 kN source R2 Na Sta BPa LPa TL H 10399 16 TL H 10399 17 FIGURE 8 MODE 1a 2 0 Modes of Operation continued MODE 2 Notch 2 Bandpass Lowpass fnotch lt fo MODE 3 Highpass Bandpass Lowpass Outputs See Figure 9 See Figure 10 fo center frequency fcik R2 fcik R2 ERI CE fo x f X fcLK E X35 fork R2 100 R4 r H 100 V R4 50 R4 Q quality factor of the complex pole pair fcLK fcLK R2 R3 f or SG notch 100 gg R4 R2 Q quality factor of the complex pole pair f R2 TAD EnS PERSE Hopp Highpass Gain ast fo _ JR27R4 1 R1 Ra R8 R3 Hopp Lowpass Gain atr fo i HoLp Lowpass output gain as f 0 R1 R2 R1 R4 OE H Lo s Gai f 0 E R2 R4 1 OLP TOWpASS aan as R1 B tput gain at f fo R3 R1 R2 H Hopp angpass ou pu gain a o Circuit dynamics LHP Hon Notch output gain as f 0 R4 Hop _ R2 Ri Hopp Houp X Holp X Q R2 R4 1 HoLP peak Q X Ho p for high Q s f H Q X Hopp for high Q s Hong Notch output gain asi gt fax R2 R1 OHP peal One for high Q s Filter dynamics
5. 0 0t g g g A 00 707 10 zm gai 0 05 e 5 o 1 20 20 0 02 30 30 40 40 0 1 05 1 2 5 10 01 02 05 10 20 50 10 01 02 05 10 2 5 10 FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz d Notch 20 10 0 10 9 8 EJ 4 0 5 Ej Zot 0 2 2 5 i E 20 0 65 S 30 40 01 02 05 10 2 5 10 0 1 02 1 2 5 10 FREQUENCY Hz FREQUENCY Hz TL H 10399 15 FIGURE 6 Response of various 2nd order filters as a function of Q Gains and center frequencies are normalized to unity 2 0 Modes of Operation fo R3 The MF10 is a switched capacitor sampled data filter To fully describe its transfer functions a time domain approach Q BW R2 is appropriate Since this is cumbersome and since the MF10 closely approximates continuous filters the following discussion is based on the well know frequency domain quality factor of the complex pole pair BW the 3 dB bandwidth of the bandpass output Each MF10 can produce a full 2nd order function See Ta Circuit dynamics ble for a summary of the characteristics of the various Hopp modes Hote a YX Hosp Holp X Q MODE 1 Notch 1 Bandpass Lowpass Outputs fnotch fo See Figure 7 ll Hon X Q HoLP peak Q X Hop for high Q s fo center frequency of the complex pole pair fcik fcLk MODE 1a Non Inverting BP LP See Figure 8 Fee Olmos 100 50 in foLK foLk i i i 100 50 fnotch center frequency of the imaginary zero pair fo p
6. 300 400 500 600 700 800 9001000 CLOCK FREQUENCY kHz CHANGE POSITIVE OUTPUT SWING V CHANGE POSITIVE OUTPUT SWING V 6 4 6 2 6 0 5 8 5 6 5 4 5 2 5 0 48 4 6 44 42 40 3 8 3 6 0 30 0 25 0 20 0 15 0 10 0 05 0 00 70 05 70 10 70 15 tk 10k Positive Output Voltage Swing vs Load Resistance N AP HP Output Ty 25 C TTT r 6 5 VOLT SUPPLIES 16 0 VOLT SUPPLIES 5 VOLT SUPPLIES 5 0 VOLT SUPPLIES 5 VOLT SUPPLIES 100k 1M LOAD RESISTANCE 0 Positive Output Swing vs Temperature 5 5 2 85 15 TEMPERATURE C Q Deviation vs Temperature Vg 25V NOMINAL Q 10 0 MODE 1 1 fp 250 kHz 5 5 25 85 025 TEMPERATURE C fcLk fo Deviation vs Temperature Vg 25V NOMINAL Q 10 0 MODE 1 fek 500 kHz 1 5 5 2 85 15 TEMPERATURE C CHANGE CROSSTALK dB NEGATIVE OUTPUT SWING V CHANGE Resistance N AP HP Output 5 tk 10k E E 70 SRSHSRSES 10 Negative Output Voltage Swing vs Load Ill 4 75 0 VOLT SUPPLIES 5 5 VOLT SUPPLIES WW 6 0 VOLT SUPPLIES 100k 1M LOAD RESISTANCE 0 Crosstalk
7. CLK ratio Note 7 The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply These are the worst case conditions Note 8 Typicals are at 25 C and represent most likely parametric norm Note 9 Tested limits are guaranteed to National s AOQL Average Outgoing Quality Level Note 10 Design limits are guaranteed but not 100 tested These limits are not used to calculate outgoing quality levels Note 11 Human body model 100 pF discharged through a 1 5 kQ resistor Typical Performance Characteristics CHANGE NEGATIVE OUTPUT SWING V POWER SUPPLY CURRENT mA CHANGE Power Supply Current vs Power Supply Voltage 80 90 100 110 120 130 140 POWER SUPPLY VOLTAGE V Negative Output Swing vs Temperature Vg 5V d G BANDPASS AND LOWPASS A R 2 5 0k0 5 15 02 85 13 TEMPERATURE 9C Q Deviation vs Temperature Vs 5V NOMINAL Q 10 0 MODE 1 5 15 25 8 13 TEMPERATURE C Q Deviation vs Clock Frequency 100 200
8. by the filter gain should therefore be less When Sag is tied to V Vosa will approximately halve The than 8 Vp p DC offset at the BP output is equal to the input offset of the lowpass integrator Vosa The offsets at the other outputs depend on the mode of operation and the resistor ratios as described in the following expressions Note that if the filter Q is high the gain at the lowpass or highpass outputs will be much greater than the nominal filter gain Figure 6 As an example a lowpass filter with a Q of 15 3 0 Applications Information continued Mode 1 and Mode 4 Voss VOS N Vos 5 1 Hore DET Vos BP Voss Vos LP Vos N Vos2 Mode 1a A v Vos N INV BP 1 V O83 os QJ Vosi o Vos INV BP Vosa VOS LP Vos N INV BP Vos2 N APMP s Mode 2 and Mode 5 Vos N Vos BP Vos LP Mode 3 Vos HP Vos BP Vos LP R 1 vos x aq Rp O81 1 R2 R4 V 1 Voss OS21 R4 R2 Qi R2 R4 Rp R1 R3 R4 Vos3 Vos N Vos2 Vos2 Voss R4 R4 Vos d Vos2 p R4 Vos3 R3 Rp R1 R2 R3 FIGURE 19 MF10 Offset Voltage Sources 5V SUPPLY TL H 10399 31 FIGURE 20 Method for Trimming Vos TL H 10399 30 16 3 0 Applications Information continued For most applications the outputs are AC coupled and DC offsets are not bothersome unless large signals are applied to the filter input However larger o
9. the 2nd order filter Q is measured at the bandpass outputs of the MF10 and is equal to fo divided by the 3 dB bandwidth of the 2nd order bandpass filter Figure 1 The value of Q determines the shape of the 2nd order filter responses as shown in Figure 6 Qz the quality factor of the second order complex zero pair if any Qz is related to the allpass characteristic which is written So Hos s 224 oc Qz Hap s m s2 c op Q O where Qz Q for an all pass response Hopp the gain in V V of the bandpass output at f fo Ho tp the gain in V V of the lowpass output as f 0 Hz Figure 2 Hopp the gain in V V of the highpass output as f fcik 2 Figure 3 How the gain in V V of the notch output as f 0 Hz and as f fci k 2 when the notch filter has equal gain above and below the center frequency Figure 4 When the low frequency gain differs from the high frequency gain as in modes 2 and 3a Figures 11 and 8 the two quantities below are used in place of How Honi the gain in V V of the notch output as f 0 Hz Howz the gain in V V of the notch output as f fci y 2 1 0 Definition of Terms continued FIGURE 1 2nd Order Bandpass Response FIGURE 2 2nd Order Low Pass Response g 90 Hopp 45 0 707 Hopp 3 0 Ei z 45 90 f fo du 1 LOG SCALE TL H 10399 5 a z Hop s 9 z Hop Ei z 0 707 Hove w 90 180 p fe f LOG SCALE TL H 10399 7
10. LP 1 20 BP 2 19 The second order lowpass bandpass SA B 6 N AP HP 3 18 and notch allpass highpass outputs These outputs can typically sink 1 5 mA and source 3 mA Each output typically swings to within 1V of each supply INV 4 17 The inverting input of the summing op amp of each filter These are high im pedance inputs but the non inverting in Vat 7 Vp 8 put is internally tied to AGND making INVA and INVg behave like summing junctions low impedance current in puts S1 5 16 S1 is a signal input pin used in the all pass filter configurations see modes 4 and 5 The pin should be driven with a source impedance of less than 1 kQ If S1 is not driven with a signal it should be tied to AGND mid supply Va 14 Vp 13 f Deviation of SLX vs Nominal Q O 10 Se oo oo Vt i5V zx Ty 25 C E Vpiu2 Y z amp 10 a Li x o SH 20 3 0 0 1 10 10 100 NOMINAL Q TL H 10399 3 This pin activates a switch that connects one of the inputs of each filter s second summer to either AGND SA g tied to V or to the lowpass LP output SA p tied to V This offers the flexibility needed for configuring the filter in its various modes of operation Analog positive supply and digital posi tive supply These pins are internally connected through the IC substra
11. RPORATION As used herein 1 Life support devices or systems are devices or 2 Systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor Corporation Europe 1111 West Bardin Road Fax 49 0 180 530 85 86 N Arlington TX 76017 Email cnjwge tevm2 nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 180 530 85 85 Fax 1 800 737 7018 English Tel 49 0 180 532 78 32 Frangais Tel 49 0 180 532 93 58 Italiano Tel 49 0 180 534 16 80 National Semiconductor Japan Ltd Tel 81 043 299 2309 Fax 81 043 299 2408 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel 852 2737 1600 Fax 852 2736 9960 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
12. able with clock to center frequency ratios of 50 or 100 It will be necessary fi to adjust E externally From Table we see that Mode 3 0 can be used to produce a low pass filter with resistor adjust able center frequency In most filter designs involving multiple second order stages it is best to place the stages with lower Q values ahead of stages with higher Q especially when the higher Q is greater than 0 707 This is due to the higher relative gain at the center frequency of a higher Q stage Placing a stage with lower Q ahead of a higher Q stage will provide some attenuation at the center frequency and thus help avoid clip ping of signals near this frequency For this example stage A has the lower Q 0 785 so it will be placed ahead of the other stage For the first section we begin the design by choosing a convenient value for the input resistance R44 20k The absolute value of the passband gain Hoj pA is made equal 13 3 0 Applications Information continued to 1 by choosing R44 such that R44 HojpA Ria Ria 20k If the 50 100 CL pin is connected to mid sup ply for nominal 100 1 clock to center frequency ratio we find R24 by foa2 529 2 R4A 5 2 X 104 ioLK 100 2 1000 2 Raa Qa VRoaRaa 0 785 5 6 x 103 x 2 X 104 8 3k Roa 5 6k and N AP HP 5V 10 CLOCK IN TUL fei 100 kHz a CLK CLKg M The resistors for the second section are found in a s
13. ains of various filter outputs are inverting and adjustable by resistor ratios Number of Adjustable Mode BP LP HP N AP Resistors feLk fo Notes 1 ii 3 No 2 May need input buffer 1a Hospi Q Holp 1 2 No Poor dynamics for Hogp2 1 high Q 2 3 Yes above fo_ 50 or fci k 100 Universal State Variable 4 yos Filter Best general purpose mode As above but also includes ds if Ygs resistor tuneable notch Gives Allpass response with 4 3 No Hoap 1andHoijp 2 5 x x 4 Gives flatter allpass response than above if R4 R2 0 02R4 6a i 3 Single pole 2 6b Holp 1 2 Single Pole Heros ee OLP2 R2 3 0 Applications Information The MF10 is a general purpose dual second order state variable filter whose center frequency is proportional to the frequency of the square wave applied to the clock input foLk By connecting pin 12 to the appropriate DC voltage the filter center frequency fo can be made equal to either fcLk 100 or fci 50 fo can be very accurately set within 6 by using a crystal clock oscillator or can be easily varied over a wide frequency range by adjusting the clock frequency If desired the fc fo ratio can be altered by external resistors as in Figures 9 10 11 13 14 and 15 The filter Q and gain are determined by external resistors All of the five second order filter types can be built using
14. cifications do not apply when operating the device beyond its specified operating conditions Note 2 When the input voltage Viy at any pin exceeds the power supply rails Vin lt V or Vin gt V the absolute value of current at that pin should be limited to 5 mA or less The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four Note 3 The maximum power dissipation must be derated at elevated temperatures and is dictated by T Ju Ax 0 4 and the ambient temperature TA The maximum allowable power dissipation at any temperature is Pp Tymax TA 0JA or the number given in the Absolute Maximum Ratings whichever is lower For this device Tymax 125 C and the typical junction to ambient thermal resistance of the MF10ACN CCN when board mounted is 55 C W For the MF10AJ CC this number increases to 95 C W and for the MF10ACWM CCWM this number is 66 C W Note 4 The accuracy of the Q value is a function of the center frequency fo This is illustrated in the curves under the heading Typical Performance Characteristics Note 5 Vos1 Vos and Vogs refer to the internal offsets as discussed in the Applications Information Section 3 4 Note 6 For 5V supplies the dynamic range is referenced to 2 82V rms 4V peak where the wideband noise over a 20 kHz bandwidth is typically 200 uV rms for the MF10 with a 50 1 CLK ratio and 280 uV rms for the MF10 with a 100 1
15. ckage 10 sec 260 C J Package 10 sec 300 C SO Package Vapor Phase 60 Sec 215 C Infrared 15 Sec 220 C See AN 450 Surface Mounting Methods and Their Effect on Product Reliability Appendix D for other methods of soldering surface mount devices Operating Ratings note 1 Temperature Range MF10ACN MF10CCN MF10CCWM MF10ACWM MF10CCJ MF10AJ Tmin lt TA X Tmax 0 C lt Ta lt 70 C 0 C lt Ta lt 70 C 40 C lt Ta lt 85 C 55 C TA lt 125 C 5 00V unless otherwise specified Boldface limits MF10ACN MF10CCN MF10ACWM MF10ccwm MF10CCJ MF10AJ Symbol Parameter Conditions Typical feno en Typical Linn yid Units Note 8 imit imit Note 8 imit imit Note 9 Note 10 Note 9 Note 10 V V Supply Voltage Min 9 9 V Max 14 14 V Is Maximum Supply Clock Applied to Pins 10 amp 11 8 12 12 8 12 mA Current No Input Signal fo Center Frequency Min fo X Q lt 200 kHz 0 1 0 2 0 1 0 2 Hz Range Max 30 20 30 20 kHz folk Clock Frequency Min 5 0 10 5 0 10 Hz Range Max 1 5 40 15 40 MHz fcik fo 50 1 Clock to MF10AQ 10 Vpin12 5V 0 2 06 06 0 2 1 0 Center Frequency MF10c Mode 1 foLk 250 kHz Ratio Deviation 0 2 t1 5 t1 5 0 2 t1 5 96 fcLk fo 100 1 Clock to MF10AQ 10 Vpini2 OV 0 2 0 6 06 502 1 0 Center Frequenc
16. e which yields optimum filter operation By tying this pin high a 50 1 clock to fil ter center frequency ratio is obtained Tying this pin at mid supplies i e analog ground with dual supplies allows the fil ter to operate at a 100 1 clock to cen ter frequency ratio When the pin is tied low i e negative supply with dual sup plies a simple current limiting circuit is triggered to limit the overall supply cur rent down to about 2 5 mA The filtering action is then aborted This is the analog ground pin This pin should be connected to the system ground for dual supply operation or bi ased to mid supply for single supply op eration For a further discussion of mid supply biasing techniques see the Appli cations Information Section 3 2 For optimum filter performance a clean ground must be provided CLKA 10 CLKB 11 50 100 CL 12 AGND 15 1 0 Definition of Terms fcuk the frequency of the external clock signal applied to pin 10 or 11 fo center frequency of the second order function complex pole pair fo is measured at the bandpass outputs of the MF10 and is the frequency of maximum bandpass gain Figure 1 fnotcn the frequency of minimum ideally zero gain at the notch outputs fz the center frequency of the second order complex zero pair if any If f is different from fo and if Qz is high it can be Observed as the frequency of a notch at the allpass output Figure 10 Q quality factor of
17. either section of the MF10 These are illustrated in Figures 1 through 5 along with their transfer functions and some relat ed equations Figure 6 shows the effect of Q on the shapes of these curves When filter orders greater than two are desired two or more MF10 sections can be cascaded 3 1 DESIGN EXAMPLE In order to design a second order filter section using the MF10 we must define the necessary values of three param eters fo the filter section s center frequency Ho the pass band gain and the filter s Q These are determined by the characteristics required of the filter being designed As an example let s assume that a system requires a fourth order Chebyshev low pass filter with 1 dB ripple unity gain at DC and 1000 Hz cutoff frequency As the system order is four it is realizable using both second order sec tions of an MF10 Many filter design texts include tables that list the characteristics fo and Q of each of the second or der filter sections needed to synthesize a given higher order filter For the Chebyshev filter defined above such a table yields the following characteristics foa 529 Hz Qa 0 785 fog 993 Hz Qg 3 559 For unity gain at DC we also specify Hoa 1 Hog 1 The desired clock to cutoff frequency ratio for the overall filter of this example is 100 and a 100 kHz clock signal is available Note that the required center frequencies for the two second order sections will not be obtain
18. ffset voltages will cause clipping to occur at lower AC signal levels and clipping at any of the outputs will cause gain nonlinearities and will change fo and Q When operating in Mode 3 offsets can become excessively large if R2 and R4 are used to make fcLk fo significantly higher than the nominal value espe cially if Q is also high An extreme example is a bandpass filter having unity gain a Q of 20 and fci k fo 250 with pin 12 tied to ground 100 1 nominal RA R2 will therefore be equal to 6 25 and the offset voltage at the lowpass out put will be about 1V Where necessary the offset voltage can be adjusted by using the circuit of Figure 20 This allows adjustment of Vos which will have varying effects on the different outputs as described in the above equations Some outputs cannot be adjusted this way in some modes how ever Vos gp in modes 1a and 3 for example 3 5 SAMPLED DATA SYSTEM CONSIDERATIONS The MF10 is a sampled data filter and as such differs in many ways from conventional continuous time filters An im portant characteristic of sampled data systems is their ef fect on signals at frequencies greater than one half the sampling frequency The MF10 s sampling frequency is the same as its clock frequency If a signal with a frequency greater than one half the sampling frequency is applied to the input of a sampled data system it will be reflected to a frequency less than one half the sampling frequency Th
19. fo will be small If the error is too large for a specific application use a mode that allows adjustment of the ratio with external resistors It should also be noted that the product of Q and fo should be limited to 300 kHz when fo 5 kHz and to 200 kHz for fo gt 5 kHz 100 1 50 1 TL H 10399 32 FIGURE 21 The Sampled Data Output Waveform 17 18 Physical Dimensions inches millimeters 0 985 0 025 25 019 gt 0 535 RAD 0 220 0 310 5 588 7 874 y JE E E e e T ed e 0 005 0 020 0 127 0 508 RAD TYP 0 037 0 005 0 940 0 127 Um 0 290 0 320 0 127 1 397 0 127 0 020 0 060 P 7 366 8 128 GLASS SEALANT 0 508 1 524 9 200 5 080 MAX 95 15 0 008 0 012 0 203 0 305 Ja 0 310 0 410 0 060 0 018 0 003 7 874 10 41 1 524 0 457 0 076 MAX BOTH ENDS 0 100 010 2 5403 0 254 420A REV M 20 Lead Ceramic Dual In Line Package J Order Number MF10AJ or MF10CCJ NS Package Number J20A 0 496 0 512 112 598 13 005 P 20 19 18 17 16 15 14 13 12 11 A 0 394 0 419 10 008 10 643 30 TYP LEAD NO 1 i IDENT u I Y YOU Q E rie mac E ae 0 010 max 0 254 0 291 0 299 7 391 7 595 0 010 0 025 H 0 093 0 104 0 254 0 737 9 m core 8 MAX TYP ALL LEADS i 0 004 0 012 Lj 0 102 0 305 NR HEHHHHEHE US Eu
20. imilar fashion Rip 20k Rap Rip 20k fog 993 Rog 08 20k L 19 7k 4B tcLi 100 2 1000 2 Rag Qg RegRa4g 3 559 1 97 X 104x 2x 104 70 6k The complete circuit is shown in Figure 16 for split 5V power supplies Supply bypass capacitors are highly recom mended Vour N AP HPp ING 50 100 CL 11 TL H 10399 25 FIGURE 16 Fourth Order Chebyshev Low Pass Filter from Example in 3 1 X 5V Power Supply 0V 5V TTL or 5V 5V CMOS Logic Levels 10V CLOCK IN TUL fg 100 kHz EE CK CLKp i N AP HPg INVg 50 100 CL TL H 10399 26 FIGURE 17 Fourth Order Chebyshev Low Pass Filter from Example in 3 1 Single 10V Power Supply 0V 5V TTL Logic Levels Input Signals Should be Referred to Half Supply or Applied through a Coupling Capacitor 3 0 Applications Information continued vt vt 10V ve Q 1 2 LM358 c TYPICAL VALUES 2k R 100k d 0 1 uF lt C lt 470 pF g T TL H 10399 28 TUH AOSSS ef b Voltage Regulator a Resistive Divider with b 9 9 TL H 10399 29 Decoupling Capacitor c Operational Amplifier with Divider vt FIGURE 18 Three Ways of Generating PE for Single Supply Operation 3 2 SINGLE SUPPLY OPERATION 10 will have a 20 dB peak in its amplitude response at fo If The MF10 can also operate with a single ended power sup the nominal gain of the filter Ho p is equal to 1 the gain at ply Figure 17 shows the example filte
21. is also important that the half supply dynamics which relate the Q and the gains at the various reference present a low impedance to the clock frequency outputs These should be consulted to determine peak cir So at very low clock frequencies the regulator or op amp cuit gains and maximum allowable signals for a given appli approaches may be preferable because they will require cation smaller capacitors to filter the clock frequency The main 3 4 OFFSET VOLTAGE power supply voltage should be clean preferably regulated and bypassed with 0 1 uF The MF10 s switched capacitor integrators have a higher equivalent input offset voltage than would be found in a 3 3 DYNAMIC CONSIDERATIONS typical continuous time active filter integrator Figure 19 The maximum signal handling capability of the MF10 like shows an equivalent circuit of the MF10 from which the out that of any active filter is limited by the power supply volt put DC offsets can be calculated Typical values for these ages used The amplifiers in the MF10 are able to swing to offsets with SA g tied to V are within about 1V of the supplies so the input signals must be Vost opamp offset 5 mV kept small enough that none of the outputs will exceed Vos2 150 mV 50 1 300 mV 100 1 these limits If the MF10 is operating on 5V for example Vosa 70 mV 50 1 140 mV 100 1 s os3 m m the outputs will clip at about 8 Vp p The maximum input iw voltage multiplied
22. of the filter a slight mismatch of fz and fo occurs causing a 0 4 dB peaking around fo of the allpass filter amplitude response which theoretically should be a straight line If this is unaccept able Mode 5 is recommended NOTCH OUT EXTERNAL OPAMP TL H 10399 20 FIGURE 11 MODE 3a TL H 10399 21 FIGURE 12 MODE 4 2 0 Modes of Operation continued MODE 5 Numerator Complex Zeros BP LP See Figure 13 fo JUR REO 1 B2 x folk R4 100 R4 50 R2 f Rif fz f x GLK ofi x CK R4 100 R4 50 Q JTF RoR x P3 R2 R3 Qz 1 RVRAX z i RI Ho gain at C Z output as f 0 Hz R2 R4 R1 R1 R2 R4 H e a fcik R2 0 2 gain at CZ output asf gt SRT R2 R3 Hopp Ri 1 x R2 4 s R4 E R2 R4 RI MODE 6a Single Pole HP LP Filter See Figure 14 cutoff frequency of LP or HP output R2 fork 4 R2 fai R3 100 R3 50 fc Hop HoHP MODE 6b Single Pole LP Filter Inverting and Non In verting See Figure 15 fc cutoff frequency of LP outputs R2 fork R2 fci r R3 100 R3 50 Hoip1 1 non inverting HoiP2 TL H 10399 22 TL H 10399 23 FIGURE 14 MODE 6a po LPANINV Vis LPa INY TL H 10399 24 FIGURE 15 MODE 6b 2 0 Modes of Operation continued TABLE I Summary of Modes Realizable filter types e g low pass denoted by asterisks Unless otherwise noted g
23. r with a single ended fo will be 10 The maximum input signal at fo must therefore power supply Vat and Vpt are again connected to the be less than 800 mVp p when the circuit is operated on positive power supply 8V to 14V and Va and Vp are 5V supplies connected to ground The Agnp pin must be tied to V 2 Also note that one output can have a reasonable small volt for single supply operation This half supply point should be age on it while another is saturated This is most likely for a very clean as any noise appearing on it will be treated as circuit such as the notch in Mode 1 Figure 7 The notch an input to the filter It can be derived from the supply volt output will be very small at fo so it might appear safe to age with a pair of resistors and a bypass capacitor Figure apply a large signal to the input However the bandpass will 18a or a low impedance half supply voltage can be made have its maximum gain at fo and can clip if overdriven If using a three terminal voltage regulator or an operational one output clips the performance at the other outputs will amplifier Figures 18b and 18c The passive resistor divider be degraded so avoid overdriving any filter section even with a bypass capacitor is sufficient for many applications ones whose outputs are not being directly used Accompa provided that the time constant is long enough to reject any nying Figures 7 through 75 are equations labeled circuit power supply noise It
24. s AM F1OffthN ES MF 10 Universal Monolithic Dual Switched Capacitor Filter General Description The MF10 consists of 2 independent and extremely easy to use general purpose CMOS active filter building blocks Each block together with an external clock and 3 to 4 resis tors can produce various 2nd order functions Each building block has 3 output pins One of the outputs can be config ured to perform either an allpass highpass or a notch func tion the remaining 2 output pins perform lowpass and band pass functions The center frequency of the lowpass and bandpass 2nd order functions can be either directly depen dent on the clock frequency or they can depend on both clock frequency and external resistor ratios The center fre quency of the notch and allpass functions is directly depen dent on the clock frequency while the highpass center fre quency depends on both resistor ratio and clock Up to 4th order functions can be performed by cascading the two 2nd order building blocks of the MF10 higher than 4th order functions can be obtained by cascading MF10 packages System Block Diagram waf TO AGND INVe _ QN vationat Semiconductor VA N AP HPA Sta BPA Vo Va N AP HPg Sip BPg December 1994 Any of the classical filter configurations such as Butter worth Bessel Cauer and Chebyshev can be formed For pin compatible device with improved performance refer to LMF100 datasheet Features m Ea
25. sy to use W Clock to center frequency ratio accuracy 0 6 W Filter cutoff frequency stability directly dependent on external clock quality W Low sensitivity to external component variation m Separate highpass or notch or allpass bandpass low pass outputs W fo X Q range up to 200 kHz W Operation up to 30 kHz m 20 pin 0 3 wide Dual In Line package m 20 pin Surface Mount SO wide body package Connection Diagram Surface Mount and Dual In Line Package TL H 10399 4 Top View Order Number MF10AJ or MF10CCJ See NS Package Number J20A Order Number MF10ACWM or MF10CCWM See NS Package Number M20B Order Number MF10ACN or LPs MF10CCN 1L H 10399 1 See NS Package Number N20A 91995 National Semiconductor Corporation TL H 10399 RRD B30M115 Printed in U S A 193JI4 40312ede payoyMs Jeng IUYPIOUON es4eAruf OLAN Absolute Maximum Ratings note 1 If Military Aerospace specified devices are required please contact the National Office Distributors for availability and specifications Supply Voltage V V7 Voltage at Any Pin Input Current at Any Pin Note 2 Package Input Current Note 2 Power Dissipation Note 3 Storage Temperature ESD Susceptability Note 11 Electrical Characteristics v Semiconductor Sales 14V Vt 0 3V v 0 3V 5mA 20 mA 500 mW 150 C 2000V apply for Twin to Tmax all other limits TA Ty 25 C 5 00V and V Soldering Information N Pa
26. te and therefore VA and Vp should be de rived from the same power supply Source They have been brought out separately so they can be bypassed by separate capacitors if desired They can be externally tied together and by passed by a single capacitor Analog and digital negative supplies The same comments as for Va and Vp apply here Pin Descriptions continued LSh 9 Level shift pin it accommodates various clock levels with dual or single supply operation With dual 5V supplies the MF10 can be driven with CMOS clock levels 5V and the LSh pin should be tied to the system ground If the same supplies as above are used but only TTL clock levels derived from OV to 5V supply are available the LSh pin should be tied to the system ground For single supply operation OV and 10V the Va_ Vp pins should be connected to the system ground the AGND pin should be biased at 5V and the LSh pin should also be tied to the system ground for TTL clock levels LSh should be biased at 5V for CMOS clock lev els in 10V single supply applications Clock inputs for each switched capaci tor filter building block They should both be of the same level TTL or CMOS The level shift LSh pin description dis cusses how to accommodate their lev els The duty cycle of the clock should be close to 50 especially when clock frequencies above 200 kHz are used This allows the maximum time for the internal op amps to settl
27. us an input signal whose frequency is fs 2 100 Hz will cause the system to respond as though the input frequency was f 2 100 Hz This phenomenon is known as alias ing and can be reduced or eliminated by limiting the input Signal spectrum to less than fs 2 This may in some cases require the use of a bandwidth limiting filter ahead of the MF10 to limit the input spectrum However since the clock frequency is much higher than the center frequency this will often not be necessary Another characteristic of sampled data circuits is that the output signal changes amplitude once every sampling peri od resulting in steps in the output voltage which occur at the clock rate Figure 21 If necessary these can be smoothed with a simple R C low pass filter at the MF10 output The ratio of fci to fc normally either 50 1 or 100 1 will also affect performance A ratio of 100 1 will reduce any aliasing problems and is usually recommended for wide band input signals In noise sensitive applications however a ratio of 50 1 may be better as it will result in 3 dB lower output noise The 50 1 ratio also results in lower DC offset voltages as discussed in Section 3 4 The accuracy of the fc_K fo ratio is dependent on the value of Q This is illustrated in the curves under the heading Typical Performance Characteristics As Q is changed the true value of the ratio changes as well Unless the Q is low the error in fci k
28. utput BP LP Pins R 5k 4 25 3 8 3 8 4 25 3 8 V Voltage Swing N AP HP PinR 3 5k 425 38 3 8 t425 3 6 V GBW Op Amp Gain BW Product 2 5 2 5 MHz SR Op Amp Slew Rate y 7 V us Dynamic Range Vpini2 5V Note 6 fcLk fo 50 3 ss ge Voini2 OV pin12 fci k fo 100 E 80 aB Isc Maximum Output Short Source 20 20 mA Circuit Current Note 7 Sink 3 0 3 0 mA Logic Input Characteristics Boldface limits apply for Tmin to Tmax all other limits TA Ty 25 C MF10ACN MF10CCN MF10ACWM MF10CCWM PAE Oe MEO Parameter Conditions Tested Design Tested Design Units Typical Typical Limit Limit Note 9 Note 10 Limit Limit Note 8 Note 9 Note 10 Note 8 CMOS Clock Min Logical 1 V 45V V 5V 3 0 43 0 3 0 v Input Voltage Max Logical o VLsh OV 3 0 3 0 3 0 v Min Logical 1 V 10V V OV 8 0 8 0 8 0 v Max Logical o VLsh 5V 20 2 0 2 0 v TTLClock Min Logical 1 v 45V V 5V 20 42 0 2 0 v Input Voltage Max Logical o VLsh OV 0 8 0 8 0 8 v Min Logical 1 V 10V V OV 20 2 0 2 0 v Max Logical 0 VLSh 0 8 0 8 0 8 v Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical spe
29. vs Clock Frequency Vg 5V Ty 25 C 50 1 MODE 1 NOMINAL Q 10 0 100 1 100 500 1000 CLOCK FREQUENCY kHz Q Deviation vs Clock Frequency Vg 45V Th 25 C NOMINAL Q 10 0 MODE 1 100 1 100 200 300 400 500 600 700 800 900 1000 CLOCK FREQUENCY kHz fcLk fo Deviation vs Temperature Vg SV NOMINAL Q 10 0 5 15 25 85 125 TEMPERATURE 9C TL H 10399 2 Typical Performance Characteristics continued fcik fo Deviation fcLk fo Deviation vs Clock Frequency vs Clock Frequency 040 16 035 Vg 5V nme 030 Ty 25 C z 025 l T pACAE 020 NOMINAE Q 10 0 NOMINAL Q 10 0 uo 015 hee 1 vy 19 wore 1 2 010 ELK ago 9 f om fo jm 4 M paz 6 p o8 8 x 2 7005 S oig 040 0 15 02 020 0 025 030 02 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000 CLOCK FREQUENCY kHz CLOCK FREQUENCY kHz Ls fcik Deviation of CLE vs Nominal Q O 05 Yt 2i5V e T 25 C z Veniz 70V Z 00 PIN12 amp gt 4 705 wl 10 01 10 10 100 NOMINAL Q Pin Descriptions
30. y MF10C Mode 1 fck 500 kHz Ratio Deviation 0 2 t1 5 t1 5 0 2 t1 5 96 Clock Feedthrough Q 10 10 10 mV Mode 1 Q Error MAX Q 10 Vpint2 5V Note 4 Mode 1 fok 250kHz PS 6 6 2 p 10 Voi 0V pin12 h fek 500kHz 2 8 id sev se i HoLP DC Lowpass Gain Mode 1 R1 R2 10k 0 0 2 0 2 0 0 2 dB Vos DC Offset Voltage Note 5 5 0 20 20 50 20 mV Vos2 DC Offset Voltage Min Vpini2 5V Save Vt 150 185 185 150 185 V Note 5 fcLk fo 50 m Max fcLk fo 85 85 85 Min Vpini2 5V Sass V pin12 A B 70 70 mV Max fcLk fo 50 Vos3 DC Offset Voltage Min Vpin12 5V All Modes 70 100 100 70 100 Note 5 fcuk fo 50 mV Max CLK O 20 20 20 Vos2 DC Offset Voltage Vpint2 0V SA B Vt Note 5 feLk fo 100 300 300 mV Vpint2 OV Sava V pint2 A B Note 5 foLK fo 100 149 140 my Vosa DC Offset Voltage Vpini2 OV All Modes J Note 5 fcuk fo 100 140 140 mV Electrical Characteristics continued v 5 00V and v 5 00V unless otherwise specified Boldface limits apply for Tyin to Tmax all other limits TA Ty 25 C MF10ACN MF10CCN MF10ACWM MFioccwm MF10CCJ MF10AJ Symbol Parameter Conditions i Tested Design Tested Design Units Typical ium fi Typical SA Y Note 8 Limit Limit Note 8 Limit Limit Note 9 Note 10 Note 9 Note 10 Vour Minimum O
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National MF10 Universal Monolithic Dual Switched Capacitor Filter handbook