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XILINX Spartan-3 FPGA Family: Complete Data Sheet

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1. 352000 FG676 XC3S2000 FG676 XC3S1000 XC3S1500 XC3S4000 Pin XC3S1000 XC3S1500 XC3S4000 Pin Bank Pin Name Pin Name Pin Name Number Type Bank Pin Name Pin Name Pin Name Number 10106 3 10106 3 AB25 O 3 10155423 10193543 L35N3 20 O NC 9 10107 3 10107 3 3 L35P 3 10_L35P_3 IO_L35P_3 P19 O 107 10 AA23 1O L38N L38N 3 L38N 22 VO NC 9 1010843 1010843 Y23 VO 3 1 8 3 L38P3 Pei O 3 IOLOBP3 08 22 L39N IO L39N 10139 3 24 NC 9 LO9N_3 1 0109 3 AA26 3 L39P L39P IO_L39P_3 P23 3 0 _LogP_3 IO 109 3 AA25 VREF 10140 3 10_L40N_3 IO LAON 3 P26 VREF VREF 3 _ 3 VREF 3 VREF3 VREF 3 Wei 3 40 3 IOL40P 3 IOL40P 3 P
2. XC3S2000 FG676 352000 FG676 XC3S1000 XC3S1500 XC3S4000 Pin XC3S1000 XC3S1500 XC3S4000 Pin Bank Pin Name Pin Name Pin Name Number Bank Pin Name Pin Name Pin Name Number 1012840 1012840 IO L28N0 Fi2 O 1 lOl09P 1 109 1 1 9 1 E20 128 128 128 0 12 lO 1 IO_L10N_1 L1ON 1 1104 1 A20 VREF 1012940 IO L29N_0 IO 2940 B12 VO VREF_1 VREF_1 VREF_1 Se ie ic 1 10 1 L10P 1 iO_LioP_1 B20 O 1013040 IO_L30N_ 0 G13 lO Tx 130 130 0 10_L30P_0 F13 uo 013 HS 0 10_L31P_0 IO 31 O lO 31 O0 C13 VREF veto etter VREF_0 VREF_O 1 10 115 1 IO_L15N1 IO L15N 1 19 lO 101324 0 L32N 0 L32N 0 GCLK 1 lOLI5P 1 115 _1 115 1 819 O GCLK7 GCLK7 GCLK7 1 IO_L16N_1 L16N 1 IO L16N 1 F18 0 IO Log 0 Id 0 1 0 1 L16P 1 L16P 1 L16P 1 618 1
3. Table 41 FG1156 Package Pinout Continued Table 41 FG1156 Package Pinout Continued FG1156 FG1156 XC3S4000 XC3S5000 Pin XC3S4000 XC3S5000 Pin Bank Pin Name Pin Name Number Bank Pin Name Pin Name Number Type 3 lO L11P 3 L11P 3 AF32 3 lO L33N 3 L33N W25 3 lO L12N 3 IO 1123 3 AE26 3 lO L33P 3 Y26 3 IO L12P 3 IO L12P 3 AF27 y o 3 lO L34N 3 lO L34N 3 W29 3 lO L13N 3 113 3 28 VREF 3 IO_L34P_3 L34P 3 W28 VREF VREF 3 VREF 3 VREF 3 VREF 3 3 lO L13P 3 L13P 3 AE27 3 lO L35N 3 lO L35N 3 W33 3 L14N 3 IO L14N 3 lO L35P 3 lO L35P 3 W32 3 L14P 3 L14P 3 AE29 3 lO L37N 3 lO L37N 3 V28 y o 3 lO L15N 3 lO L15N 3 AE32 3 lO L37P 3 lO L37P 3 V27 y o 3 lO L15P 3 L15P 3 1 3 lO L38N 3 lO L38N 3 3 L16N 3 IO L16N 3 AE34 3 lO L38P 3 lO L38P 3 V29 3 lO L16P 3 IO L16P 3 3 lO L39N 3 lO L39N 3 V32 3 lO 117 _3 lO L17N 3 AD26 3 lO L39P 3 lO L39P V31 3 lO L17P 3 1O_L17P_3 AD25 VREF 3 lO 140 3 L40N 3 V34 VREF VREF 3 VREF 3 VREF 3 VREF 3 3 lO L19N 3 IO L19N 3 AD34 3 lO L40P 3 lO L40P 3 V33
4. XC3S4000 FG900 XC3S4000 FG900 XC3S2000 XC3S5000 Pin XC3S2000 XC3S5000 Pin Bank Pin Name Name Number Type Bank Pin Name Pin Name Number Type 1 IO L25N 1 10125 1 C19 2 103 2 IO LOSP 2 D30 1 IO L25P 1 L25P 1 D19 2 1010442 O LOAN 2 E29 1 IO L26N 1 10 L26N 1 A19 2 104 2 JIO L04P_2 0 1 IO L26P 1 L26P 1 B19 2 105 2 10105 2 F28 1 IO L27N 1 L27N 1 F17 2 105 2 JIO 105 2 F29 1 IO L27P 1 L27P 1 G17 2 106 2 10 106 2 G27 1 IO 1284 1 L28N 1 B17 2 106 2 106 2 G28 1 IO L28P 1 L28P 1 C17 2 107 42 10 LOIN 2 G29 1 IO L29N 1 10129 1 J16 2 107 2 0 LO7P 2 G30 I O 1 IO L29P 1 L29P 1 K16 2 10108 2 O 108 2 G25 1 IO 13041 L30N 1 G16 2 108 2 108 2 24 1 IO L30P 1 1 H16 2 10109 2 109 2 H25 VREF 1 1 016 VREF VREF 2 VREF 2 VREF 1 VREF 1 2 109 2 O LOOP 2 H26 I O 1 IO L31P 1 1 E16 2 O L10N 2 H27 1 IO L32N 1 L32N 1 B16 GCLK 2 110 2 2 H28 GCLKS GCLKS 2 IOLI12N 2
5. XC3S400 XC3S400 XC3S1000 FG320 XC3S1000 FG320 XC3S1500 Pin XC3S1500 Pin Bank Pin Name Number Type Bank Pin Name Number Type 7 IO L34P 7 H3 GND 9 7 IO L35N 7 H1 GND U17 GND 7 IO L35P 7 H2 GND U2 GND 7 IO L39N 7 J1 GND V1 GND 7 IO L39P 7 J2 y o N A GND V13 GND 7 IO 140 7 VREF 7 J5 VREF N A GND V18 GND 7 IO L40P 7 J4 GND V6 GND 7 VCCO 7 F3 VCCO N A VCCAUX B12 VCCAUX 7 VCCO 7 H7 VCCO N A VCCAUX B7 VCCAUX 7 VCCO 7 J7 VCCO N A VCCAUX G17 VCCAUX NA GND N A VCCAUX G2 VCCAUX N A GND A13 GND N A VCCAUX M17 VCCAUX N A GND A18 GND N A VCCAUX M2 VCCAUX N A GND A6 GND N A VCCAUX U12 VCCAUX N A GND B17 GND N A VCCAUX 07 VCCAUX N A GND B2 GND N A VCCINT 12 GND C10 GND N A VCCINT F13 VCCINT N A GND C9 GND N A VCCINT F6 VCCINT N A GND F1 GND N A VCCINT F7 VCCINT N A GND F18 GND N A VCCINT G13 VCCINT N A GND G12 GND N A VCCINT G6 VCCINT N A GND G7 GND N A VCCINT M13 VCCINT N A GND H10 GND N A VCCINT M6 VCCINT N A GND H11 GND N A VCCINT N12 VCCINT N A GND H8 GND N A VCCINT N13 VCCINT N A GND H9 GND N A VCCINT N6 VCCINT N A GND J11 GND N A VCCINT 7 916 GND VCCAUX CCLK 15 CONFIG N A GND J3 GND VCCAUX DONE R15 CON
6. XC3S200 PQ208 XC3S200 PQ208 XC3S50 XC3S400 Pin XC3S50 XC3S400 Pin Bank Pin Name Pin Name Number Type Bank Pin Name Pin Name Number Type 5 lO L32N 5 L32N 5 P77 GCLK 7 lO L21P 7 21 7 12 GCLK3 GCLK3 7 lO 12247 10_L22N_7 16 5 IO L32P 5 L32P 5 P76 GCLK gt L22P 7 012227 P15 lo GCLK2 GCLK2 Seas 7 IO 1234 7 10123 7 19 E ee 7 IO L23P 7 123 7 P18 ETT EE 7 IO L24N 7 10124 7 21 O 6 IO LOIN 6 1O_LO1N_6 P52 DCI ia d VRP 6 VRP 6 7 L39N 7 P24 6 6 6 amp P51 DCI pez VRN 6 VRN 6 7 IO_L40N_7 140 7 27 6 IO L19N 6 10119 6 P48 VREF_7 VREF_7 6 lO 119 6 Lisp 6 P46 UO 7 IO 14007 140 7 P26 6 IO 1294 6 L20N 6 P45 7 VCCO 7 VCCO 7 P6 VCCO 6 IO L20P 6 L20P 6 P44 7 VCCO 7 VCCO 7 P23 VCCO 6 IOL21N 6 IO L21N 6 P43 GND GND P1 GND 6 IO L21P 6 L21P 6 P42 GND GND P186 GND 6 10122 6 IO L22N 6 P40 N A GND GND P195 GND 6 IO L22P 6 122 6 P39 N A GND GND P202 GND 6 IO L23N 6 L23N 6 P37 NA GND GND P163 GND 6 IO_L23P_6 123 6 P36 NA GND GND P170 GND 6 IO L24N 6 L24N 6 P35 VREF N A GND P179 GND VREF 6 VREF
7. XC3S200 PQ208 XC3S200 PQ208 XC3S50 XC3S400 Pin XC3S50 XC3S400 Pin Bank Pin Name Pin Name Number Type Bank Pin Name Pin Name Number Type 2 IO L23N 2 L23N 2 P141 VREF 4 _4 O VREF_4 P102 VREF VREF 2 VREF 2 4 IO LOIN 47 LOIN 4 P101 DCI 2 lO L23P 2 123 2 P140 VRP 4 VRP 4 2 IO L24N 2 10 L24N 2 P139 4 IO LO1P 4 1 101 4 P100 DCI 2 IO 24 2 124 2 138 VRN_4 VRN_4 4 lO L27N 4 L27N 4 P92 DUAL 2 IO LAON 2 IO L40N 2 P133 DIN DO DIN DO 2 IO L40P 2 10_L40P_2 P132 VREF VREF 2 VREF 2 4 D L27P 4 S L27P 4 P90 DUAL 2 VCCO 2 VCCO 2 P136 VCCO 4 IO L30N 4 L30N 4 P87 DUAL _2 2 153 VCCO D2 D2 IO LOIN 3 LOIN 3 P107 DCI 4 IO L30P 4 IO_L30P_4 P86 DUAL VRP 3 3 D3 D3 VRN_3 INIT_B INIT_B NC IO L17N P109 4 131 4 L31P 4 P81 DUAL 3 N C 9 lO L17P 3 P108 VREF DOUT BUSY DOUT BUSY VREF 3 4 IO L32N 4 L32N 4 P80 GCLK 3 IO L19N L19N 3 P113 GCLK1 GCLK1 3 IO L19P IO L19P 3 P111 4 lO L32P 4 L32P 4 P79 GCLK 3 OL20N3 12093 P115 O GCLKO GCLKO 3 120 32 12 3 P114 O o TWEPEOS 6005 P84 650 3 IOL2IN3 P117 O f CCOA VOCO 3 2
8. XC3S200 XC3S200 XC3S400 FT256 XC3S400 FT256 XC3S1000 Pin XC3S1000 Pin Bank Pin Name Number Type Bank Pin Name Number Type 5 VCCO_5 M8 VCCO 7 lO L22N 7 F2 y o 6 IO K1 7 lO L22P 7 F3 6 IO LO1N 6 VRP 6 R1 DCI 7 lO L23N 7 G5 6 IO LO1P 6 VRN 6 P1 DCI 7 lO L23P 7 F5 6 L16N 6 P2 7 lO L24N 7 G3 6 lO L16P 6 N3 7 lO L24P 7 G4 y o 6 lO L17N 6 N2 7 lO L39N 7 H3 6 lO 17 6 VREF 6 1 VREF 7 lO L39P 7 H4 y o 6 lO L19N 6 M4 7 lO L4ON 7 VREF 7 H1 VREF 6 lO L19P 6 M3 7 lO L40P 7 G1 y o 6 L20N 6 M2 7 VCCO 7 G6 vcco 6 lO L20P 6 M1 7 VCCO 7 H5 vcco 6 lO L21N 6 L5 7 VCCO 7 H6 vcco 6 2 6 14 GND 1 6 lO L22N 6 L3 GND A16 GND 6 lO L22P 6 L2 GND B2 GND 6 123 6 K5 GND 9 GND 6 lO L23P 6 K4 GND 15 GND 6 IO L24N 6 VREF 6 K3 VREF N A GND F6 GND 6 lO L24P 6 K2 GND 11 GND 6 L39N 6 J4 GND G7 GND 6 lO L39P 6 J3 GND G8 GND 6 L40N 6 J2 GND G9 GND 6 IO L40P 6 VREF 6 J1 VREF N A GND G10 GND 6 VCCO 6 J5 VCCO N A GND H2 GND 6 VCCO 6 J6 VCCO N A GND H7 GND 6 VCCO 6 K6 VCCO N A GND H8 GND 7 IO G2 GND H9 GND 7 IO LO1N 7 VRP 7 C1 DCI N A GND H10 GND 7 IO LO1P 7 VRN 7 B1 DCI N A GND J7 GND 7 lO
9. FG1156 FG1156 XC3S4000 XC3S5000 Pin XC3S4000 XC3S5000 Pin Bank Pin Name Pin Name Number Bank Pin Name Pin Name Number Type 2 10_L29N2 IO L29N 2 R24 2 2 VCCO_2 032 VCCO 2 OL29P2 O L29P 2 R25 2 2 2 H28 VCCO 2 10_L30N_2 10 1304 2 R28 2 vcco2 2 H32 VCCO 2 1 2 IO L30P 2 R29 2 VCCO_2 2 127 2 OLSIN2 1 2 R31 2 2 131 2 OLSIP2 1 1 _2 R32 2 VCCO_2 VCCO_2 N23 2 OL32N2 0 1324 2 R33 2 2 2 N29 VCCO 2 01 2 10 L32P 2 R34 gt 2 N33 VCCO 2 10_L33N_2 L33N 2 R26 2 _ 2 2 P23 VCCO 2 OL33P2 IO L33P 2 T25 2 2 2 R23 VCCO 2 0124 2 L34N 2 VREF 2 vcco2 2 R27 VCCO VREF 2 VREF 2 2 2 VCCO 2 VCCO 2 134 2 IO 134 2 T29 gt VCCO 2 2 Tal VCCO 2 OL35N2 L35N 2 T32 S 2 OL35P2 L35P 2 T33 lie lo ZU lo 2 01372 IO L37N 2 U27 lo Vas lo 2 13722 O L37P 2 U28 lo TA lo 2 013842 L38N 2 U29 3 1 0 101 3 AM34 DCI 2 1 8 2 IO 138 2 030 VRP 3 VRP 3 2
10. Table 34 FG676 Package Pinout Continued Table 34 FG676 Package Pinout Continued 352000 FG676 352000 FG676 XC3S1000 XC3S1500 XC3S4000 Pin XC3S1000 XC3S1500 XC3S4000 Pin Bank Pin Name Pin Name Pin Name Number Type Bank Pin Name Pin Name Pin Name Number 1 VCCO1 VCCO1 VCCO1 J6 2 124 2 24 2 L24P 2 K24 1 VCCO 1 VCCO K14 VCCO 2 10126 2 1012642 1264 2 K25 O gt INC 9 lO gt YO 2 126 2 126 2 126 2 26 2 LOIN 2 IO LOIN 2 IO LOIN 2 C25 DCI 2 10127 2 IO 1272 IOL2Z7N2 119 O VRP_2 VRP 2 VRP 2 2 127 2 IOL27P 2 IO L27P 2 L20 5 2 1 2 ae 228 G26 2 1012842 1012842 L28N 2 Lat VO IO 102 2 10 LO2N 2 LO2N 2 E23 ue UT RLNC ITO EET DE Uo 2 IOL129N2 1294 2 1294 2 125 2 10_LO3N_2 1O_LO3N_2 10_LO3N_2 025 VREF 2 129 2 lI0_L29P_2 I0_L29P_2 126 vo VREF 2 2 VREF 2 2 10131 2 2 1314 2 M19 2 1 2 03 2 1O_LO3P_2 026 O 2 31 2 2 2 M20 O 2 NC 9 LO5N2 IO LOSN2 E25 VO 2 2 IO L32N2 Mei O 2 105 2 IO 05 2 E26 O 2 132 2 132 2
11. XC3S4000 FG900 XC3S4000 FG900 XC3S2000 XC3S5000 Pin XC3S2000 XC3S5000 Pin Bank Pin Name Pin Name Number Type Bank Pin Name Pin Name Number Type 4 lO L15N 4 L15N 4 20 4 N C lO L33P 4 AJ25 4 IO L15P 4 IO L15P 4 AF20 4 L34N 4 AE25 4 IO L16N 4 116 4 AG20 4 IO L34P 4 AE24 4 lO L16P 4 L16P 4 AH20 4 L35N 4 AG24 O 4 lO L17N 4 1 0 117 4 AJ20 4 IO L35P 4 24 4 lO L17P 4 117 _4 20 4 138 4 AJ24 O 4 lO L18N 4 IO_L18N_4 AA19 4 L38P 4 AK24 O 4 IO L18P 4 IO L18P 4 AB19 4 VCCO 4 VCCO 4 Y17 VCCO 4 IO L19N 4 IO L19N 4 AC19 4 VCCO 4 VCCO 4 Y18 VCCO 4 L19P 4 L19P 4 AD19 4 4 VCCO 4 ADi8 VCCO 4 IO 12044 10120 4 19 4 VCCO 4 VCCO 4 AH18 VCCO 4 IO L20P 4 L20P 4 AF19 4 VCCO 4 VCCO 4 Y19 VCCO 4 lO L21N 4 IO L21N 4 AG19 4 VCCO 4 VCCO 4 AB20 VCCO 4 lO L21P 4 L21P 4 AH19 4 VCCO 4 VCCO 4 AD22 VCCO 4 IO L22N 4 L22N 4 AJ19 VREF 4 VCCO 4 VCCO 4 AH22 VCCO VREF 4 VREF 4 4 VCCO 4 VCCO 4 AF24 VCCO 4 IO L22P 4 IO L22P 4 AK19 4 VCCO 4 VCCO 4 AH26 VCCO 4 IO L23N 4 IO L23N 4 AB18 TET S 4 IO L23P 4 IO L23P 4 AC18 5 lO lO AB10 4 IO L24N 4 IO L24N 4 AE18
12. 5 5 5 m VCCINT VCCINT 2 ME m GCLK4 VCCINT VCCINT VCCINT VCCINT 1 0 VCCINT yo L32N 5 L32N_4 VCCINT VCCINT e x GCLK3 GCLK1 x s 5 0 ii 2 5 yo L32P 5 L32P 4 m GCLK2 1 0 1 0 Vo L15P 5 130 5 VREF 5 VREF 4 1293 4 1 0 1 0 Vo LO6P_5 LO6N 5 L10N 4 1 0 VO Vo L16P 5 VREF 4 L10P 4 109 4 1 0 Vo L16N 5 Vo LO9P 4 Bank 5 4 ds099 3 16 121103 Figure 10 FG320 Package Footprint top view 156 Unrestricted general purpose user I O DUAL Configuration pin then possible 29 VREF User or input voltage reference for user I O bank 16 DCI User or reference resistor input for B GCLK User I O or global clock buffer input 28 VCCO Output voltage supply for bank bank CONFIG Dedicated configuration pins 4 JTAG Dedicated JTAG port pins 12 VCCINT Internal core voltage supply 1 2V 0 unconnected pins this package 40 GND Ground VCCAUX Auxiliary voltage supply 2 5V 52 www xilinx com DS099 4 v1 7 August 19 2005 Product Specification 2 XILINX FG456 456 lead Fine pitch Ball Grid Array The 456 lead fine pitch ball grid array package FG456 supports four diff
13. Bank 1 17 18 19 20 21 22 vo A Right Half of Package L21N 1 L15N 1 E t p view O vO vo L17N1 B L21P_4 115 _1 vO Vo L20N 1 L17P 1 2 C D E L19P 1 L16N 1 L19N 1 F L18N 1 L16P 1 G L12N 2 H N vo J 2 G tn K vo VCCINT E L21N_2 L vO VCCINT VCCINT VCCINT L50N 2 _2 2 VCCINT vo N VCCINT P GND VCCINT R vo GND VCCINT Tov is _3 T VCCINT GND VCCINT VCCINT VCCINT VCCINT VCCINT Vo vO Vo vo 9 Exil 9 i Bank 3 VO vo vo vo 4262 4 123 _4 L13N_4 LOEN 4 L16P vo vo vo vo vo L29P_4 L23P_4 LosP 4 4 LooN 111 _3 LHN 1 0 Vo L14P 4 LTIN 4 vO 3 LO7N 3 CP IP OF gt gt OF WH gt gt lt vo vO Vo vo L24N 4 L15N 4 11 4 LO5N 4 Vo vo vO vo vo VREF 4 2 4 115 4 4 105 4 105 3 vO vO vO vo vo 106 4 LO2N 3 L16N 4 LO9P_4 VREF 4 LO2P 3 VREF 3 vO vO Vo L35P_4 L39N 4 L16P 4 L12N_4 LO6P 4 Vo vO VO PSA L28P_4 L25N_4 i a Lon a OA Se GCLK1 vo VO vo vO yo vo 10 L32P 4 GND GND L38P_4 LO1P 4 GND GND Cu L25P 4 L17P 4 LIP 4 LO7P 4 7 Bank 4 DS099 4 13b 121103 DS099 4 v1 7 Augus
14. Table 23 Recommended Number of Simultaneously Table 23 Recommended Number of Simultaneously Switching Outputs per Vcco GND Pair Switching Outputs per Vcco GND Pair Continued Package Package FT256 FT256 FG320 FG320 FG456 FG456 FG676 FG676 Signal Standard PQ FG900 Signal Standard PQ FG900 IOSTANDARD 100 144 208 132 FG1156 IOSTANDARD 100 144 208 132 FG1156 Singe EndedStandads 58 5 2 19 11 9 29 64 GTL 0 0 0 1 4 4 13 7 6 19 34 GTL_DCI 0 0 0 1 4 6 6 3 3 9 22 GTLP 0 0 0 1 4 8 6 3 3 9 18 GTLP_DCI 0 0 0 1 4 12 3 1 1 3 13 HSLVDCI_15 2 1 1 3 14 16 2 1 1 3 10 HSLVDCI_18 4 2 2 6 10 Fast 2 13 7 6 19 36 HSLVDCI_25 4 2 2 6 11 4 8 5 4 13 21 HSLVDCI_33 4 2 2 6 9 6 4 2 2 6 13 HSTL 1 3 1 1 5 17 8 4 2 2 6 10 DCI 3 1 1 5 17 12 2 1 1 3 9 HSTL III 2 1 1 3 7 16 2 1 1 3 6 HSTL III DCI 2 1 1 3 7 LVDCI 18 4 2 2 6 10 HSTL 18 4 2 2 6 17 LVDCI_DV2_18 4 2 2 6 10 HSTL_I_DCI_18 4 2 2 6 17 LVCMOS25 Slow 2 28 16 13 42 76 HSTL 18 2 1 1 3 9 4 13 7 6 19 46 HSTL 18 2 1 1 3 9 6 13 7 6 19 33 HSTL 18 2 1 1 3 8 8 6 3 3 9 24 HSTL Ill DCI 18 2 1 1 3 8 12 6 3 3 9 18 LVCMOS12 Slow 2 17 8 5 16 55 16 2 1 1 3 11 4 10 5 2 6 32 24 2 1 1 3 7 6 5 3 2 6 18 Fast 2 17 10 8 26 42 Fast 2 6 4 2 6 31 4 8 5 4 13 20 4 4 1 1 3 13 6 8 5
15. vO Maximuri All Possible I O Pins by Type Edge Bank DCI VREF 0 35 27 0 2 4 2 Top 1 35 27 0 2 4 2 2 31 25 0 2 4 0 Right 3 31 25 0 2 4 0 4 35 21 6 2 4 2 Bottom 5 35 21 6 2 4 2 6 31 25 0 2 4 0 Left 7 31 25 0 2 4 0 Table 33 User I Os Per Bank for XC3S1000 XC3S1500 and XC3S2000 FG456 Package Maximum All Possible I O Pins by Type Edge Bank DCI VREF 0 40 31 0 2 5 2 Top 1 40 31 0 2 5 2 2 43 37 0 2 4 0 Right 3 43 37 0 2 4 0 4 41 26 6 2 5 2 Bottom 5 40 25 6 2 5 2 6 43 37 0 2 4 0 Left 7 43 37 0 2 4 0 DS099 4 v1 7 August 19 2005 Product Specification www xilinx com 59 Spartan 3 FPGA Family Pinout Descriptions 2 XILINX FG456 Footprint Left Half of Package top view XC3S400 264 max user I O Unrestricted 196 general purpose user I O VREF User I O or input voltage reference for bank N C Unconnected pins for 69 XC3s400 351000 351500 XC3S2000 333 max user I O Unrestricted 261 general purpose user I O VREF User I O or input voltage reference for bank 36 N C No unconnected pins in this package All devices DUAL Configuration pin then possible user I O GCLK User I O or global clock buffer input DCI User I O or reference resistor input for bank configuration pins JTAG Dedicated JTAG
16. XC3S50 XC3S50 XC3S200 XC3S200 XC3S400 TQ144 Pin XC3S400 TQ144 Pin Bank Pin Name Number Type Bank Pin Name Number Type 5 IO L28N 5 D6 P47 DUAL 4 5 VCCO_BOTTOM P43 VCCO 5 IO L28P 5 D7 DUAL 4 5 VCCO BOTTOM P66 VCCO 5 IO 5 D4 P51 DUAL 6 7 VCCO LEFT P19 VCCO 5 lO 5 D5 P50 DUAL 6 7 VCCO LEFT P34 VCCO 5 L32N 5 GCLK3 P53 GCLK 6 7 VCCO LEFT P3 VCCO 5 IO L32P 5 GCLK2 52 GCLK N A GND P136 GND 6 IO LO1N 6 VRP 6 P36 DCI N A GND P139 GND 6 IO LO1P 6 VRN 6 P35 DCI N A GND P114 GND 6 L20N 6 P33 y o N A GND P117 GND 6 lO L20P 6 P32 yo N A GND P94 GND 6 IO L21N 6 P31 y o N A GND P101 GND 6 IO L21P 6 0 yo N A GND P81 GND 6 IO L22N 6 P28 y o N A GND P88 GND 6 IO L22P 6 P27 y o N A GND P64 GND 6 L23N 6 P26 y o N A GND P67 GND 6 lO L23P 6 P25 y o N A GND P42 GND 6 IO L24N 6 VREF 6 P24 VREF N A GND P45 GND 6 IO L24P 6 P23 yo N A GND P22 GND 6 IO L40N 6 P21 y o N A GND P29 GND 6 IO L40P 6 VREF 6 P20 VREF N A GND P9 GND 7 IO VREF 7 P4 VREF N A GND P16 GND 7 IO LO1N 7 VRP 7 P2 DCI N A VCCAUX P134 VCCAUX 7 IO LO1P 7 VRN 7 P1 DCI N A VCCAUX P120 VCCAUX 7 IO L20N 7 P6 y o N A VCCAUX P62 VCCAUX 7 IO L20P 7 P5 yo N A VCCAUX P48 VCCAUX 7 L21N 7 P8 y o N A VCCINT P133 VCCINT 7 lO L21P 7 P7 y o N A VCCINT P121 VCCINT 7 L22N 7 11 61 7 lO L22P 7 P10 y o N A VCCINT 49 7 123 7 1 VCCAUX P72 CONFIG 7 lO L23P 7 P12 yo VCCAUX
17. 2004 2005 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice DS099 3 v1 6 August 19 2005 Preliminary Product Specification www xilinx com 1 Spartan 3 FPGA Family DC and Switching Characteristics XILINX Table 1 Absolute Maximum Ratings Continued Symbol Description Conditions Min Max Units Vesp Electrostatic Discharge Voltage pins relative Human body XC3S50 1500 V meds Other 2000 Charged device model 500 Machine model 200 Ty Junction temperature 125 C TsoL Soldering temperature 220 C Storage temperature 65 150 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability The limits apply to both the DC and AC components of signals Simple application solutions are available that show how to handle overshoo
18. DS099 3 v1 6 August 19 2005 www xilinx com 21 Preliminary Product Specification Spartan 3 FPGA Family DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable l Os different signal standards call for different test condi tions Table 21 presents the conditions to use for each stan dard The method for measuring Input timing is as follows A sig nal that swings between a Low logic level of V and a High logic level of is applied to the Input under test Some standards also require the application of a bias voltage to the Vref pins of a given bank to properly set the input switching threshold The measurement point of the Input signal is commonly located halfway between and The Output test setup is shown in Figure 4 A termination voltage is applied to the termination resistor the other end of which is connected to the Output For each standard and generally take on the standard values recom mended for minimizing signal reflections If the standard does not ordinarily use terminations e g LVCMOS Table 21 Test Methods for Timing Measurement at l Os 2 XILINX LVTTL then is set to 1MQ to indicate an open connec tion and is set to zero The same measurement point that was used at the Input is also used at the Output FPGA Output 2 Raer 5
19. L39P 5 AE11 O 5 IO L22P 5 IO L22P 5 AN14 5 140 5 11 5 123 5 123 5 AF15 5 lO L40P_5 11 5 IO L23P 5 IO L23P 5 AE15 5 5 VCCO 5 13 VCCO 5 IO L24N 5 IO L24N 5 AJ15 y o 5 VCCO 5 VCCO 5 14 VCCO 5 IO L24P 5 IO L24P 5 AH15 5 5 5 15 VCCO 5 IO L25N 5 IO L25N 5 AM15 5 5 VCCO 5 16 VCCO 5 IO L25P 5 IO L25P 5 AL15 5 5 VCCO 5 AG11 VCCO 5 IO L26N 5 IO L26N 5 AP15 5 5 5 15 VCCO 5 IO L26P 5 IO L26P 5 AN15 1 0 5 VCCO_5 5 AH8 VCCO 5 IO L27N 5 IO L27N 5 AJ16 VREF 5 VCCO 5 VCCO 5 AJ13 VCCO VREF 5 VREF 5 5 VCCO 5 VCCO 5 AL11 VCCO 96 www xilinx com DS099 4 v1 7 August 19 2005 Product Specification 2 XILINX Spartan 3 FPGA Family Pinout Descriptions Table 41 FG1156 Package Pinout Continued Table 41 FG1156 Package Pinout Continued FG1156 FG1156 XC3S4000 XC3S5000 Pin XC3S4000 XC3S5000 Pin Bank Pin Name Pin Name Number Bank Pin Name Pin Name Number Type 5 VCCO_5 VCCO 5 AL16 VCCO 6 IO_L15P_6 IO L15P 6
20. NN T 5 NC 9 123 5 10_L23P_5 AE10 27 5 5 10124 5 10124 5 IO 12445 5 5 24 5 IO 124 5 24 5 Wii vi 5 125 5 1012545 10125 5 11 O C ONEA NONE 5 125 _5 25 5 IO 125 5 O VREF 6 6 5 1012645 IO 12645 11 6 IO Lo9P6 IO LO9P6 5 NC 9 OL26P5 26 5 11 O 6 NC 9 IOLIoN6 IOLIONG 5 10_L27N_5 L27N 5 10_L27N_5 12 VREF 6 6 L10P 6 Y1 5 VREF 5 VREF_5 6 10 L14N 6 IO LIAN 6 IO_L14N_6 W7 IO L27P 5 127 5 127 W12 O S olis IBS COMPRE We i L28N_5 128 5 L28N 5 ABI2 DUAL 6 1011646 1011646 IOL16N 6 V6 5 L28P 5 128 5 10_L28P_5 AA12 DUAL 6 116 6 IO_L16P_6 WS O D7 D7 D7 6 IOLI7N6 IO_L17N 6 VO L29N 5 L29N 5 IO L29N 5 AF12 VO 6 6 IO L17P 6 IO LI7P 6 VREF IO 129 5 L29P 5 L29P 5 AE12 VREF VBEF B 6 5 VREF 5 VREF 5 6 lOL19N 6 6 IO_LI9N6 W2 VO IO L30N 5 10130 5 L30N 5 13 VO 6 lOL19P 6 10 19 6 OLI9P6 Wi O IO L30P 5 L30P 5 L30P 5 W13 UO 6 120 6 10 12096 012096 V7 O IO L31N 5 1O_L31N_5 10_L31N_5 1 DUAL 6 12 6 10_L20P_6
21. 1 4 IOL16P 4 1 116 4 16 4 8 5 IO ABO O NC 1011744 ABI8 Vo 5 NC 9 0 O NC 9 18 Vo 5 10 11 VO NC 9 OLI8N4 1011844 018 1O 5 IO AD10 NC 9 18 4 AEI8 1O 5 ADi2 WO 4 LI9N 4 IO LI9N 4 LI9N 4 ACI7 O 5 UO 4 19 4 OLI9P 4 lOLI9P 4 17 5 IO Y8 4 10_L22N_4 L22N 4 1224 4 017 VREF 5 5 5 IOWREF 5 AF5 VREF VREF 4 RERS VREF 4 5 IONREF5 IONREF 5 5 AF13 VREF 4 10_L22P_4 AB17 10 5 1 _5 5 1014 5 ACS DUAL 2 1012354 AEI7 VO RDWR B _ _ RDWRB NC 9 OL23P4 17 5 01 5 5 5 ABB DUAL 4 12444 1012444 L24N 4 Y16 CS_B cs_B CS B 4 lOL24P 4 lOL24P 4 16 10 5 5 5 I0_L04N_5 AER 4 1012544 10125 4 125 4 16 1O 5 5 10_L04P_5 I0_L04P_5 ADM m 4 25 4 125 4 lOL25P4 16 0 5 JO LOSN S 10545 1010545 I 5 105 5 05 5 IO 105 5 AAG VO 4 IOL26P 47 IO_L26P_4 AF16 VREF pesos ABS VO VREF 4 VREF_4 5 106 _5 IO_LO6P_
22. VCCO VCCAUX TMS A14 JTAG 6 7 VCCO_LEFT L2 28 www xilinx com DS099 4 v1 7 August 19 2005 Product Specification 2 XILINX User I Os by Bank Table 21 indicates how the 89 available user I O pins Spartan 3 FPGA Family Pinout Descriptions age There are only four output banks each with its own distributed between the eight I O banks on the CP 132 pack Table 21 User I Os Per Bank for XC3S50 CP132 Package VCCO voltage input Maxi All Possible I O Pins by Package Edge Bank DCI VREF 0 10 5 0 2 1 2 Top 1 10 5 0 2 1 2 2 12 8 0 2 2 0 Right 3 12 8 0 2 2 0 4 11 0 6 2 1 2 Bottom 5 10 1 6 0 1 2 6 12 8 0 2 2 0 Left 7 12 9 0 2 1 0 DS099 4 v1 7 August 19 2005 Product Specification www xilinx com 29 Spartan 3 FPGA Family Pinout Descriptions 2 XILINX CP132 Footprint Outputs 5 5 o ul zi o o gt 44 14 0 for Top Edge Outputs 101 7 7 7 6 0 L30P 0 s 27 L30N_o 0817 0 1 0 1 0 127 0 VECINT 0 5 L32P_1 GCLK4 Vo 1 VREF 1 Bank 1 10 Vo L31P 1 128 1 11 12 13 Vo Vo L2
23. 1 35 1 745 0 565 1 005 RSDS_25 100 600 0 80 1 6 0 85 1 90 0 50 1 55 Future 100 400 14 1 4 1 15 1 60 0 90 1 35 DIFF_HSTL_II_18 All Vcco 0 40 0 40 DIFF SSTL2 II All VIT VIT 0 80 0 80 Notes 1 mask revision code appears on the device top marking See Package Marking Module 1 2 numbers in this table are based on the conditions set forth Table 5 and Table 10 3 and are differential measurements 4 This value must be compatible with the receiver to which the FPGA s output pair is connected 5 Output voltage measurements for all differential standards are made with a termination resistor of 1000 across the and P pins of the differential signal pair 6 At any given time only one 2 5V differential output standard LDT LVDS LVDS EXT RSDS may be assigned to each bank 7 Each LVPECL output pair requires three external resistors a 700 resistor in series with each output followed by 2400 shunt resistor These are in addition to the external 1000 termination resistor at the receiver side See Figure 3 C 1000 C ds099 3 08 020304 700 700 Figure 3 External Terminations for LVPECL DS099 3 v1 6 August 19 2005 www xilinx com 11 Preliminary Product Specification Spartan 3 FPGA Family DC and Switching Characteristics Switching Characteristic
24. Table 19 User I Os Per Bank in VQ100 Package XC3S50 XC3S50 XC3S200 VQ100 Pin XC3S200 VQ100 Pin Bank Pin Name Number Type Bank Pin Name Number Type 7 IO L40N 7 NVREF 7 P12 VREF N A VCCINT P69 VCCINT 7 IO L40P 7 P11 P93 VCCINT 7 VCCO_7 P6 VCCO VCCAUX CCLK P52 CONFIG N A GND P3 GND VCCAUX DONE P51 CONFIG N A GND P10 GND VCCAUX HSWAP EN P98 CONFIG N A GND P20 GND VCCAUX P25 CONFIG N A GND P29 GND VCCAUX 1 P24 CONFIG N A GND P41 GND VCCAUX 2 26 CONFIG N A GND P56 GND VCCAUX PROG_B P99 CONFIG N A GND P66 GND VCCAUX P77 JTAG N A GND P73 GND VCCAUX TDI P100 JTAG N A GND P82 GND VCCAUX TDO P76 JTAG N A GND P95 GND VCCAUX 5 P78 JTAG N A VCCAUX P7 VCCAUX N A VCCAUX P33 vccaux User I Os by Bank N A VCCAUX P58 VCCAUX Table 19 indicates how the available user I O pins are dis N A VCCAUX P84 VCCAUX 22 between the eight I O banks on the VQ100 N A VCCINT P18 VCCINT N A VCCINT P45 VCCINT All Possible I O Pins by Maximum Package Edge Bank y o yo DCI VREF 0 6 1 0 2 1 2 Top 1 7 2 0 2 1 2 2 8 5 0 2 1 0 Right 3 8 5 0 2 1 0 4 10 0 6 2 0 2 Bottom 5 8 0 6 0 0 2 6 8 4 0 2 2 0 Left 7 8 5 0 2 1 0 DS099 4 v1 7 August 19 2005 Product Specification www xilinx com 25 Spartan 3 FPGA Family Pinout Descriptions 2 XILINX VQ100 Footprint 99 2 552 orc
25. The time it takes for data 1 5250 12mA XC3S200 1 28 1 46 ns travel from the IOB s O input output drive Fast slew XC3S400 Tone Output pin fate XC3S50 194 223 ns XC3S1000 51500 XC3S2000 XC3S4000 XC3S5000 TiooLP The time it takes for data to XC3S200 1 63 1 87 ns travel from the O input XC3S400 XC3S50 230 264 ns put p XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Set Reset Times TiosnP Time from asserting the LVCMOS250 12mA XC3S200 2 44 2 81 ns OFF s SR input to output drive Fast slew XC3S400 2 data at the rate 3550 311 3 57 Aa put p XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 TiocsRQ Time from asserting the All 8 07 9 28 ns Global Set Reset GSR net to setting resetting data at the Output pin Notes 1 numbers in this table are tested using the methodology presented in Table 21 and are based on the operating conditions set forth in Table 5 and Table 8 2 This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output When this is true add the appropriate Output adjustment from Table 20 18 www xilinx com DS099 3 v1 6 August 19 2005 Preliminary Product Specification 2 XILINX Table 19 Timing for the Three State Path Spartan 3 FPGA Family DC and Switching Characteristics Speed Grade 5
26. either 0 or 1 no resistor is present on its respective mode pin MO M1 or M2 The Bitstream generator option HswapenPin determines whether a pull up resistor to VCCAUX a pull down resistor or no resistor is present HSWAP_EN after configuration DS099 4 v1 7 August 19 2005 www xilinx com 13 Product Specification Spartan 3 FPGA Family Pinout Descriptions Table 9 JTAG Pin Descriptions 2 XILINX Pin Name Direction Description Bitstream Generation Option TCK Input Test Clock The TCK clock signal synchronizes all The BitGen option TckPin boundary scan operations on its rising edge determines whether a pull up resistor pull down resistor or no resistor is present TDI Input Test Data Input TDI is the serial data input for all JTAG The BitGen option TdiPin instruction and data registers This input is sampled on determines whether a pull up the rising edge of TCK resistor pull down resistor or no resistor is present TMS Input Test Mode Select The 5 input controls the The BitGen option TmsPin sequence of states through which the JTAG TAP state determines whether a pull up machine passes This input is sampled on the rising resistor pull down resistor or no edge of TCK resistor is present TDO Output Test Data Output The TDO pin is the data output for The BitGen option TdoPin all JTAG instruction and data registers This output is determines whether a pull up sam
27. Auxiliary supply voltage 2 375 2 500 2 625 Voltage variance on when using a DCM 10 mV ms Voltage applied to all User 3 3V 0 3 3 75 V 42 Yoora Voltage applied to all 0 3 Vocauxt 0 34 Dedicated pins relative to GND Notes 1 The Veco range given here spans the lowest and highest operating voltages of all supported I O standards The recommended Veco range specific to each of the single ended I O standards is given in Table 8 and that specific to the differential standards is given in Table 10 2 Only during DCM operation is it recommended that the rate of change of not exceed 10 mV ms Table 6 General DC Characteristics of User I O Dual Purpose and Dedicated Pins Symbol Description Test Conditions Min Typ Max Units I Leakage current at User Driver is Hi Z VN gt 3 0V 25 Dual Purpose Dedicated pins OV or V V 1 sample tested cco lt 3 0 Dd IRpu Current through pull up resistor at User Vin OV Veco 3 3V 0 84 2 35 Dual Purpose and Dedicated pins Vin OV Veco 3 0V 0 69 2199 m Vin OV 2 5 0 47 1 41 Vin OV 1 8V 0 21 0 69 Vin OV 1 5V 0 13 0 43 Vin OV 1 2
28. IO LO1P ZVRN 7 IO LO1N 7NRP 7 VCCO LEFT 7 4 IO L20P 7 IO L20N 7 6 IO L21P 7 IO L21N 7 8 IO L22P 7 IO L22N 7 IO L23P 7 IO L23N 7 IO L24P 7 IO L24N 7 IO L40P 7 IO L40N 7NREF 7 VCCO LEFT IO L40P 6VREF 6 IO L4ON 6 2 IO L24P 6 IO L24N 6NREF 6 IO L23P 6 IO L23N 6 IO L22P 6 IO L22N 6 29 IO L21P 6 IO L21N 6 IO L20P 6 IO L20N 6 5 gt Lg gt 298 555 amp 2 2 20 zaza 5 oc 5 9 9 9 9 9 9 lt TA 12121219 95 feel CO ev 61 C C T VCCO for Top Edge 118 1 L28P 1 GND 22 2 0 9 a9 9 a 2 gt OSOCOFFE lt gt B 108 10 101 2NRP 2 IO LO1P 2VRN 2 VCCO RIGHT 105 L20N 2 104 10 L20P 2 H03 IO L21N 2 192 121 2 GND 100 10 L22N 2 99 L22P 2 08 0 L23N 2WREF 2 07 L23P 2 06 L24N 2 05 lO 124 2 94 03 L40N 2 92 0 L40P 2VREF 2 VCCO_RIGHT 00 1404 3 89 L40P GND 87 lO L24N 86 L24P 3 85 L23N 3 IO L23P 3 VREF 3 83 lO L22N 82 lO
29. 5 VCCO 5 VCCO 5 AM4 VCCO 6 OL16N 6 L16N 6 AE2 5 5 5 AM8 VCCO 6 IO_L16P_6 IO_L16P_6 5 VCCO 5 VCCO 5 AN13 VCCO 6 OL1 7N 6 L17N 6 AD10 810 IO AHT 6 6 L17P 6 9 VREF 6 IO AH2 O 6 VREF 6 E ia 6 IO_L19N6 L19N 6 AD2 iD T 6 OL19P6 L19P 6 AD1 6 IOLOING AM2 DCI SACTE 29 6 VRP 6 6 1012026 L20P 6 AC10 6 OLOIP amp 6 AM1 DCI 6 121 6 2 6 AC8 6 6 10 121 6 OL21P 6 lO_LO2N_6 10 102 6 12 6 IOL22N 6 L22N 6 AC6 O I0_L02P_6 10 102 6 6 OL 22P6 122 6 5 O EE D 6 vues 6 AKS 6 10123 6 L23N 6 AC2 6 OLOSP6 LO3P 6 AK2 9 eodem 24 e 6 OLONN6 10104 6 AJA VEO a Hee 6 1 6 IO LO4P 6 Vo 6 lIOL24P 6 L24P 6 AB10 O 6 1010546 10 105 6 2 6 01256 L25N 6 8 O 6 I0_L05P_6 105 6 An 6 125 66 10_L25P_6 7 6 6 LOGN 6 Vo 6 10126 6 IO L26N 6 4 O 6 1010626 IO LOGP 6 AHS 6 IO L26P 6 L26P 6 AB3 O 6 10 107 6 10 LO7N 6 AG6 6 1012796 10127 6 11 O 6 0 LO7P 6 IO LO7P 6 AGS Vo 6 l OL 7P 6 L27P 6 AA11 6 010846 LOBN 6 AG2 VO 6 L28N6 10128 6 AAB O 6 10 10826 10 LOBP 6 AGI Vo 6 OL28P6 L28P 6 6 6
30. 113 Unrestricted general purpose user DUAL Configuration pin then possible 24 VREF User I O or input voltage reference for user I O bank 16 DCI User or reference resistor input for bank GCLK User or global clock buffer input E VCCO Output voltage supply for bank 1 2V 0 N C No unconnected pins in this package GND Ground VCCAUX Auxiliary voltage supply 2 5V 7 CONFIG Dedicated configuration pins JTAG Dedicated JTAG port pins VCCINT Internal core voltage supply 46 www xilinx com 0 099 4 v1 7 August 19 2005 Product Specification 2 XILINX FG320 320 lead Fine pitch Ball Grid Table 29 FG320 Package Pinout Continued Spartan 3 FPGA Family Pinout Descriptions Array XC3S400 The 320 lead fine pitch ball grid array package FG320 XC3S1000 FG320 supports three different Spartan 3 devices including the XC3S1500 Pin XC3S400 the XC3S1000 and the XC3S1500 The footprint Bank Pin Name Number Type for all three devices is identical as shown in Table 29 and 0 IO L32P 0 GCLK6 F9 GCLK Figure 10 0 0 B8 FG320 package is 18x 18 array of solder balls 0 VCCO 0 C6 VCCO minus the f
31. 4 12494 AJO VO 4 010544 10 105 4 26 4 10125 4 10125 4 120 4 125 4 2 1 0 4 10106 4 LOON 4 126 VREF 4 12884 ONA ANB VREF 4 VREF 4 IO LO6P 4 LOGP 4 26 3 MBER IO LO7N 4 IO LO7N 4 AF25 Vo 4 OL27N 4 L27N 4 19 DUAL IO LO7P 4 107 4 AG25 DIN DO DIN DO 94 www xilinx com 0 099 4 v1 7 August 19 2005 Product Specification 2 XILINX Table 41 FG1156 Package Pinout Continued Table 41 FG1156 Package Pinout Continued Spartan 3 FPGA Family Pinout Descriptions FG1156 FG1156 XC3S4000 XC3S5000 Pin XC3S4000 XC3S5000 Pin Bank Pin Name Pin Name Number Type Bank Pin Name Pin Name Number Type 4 lO L27P 4 L27P 4 AJ19 DUAL 4 VCCO 4 VCCO 4 AL24 VCCO Di 4 VCCO 4 VCCO 4 AM27 VCCO 4 IO L28N 4 10 L28N 4 19 4 VCCO 4 VCCO 4 Veco 4 lO L28P 4 L28P 4 AN19 4 VCCO 4 VCCO 4 AN22 VCCO 4 L29N 4 IO L29N 4 AF18 1 Ta NE 4 L29P 4 IO L29P 4 AG18 5 ADI lo 4 IO L30N 4 L30N 4 AH18 DUAL 5 lo
32. 1 AB21 VCCINT N A VCCAUX VCCAUX AD30 VCCAUX N A VCCINT VCCINT AB22 VCCINT N A VCCAUX VCCAUX AD5 VCCAUX N A VCCINT VCCINT AC12 VCCINT N A VCCAUX VCCAUX AG16 VCCAUX N A VCCINT VCCINT AC17 VCCINT N A VCCAUX VCCAUX AG19 VCCAUX N A VCCINT VCCINT AC18 VCCINT N A VCCAUX VCCAUX AJ30 VCCAUX N A VCCINT VCCINT AC23 VCCINT N A VCCAUX VCCAUX AJ5 VCCAUX N A VCCINT VCCINT M12 VCCINT N A VCCAUX VCCAUX AK11 VCCAUX N A VCCINT VCCINT M17 VCCINT N A VCCAUX VCCAUX AK15 VCCAUX N A VCCINT VCCINT M18 VCCINT N A VCCAUX VCCAUX AK20 VCCAUX N A VCCINT VCCINT M23 VCCINT N A VCCAUX VCCAUX AK24 VCCAUX N A VCCINT VCCINT N13 VCCINT N A VCCAUX VCCAUX AK29 VCCAUX N A VCCINT VCCINT N14 VCCINT N A VCCAUX VCCAUX AK6 N A VCCINT VCCINT N15 VCCINT N A VCCAUX VCCAUX E11 VCCAUX N A VCCINT VCCINT N16 VCCINT N A VCCAUX VCCAUX E15 VCCAUX N A VCCINT VCCINT N19 VCCINT N A VCCAUX VCCAUX E20 VCCAUX N A VCCINT VCCINT N20 VCCAUX VCCAUX E24 VCCAUX N A VCCINT VCCINT N21 VCCINT N A VCCAUX VCCAUX E29 VCCAUX N A VCCINT VCCINT N22 VCCINT N A VCCAUX VCCAUX VCCAUX N A VCCINT VCCINT P13 VCCINT N A VCCAUX VCCAUX F30 VCCAUX N A VCCINT VCCINT P22 VCCAUX VCCAUX F5 VCCAUX N A VCCINT VCCINT R13 VCCINT N A VCCAUX VCCAUX H16 VCCAUX N A VCCINT VCCINT R22 VCCINT N A VCCAUX VCCAUX H19 VCCAUX N A VCCINT VCCINT T13 VCCINT N A VCCAUX VCCAUX L30 VCCAUX N A VCCINT VCCINT T22 VCCINT
33. 32 2 M22 O 2 NC 9 1010642 IO LO6N2 G20 O 2 10133 2 IO L33N2 IO 1334 2 123 2 NC 9 1062 IO 106 2 621 O 2 133 2 133 2 IO L33P_2 M24 O 2 1010742 107 2 F23 O 2 10_L34N_2 10_L34N_2 10_L34N_2 M25 VREF 2 NC 9 IO 107 2 IO 107 2 F24 O VREF E NER VREF_2 TINCT OER ES 2 10_L34P_2 2 134 2 M26 O 2 10135 2 135 2 IO_L35N_2 9 2 1094 2 1094 2 F25 VREF 2 135 2 l0_L35P_2 10_L35P_2 2 2 2 10138 2 13842 10_L38N_2 1 O 2 NC 9 109 2 IO LO9P2 F26 O 2 138 2 138 2 2 N22 O 2 NC 9 IO LION 2 625 O 2 10139 2 L39N 2 L39N 2 3 2 NC 9 1 2 IOLI0P2 626 2 10_139P_2 139 2 2 4 UO 2 IO_L14N_2 IO LI4N 2 IO 2 H20 2 1014042 1014042 IO_L40N_2 N25 IO L11N 2 2 L40P 2 L40P 2 L40P 2 N26 VREF 2 14 2 OLI4P2 14 2 Hei 2 2 VREF 2 IO 11 2 2 2 VCCO2 2 624 VCCO 2 IO_L16N_2 IO_L16N_2 2 VCCO 2 2 1162 16 2 116 2 421 2 veco_2 09 K19 veco IO L12P 2 2 VCCO2 VCCO 2 VCCO2 18 VCCO 2 1 7 2 OLIN2 IO_L17N_2 VO 2 2 _ 2 2 24
34. gt Fi SHIFTIN COUT 1 CYSELG CYMUXG i JA p mE FXINA FXINB gt 1 1 t XORG 1 4 1 ALTDIG BY gt 4 1 G LUT MC15 o2 D gt Portion SRL SLICEWE1 E 4 1 BX C gt p TER EIS 10 1 1 1 1 L Common Logic gt XB L F5 FXMUX 1 1 1 i FAND CYINIT T1 1 i bd 1 Bottom Portion m LEGEND Logic Functions Distribu