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TEXAS INSTRUMENTS SN54LS396 SN74LS396 OCTAL STORAGE REGISTERS Data Sheet

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1. IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated
2. level output from strobe PLH m 4 P E See Note 3 PHL Propagation delay time high to low leve output from strobe NOTE 3 Load circuits and voltage waveforms are shown in Section 1 vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE
3. 4 respectively before the most recent transition of the clock PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments e a a A parh Production processing does not necessarily include H EXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 Copyright 1988 Texas Instruments Incorporated SN54LS396 SN74LS396 OCTAL STORAGE REGISTERS SDLS173 MARCH 1977 REVISED MARCH 1988 logic diagram positive logic schematics of inputs and outputs EQUIVALENT OF EACH TYPICAL OF ALL OUTPUTS INPUT Vcc Vec 120 2 NOM CLOCK Reg 10k NOM OTHERS Reg 20 kQ NOM Pin numbers shown are for D J N and W packages absolute maximum ratings over operating free air temperature range unless otherwise noted Supply voltage Vcc see Note1 2 ww ee 7V Input voltage a a a a a a a 7V Operating free air temperature range SN54LS396 o aa a a a a aaa a 55 C to 125 C SN74LS396 laaa a Sa ee aa WOME Storage temperature range n lo a a a a a a a a ee es 65 C to 150 C NOTE 1 Voltage values are with respect to network ground terminal recommended operating conditions Supply voltage Voc 4 5 5 65 4 75 5 5 25 Low level output current IOL ae eee Clock frequency felock 0 30 MHz ae ie ae E Setup time ts Hoid time th Operating free air temperature Ta 4 TEXAS INSTRUMENTS 2 POST OFFICE
4. BOX 655303 DALLAS TEXAS 75265 SN54LS396 SN74LS396 OCTAL STORAGE REGISTERS SDLS173 MARCH 1977 REVISED MARCH 1988 electrical characteristics over recommended operating free air temperature range unless otherwise noted PARAMETER VIH High level input voltage BOSRAND Vik Input clamp voltage E SCS A Vec MIN Vip 2V VoH High level output voltage 2 5 3 4 2 7 3 4 v Vit MAX lop 400 pA VoL Low level output voltage Input cuventat Glock input a ed i i Veco MAX V 7V mA maximum input voltage ee E Low level Clock input 58 wt 2 TELLI vec MAax Vy 0 4V mA input current Other inputs OOOO oa 0 4 tos Short circuit output current8 Vec MAX 20 100 20 100 icc Supply current Vcc MAX See Note 2 24 40 24 t For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions fan typical values are at Voc 5 V Ta 28 C S Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second NOTE 2 Icc is measured with 4 5 V applied to all inputs and all outputs open switching characteristics Vcc 5 V TA 25 C PARAMETER tPLH Propagation delay time low to high level output from clock TEST CONDITIONS 7 5 3 CL 15 pF tPHL Propagation delay time high to low level output from clock a SKG n 3 i t Propagation delay time fow to high
5. SN 54L S396 AY FS SN54LS396 SN74LS396 OCTAL STORAGE REGISTERS SDLS173 MARCH 1977 REVISED MARCH 1988 Parallel Access SN54LS396 J OR W PACKAGE SN74LS396 D OR N PACKAGE TOP VIEW e Typical Propagation Delay Time 20 ns e Typical Power Dissipation 120 mW 201 e Applications 1Q1 N Bit Storage Files D1 Hex BCD Serial To Parallel Converters 2Q2 DEA 102 description D2 These octal registers are organized as two 4 bit bytes CLK of storage Upon application of a positive going clock GND signal the information stored in byte 1 is transferred into byte 2 as a new 4 bit byte is loaded into the byte 1 location via the four data lines The full 8 bit SN54LS396 FK PACKAGE word is available at the outputs after two clock TOP VIEW cycles Both the clock and the strobe lines are fully S buffered logic symbol t D1 18 204 STROBE G 2Q2 17 104 CLK NC 16 NC 102 15 0 D4 D1 D2 10 11 12 13 3 D2 9 ame ote 5 ee omy x D3 s928 og NC No intemal connection tThis symbol is in accordance with ANSI IEEE Std 91 1984 and IEC Publication 617 12 Pin numbers shown are for D J N and W packages FUNCTION TABLE INPUTS OUTPUTS H high level steady state L low level steady state X irrelevant any input including transitions t transition from tow to high tevet 1Q1 142 103 194 the level of 1Q1 1Q2 1Q3 and 10

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