AMD PALCE29MA16H-25 24-Pin EE CMOS Programmable Array Logic
Contents
1. sl 23 27 13 22 26 OBSERVE VOF PRODUCT Input 7 TERM Output 5 4 Input VOF4 Output Macro e e 21 25 VOFg La e 6 5 1 00 kd d 20 24 H 102 La CH Input Output CO Macro c ta e H D 3 19 23 H 1 06 H LJ Continued on Next Page 08811G 19 2 358 PALCE29MA16H 25 LOGIC DIAGRAM SKINNY DIP PLCC Pinouts Continued from Previous Page AMD cl2. 12 16 20 24 28 32 36 40 44 48 52 56 la 9 7 VO2 ta a e 18 21 1 05 10 8 t VO3 ci e e 5 R 17 20 1 04 H 11 9 SH Input l OFo Output Macro a e H 16 19 Input Output VOFS Macro e Ly 12 10 S V OF 3 la d e e kd 5 PRELOAD D 15 18 PRODUCT B VOFA TERM D 13 11 De A D VoE M l Ly 4 14 17 lo T 13 16 l4 12 16 20 24 28 32 36 40 44 48 52 56 PALCE29MA16H 25 08811G 19 concluded 2 359 cl AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature 65 C to 150 C Commercial C Devices Ambient Temperature Ambient Temperature Ta with Power Applied 55 C to 125 C Operating in Free Air 0 C to 75 C Supply Voltage with Supply Voltage Vcc Respect to Ground 0 5 V to 7 0V vvith Respeci to Ground 4 75 V to 5 25 V DC Input Voltage 0 5 V to Vcc 0 5 V Operating ranges define those limits between which the func DC Output or I O tionality of the device is guaranteed Pin Voltage 0 5 V to Vcc 0 5 V Static Discharge Voltage 2001 V Latchup Current Ta 0 C to 75 C 100 mA Stresses above those listed under Absolute Maximum Rat ings may cause permanent device failure Functionality at or above these limits is not implied Exposure to
3. Notes 1 Erased State Charged or disconnected 0 Programmed State Discharged or connected Active LOW LE means that data is stored when the LE pin is HIGH and the latch is transparent when the LE pin is LOW Active HIGH LE means the opposite 2 354 PALCE29MA16H 25 AMD cl SOME POSSIBLE CONFIGURATIONS OF THE INPUT OUTPUT LOGIC MACROCELL For other useful configurations please refer to the macrocell diagrams in Figure 2 All macrocell architecture cells are independently programmable e S l lt s So 1 So 1 4 SM des 85 1 __ lt EEA 08811G 6 SECH Output Registered Active Low 08811G 7 Output Combinatorial Active Low d H rez 88 S4 i Sp 0 id Sa Z4 cmm SECH Z4 SECH 08811G 8 08811G 9 Output Registered Active High Output Combinatorial Active High Figure 3a Dual Feedback Macrocells D Q l E E gt Q So 1 Sg 1 Si 0 S4 St gi SR Z Sa 0 08811G 11 08811G 10 Output Registered Active Low I O Feedback Output Combinatorial Active Low I O Feedback LE Q So 0 Sp 0 Si 0 s S3 z i S3 1 SSC 2 0 1 Sg 0 08811G 12 AERIS Output Latched Active High I O Feedback Output Combinatorial Active High UO Feedback Figure 3b Single Feedback Macrocells PALCE29MA16H 25 2 355 cl AMD SOME POSSIBLE CONFIGURATIONS OF THE INPUT OUTPUT LOGIC MACROCELL D D gt
4. CLK input 5 Input Output Register Register J tcorp gt tpp 08811G 21 Input Output Register Specs PT CLK Reference 2 362 PALCE29MA16H 25 AMD cl SWITCHING WAVEFORMS Combinatorial V Input T Le tpp gt i i ANM Mir MAMMA 08811G 22 Combinatorial Output a F IsOR gt HOR Clock Vr lt tcon gt i WA Miror WAAT 08811G 23 Output Register Pin Clock Combinatorial Input Combinatorial Input as Clock i Wun OS put MA ii 08811G 24 Output Register PT Clock I lt iSIR t HIR9 Clock Vr tciR i i WARUM Comp MBA 08811G 25 Input Register PALCE29MA16H 25 2 363 cl AMD SWITCHING WAVEFORMS Clock 08811G 26 Pin Clock Width Combinatorial Input as Clock 08811G 27 PT Clock Width 2 364 PALCE29MA16H 25 AMD cl SWITCHING CHARACTERISTICS Latched Operation a ee EE Symbol Parameter Description wo Input or vO Pin to Combinatorial oup TT tero Input or VO Pin to Output via Transparent Laten 28 ms Output Latch Pin LE ro mweroPwsOmumumeSap LL s Input or I O Pin to Output Latch Setup via Transparent Input Latch Output Latch Product Term LE Input or I O Pin to Output Latch Setup via Transparent Input Latch UO Pin to Input Latch Setup 2 GIL Latch Feedback Latch Enable Transparent Mode to Combinatorial Output Data Hold Time for Input Latch Latch Enable tals Latch Feedba
5. Reset and CLK LE Each product term on the PALCE29MA16 consists of a 58 input AND gate The outputs of these AND gates are connected to a fixed OR plane Product terms are allo cated to OR gates in a varied distribution across the device ranging from 4 to 12 wide with an average of 7 logic product terms per output An increased number of product terms per output allows more complex functions to be implemented in a single PAL device This flexibility aids in implementing functions such as counters exclu sive OR functions or complex state machines where different states require different numbers of product terms Individual asynchronous Preset and Reset product terms are connected to all Registered or Latched I Os When the asynchronous Preset product term is as serted HIGH the register or latch will immediately be loaded with a HIGH independent of the clock When the asynchronous Reset product term is asserted HIGH the register or latch will be immediately loaded with a LOW independent of the clock The actual output state will depend on the macrocell polarity selection The latches must be in latched mode nottransparent mode for the Reset Preset Preload and power up Reset modes to be meaningful Input Output Logic Macrocells The I O logic macrocell allows the user the flexibility of defining the architecture of each input or output on an in dividual basis It also provides the capability of using the associated pin
6. a product term VO Logic Macrocell Configuration AMD s unique I O macrocell offers major benefits through its versatile programmable input output cell structure multiple clock choices flexible Output Enable and feedback selection Eight I O macrocells with single feedback contain 9 EE cells while the other eight ma crocells contain 8 EE cells for programming the input output functions see Table 1 EE cell S1 controls whether the macrocell will be combi natorial or registered latched So controls the output po larity active HIGH or active LOW S2 determines whether the storage element is a register or a latch S3 allows the use of the macrocell as an input register latch or as an output register latch It selects the direction of the data path through the register latch If connected to the usual AND OR array output the register latch is an output connected to the I O pin If connected to the I O pin the register latch becomes an input register latch to the AND array using the feedback data path Programmable EE cells S4 and Ss allow the user to se lect one of the four CLK LE signals for each macrocell Seand S7 are used to control Output Enable as pin con trolled product term controlled permanently enabled or permanently disabled Ss controls a feedback multi plexer for the macrocells with a single feedback path only Using the programmable EE cells So Se various input and output configurations can be selected Some o
7. I O pins Remove the Preload condition Verify Vo Von for all output pins as per pro grammed pattern Because the Preload command is a product term any input to the array can be used to set Preload including I O pins and registers Preload itself will change the val ues of the I O pins and registers This will have unpre dictable results Therefore only dedicated input pins should be used for the Preload command W Inputs VO Pins CLK Pin 1 2 Vin Vit Vou NViH Von Vum Vit 08811G 42 Preload Waveform 2 370 PALCE29MA16H 25 OBSERVABILITY The PALCE29MA16 has the capability for product term Observability When the global Observe product term is true the PALCE29MA16 will enter the Observe mode This feature aids functional testing by allowing direct ob servation of register states When the PALCE29MA16 is in the Observe mode the output buffer is enabled and the I O pin value will be Q of the corresponding register This overrides any OE inputs The procedure for Observe is W Remove the inputs to all the I O pins Parameter Symbol Parameter Description AMD cl m Set the inputs to the user selected Observe configuration W The register values will be sent to the correspond ing I O pins W Remove the Observe configuration from the se lected I O pins Because the Observe command is a product term any input to the array can be used to set Observe including I O pins and re
8. Soz1 D Q So 1 Sj 0 Sj S3 1 gt Q 83 1 Sg 1 SCH 4 s 1 s 1 08811G 14 Z Output Registered Active Low 08811G 15 Register Feedback Output Combinatorial Active Low Latched Feedback D o gt LE Q Soz1 EIER E 3 S3 1 E lt Sg 1 S8 1 Sech Sch 08811G 16 Z Output Latched Active Low 08811G 17 Latched Feedback Output Combinatorial Active Low Latched Feedback Figure 3b Single Feedback Macrocells Continued 3 0 Sg 1 FOR SINGLE FEEDBACK ONLY So 1 REGISTER 0 LATCH 08811G 18 Programmable AND Array Figure 3c All Macrocells 2 356 PALCE29MA16H 25 Power Up Reset All flip flops power up to a logic LOW for predictable sys tem initialization The outputs of the PALCE29MA16 depend on whether they are selected as registered or combinatorial If registered is selected the output will be LOW if programmed as active LOW and HIGH if pro grammed as active HIGH If combinatorial is selected the output will be a function of the logic Preload To simplify testing the PALCE29MA16 is designed with preload circuitry that provides an easy method for test ing logical functionality Both product term controlled and supervoltage enabled preload modes are available The TTL level preload product term can be useful during debugging where supervoltages may not be available Preload allows any arbitrary state value to be loaded into the registers la
9. either as an input or an output The PALCE29MA16 has 16 macrocells one for each UO pin Each I O macrocell can be programmed for combinatorial registered or latched operation see Fig ure 2 Combinatorial output is desired when the PAL device is used to replace combinatorial glue logic Reg isters and Latches are used in synchronous logic applications Registers and Latches with product term controlled clocks can also be used in asychronous application Common I OE Pin Individual OE Individual Asynchronous Preset Prorpit Common CLK LE PIN j r gq Individual CLKLE er p IVUOx Individual Asynchronous Reset To AND Array Rx 08811G 4 Figure 2a PALCE29MA16 Macrocell Single Feedback 2 352 PALCE29MA16H 25 The output polarity for each macrocell in each of the three modes of operation is user selectable allowing complete flexibility of the macrocell configuration Eight of the macrocells VOFo VOF7 have two inde pendent feedback paths to the AND array see Figure 2b The first is a dedicated I O pin feedback to the AND array for combinatorial input The second path consists of a direct register latch feedback to the array If the pin is used as a dedicated input using the first feedback path the register latch feedback path is still available to the AND array This path provides the capability of using the register latch as a bur
10. 4578 PALCE29MA 16f nv ge COM L H 25 PALCE29MA16H 25 24 Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS m High performance semicustom logic replacement Electrically Erasable EE technology allows reprogrammability m 16 bidirectional user programmable UO logic macrocells for Combinatorial Registered Latched operation B Output Enable controlled by a pin or product terms m Varied product term distribution for increased design flexibility m Programmable clock selection with common pin clock latch enable LE or individual product term clock LE with LOW HIGH clock LE polarity GENERAL DESCRIPTION The PALCE29MA16 is a high speed EE CMOS Pro grammable Array Logic PAL device designed for gen eral logic replacement in TTL or CMOS digital systems It offers high speed low power consumption high BLOCK DIAGRAM AMD 1 VANTIS AN AMD COMPANY m Register Latch Preload permits full logic verification W High speed tro 25 ns fmax 33 MHz and fmax internal 50 MHz W Full function AC and DC testing at the factory for high programming and functional yields and high reliability B 24 pin 300 mil SKINNYDIP and 28 pin plastic leaded chip carrier packages W Extensive third party software and programmer support through FusionPLD partners programming yield fast programming and excellent reliability PAL devices combine the flexibility of custom logic with the off the shelf availa
11. 5 0 V TA 25 C Note 1 These parameters are not 100 tested but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected SWITCHING CHARACTERISTICS Registered Operation Parameter Symbol Parameter Description Combinatorial Output wo mworWOPmwCommaoa Output Js tson Input or VO Pin to Output Register Setup ff EEN thon Data Hold Time for Output Register o o dolf Output Register Product Term Clock tsorp VOPinor Input to Output Register Setup o 4 frn Output Register Clock to Output E Data Hold Time for Output Register Input Register Pin Clock VO Pin to Input Register Setup Register Feedback Clock to Combinatorial Output Data Hold time for Input Register Clock and Frequency Register Feedback Pin Driven Clock to Output Register Latch Pin Driven Setup Register Feedback PT Driven Clock to Output Register Latch PT Driven Setup Maximum Frequency Pin Driven 1 tsor tcor Maximum Internal Frequency Pin Driven 1 tcis Maximum Frequency PT Driven 1 tsoRP tcorp Maximum Internal Frequency PT Driven 1 tcisPP Pin Clock Width HIGH Pin Clock Width LOW PT Clock Width HIGH PT Clock Width LOW Wu AB aj cia n2 MI N ec Kc as PALCE29MA16H 25 Com l 2 361 cl AMD Input Output Register Register 08811G 20 Input Output Register Specs Pin CLK Reference
12. AMD FUNCTIONAL DESCRIPTION Inputs The PALCE29MA 16 has 29 inputs to drive each product term up to 58 inputs with both TRUE and complement versions available to the AND array as shown in the block diagram in Figure 1 Of these 29 inputs 4 are dedicated inputs 16 are from eight I O logic macrocells with two feedbacks 8 are from other I O logic macro cells with single feedback and one is the I OE input Initially the AND array gates are disconnected from all the inputs This condition represents a logical TRUE for the AND array By selectively programming the EE cells the AND array may be connected to either the TRUE in put or the complement input When both the TRUE and complement inputs are connected a logical FALSE re sults at the output of the AND gate Product Terms The degree of programmability and complexity of a PAL device is determined by the number of connections that form the programmable AND and OR gates Each pro grammable AND gate is called a product term The PALCE29MA16 has 178 product terms 112 of these product terms provide logic capability and others are ar chitectural product terms Among the control product terms one is for Observability and one is for Preload The Output Enable of each macrocell can be pro grammed to be controlled by a common Output Enable pin or an individual product term It may also be perma nently disabled In addition independent product terms for each macrocell control Preset
13. Absolute Maxi mum Ratings for extended periods may affect device reliabil ity Programming conditions may differ DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage loH 2 mA VIN ViH or VIL 2 4 V Vcc Min Vo os Output LOW Voltage VIN ViH or VIL Vcc Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs Note 1 Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs Note 1 Input HIGH Leakage Current Vin 5 5 V Voc Max Note 2 Input LOW Leakage Current Vin 0 V Vcc Max Note 2 Off State Output Leakage Vout 5 5 V Vcc Max Current HIGH Vin Vinor ViL Note 2 Off State Output Leakage VouT 5 5 V Vcc Max Current LOW Vin Vinor ViL Note 2 Supply Current VIN 0 V Outputs Open lout 0 mA Vcc Max 1 These are absolute values with respect to device ground all overshoots due to system and or tester noise are included 2 VO pin leakage is the worst case of liy and loz or liq and lozu 3 Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second VouT 0 5 V has been chosen to avoid test problems caused by tester ground degradation 2 360 PALCE29MA16H 25 Com l AMD cl CAPACITANCE Note 1 Parameter Symbol Parameter Description Test Conditions ON O Input SESS Voc
14. E goes into the transparent mode If the com binatorial input changes while LE is in the latched mode and LE goes into the transparent mode before ep ns has elapsed the corresponding latched output will change at the later of the following tprp ns after the combinatorial input changes or taoL ns after LE goes into the latched mode PALCE29MA16H 25 2 367 cl AMD SWITCHING CHARACTERISTICS Reset Preset Enable Parameter Symbol Parameter Description 3 CH Input or I O Pin to Output Register Latch Reset Preset Asynchronous Reset Preset Pulse Width Asynchronous Reset Preset to Output Register Latch Recovery Asynchronous Reset Preset to Input 1 Register Latch Recovery taRPO Asynchronous Reset Preset to Output Register Latch Recovery PT Clock LE tARPI Asynchronous Reset Preset to Input Register Latch Recovery PT Clock LE Output Enable Operation l OE Pin to Output Enable 20 l OE Pin to Output Disable Note 1 2 Input or I O to Output Enable via PT Input or I O to Output Disable via PT Note 1 1 Output disable times do not include test load RC time constants ewj ak aja 2 4 CH 2 2 Wu SWITCHING WAVEFORMS Combinatorial Asynchronous Reset Preset Registered Pin 11 Latched Output Combinatorial Registered Clock I Eeer 08811G 37 Output 08811G 39 Output Register Latch Reset Preset Pin 11 to Output Disable Enable Combinatorial Asynchronous e Reset Preset E EE MT Co
15. bility of standard products providing major advantages over other CLK LE VOF7 VOFE 1 07 1 05 VO4 AP VOFA H D H V Q D Y A e En ES a A A gt VO N VO 1 0 VO VO gt Logic gic Logic gt Logic gt Logic P Logic Macrocell EH e N Macrocell Macrocell Macrocell Macrocell NA 4 NA M NA Mw MM M L am M ZE D 4 Programmable AND Array 58x178 W A 4 NA A 8 W h a A N 4 J 4U AIT ULLA io SN Km KT Km gl um P ogic d c ogic ogic ic Logic ogic I Macrocell aA E Per LI Km mi Macrocell N Macrocell V o v v v 4 l I i V v y NI N Y Ad H W U Q Q U V V lg la VOE VOFo VOF VO 1 04 1 02 1 03 VOF2 VOF3 08811G 1 Publication 08811 Rev G Amendment O Issue Date June 1993 2 349 cl AMD GENERAL DESCRIPTION continued semicustom solutions such as gate arrays and standard cells including reduced development time and low up front development cost The PALCE29MA16 uses the familiar sum of products AND OR structure allowing users to customize logic functions by programming the device for specific appli cations It provides up to 29 array inputs and 16 outputs It incorporates AMD s unique input output logic macro cell which provides flexible input output structure and polarity flexible feedback selection multiple Output En able choices and a programmable clocking scheme The macrocells can be individually programmed as combinatorial regis
16. c ts 08811G 44 Power Up Reset Waveform 2 372 PALCE29MA16H 25 TYPICAL THERMAL CHARACTERISTICS Measured at 25 C ambient These parameters are not tested Parameter Typ Symbol Parameter Description SKINNYDIP PLCC E T 800 pm air Plastic 0jc Considerations The data listed for plastic 0jc are for reference only and are not recommended for use in calculating junction temperatures The heat flow paths in plastic encapsulated devices are complex making the 0jc measurement relative to a specific location on the package surface Tests indicate this measurement reference point is directly below the die attach area on the bottom center of the package Furthermore 0jc tests on packages are performed in a constant temperature bath keeping the package surface at a constant temperature Therefore the measurements can only be used in a similar environment PALCE29MA16H 25 2 373
17. ck Pin Driven to Output Register Latch 20 Pin Driven Setup Latch Feedback PT Driven to Output Register Latch PT Driven Setup af a Po PO N an PALCE29MA16H 25 Com l 2 365 cl AMD 08811G 28 Input Output Latch Specs Pin LE Reference yo tPTD gt tpp 08811G 29 Input Output Latch Specs PT LE Reference 2 366 PALCE29MA16H 25 SWITCHING WAVEFORMS Latched Input Combinatorial Input Combinatorial Output Latched Output Latched Input Combinatorial Input LE Latched Output Latched Input Combinatorial Output Note 08811G 30 Latch Transparent Mode 08811G 32 Output Latch Pin LE 08811G 34 Input Latch Pin LE AMD cl TE Latched Transparent VT Input Latch tals Output VT Latched Latch LE Transparent 08811G 31 Input and Output Latch Relationship Latched Input Combinatorial Input Combinatorial Input as LE Latched IMN WWW Output DO kor JD t 08811G 33 Output Latch PT LE LATCHED TRANSPARENT LE Vr Vr Vr tew gt tew gt 08811G 35 Pin LE Width Latched Transparent Combinatorial Input as LE 7 lt tqwip gt lt tGewHP gt PTLE Width 08811036 1 Ifthe combinatorial input changes while LE is in the latched mode and LE goes into the transparent mode after tprp ns has elasped the corresponding latched output will change taoL ns after L
18. ermit full logic verification of the design The PALCE29MA16 is offered in the space saving 300 mil SKINNYDIP package as well as the plastic leaded chip carrier package l OF4 l OFg VOO O7 l O1 l Og NC NC VO2 l O5 VO3 1 04 VOF2 l OF5 12 13 14 15 16 17 SE 08811G 3 PALCE29MA16H 25 AMD cl ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available with several ordering options The order number Valid Combination is formed by a combination of these elements PAL CE 29 MA 16H 25 P C 4 KS OPTIONAL PROCESSING Blank Standard Processing FAMILY TYPE PAL Programmable Array Logic TECHNOLOGY CE CMOS Electrically Erasable PROGRAMMING REVISION 4 First Revision Requires current programming Algorithm NUMBER OF ARRAY INPUTS OUTPUT TYPE MA Advanced Asynchronous Macrocell TEMPERATURE RANGE C Commercial 0 C to 75 C NUMBER OF FLIP FLOPS POWER PACKAGE TYPE H Half Power 100 mA P 24 Pin Plastic SKINNYDIP PD3024 J 28 Pin Plastic Leaded Chip SPEED Carrier PL 028 25 25ns Valid Combinations Valid Combinations PALCE29MA16H 25 PC JC Valid Combinations lists configurations planned to be supported in volume for this device Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations PALCE29MA16H 25 Com l 2 351 cl
19. f the possible configuration options are shown in Figure 3 In the erased state charged disconnected an archi tectural cell is said to have a value of 1 in the pro grammed state discharged connected to GND an architectural cell is said to have a value of 0 Individual OE I Individual Asynchronous Preset 2 P3 Common CLK LE PIN 4 1 1 L d1 0 Individual CLK LE o 1 d0 0 EZ VOF sal 185 Kee Individual Asynchronous Reset To AND Array 47 1 RFy To AND Array 1 08811G 5 Figure 2b PALCE29MA16 Macrocell Dual Feedback PALCE29MA16H 25 2 353 cl AMD Table 1a PALCE29MA16 I O Logic Macrocell Architecture Selections sa VO Cell Storage Element Output Type so Output Polarity Combinatorial TAT Active LOW Register Latch CH Active HIGH se Feedback Register Latch ee Applies to macrocells with single feedback only Table 1b PALCE29MA16 I O Logic Macrocell Clock Polarity and Output Enable Selections s s Glock Eagerkaten Enable tev 1 o GE pn resa oona edge soenen t 5 1 GRI PT pesine gong edge see TOWE Co 0 OKE PT negative going edge ave HIGHLE s s Output Burr coma 1 9 Pr conroted Tree Ser Enable o 3 PemenenyEnabediOupurony o 9 Permanently Disable trputony
20. gisters If I O pins are used the observe mode could cause a value change which would cause the device to oscillate in and out of the Observe mode Therefore only dedicated input pins should be used for the Observe command Ce e Input Vin Pins Observe Mode T IL tp tio VoH VO Pins VoL Eom uM CLK Pin 1 2 Vu 08811G 43 Observability Waveform PALCE29MA16H 25 2 371 cl AMD POWER UP RESET The registered devices in the AMD PAL Family have been designed with the capability to reset during system power up Following power up all registers will be reset to LOW The output state will depend on the polarity of the output buffer This feature provides extra flexibility tothe designer and is especially valuable in simplify ingstate machine initialization A timing diagram and parameter table are shown below Due to the asynchronous operation of the power up reset and the wide range of ways Vcc can rise to its steady state two conditions are required to ensure a valid power up re set These conditions are m The Vcc rise must be monotonic W Following reset the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Parameter Symbol Parameter Description en Power Up Reset Time Io Im zs Input or Feedback Setup Time Clock Width See Switching Characteristics CHE fo Io 4V Power tR i ter Registered Active LOVV Output Clock Vc
21. ied state register latch The other eight macrocells have a single feedback path to the AND array This feedback is user selectable as either an I O pin or a register latch feedback see Figure 2a Each macrocell can provide true input output capability The user can select each macrocell register latch to be driven by either the signal generated by the AND OR ar ray or the corresponding I O pin When the I O pin is se lected as the input the feedback path provides the register latch input to the array When used as an input each macrocell is also user programmable for regis tered latched or combinatorial input The PALCE29MA16 has a dedicated CLK LE pin and one individual CLK LE product term or macrocell All macrocells have a programmable switch to choose be tween the CLK LE pin and the CLK LE product term as the clock or latch enable signal These signals are clock signals for macrocells configured as registers and latch enable signals for macrocells configured as latches The polarity of these CLK LE signals is also individually programmable Thus different registers or latches can be driven by different clocks and clock phases The Output Enable mode of each of the macrocells can be selected by the user The I O pin can be configured as an output pin permanently enabled or as an input pin permanently disabled It can also be configured as Common I OE Pin AMD cl a dynamic I O controlled by the Output Enable pin or by
22. mbinatorial Clock Vr Registered Latched 08811G 38 Output 08811G 40 Input Register Latch Reset Preset Input to Output Disable Enable 2 368 PALCE29MA16H 25 Com l KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don t Care Any Change OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing State AMD cl Permitted Unknown Center Line is High Impedance Off State KS000010 PAL SVO Ri Output R2 08811G 41 Does Not Apply SWITCHING TEST CIRCUIT R Measured Output Value 1 5V 390 Q H gt Z VoH 0 5 V 1 CL I Specification 1 SwithS e R tea tPZX ZH open 35 pF Z L closed 470 Q Ss LZ Vor 0 5 V LZ closed PALCE29MA16H 25 2 369 cl AMD PRELOAD The PALCE29MA16 has the capability for product term Preload When the global preload product term is true the PALCE29MA16 will enter the preload mode This feature aids functional testing by allowing direct setting of register states The procedure for Preload is as follows m Set the selected input pins to the user selected preload condition W Apply the desired register value to the I O pins This sets Q of the register The value seen on the I O pin after Preload will depend on whether the macrocell is active high or active low Pulse the clock pin pin 1 Remove the inputs to the
23. tches of the device A typical func tional test sequence would be to verify all possible state transitions for the device being tested This requires the ability to set the state registers into an arbitrary present state value and to set the device s inputs into an arbi trary present input value Once this is done the state machine is clocked into a new state or next state which can be checked to validate the transition from the present state In this way any transition can be checked Since preload can provide the capability to go directly to any desired arbitrary state test sequences may be greatly shortened Also all possible states can be tested thus greatly reducing test time and development costs and guaranteeing proper in system operation Observability The output register latch observability product term when asserted suppresses the combinatorial output data from appearing on the I O pin and allows the obser vation of the contents of the register latch on the output PALCE29MA16H 25 AMD cl pin for each of the logic macrocells This unique feature allows for easy debugging and tracing of the buried state machines In addition a capability of supervoltage ob servability is also provided Security Cell Asecurity cell is provided on each device to prevent un authorized copying of the user s proprietary logic de sign Once programmed the security cell disables the programming verifica
24. tered or latched with active HIGH or active LOW polarity The flexibility of the logic macro cells permits the system designer to tailor the device to particular application requirements Increased logic power has been built into the PALCE29MA16 by providing a varied number of logic CONNECTION DIAGRAMS Top View SKINNYDIP CLK LE 1 24 vec lo L 2 23 13 l OFo Lj 3 22 Ll VOF7 VOF LI 4 21 LI vOFe Oo 5 20 107 Vo L 6 19 LI VOs O2 L 7 18 Os 10s 8 17 1 04 VOFe 9 16 LI l OFs l OFs 10 15 LI VOF4 log 11 141 Io GND 12 13 h Note 08811G 2 Pin 1 is marked for orientation PIN DESIGNATIONS CLK LE Clock or Latch Enable GND Ground I Input UO Input Output VOF Input Output with Dual Feedback Vcc Supply Voltage NC No Connection product terms per output Of the 16 outputs 8 outputs have 4 product terms each 4 outputs have 8 product terms each and the other 4 outputs have 12 product terms each This varied product term distribution allows complex functions to be implemented in a single PAL device Each output can be dynamically controlled by a common Output Enable pin or Output Enable product term Each output can also be permanently enabled or disabled System operation has been enhanced by the addition of common asynchronous Preset and Reset product terms and a power up Reset feature The PALCE29MA 16 also incorporates Preload and Obser vability functions which p
25. tion preload and the obser vability modes The only way to erase the protection cell is by erasing the entire array and architecture cells in which case no proprietary design can be copied This cell should be programmed only after the rest of the de vice has been completely programmed and verified Programming and Erasing The PALCE29MA16 can be programmed on standard logic programmers It may also be erased to reset a pre viously configured device back to its virgin state Erasure is automatically performed by the programming hardware No special erasure operation is required Quality and Testability The PALCE29MA16 offers a very high level of built in quality The erasability of the device provides a direct means of verifying performance of all the AC and DC pa rameters In addition this verifies complete pro grammability and functionality of the device to yield the highest programming yield and post programming func tional yield in the industry Technology The high speed PALCE29MA16 is fabricated with AMD s advanced electrically erasable EE CMOS process The array connections are formed with proven EE cells Inputs and outputs are designed to be compat ible with TTL devices This technology provides strong input clamp diodes output slew rate control and a grounded substrate for clean switching 2 357 cl AMD LOGIC DIAGRAM SKINNY DIP PLCC Pinouts CLK LE 2 1
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AMD PALCE29MA16H 25 24 Pin EE CMOS Programmable Array Logic