ANALOG DEVICES Dual High Output Current High Speed Amplifier AD8017 handbook
Contents
1. Vs Figure 4 Test Circuit Gain 42 Figure 7 Test Circuit Gain gt 1 OUTPUT 100mV OUTPUT 100mV gt gt gt a 8 gt a INPUT 50mV INPUT 100mv gt B 200ns DIV 200ns DIV Figure 5 100 mV Step Response G 42 Vs gt 2 5 V or Figure 8 100 mV Step Response G 1 Vs 2 5 V or 6 V R 100 Q 6 V R 100 Q OUTPUT 4V OUTPUT 4V gt gt gt INPUT 2V gt e amp INPUT lt 4V 200ns DIV 200ns DIV Figure 6 4 V Step Response G 2 Vs gt t6 V Figure 9 4 V Step Response G 1 Vs 6 V R 100 Q R 100 Q REV A AD8017 Vout 2V p p G 2 DISTORTION dBc 0 1 1 10 100 FREQUENCY MHz Figure 10 Distortion vs Frequency Vs 6 V R 100 Q DISTORTION dBc 0 1 1 10 1 FREQUENCY MHz Figure 11 Distortion vs Frequency Vs 6 V R 25 Q HIGHEST HARMONIC DISTORTION dBc 0 100 200 300 400 500 600 OUTPUT CURRENT mA Figure 12 Distortion vs Output Current Vs 6 V f 1 MHz G 2 Vour 2V p p G 2 20 40 D I2. 0 1 1 10 100 1000 FREQUENCY MHz Figure 35 Output Crosstalk vs Frequency 1000000 100000 10000 INPUT IMPEDANCE Q OUTPUT IMPEDANCE Q 0 1 1 10 100 1000 FREQUENCY MHz Figure 36 Input and Output Impedance vs Frequency _10 REV A AD8017 THEORY OF OPERATION The AD8017 is a dual high speed CF amplifier that attains new levels of bandwidth BW power distortion and signal swing under heavy current loads Its wide dynamic performance in cluding noise is the result of both a new complementary high speed bipolar process and a new and unique architectural design The AD8017 basically uses a two gain stage complemen tary design approach versus the traditional single stage complementary mirror structure sometimes referred to as the Nelson amplifier Though twin stages have been tried before they typically consumed high power since they were of a folded cascode design much like the AD9617 This design allows for the standing or quiescent current to add to the high signal or slew current induced stages In the time domain the large signal output rise fall time and slew rate is typically controlled by the small signal BW of the amplifier and the input signal step amplitude respectively not the dc quies cent current of the gain stages with the exception of input level shift diodes Q1 Q2
3. t2 5V Output Short Circuit Duration ei en Un e edens dra Observe Power Derating Curves Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C Lead Temperature Range Soldering 10 sec 300 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device on a two layer board with 2500 mm of 2 oz copper at 25 C 8 lead SOIC package D 95 0 C W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8017 is limited by the associated rise in junction temperature The maximum safe junction temperature for plastic encapsulated device is determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junc tion temperature of 175 C for an extended period can result in device failure The output stage of the AD8017 is designed for maximum load current capability As a result shorting the output to common
4. E 60 S 2ND Ed D 80 3RD 100 120 0 1 1 10 FREQUENCY MHz 100 Figure 13 Distortion vs Frequency Vs 2 2 5 V R 100 Q Vi 2V p p 10g 2 20 a 30 5 LI z 40 o 50 D 2ND a 60 70 3RD 80 90 0 1 1 10 FREQUENCY MHz 100 Figure 14 Distortion vs Frequency Vs 2 5 V R 25 2 HIGHEST HARMONIC DISTORTION dBc 100 200 OUTPUT CURRENT mA 400 Figure 15 Distortion vs Output Current Vs 2 5 V f 1 MHz G 2 REV A AD8017 20 0 40 20 40 60 E os I I Z z 60 80 2ND 0 80 5 2ND 2 A 100 a 3RD 100 3RD 120 z420 140 140 0 10 100 1000 0 10 100 1000 LOAD RESISTANCE 0 LOAD RESISTANCE Q Figure 16 Distortion vs R Vs 6 V G 42 Vour 2 V p p Figure 19 Distortion vs R Vs 2 5 V G 2 f 1 MHz Vout 2 V p p f 1 MHz Vs 6V 10 t 1MHz 8 T G 2 S 20 5 8 30 a a 40 S 6 50 lt RL 250 lt l 60 u u 2 70 S RL 1000 80 0 1 2 3 4 5 6 0 0 5 1 0 1 5 2 0 2
5. CPE equipment for ADSL SDSL VDSL and proprietary xDSL systems REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices OUTPUT VOLTAGE SWING V p p 1 10 100 1000 LOAD RESISTANCE Q Figure 1 Output Swing vs Load Resistance The AD8017 drive capability comes in a very compact form Utilizing ADI s proprietary Thermal Coastline SOIC package the AD8017 s total static and dynamic power on 12 V sup plies is easily dissipated without external heatsink other than to place the AD8017 on a 4 layer PCB The AD8017 will operate over the commercial temperature range 40 C to 85 C v LINE OUT POWER Vin INdB Np Ns TRANSFORMER Figure 2 Differential Drive Circuit for xDSL Applications One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2000 AD801 7 SPECIFICATIONS 25 C V 6 V R 100 Q Rc R 619 unless otherwise noted Parameter Conditions Min Typ Max Unit DYNAMI
6. POWER SUPPLY Supply Current Amp 7 0 7 7 mA Operating Range Dual Supply t2 2 6 0 V Power Supply Rejection Ratio 58 61 dB Operating Temperature Range 40 85 C NOTES Output current is defined here as the highest current load delivered by the output of each amplifier into a specified resistive load Ry 10 Q while maintaining an acceptable distortion level i e less than 60 dBc highest harmonic at a given frequency f 1 MHz Specifications subject to change without notice REV A AD8017 SPEC FI CATI 0 NS 25 C Vs 2 5 V R 100 Q Rr Rg 619 Q unless otherwise noted Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 2 Vour lt 0 4 V p p 75 120 MHz 0 1 dB Bandwidth Vour lt 0 4 V p p 40 MHz Large Signal Bandwidth Vour 4 V p p 100 MHz Slew Rate Noninverting Vour 2 V p p G 2 800 V us Rise and Fall Time Noninverting Vour 2 V p p 2 0 ns Settling Time 0 1 Vour 2 V Step 35 ns Overload Recovery Vin 2 5 V p p 74 ns NOISE HARMONIC PERFORMANCE Distortion Vout 2 V p p 2nd Harmonic 500 kHz Ry 100 0 25 Q 75 68 dBc 1 MHz Ry 100 0 25 Q 13 66 dBc 3rd Harmonic 500 kHz Ry 100 0 25 Q 91 88 dBc 1 MHz Ry 100 9 25 Q 19 14 dBc IP3 500 kHz Rr 100 0 25 Q 40 36 dBm IMD 500 kHz Rr 100 0 25 Q 18 64 dBc MTPR 26 kHz to 1 1 MHz 66 dBc Input Noise Voltage f 10 kHz 1 8 nV VHz Input Noise Current f 10 kH
7. Using two stages as opposed to one also allows for a higher overall gain bandwidth product GBWP for the same power thus providing lower signal distortion and the ability to drive heavier external loads In addition the second gain stage also isolates divides down A3 s input reflected load drive and the nonlinearities created resulting in relatively lower distortion and higher open loop gain See Figure 38 Z1 1 C1 21 IR IFC Overall when high external load drive and low ac distortion is a requirement a twin gain stage integrating amplifier like the AD8017 will provide excellent results for low power over the traditional single stage complementary devices In addition being a CF amplifier closed loop BW variations versus external gain variations varying Rg will be much lower compared to a VF op amp where the BW varies inversely with gain Another key attribute of this amplifier is its ability to run on a single 5 V supply due in part to its wide common mode input and output voltage range capability For 5 V supply operation the device obviously consumes less than half the quiescent power vs 12 V supply with little degradation in its ac and dc performance characteristics See specification pages for comparisons DC GAIN CHARACTER Gain stages A1 A1 and A2 A2 combined provide negative feedforward transresistance gain See Figure 38 Stage A3 is a unity gain buffer which provides external load isolation to
8. PSRR 5 2 O 60 50 70 60 80 70 90 100 80 0 1 1 10 100 1000 0 1 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 29 CMRR vs Frequency Vs gt x6 Vor Vs lt 2 5 V Figure 32 PSRR vs Frequency Vs 6 V or Vs 2 5 V 0 4 12 1000 N 10 jn c lt x I 8 100 ul ul o o o S o o z z lt a K 02 B a a 0 a ul 7 i 5 lt N en E o 4 gt lt 10 gt E 5 E 2 04 2 z 2 Z 0 0 1 0 0 01 0 1 1 10 100 0 0001 0 01 0 1 1 10 100 1000 FREQUENCY kHz FREQUENCY MHz Figure 30 Noise vs Frequency Figure 33 Open Loop Transimpedance and Phase vs Frequency REV A VN AD8017 G 2 Vout 2Vstep Ri 1000 Vs 6V Vout N O A a Q VOLTS OUTPUT VOLTAGE ERROR mV DIV DIV 0 10 20 30 40 50 60 70 80 90 TIME ns Figure 34 Settling Time Vs 6 0 V VOLTS Vour 2V p p 30 G 2 10 10 30 50 70 90 110 130 150 HL 1000 TIME ns Figure 37 Overload Recovery Vs 6 V G 2 50 R 100 Q Vy 5 Vp p T 1us CROSSTALK dB
9. ab R Refer to Figure 41 The situation is more complicated with a complex modulated signal In the case of a DMT signal taking the equivalent sine wave power overestimates the power dissipation by gt 15 For example Pour 16 dBm 40 mW Vour 50 Q 2 1 41 V rms or Vo 1 0 V at each amplifier output which yields a Pp of 0 436 W By actual measurement Pp for a DMT signal of 16 dBm requires 0 38 W of power to be dissipated by the AD8017 13 AD8017 0 8 POWER DISSIPATION Pp W e A 0 1 2 3 4 5 6 OUTPUT VOLTAGE Vo Vpk Figure 41 Power Dissipation Pp vs Output Voltage Vo R 50 Q Thermal Considerations The AD8017 in a Thermal Coastline SO 8 package relies on the device pins to assist in removing heat from the die at a faster rate than that of conventional packages The effect is to provide a lower Dc for the device To make the most effective use of this special details should be worked into the copper traces of the printed circuit board There will be a tradeoff however between designing a board that will maximally remove heat and one that will provide the desired ac performance This is the result of the additional para sitic capacitance on some of the pins that would be caused by the addition of extra heatsinking copper traces The first technique for maximum heatsinking is to use a heavy layer of copper 2 oz copper will provide better heatsinki
10. can cause the AD8017 to source or sink 500 mA To ensure proper operation it is necessary to observe the maximum power derating curves Direct connection of the output to either power supply rail can destroy the device MAXIMUM POWER DISSIPATION Watts 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE C Figure 3 Plot of Maximum Power Dissipation vs Temperature for AD8017 ORDERING GUIDE Model Temperature Range Package Description Package Option AD8017AR 40 C to 85 C 8 Lead SOIC SO 8 AD8017AR REEL 40 C to 85 C Tape and Reel 13 SO 8 AD8017AR REEL7 40 C to 85 C Tape and Reel 7 SO 8 AD8017AR EVAL Evaluation Board CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8017 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING emma ESD SENSITIVE DEVICE REV A Typical Performance Characteristics AD8017 6190 6190 6190 6190 Vin Vout Vs 0 1 10pF I 10uF
11. that this will not track the middle of the supplies as it will always have an output that is a fixed voltage from ground This also requires an additional active component that will impact the cost of the total solution A two resistor divider could also be used There is a tradeoff required here in the selection of the value of the resistors As the resistors become smaller the amount of power that they will dissipate will increase For two 1 kQ resistors the power dissi pation in this circuit would be 72 mW Thus in order to keep this power to a minimum it is desirable to make the resistors as large as possible Table I DSL Drive Amplifier Requirements for Various Combinations of Line Power Line Impedance and Turn Ratios Line Insertion Line Turns Crest Reflected Per Amp Peak Per Amplifier Peak Current Power Loss Load Ratio Factor Impedance R1 R2 Voltage Voltage Output Output 13 dBm 1 dB 1000 1 1 5 3 100 Q 50 Q 1 585 V rms 8 4 V peak 84 mA 13 dBm 1 dB 1000 1 2 5 3 25 Q 12 5Q 0 792 V rms 4 2 V peak 168 mA 12 REV A AD8017 The practical maximum value that these resistors can have is determined by the offset voltage that is created by the input bias current that flows through them The maximum input bias current into the inputs is 45 uA This will create an offset voltage of 45 mV per 1 kQ of bias resistor Fortunately the ac coupling of the stages provide
12. 5 OUTPUT VOLTAGE Volts OUTPUT VOLTAGE Volts Figure 17 Distortion vs Output Voltage Vs t6 V G 2 Figure 20 Distortion vs Output Voltage Vs 2 8 V f 1MHz G 2 f 1 MHz HIGHEST HARMONIC DISTORTION dBc HIGHEST HARMONIC DISTORTION dBc 0 1 2 3 4 5 6 0 0 5 1 1 5 2 2 5 OUTPUT VOLTAGE Volts OUTPUT VOLTAGE Volts Figure 18 Distortion vs Output Voltage Vs 6 V G 2 Figure 21 Distortion vs Output Voltage Vs 2 5 V f 10 MHz G 2 f 10 MHz REV A 7 AD8017 1 LR 1000 0 5 8 GAIN 2 l z 1 lt lt 3 E GAIN 5 g Ji ul ul N N E 3 GAIN 10 9 o z z a 5 6 1 10 100 1000 0 1 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 22 Frequenc
13. A2 Each stage uses a symmetrical complementary design A3 is also complementary though not explicitly shown This is done to reduce both second order signal distortion and overall quies cent power as discussed above In the quasi dc to low frequency region the closed loop gain relationship can be approximated as G 1 R Rg for Noninverting Operation G R Rg for Inverting Operation These basic relationships above are common to all traditional operational amplifiers AD8017 Figure 38 Simplified Block Diagram REV A 11 AD8017 APPLICATIONS Output Power Characteristics as Applied to ADSL Signals The AD8017 was designed to provide both relatively high cur rent and voltage output capability Figures 17 and 20 quantify the ac load current versus distortion of the device at loads of 100 O and 25 2 at 1 MHz Using approximately 50 dBc as the worst case distortion limit the AD8017 exhibits acceptable linearity to within approximately 1 4 V of either supply rail 12 V or 6 V while simultaneously providing 200 mA of load cur rent These levels are achieved at only 7 mA of quiescent cur rent for each amplifier ADSL applications require signal line powers of 13 dBm that can randomly peak to an instantaneous power or V x I product of 28 5 dBm This equates to peak to rms voltage ratio of 5 3 to 1 Using a 1 2 transformer in the ADSL circuit illustrated below and 100 Q as the line resistance a peak voltage of 4 2
14. C PERFORMANCE 3 dB Bandwidth G 2 Vour lt 0 4 V p p 100 160 MHz 0 1 dB Bandwidth Vour lt 0 4 V p p 70 MHz Large Signal Bandwidth Vour 4 V p p 105 MHz Slew Rate Noninverting Vour 2 V p p G 2 1600 V us Rise and Fall Time Noninverting Vour 2 V p p 2 6 ns Settling Time 0 1 Vour 4 V Step 35 ns Overload Recovery Vin 5 V p p 74 ns NOISE HARMONIC PERFORMANCE Distortion Vour 2 V p p 2nd Harmonic 500 kHz Rr 100 9 25 Q 78 71 dBc 1 MHz Ry 100 Q 25 Q 16 69 dBc 3rd Harmonic 500 kHz Ry 100 0 25 Q 105 91 dBc 1 MHz Ry 100 0 25 Q 81 72 dBc IP3 500 kHz Ry gt 100 0 25 Q 40 35 dBm IMD 500 kHz Ry 100 0 25 Q 16 66 dBc MTPR 26 kHz to 1 1 MHz 66 dBc Input Noise Voltage f 10 kHz 1 9 nV VHz Input Noise Current f 10 kHz Inputs 23 pANHz f 10 kHz Inputs 21 pANHz Crosstalk f 5 MHz 2 66 dB DC PERFORMANCE Input Offset Voltage 1 8 3 0 mV Tum T Max 4 0 mV Open Loop Transimpedance Vour 2 V p p 185 700 kQ INPUT CHARACTERISTICS Input Resistance Input 50 kQ Input Capacitance Input 2 4 pF Input Bias Current 16 45 UA Tum Tmax 67 UA Input Bias Current 1 0 25 UA Tum T ax 32 HA CMRR Vom 32 5 V 59 63 dB Input CM Voltage Range 5 1 V OUTPUT CHARACTERISTICS Output Resistance 0 2 Q Output Voltage Swing Ry 25Q t4 6 5 0 V Output Current Highest Harmonic lt 58 dBc 200 270 mA f 1 MHz Rr 10 Q Tum IMax Highest Harmonic lt 52 dBc 100 mA Short Circuit Current 1500 mA
15. U 0 Ab8017 ANALOG DEVICES Dual High Output Current High Speed Amplifier AD8017 PIN CONFIGURATION 8 Lead Thermal Coastline SOIC SO 8 FEATURES High Output Drive Capability 20 V p p Differential Output Voltage R 50 O 10 V p p Single Ended Output Voltage While Delivering 200 mA to a 25 O Load Low Power Operation 5 V to 12 V Voltage Supply 7 mA Amplifier Low Distortion 78 dBc 500 kHz SFDR R 100 0 Vo 2 V p p 58 dBc Highest Harmonic 1 MHz lo 270 mA RL 10 Q High Speed 160 MHz 3 dB Bandwidth G 2 1600 V ps Slew Rate APPLICATIONS xDSL PCI Cards Consumer DSL Modems Line Driver Video Distribution PRODUCT DESCRIPTION The AD8017 is a low cost dual high speed amplifier capable of driving low distortion signals to within 1 0 V of the supply rail It is intended for use in single supply xDSL systems where low distortion and low cost are essential The amplifiers will be able to drive a minimum of 200 mA of output current per amplifier The AD8017 will deliver 78 dBc of SFDR at 500 kHz required for many xDSL applications Fabricated in ADI s high speed XFCB process the high band width and fast slew rate of the AD8017 keep distortion to a minimum while dissipating a minimum amount of power The quiescent current of the AD8017 is 7 mA amplifier Low distortion high output voltage drive and high output current drive make the AD8017 ideal for use in low cost Cus tomer Premise End
16. V at a peak current of 168 mA will be required from the line driver output see Table I See detailed application below A higher turns ratio transformer can be used to reduce the primary out put voltage swing of the amplifier for devices that do not have the voltage swing but do have the current drive capability However this requires more than an equivalent increase in current due to the added Ix R losses from the transformer for the same receiver power Generally this will result in added distortion Table I below shows the ADSL ac current and volt ages required for both a 1 1 and 1 2 transformer turns ratio 12V O 1uF Figure 39 Single 12 V Supply ADSL Remote Terminal Transmitter Single 12 V Supply ADSL Remote Terminal RT Transmitter For consumer use it 15 desirable to create an ADSL modem that can be a plug in accessory for a PC In such an application the circuit should dissipate a minimum of power yet still meet the ADSL specification The circuit in Figure 39 shows a single 12 V supply circuit that uses the AD8017 as a remote terminal transmitter This supply voltage is readily available on the PCI connector of PCs The circuit configures each half of the AD8017 as an inverter with a gain of about six Both of the amplifier circuits are ac coupled at both the inputs and the outputs This makes the dc levels of the circuit independent of the other dc levels of the signal chain The inputs will generally be driv
17. distortion performance will be better When the circuit was run while providing the upstream drive signal in an ADSL system the supply current to the part was measured at 25 mA Thus the total power to the drive circuit was 300 mW This power winds up in three places the drive amplifier down the line and in the termination and interface circuitry The ADSL specification calls for 13 dBm or 20 mW into the line The line termination will consume an equal amount of power as it is the same resistance value About a 1 dB loss can be expected in the losses in the interface circuitry which trans lates into about 10 mW of power Thus the total power dissi pated in the AD8017 when used as a driver in this application is about 250 mW REV A Figure 40 Differential Driver Simplified Circuit Schematic It is important to consider the total power dissipation of the AD8017 in order to properly size the heatsinking area for your application The dc power dissipation for Vin 0 is simply Io Vcc Ver or 2 X Ig x Vs For the AD8017 this number is 0 17 W In this purely differential circuit we can use symmetry to simplify the computation for a dc input signal Pp 2x Io XVs Ax Vs Vo x 2 Rr This formula is slightly pessimistic due to the fact that some of the quiescent supply current commutates during sourcing or sinking current into the load For a sine wave source integra tion over a half cycle yields AVoVs Vo Pp 2xIgxVs 2x
18. ecommended component values for the AD8017 and Figures 42 44 show recommended layouts for the 8 lead SOIC package for a positive gain Proper RF design techniques and low parasitic component selections are mandatory Table II Typical Bandwidth vs Gain Setting Resistors Vs 6 V Rr 100 Q Small Signal Gain Re Q Re O Rr OD 3 dB BW MHz 1 619 619 54 5 110 1 619 49 9 320 Figure 43 Universal SOIC Noninverter Top 2 619 619 49 9 160 10 619 68 8 49 9 40 Ry chosen for 50 Q characteristic input impedance The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path The ground plane should be removed from the area near the input pins to reduce stray capacitance Chip capacitors should be used for supply bypassing see Fig ures 4 and 7 One end should be connected to the ground plane and the other within 1 8 in of each power pin An addi tional 4 7 uF 10 uF tantalum electrolytic capacitor should be connected in parallel The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum Capacitance greater than 1 5 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gain Figure 44 Universal SOIC Noninverter Bottom B ANALOS O DEUICES a U 0UT2 Figure 42 Universal SOIC Non
19. en by the output of an active filter which has a low output impedance Thus there will be a minimum of loading of the source caused by the 169 Q input impedance in the pass band The output will require a 1 2 step up transformer to drive a 100 Q line The reflected impedance back to the primary will be 25 Q With 25 Q of series termina tion added 12 5 Q in each output the effective load that the differential amplifier outputs will drive is 50 2 The input and output ac coupling provides two high pass cir cuits The inputs are formed by the 0 1 uF capacitor and the 169 2 resistor which provides a break frequency of about 9 4 kHz The two 1 uF capacitors in the output along with the 50 Q effective load provides a 6 4 kHz break frequency in the output side Both of these circuits want to reject the Plain Old Telephone System POTS band dc to 4 kHz while passing the ADSL upstream band which starts at about 20 kHz The positive inputs must be biased at mid supply which is nominally 6 V This will maintain the maximum dynamic range of the output in each direction regardless of the tolerance of the supply The inverting configuration was chosen as this requires a steady dc current from this supply as opposed to the signal dependent current that would be required in a noninvert ing configuration Several options were studied for creating this supply A voltage regulator could be used but there are several disad vantages The first is
20. he remainder of the device pins are active signal pins and must be treated a bit more carefully Pins 2 and 6 are the summing junctions of the op amps and will be the most adversely affected by stray capacitance For this reason the copper area of these pins should be minimized In addition the copper nearby on the component layer should be kept more than 3 mm 5 mm away from these pins where possible The inner and opposite side circuit layers directly below the summing junctions should also be void of copper The positive inputs and outputs can withstand somewhat more capacitance than the summing junctions without adversely af fecting ac performance However these pins should be treated carefully and the amount of heatsinking and excess capacitance should be analyzed and adjusted depending on the application If maximum ac performance is desired and the power dissipa tion 15 not extreme then the copper area connected to these pins should be minimized If the ac performance is not very critical and maximum power must be dissipated then the cop per area connected to these pins can be increased As in many other areas of analog design the designer must use some judg ment based on the consideration of the above in order to pro duce a satisfactory design REV A AD8017 LAYOUT CONSIDERATIONS The specified high speed performance of the AD8017 requires careful attention to board layout and component selection Table II shows r
21. inverter Top Silkscreen REV A 15 AD801 7 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead SOIC SO 8 0 1968 5 00 oa A 8 5 0 1574 4 00 0 2440 6 20 V e 0 1497 3 80 4 0 2284 5 80 PIN 1 0 0688 1 75 F 0 0196 0 50 5 0 0098 0 25 0 0532 T 38 Fe 0 0099 0 25 0 0040 0 10 D A gt k Jt SEATING Gan 0 0098 UR 25 0 e 27 PLANE 0 35 55075 0 19 0 0160 0 41 16 REV A C3428 0 5 00 rev A 01042 PRINTED IN U S A
22. ng than 1 oz copper Additional internal circuit layers can also be used to more effectively remove heat and to provide better power and ground distribution There are no ground pins per se on the AD8017 when run on a dual supply but the power supplies Pins 4 and 8 are at ac ground Thus these pins can be safely tied to a maximum 14 area of copper foil without affecting the ac performance of the part On the surface side of the board the copper area that connects to Pins 4 and 8 should be enlarged and spread out to the maximum extent possible As a practical matter there will be diminishing returns from adding copper more than a few centimeters from the pins When the power supplies are run on the board on internal power planes then these should also be made as large as practi cal and multiple vias 70 012 in or 0 3 mm should be pro vided from the component layer near the power supply pins of the AD8017 to the inner layers These vias should not have any of the traditional thermal relief spokes to the planes because the function of these is to impede heat flow for ease of soldering This is counter to the effect desired for heatsinking On the side of the board opposite the component additional heatsinking can be provided by adding copper area near the vias to further lower the thermal resistance Additional vias can be provided throughout to better conduct heat from the inner layers to the outer layers T
23. s only unity gain for this dc offset voltage which is another advantage of this configuration Any dc offset in the output will limit the amount of dynamic signal swing that will be available between the rails The circuit shown uses two 4 7 V Zener diodes that provide a voltage drop which serves to limit the power dissipation in the bias circuit This allows the use of smaller value resistors in the bias circuit Thus for this circuit the current will be 12 V 2 x 4 7 V 2 kQ 1 3 mA Thus this circuit will dissipate only 15 6 mW yet only induce a maximum of 40 mV of offset at the output This circuit will also track the midpoint of the supplies over their specified tolerance range The distortion of the circuit was measured with a 50 Q load The frequency used was 500 kHz which is beyond the maxi mum required for the upstream signal For ADSL over POTS a maximum frequency of 135 kHz is required For ADSL over ISDN the maximum frequency is 276 kHz The amplitude was 20 V p p 10 V p p for each amplifier which is the maximum crest signal that will be required The second harmonic was better than 80 dBc while the third harmonic was 64 dBc This represents a worst case of the absolute maximum signal that will be required for only a very small statistical basis and at a frequency that is higher than the maximum required For a statistical majority of the time the signal will be at a lower am plitude and frequency where the
24. y Response Vs gt x6 V Figure 25 Frequency Response Vs 2 5 V 0 3 0 3 G 2 RL 1000 0 2 G 2 0 2 RL 1000 m 01 9 0 l o E 2 S 00 00 lt d m m 8 0 1 201 ei e 0 2 0 2 0 3 0 3 0 1 1 10 100 1000 0 1 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 23 Gain Flatness Vs 6 V Figure 26 Gain Flatness Vs 2 5 V 9 3 Vour 1Vj Vi 2V p OUT VRMS 3 OUT p p m 6 3 PITI ITT gt 6 a 9 S 1 a d 12 d lt 15 lt 12 sl 8 8 9 18 L LU 9 15 HHH LU LI d IN E NIL Y 5 2 21 M a 18 E G 2 NN o N 8 21 R 1000 vi 2 24 NH A A T e 27 G 2 24 X Y 1000 T VU 30 x 27 33 30 0 1 1 10 100 1000 01 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 24 Output Voltage vs Frequency Vs 2 t6 V Figure 27 Output Voltage vs Frequency Vs 2 5 V g REV A AD8017 120 100 80 5 d m I 1 60 9 a 3 40 20 0 0 2 4 6 8 FREQUENCY kHz SERIES RESISTANCE 0 Figure 28 Multitone Power Ratio Vs 6 V 13 dBm Figure 31 Rs and C vs 30 Overshoot Output Power into 25 Q 0 0 10 10 20 20 PSRR 30 20 m 40 Ki I 50 40
25. z Inputs 23 pANHz f 10 kHz Inputs 21 pANHz Crosstalk f 5 MHz 2 66 dB DC PERFORMANCE Input Offset Voltage 0 8 2 0 mV Open Loop Transimpedance Vour 2Vp p 40 166 Hi INPUT CHARACTERISTICS Input Resistance Input 50 kQ Input Capacitance Input 2 4 pF Input Bias Current 16 40 UA Tum Tmax 62 HA Input Bias Current 2 25 UA Tum Tmax 32 UA CMRR Vem 11 0 1 0 57 60 dB Input CM Voltage Range 1 6 V OUTPUT CHARACTERISTICS Output Resistance 0 2 Q Output Voltage Swing Rp 25 Q 1 55 1 65 V Output Current Highest Harmonic lt 55 dBc 100 120 mA f 1 MHz 10 Q Tum max Highest Harmonic lt 50 dBc 60 mA Short Circuit Current 1300 mA POWER SUPPLY Supply Current Amp 6 2 7 mA Operating Range Dual Supply t2 2 t6 0 V Power Supply Rejection Ratio 59 62 dB Operating Temperature Range 40 85 C NOTES Output current is defined here as the highest current load delivered by the output of each amplifier into a specified resistive load Ry 10 Q while maintaining an acceptable distortion level i e less than 60 dBc highest harmonic at a given frequency f 1 MHz Specifications subject to change without notice REV A AD8017 ABSOLUTE MAXIMUM RATINGS Supply Voltage 13 2 V Internal Power Dissipation2 Small Outline Package R 1 3 W Input Voltage Common Mode Vs Differential Input Voltage
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