ANALOG DEVICES Low Power High Output Current xDSL Line Driver AD8016 handbook
Contents
1. 1 10 100 500 FREQUENCY MHz Figure 24 Frequency Response Vs 6 V PWDN1 PWDNO Codes 11 5 8 1000 4990 5 2 4 7 10 13 16 19 10 100 500 FREQUENCY MHz Figure 25 PSRR vs Frequency Vs 6 10 FREQUENCY MHz Figure 26 PSRR vs Frequency Vs 12 100 500 REV 180 90 160 80 3140 gt T 120 60 o o Z 100 509 gt 409 60 309 2 5 2 40 20 2 20 10 0 0 10 100 1k 10k 100k 1M 10M FREQUENCY MHz Figure 27 Noise vs Frequency gt 5 2 x Rp 1kO S Vout 2VsrEP gt 1000 a gt N 1 tc tc ul lt E gt gt a 2 o 5 0 5 10 15 20 25 30 35 40 45 TIME ns Figure 28 Settling Time 0 1 V 12 20 Vour 2V p p 30 HT Rf 4990 5 1000 a 1 50 9 60 70 80 90 0 03 0 1 10 100 500 FREQUENCY MHz Figure 29 Output Crosstalk vs Fre2. 26 4 Internal Power Dissipation PSOP3 Package 2 2 W Batwing Package 14 EPAD Package 14 Input Voltage Common Mode tVs Differential Input Voltage tVs Output Short Circuit Duration Sas oh Sug acest ee odd doa Observe Power Derating Curves Storage Temperature Range 65 C to 125 Operating Temperature Range 40 C to 85 Lead Temperature Range Soldering 10 sec 300 C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device on a four layer board with 10 inches of 1 oz copper at 85 20 lead PSOP3 package 18 C W Specification is for device on four layer board with 10 inches of 1 oz copper at 85 24 lead Batwing package 28 C W Specification is for device on a four layer board with 9 inches of 1 oz copper at 85 C 28 lead EPAD package 29 C W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipat
3. SE 15 Que TO e Figure 50 Layer 1 Figure 48 Layer 1 Figure 51 Silkscreen Bottom Figure 49 Power Ground Plane 18 REV 8016 ALP EVALUATION BOARD BILL OF MATERIALS PTION AD8016 SOIC Rev A Evaluation PC Board 4 40 x 1 4 Panhead SS Machine Screw 4 40 x 1 2 Threaded Alum Standoffs SIERRA PROTO EXPRESS ADS 30 1 1 ADS 30 16 2 Eval PC Board Qty Description Vendor Ref Desc 5 10 uF 25 V Size Tantalum Chip Capacitor ADS 4 7 2 1 3 13 14 10 0 1 50 1206 Size Ceramic Chip Capacitor ADS 4 5 18 C15 21 24 26 2 49 9 01 1 8 W 1206 Size Chip Resistor ADS 3 14 26 R11 15 2 100 Q 1 1 8 W 1206 Size Chip Resistor ADS 3 18 40 R8 14 1 100 Q 5 3 0 W Metal Film Power Resistor ADS 3 24 1 3 1 00 1 1 6 W 1206 Size Chip Resistor ADS 3 18 11 R17 R19 2 10 0 kQ 1 1 6 W 1206 Size Chip Resistor ADS 3 18 119 R13 and 16 1 Test Point Black GND ADS 12 18 44 GND 2 Test Point Brown ADS 12 18 59 TP10 11 4 Test Point Red ADS 12 18 43 17 19 21 2 Test Point Orange ADS 12 18 60 TP3 15 16 1 Test Point Yellow ADS 12 18 32 TP12 2 Test Point Green ADS 12 18 61 TP7 9 2 Test Point Blue ADS 12 18 62 TP20 22 2 Test Point Violet ADS 12 18 63 TP4 5 4 Test Point Grey ADS 12 18 64 2 13 14 2 Test Point White ADS 12 18 42 6 8 2 3 Green Terminal Block ONSHORE EDZ250 3 ADS 12 19 14 1
4. 30 40 50 a eo 5 a o 70 a 80 PWDN 1 0 1 1 90 0 5 10 15 20 0 5 10 15 20 DIFFERENTIAL OUTPUT V p p DIFFERENTIAL OUTPUT V p p Figure 17 Distortion vs Output Voltage Second Figure 20 Distortion vs Output Voltage Third Harmonic Harmonic 6 V G 10 f 1 MHz 500 Vs 6 V G 10 f 1 MHz R 500 Differential Differential REV 7 8016 NORMALIZED FREQUENCY RESPONSE dB OUTPUT VOLTAGE Figure 22 Output Voltage vs Frequency Vs 12 V CMRR dB Ri 1000 1 0 12 04 15 18 0 0 21 24 27 1 10 100 500 FREQUENCY MHz Figure 21 Frequency Response Vs 12 V PWDN1 PWDNO Codes 11 19 1 10 100 FREQUENCY MHz 20 500 1 0 0 0 80 0 03 0 1 1 10 FREQUENCY MHz 100 500 Figure 23 vs Frequency Vs 12 PWDN1 PWDNO Codes NORMALIZED FREQUENCY RESPONSE dB PSRR dB PSRR dB 6 Vin 40 5 g 1000 1 0 12 0 1 15 18 0 0 21 24
5. at Vs 12 V 2 PWDN1 0 1 1 Vg PWDN1 0 1 1 PWDN1 0 1 0 Ris Vs 11 4V PWDN1 0 1 0 DYNAMIC HEADROOM dB 1 11 12 13 14 15 16 17 18 19 2 DOWNSTREAM TURNS RATIO Figure 40 Dynamic Headroom vs XFMR Turns Ratio Vs r 12 V Once an optimum turns ratio is determined the amplifier will have an MTPR performance for each setting of the power down pins The table below demonstrates the effects of reducing the total power dissipated by using the PWDN pins on MTPR performance when driving 20 4 dBm downstream onto the line with a transformer turns ratio of 1 1 4 Table III Dynamic Power Dissipation for Downstream Transmission PWDNI PWDNO PD W MTPR 1 1 1 454 78 dBc 1 0 1 262 75 3 dBc 0 1 1 142 57 2 dBc 0 0 0 120 This mode is quiescent power dissipation REV A GENERATING DMT At this time DMT modulated waveforms are not typically menu selectable items contained within arbitrary waveform generators Even using AWG software to generate DMT signals AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the D A converters and output drivers used by AWG manufactur ers Similar to evaluating single tone distortion performance of an amplifier MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver un
6. 2 1 2 Green Terminal Block ONSHORE EDZ250 2 ADS 12 19 13 TB3 5 1 Inch Center Shunt Berg 65474 001 ADS 11 2 38 5 Male Header 1 Inch Center Berg 69157 102 ADS 11 2 37 5 Conn BNC Vert MT Telegartner 10100141944 ADS 12 6 22 52 56 1 AMP 555154 1 MOD JACK SHIELDED 6 6 D K A 9024 1 3 Pin Gold Male Header Waldom WM 2723 ND D K WM 2723 ND JP6 3 3 Pin Gold Male Locking Header Waldom WM 2701 ND D K WM 2701 ND P2 4 1 AD8016 ARB ADS AD 8016 XRP D U T 1 4 4 0 2 1 1 4 Turns Ratio RF Transformer from CoEv C1374 Rev 2 T1 T2 REV A 19 AD8016 0 0433 1 10 MAX x 45 0 4370 11 10 0 4331 11 00 0 4252 10 80 TOP VIEW 0 5709 14 50 0 5591 14 20 0 5472 13 90 0 6299 16 00 0 6260 15 90 OUTLINE DIMENSIONS Dimensions shown in inches and mm 20 Lead PSOP3 RP 20A 0 5118 13 00 m 0 3543 9 00 0 2441 6 20 0 2283 5 80 ME 0 0039 0 10 0 0020 0 05 0 0433 1 10 MAX 0 1142 2 90 MAX AE 2 PLACES 2 PLACES DETAILA 22020 2 09 0 6220 15 80 0 0000 0 00 0 1417 3 60 0 00 0 1319 3 35 0 0394 1 00 0 1220 3 10 0 0354 0 90 he 0 0315 0 80 187 END VIEW SEATING 0 0500 0 0209 0 53 05 0 0079 0 20 1 27 0 0157 0 40 0 0433 1 10 0 0039 0 10 BSC 0 0315 0 80 24 Lead Ba
7. 5 0 1 60 tc E o 70 PWDN 1 0 1 1 90 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 PEAK OUTPUT CURRENT mA PEAK OUTPUT CURRENT mA Figure 11 Distortion vs Peak Output Current Second Figure 14 Distortion vs Peak Output Current Third Harmonic 12 100 f 100 kHz Single Ended Harmonic Vs 12 100 5 100 kHz Single Ended 6 REV 08016 DISTORTION dBc DISTORTION dBc PWDN 1 0 1 1 WDN 1 0 1 1 0 100 200 300 400 500 600 0 100 200 300 400 500 600 PEAK OUTPUT CURRENT mA PEAK OUTPUT CURRENT mA Figure 15 Distortion vs Peak Output Current Second Figure 18 Distortion vs Peak Output Current Third Harmonic Vs 6 5 f 100 kHz Single Ended Harmonic Vs 6 V 5 5 f 100 kHz Single Ended DISTORTION dBc DISTORTION dBc PWDN 1 0 1 1 PWDN 1 0 1 1 0 5 10 15 20 2 30 35 40 0 5 10 15 20 2 30 35 40 DIFFERENTIAL OUTPUT p p DIFFERENTIAL OUTPUT Figure 16 Distortion vs Output Voltage Second Figure 19 Distortion vs Output Voltage Third Harmonic Vs 12 G 10 f 1 MHz 500 Harmonic 12 10 f 1 MHz 50Q Differential Differential
8. an external pull down resistor to ground or a current sink attached to the BIAS pin can be used to set Ig to lower levels see Figure 39 The BIAS pin may be used in combination with the PWDNI and PWDNO pins however diminished performance may result when Io is lowered too much Current pulled away from the BIAS pin will shunt away a portion of the internal bias cur rent Setting PVDNI PWDNO to Logic 0 also shunts away a portion of the internal bias current The reduction of quiescent bias levels due to the use of PWDN1 and PWDNO is consistent with the percentages established in Table II When PWDNO alone is set to Logic 0 and no other means of reducing the internal bias currents is used full rate ADSL signals may be driven while maintaining reasonable levels of MTPR 3 3V LOGIC R2 R1 BIAS 2N3904 1 47 FOR 12Vg OR 12 5 R1 22kO FOR x6Vs Figure 38 Logic Drive of BIAS Pin for Complete Amplifier Shutdown THERMAL SHUTDOWN AD8016ARB and ARP have been designed to incorporate shutdown protection against accidental thermal overload In the event of thermal overload the AD8016 was designed to shut down at a junction temperature of 165 C and return to normal operation at a junction temperature 140 C AD8016 will continue to operate cycling on and off as long as the thermal overload condition remains The frequency of the protection cycle depends on the ambient environment severity
9. use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices PIN CONFIGURATION 20 Lead PSOP3 24 Lead Batwing RP 20 RB 24 NC NO CONNECT NC NO CONNECT 28 Lead HTSSOP RE 28 NC NO CONNECT AD8016 is available low cost 24 lead SOIC a ther mally enhanced 20 lead PSOP and a 28 lead HTSSOP with an exposed leadframe ePAD Operating from 12 V supplies the AD8016 requires only 1 5 W of total power dissipation refer to the Power Dissipation section for details while driving 20 4 dBm of power downstream using the xDSL hybrid in Figure 33a and Figure 33b Two digital bits PWDNO PWDN1 allow the driver to be capable of full performance an output keep alive state or two intermediate bias states The keep alive state biases the output transistors enough to provide a low imped ance at the amplifier outputs for back termination The low power dissipation high output current high output voltage swing flexible power down and robust thermal packaging enable the AD8016 to be used as the Central Office CO terminal driver in ADSL HDSL2 VDSL and proprietary xDSL systems One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 200
10. REV A 15 8016 841 019 SLNdLNO LWA TIVILN3H3HHIG L 4 L 8 e or zaa ega vaa 1202 MY sf eco _ _ Te 2H 98 620 ead 2 sco CEPR EEESRESIESISEE dt _ o __ vi sco L 2 22 3201 amp 1 82 610 o 6 a lt 60 aa v o S3H T h dIGNid9t 1444 44 44 41 144444444 au 5 ele Lo o 191X3 a v 390 3101 3101 3101 lar vo 9 o 541 mm T 8141 441 941 Edl 99 sa va 33AV an9a Figure 45 DMT Signal Generator Schematic REV A 16 8016 10 5 AGND3 4 5 TP7 1 TP15 R20 C11 R2 AD8016 VT C6 R4 TP16 P1 VR 8 Figure 46a Schematic AD8016ARB EVAL 19 L5 BEAD EE c15 c26 108 2 1 ET C16 C25 TP21 L4 1821 o VR TP22 12 12 1 T 4 VL TP24 23 TP25 26 TP27 28 TP29 4562 C20 c18 10 Figure 46b Schematic AD8016ARB EVAL REV A 17 8016 LAYOUT AD8016ARB EVAL 4 ANALOG DEVICES AD8016 SOIC Pa
11. current demands from the differential driver changes depending on the transformer REV A 8016 turns ratio The point on the curve indicating maximum dynamic headroom is achieved when the differential driver delivers both the maximum voltage and current while maintaining the lowest possible distortion Below this point the driver has reserve cur rent driving capability and experiences voltage clipping while above this point the amplifier runs out of current drive capabil ity before the maximum voltage drive capability is reached Since a transformer reflects the secondary load impedance back to the primary side by the square of the turns ratio varying the turns ratio changes the load across the differential driver In the transformer configuration of Figure 46a and 46b the turns ratio of the selected transformer is effectively doubled due to the parallel wiring of the transformer primaries within this ADSL driver hybrid The following equation may be used to calculate the load impedance across the output of the differential driver reflected by the transformers from the line side of the xDSL driver hybrid 7 is the primary side impedance as seen by the differential driver 72 is the line impedance and is the trans former turns ratio 22 2 2x Figure 40 shows the dynamic headroom in each subband of a downstream DMT waveform versus turns ratio running at 100 and 60 of the quiescent power while maintaining 65 dBc of
12. of full quiescent power see Table II Table II PWDN Code Selection Guide PWDNI PWDNO Code Code Quiescent Bias Level 1 1 100 Full ON 1 0 60 0 1 40 0 0 25 Low Zour but Not OFF X X Full OFF High via 250 uA Pulled Out of BIAS Pin The bias level can be controlled with TTL logic levels HI 1 applied to PVDNI and PWDNO pins alone or in combination with BIAS control pin The DGND or digital ground pin is the logic ground reference for PWDN1 PWDNO pins In typical ADSL applications where 12 V or 6 V supplies also single supplies are used the DGND pin is connected to analog ground The BIAS control pin by itself is a means to continuously adjust the AD8016 internal biasing and thus quiescent current pulling out a current of 0 or open to approximately 200 the quiescent current can be adjusted from 100 full ON to a full OFF condition The full OFF condition yields a high output impedance Because of on chip resistor variation of up to 20 the actual amount of current required to fully shut down the AD8016 can vary To institute a full chip shutdown a pull down current of 250 is recommended See Figure 38 for logic drive circuit for complete amplifier shutdown Figures 34 and 35 show the relationship between current pulled out of 11 8016 BIAS Ipras and the supply current Ig A typical shut down Ig is less than 1 mA total Alternatively
13. to air thermal resistance or THERMAL TESTING A wind tunnel study was conducted to determine the relationship between thermal capacity i e printed circuit board copper area air flow and junction temperature Junction to ambient ther mal resistance was also calculated for the AD8016ARP AD8016ARE and AD8016ARB packages The AD8016 was operated in a noninverting differential driver configuration typical of an xDSL application yet isolated from any other modem components Testing was conducted using a 1 ounce copper board in an ambient temperature of 24 C over air flows of 200 150 100 and 50 0 200 and 400 for AD8016ARE linear feet per minute LFM and for ARP and ARB packages as well as in still air The four layer PCB was designed to maximize the area of copper on the outer two layers of the board while the inner layers were used to configure the AD8016 in a differential driver circuit The PCB measured 3 x 4 inches in the beginning of the study and was progressively reduced in size to approxi mately 2 x 2 inches The testing was performed in a wind tunnel to control air flow in units of LFM The tunnel is approximately 11 inches in diameter AIR FLOW TEST CONDITIONS DUT Power Typical DSL DMT signal produces about 1 5 W of power dissipation in the AD8016 package The fully biased PWDNO and PWDNI Logic 1 quiescent current of the AD8016 is 25 mA 1 MHz differential sine wave at an ampli tude of 8 V p p amp
14. 0 AD8016 SPECIFICATIONS 25 C V 12 V 100 PWDNO PWDN1 1 1 40 C Tmax 85 C unless otherwise noted Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth 1 Rp 1 5 0 2 V 380 MHz 5 499 Q Vout lt 0 5 69 78 MHz Bandwidth for 0 1 dB Flatness 5 499 0 0 2 V 16 38 MHz Large Signal Bandwidth Vout 4 V p p 90 MHz Peaking Vout 0 2 V lt 50 MHz 0 1 dB Slew Rate Vout 4 V p p G 2 1000 V us Rise and Fall Time Vout 2 V p p 2 ns Settling Time 0 1 Vour 2 V p p 23 ns Input Overdrive Recovery Time Vout 12 5 V 350 ns NOISE DISTORTION PERFORMANCE Distortion Single Ended Vout 2 V p p 5 Rp 499 Q 2nd Harmonic fo 1 MHz R 100 0 25 Q 75 62 64 dBc 3rd Harmonic fo 1 MHz R 100 0 25 Q 88 74 93 16 dBc Multitone Power Ratio 26 kHz to 1 1 MHz 1000 PLINE 20 4 dBm 75 dBc IMD 500 kHz Af 10 kHz 100 9 25 Q 84 80 88 85 dBc IP3 500 kHz 100 0 25 Q 42 40 43 41 dBm Voltage Noise RTI f 10 kHz 2 6 4 5 nV VHz Input Current Noise f 10 kHz 18 21 pANHz INPUT CHARACTERISTICS RTI Offset Voltage 3 0 1 0 3 0 mV Input Bias Current 45 45 Input Bias Current 75 4 75 Input Resistance 400 kQ Input Capacitance 2 pF Input Common Mode Voltage Range 10 10 Common Mode Rejection Ratio 58 64
15. 00 0 100 200 300 400 500 600 700 800 900 5 b Overload Recovery Va 12 G 5 1000 33 PWDN 1 0 BA Figure 34 lo vs Pin Current 12 10 lg mA OUTPUT SWING Volts PWDN 1 0 1 1 1 0 8 0 1 0 0 0 50 100 150 200 Igias BA Figure 35 Ig Pin Current VS 6 6v 6V Figure 36 Output Voltage vs REV A 8016 THEORY OF OPERATION The AD80106 is a current feedback amplifier with high 500 mA output current capability With a current feedback amplifier the current into the inverting input is the feedback signal and the open loop behavior is that of a transimpedance 4 or The open loop transimpedance is analogous to the open loop voltage gain of a voltage feedback amplifier Figure 37 shows a simplified model of a current feedback amplifier Since is proportional 1 g the equivalent voltage gain is just Tz X gy where gn is the transconductance of the input stage Basic analysis of the follower with gain circuit yields RES 8 Tz S Gx where G 1 1 Rw 25 Recognizing that x lt lt low gains the familiar result of constant bandwidt
16. 25 Q 80 68 82 70 Multitone Power Ratio 26 kHz to 138 kHz 1000 Pune 13 dBm 68 dBc IMD 500 kHz Af 110 kHz 1002 25 Q 87 82 88 83 dBc IP3 500 kHz 42 39 42 39 dBm Voltage Noise RTI f 10 kHz 4 5 nV VHz Input Current Noise f 10 kHz 17 20 pANHz INPUT CHARACTERISTICS RTI Offset Voltage 3 0 0 2 3 0 Input Bias Current 25 10 25 Input Bias Current 30 10 30 Input Resistance 400 Input Capacitance 2 pF Input Common Mode Voltage Range 4 4 Common Mode Rejection Ratio 60 66 dB OUTPUT CHARACTERISTICS Output Voltage Swing Single Ended 1000 5 5 Linear Output Current G 5 R 5 Q f 100 kHz 60 dBc SFDR 300 420 mA Short Circuit Current 830 mA Capacitive Load Drive Rs 100 50 pF POWER SUPPLY Quiescent Current PWDNI PWDNO 1 1 8 9 7 mA Amp 1 0 6 6 9 mA Amp 0 1 4 5 0 mA Amp 0 0 3 4 1 mA Amp Recovery Time To 95 of Ig 23 us Shutdown Current 250 uA Out of Bias Pin 1 0 2 0 mA Amp Power Supply Rejection Ratio AVs 1V 63 80 dB OPERATING TEMPERATURE RANGE 40 85 5 15 Figure 43 R20 R21 0 Q open Specifications subject to change without notice LOGIC INPUTS CMOS Compatible Logic wono 12 or 6 V Full Temperature Range Parameter Min Typ Max Unit Logic 1 Voltage 2 2 Logic 0 Voltage 0 0 8 REV 3 8016 ABSOLUTE MAXIMUM RATINGS Supply
17. 39 8016 hy ANALOG DEVICES Low Power High Output Current XDSL Line Driver AD8016 FEATURES xDSL Line Driver that Features Full ADSL CO Central Office Performance on 12 V Supplies Low Power Operation 5 V to 12 V Voltage Supply 12 5 mA Amp Typ Total Supply Current Power Reduced Keep Alive Current of 4 5 mA Amp High Output Voltage and Current Drive lout 600 mA 40 V Differential Output Voltage 50 Vs 12V Low Single Tone Distortion 75 dBc 1 MHz SFDR 100 Vo 2 V p p 75 dBc 26 kHz to 1 1 MHz 2 ne 100 Pune 20 4 dBm High Speed 78 MHz Bandwidth 3 dB G 5 40 MHz Gain Flatness 1000 V s Slew Rates PRODUCT DESCRIPTION The AD8016 high output current dual amplifier is designed for the line drive interface in Digital Subscriber Line systems such as ADSL HDSL2 and proprietary xDSL systems The drivers are capable in full bias operation of providing 24 4 dBm output power into low resistance loads enough to power a 20 4 dBm line including hybrid insertion loss 1OdB DIV 549 3 550 3 551 3 552 3 553 3 554 3 555 3 556 3 557 3 558 3 559 3 FREQUENCY kHz Figure 1 Multitone Power Ratio Vs 12 V 20 4 Output Power into 100 O Downstream REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its
18. 4 bit DMT waveforms Upstream data is contained in the 24 wfm files and down stream data in the 128 wfm files These DMT modulated signals are used to evaluate xDSL products for Multitone Power Ratio or MTPR performance The data files are used in pairs adslu24 wfm and adsll24 wfm go together etc and are loaded into Tektronics AWG2021 arbitrary waveform generator The adslu24 wfm is loaded via the AWG2021 floppy drive into Channel 1 while the adsll24 wfm is simultaneously loaded into Channel 2 The num ber in the file name prefixed with u goes into CH1 or upper channel and the 1 goes into CH2 or the lower channel 12 bits from are combined with 2 bits from CH2 to achieve 14 bit digital data at the digital outputs of the TEK 2021 The resulting waveforms produced at the AD9754 EB outputs are then buffered and amplified by the AD8002 differential driver to achieve 14 bit performance from this DMT signal source POWER DISSIPATION In order to properly size the heat sinking area for your applica tion it is important to consider the total power dissipation of the AD8016 dc power dissipation for 0 is Io VCC VEE or 2 X Ig x Vs For the AD8016 powered on 12 V and 12 V supplies Vs the number is 0 6 W In a differential driver circuit Figure 6 13 8016 we use symmetry to simplify the computation for a dc input signal Dp22x Io Vs 4x Vs w
19. ad HTSSOP ARE Reel AD8016ARE EVAL 409 to 85 C Evaluation Board ARE EVAL ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8016 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING i ESD SENSITIVE DEVICE REV A Typical Performance Characteristics AD8016 1240 4990 Vout Vs Vs Figure 3 Single Ended Test Circuit 6 5 Figure 6 Differential Test Circuit 410 Vou 100mv 1 Vour 100mV 2 E e d puppe gt 20 gt Vin 20 TIME TIME 100ns DIV Figure 4 100 mV Step Response 5 Vs 6 V Figure 7 100 mV Step Response G 5 Vs 12 V 250 Single Ended 25 Single Ended VOLTS VOLTS TIME 100ns DIV TIME 100ns DIV Figure 5 4 V Step Response 5 Vs 6 V Figure 8 4 V Step Response 5 Vs 12 V 25 Single En
20. be placed onto a single printed cir cuit board residing in a card cage located in a variety of ambient conditions Environmental conditioners such as fans or air con ditioning may or may not be available depending on the density of modems and the facilities contained at the CO site To achieve long term reliability and consistent modem performance designers of CO solutions must consider the wide array of ambient condi tions that exist within various CO sites MULTITONE POWER RATIO OR MTPR ADSL systems rely on Discrete Multitone or DMT modulation to carry digital data over phone lines DMT modulation appears in the frequency domain as power contained in several individual frequency subbands sometimes referred to as tones or bins each of which is uniformly separated in frequency See Figure 1 for example of downstream DMT signals used in evaluating MTPR performance A uniquely encoded Quadrature Amplitude Modu lation QAM signal occurs at the center frequency of each subband or tone Difficulties will exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal s from other subbands regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands Conventional methods of expressing the output signal integrity of line drivers such as spurious free dynamic range SFDR single tone harmonic distortion or THD two tone Intermodulation Distortion IMD and 3rd order i
21. chniques such as interlacing sometimes referred to as stitching or interconnection of the layers immedi ately beneath the line driver This technique serves to increase the thermal mass or capacity of the PCB immediately beneath the driver See AD8016 EVAL boards for an example of this method of thermal enhancement A cooling fan that draws moving air over the PCB and xDSL drivers while not always required may be useful in reducing the operating temperature 14 of the die allowing more drivers square inch within the design The AD8016 whether in a PSOP3 ARP or batwing ARB package can be designed to operate in the CO solution using prudent measures to manage the power dissipation through careful PCB design The PSOP3 package is available for use in designing the highest density CO solutions Maximum heat trans fer to the PCB can be accomplished using the PSOP3 package when the thermal slug is soldered to an exposed copper pad directly beneath the AD8016 Optimum thermal performance can be achieved in the ARE package only when the back of the package is soldered to a PCB designed for maximum thermal capacity see Figure 44 Thermal experiments with the PSOP3 package were conducted without soldering the heat slug to the PCB Heat transfer was through physical contact only The following offers some insight into the AD8016 power dissipation and relative junction temperature the effects of PCB size and composition on the junction
22. dB OUTPUT CHARACTERISTICS Output Voltage Swing Single Ended Ry 1000 11 11 V Linear Output Current G 5 10 Q fi 100 kHz 60 dBc SFDR 400 600 mA Short Circuit Current 2000 mA Capacitive Load Drive 80 pF POWER SUPPLY Operating Range 3 13 Quiescent Current PWDNI PWDNO 1 1 12 5 13 2 mA Amp 1 0 8 10 mA Amp 0 1 5 8 mA Amp 0 0 4 6 mA Amp Recovery Time To 95 of Ig 25 us Shutdown Current 250 Out of Bias Pin 1 5 4 0 mA Amp Power Supply Rejection Ratio AVs 1 V 63 75 dB OPERATING TEMPERATURE RANGE 40 85 C NOTES 15 Figure 43 R20 R21 0 Q R1 open Specifications subject to change without notice 2 REV SPECIFICATIONS 405 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth 1 1 5 0 2 320 MHz G 5 Re 499 Q lt 0 5 Vp p 70 71 MHz Bandwidth for 0 1 dB Flatness 5 499 Q 0 2 V 10 15 MHz Large Signal Bandwidth Vout 1 V rms 80 MHz Peaking Vour 0 2 V lt 50 MHz 0 7 1 0 dB Slew Rate Vour 4 V p p G 2 300 V us Rise and Fall Time Vout 2 V p p 2 ns Settling Time 0 1 Vour 2 p p 39 ns Input Overdrive Recovery Time Vout 6 5 350 ns NOISE DISTORTION PERFORMANCE Distortion Single Ended G 5 Vou 2 V p p Rg 499 Q 2nd Harmonic fo 1 MHz 100 0 25 Q 73 61 75 63 fo 1 MHz 100 0
23. ded 25 Single Ended REV _5 8016 30 30 40 40 50 50 a 60 p 60 gt z 2 70 tr B 5 80 t 80 a a 90 90 100 100 110 110 0 01 0 1 1 10 20 0 01 1 10 20 FREQUENCY MHz FREQUENCY MHz Figure 9 Distortion vs Frequency Second Harmonic Figure 12 Distortion vs Frequency Third Harmonic 12 50 Differential Vs 12 50 Q Differential 30 30 4990 Rp 4990 740 10 40 10 0 0 4 Vo 4V p p NTL 50 50 01 tA 5 60 5 54 7 5 5 70 70 o A PWDN 1 0 1 1 15 80 PWDN 1 0 1 1 5 80 Bau sE 90 100 110 110 0 01 0 1 1 10 20 0 01 0 1 1 10 20 FREQUENCY MHz FREQUENCY MHz Figure 10 Distortion vs Frequency Second Figure 13 Distortion vs Frequency Third Harmonic Vs 6 V 50 Different Vs 6 50 Differential 30 Rp 4990 40 5 1 0 0 0 8 8 50
24. der evaluation Generating DMT signals can be accom plished using a Tektronics AWG 2021 equipped with opt 4 12 24 Bit TTL Digital Data Out digitally coupled to Analog Devices AD9754 a 14 bit TxDAC buffered by an AD8002 amplifier configured as a differential driver See Figure 45 for schematics of a circuit used to generate DMT signals that can achieve down to 80 dBc of MTPR performance sufficient for use in evaluating xDSL drivers Note that the DMT waveforms available with the AD8016ARP EVAL and AD8016ARB EVAL boards or similar WFM files are needed to produce the neces sary digital data required to drive the TxDAC from the optional TTL Digital Data output of the TEK AWG2021 Copies of these files can be obtained through the Analog Devices website http www analog com EVALUATION BOARDS The AD8016ARP EVAL AD8016ARB EVAL AD8016ARE EVAL boards available through Analog Device provide a platform for evaluating the AD8016 in an ADSL differential line driver circuit The board is laid out to accommodate Analog Devices two transformer line driver hybrid circuit see Figures 46a and 46b including line matching network an RJ11 jack for interfac ing to line simulators transformer coupled input for single to differential input conversion and accommodations for the receiver function Schematics and layout information are available for both versions of the EVAL board Also included in the package are WFM files for use in generating 1
25. ed by the AD8016 is limited by the associated rise in junction temperature The maximum safe junction temperature for plastic encapsulated device is determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package The output stage of the AD8016 is designed for maximum load current capability As a result shorting the output to common can cause the AD8016 to source or sink 2000 mA To ensure proper operation it is necessary to observe the maximum power derating curves Direct connection of the output to either power supply rail can destroy the device MAXIMUM POWER DISSIPATION Watts 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE Figure 2 Plot of Maximum Power Dissipation vs Temperature AD8016 for T 125 C CAUTION ORDERING GUIDE Temperature Package Package Model Range Description Option AD8016ARP 40 to 85 C 20 Lead PSOP3 RP 20 AD8016ARP Reel 40 C to 85 C 20 Lead PSOP3 ARP Reel AD8016ARP EVAL 40 to 85 C Evaluation Board ARP EVAL AD8016ARB 409 to 85 C 24 Lead Batwing RB 24 AD8016ARB Reel 409 to 85 C 24 Lead Batwing ARB Reel AD8016ARB EVAL 409 to 85 C Evaluation Board ARB EVAL AD8016ARE 40 to 85 C 28 Lead HTSSOP RE 28 AD8016ARE Reel 40 to 85 C 28 Le
26. erature 25 of 24 C in both the ARB and ARP packages For the worst case 5 package the AD8016ARB and the worst case PCB at 4 7 square n ARP 0 LFM UM ARB 200 LFM gt inches the extrapolated junction temperature for an ambient gt 20 ARP 50 LFM eM environment of 85 C would be approximately 132 C with 0 LFM of air flow If the target maximum junction temperature of the AD8016ARB is 125 C a 4 layer PCB with 1 0z copper covering 13 the outer layers and measuring 9 square inches is required ARP 150 LFM ARP 200 LFM with 0 LEM of air flow 10 00 4 7 10 Note that the AD8016ARE is targeted at xDSL applications PCB AREA SQ IN other than full rate CO ADSL The AD8016ARE is targeted at Figure 43 Junction to Ambient Thermal Resistance vs g lite and other xDSL applications where reduced power dissi PCB Area pation can be achieved through a reduction in output power Extreme temperatures associated with full rate ADSL using the AD8016ARE should be avoided whenever possible 50 75 45 ARB 4 7 SQ IN 24 AMBIENT 70 ARB 6 SQ IN 40 p 5 35 ARE 0 LFM 65 gt 5 ARB 7 125 SQ IN 30 ARE 200 LFM 60 9 SQ IN ae ARP 4 7 SQ IN ARE 400 LFM ARP 6 SQ IN 20 950 15 gt gt 9 SQ IN 10 1 2 3 4 5 6 7 8 9 10 ARP 12 SQ IN PCB AREA SQ IN 0 50 100 150 200 3 AIR FLOW LFM Figure 44 Junction to Ambient Thermal Resistance vs Figure 42 Junction Temperature vs Air Flow OR Aree
27. h with gain for current feedback amplifiers is evident the 3 dB point being set when Tz Rr Of course for a real amplifier there are additional poles that contribute excess phase and there will be a value for Rg below which the amplifier is unstable Tolerance for peaking and desired flatness will determine the optimum in each application Figure 37 Simplified Block Diagram The AD8016 is the first current feedback amplifier capable of delivering 400 mA of output current while swinging to within 2 V of either power supply rail This enables full CO ADSL performance on only 12 V rails an immediate 20 power saving AD8016 is also unique in that it has a power management system included on chip It features four user programmable power levels all of which provide a low output impedance of the driver as well as the provision for complete shutdown high impedance state Also featured is a thermal shutdown with alarm signal POWER SUPPLY AND DECOUPLING The AD8016 should be powered with a good quality low noise dual supply of 12 V for the best distortion and Multi tone Power Ratio MTPR performance Careful attention must be paid to decoupling the power supply pins 10 capacitor located in near proximity to the AD8016 is required to provide good decoupling for lower frequency signals In addition 0 1 UF decoupling capacitors should be located as close to each of the four power supply pins as is physical
28. here Vo is the peak output voltage of an amplifier This formula is slightly pessimistic due to the fact that some of the quiescent supply current is commutated during sourcing or sinking current into the load For a sine wave source integration over a half cycle yields 4VoVs Vo Pp 2 Vs 2 ok The situation is more complicated with complex modulated signal In the case of a DMT signal taking the equivalent sine wave power overestimates the power dissipation by 23 For example Pour 23 4 dBm 220 mW Vour 500 3 31 Vrms Vo 2 354 V at each amplifier output which yields a Pp of 1 81 W Through measurement a DMT signal of 23 4 dBm requires 1 47 W of power to be dissipated by the AD8016 Figure 41 shows the results of calculation and actual measurements detailing the relationship between the power dissipated by the AD8016 versus the total output power delivered to the back termination resistors and the load combined A 1 2 transformer turns ratio was used in the calculations and measurements 2 5 I o MEASURED SINE POWER DISSIPATION 0 100 200 300 OUTPUT mw Figure 41 Power Dissipation vs Output Power Including Back Terminations See Figure 7 for Test Circuit THERMAL ENHANCEMENTS AND PCB LAYOUT There are several ways to enhance the thermal capacity of the CO solution Additional thermal capacity can be created using enhanced PCB layout te
29. lifier into an Ry oAp of 100 differential 50 Q per side will produce the 1 5 W of power typical in the AD8016 device See the Power Dissipation section for details Thermal Resistance The junction to case thermal resistance of the AD8016ARB or batwing package is 8 6 C W AD8016ARE is 5 6 C W and the AD8016ARP or PSOP3 package is 0 86 C W These package specifications were used in this study to determine junction temperature based on the mea sured case temperature PCB Dimensions of a Differential Driver Circuit Several components are required to support the AD8016 in a differential driver circuit The PCB area necessary for these components 1 feedback and gain resistors ac coupling and decoupling capaci tors termination and load resistors dictated the area of the smallest PCB in this study 4 7 square inches Further reduction in PCB area although possible will have consequences in terms of the maximum operating junction temperature REV A 8016 EXPERIMENTAL RESULTS 35 The experimental data suggests that for both packages and a ARB OLEM PCB as small as 4 7 square inches reasonable junction tempera ARB 50 LFM tures can be maintained even in the absence of air flow The graph ARB 100 in Figure 42 shows junction temperature versus air flow for various dimensions of 1 ounce copper PCBs at an ambient temp
30. ly possible All ground pins should be connected to a common low impedance ground plane REV A FEEDBACK RESISTOR SELECTION In current feedback amplifiers selection of feedback and gain resistors will have an impact on the MTPR performance band width and gain flatness Care should be exercised in the selec tion of these resistors so that optimum performance is achieved table below shows the recommended resistor values for use in a variety of gain settings These values are suggested as a good starting point when designing for any application Table I Resistor Selection Guide Gain Rg 1 1k 1 500 500 2 650 650 5 750 187 10 1k 111 BIAS PIN AND PWDN FEATURES The AD8016 is designed to cover both CO Central Office and CPE Customer Premise Equipment ends of an xDSL applica tion It offers full versatility in setting quiescent bias levels for the particular application from full ON to reduced bias in three steps to full OFF via BIAS pin This versatility gives the modem designer the flexibility to maximize efficiency while maintaining reasonable levels of Multitone Power Ratio MTPR performance Optimizing driver efficiency while delivering the required DMT power is accomplished with the AD8016 through the use of on chip power management features Two digitally programmable logic pins PWDN1 PWDNO may be used to select four different bias levels 100 60 40 and 25
31. ntercept IP3 become significantly less meaningful when amplifiers are required to drive DMT and other heavily modulated waveforms A typical xDSL downstream DMT signal may contain as many as 256 carriers subbands or tones of QAM signals Multitone Power Ratio MTPR is the relative difference between the measured power in a typical subband at one tone or carrier versus the power at another subband specifically selected to contain no QAM data In other words a selected subband or tone remains open or void of intentional power without a QAM signal yielding an empty frequency bin MTPR sometimes referred to as the empty bin test is typically expressed in dBc similar to expressing the relative difference between single tone fundamentals and 2nd or 3rd harmonic distortion components See Figure 1 for a sample of the ADSL downstream spectrum showing MTPR results while driving 20 4 dBm of power onto a 100 Q line Measurements of MTPR are typically made at the output line side of ADSL hybrid circuits See Figure 46a for an example of Analog Devices hybrid schematic MTPR can be affected by the components contained in the hybrid circuit including the quality of the capacitor dielectrics voltage ratings and the turns ratio of the selected transformers Other compo nents aside an ADSL driver hybrid containing the AD8016 can be optimized for the best MTPR performance by selecting the turns ratio of the transformers The voltage and
32. of the ther mal overload condition the power being dissipated and the ther mal mass of the PCB beneath the AD8016 When the AD8016 begins to cycle due to thermal stress the internal shutdown circuitry draws current out of the node connected in common with the BIAS pin while the voltage at the BIAS pin goes to the negative rail When the junction temperature returns to 140 C current is no longer drawn from this node and the BIAS pin voltage returns to the positive rail Under these circumstances the BIAS pin can be used to trip an alarm indicating the pres ence of a thermal overload condition Figure 39 also shows three circuits for converting this signal to a standard logic level AD8016 ALARM BIAS ALARM OR BIAS MIN 350 1 4 HCF 40109B SGS THOMSON Figure 39 Shutdown and Alarm Circuit 12 APPLICATIONS The AD8016ARP and AD8016ARB dual xDSL line driver amplifiers are the most efficient xDSL line drivers available to the market today The AD8016 may be applied in driving modu lated signals including Discrete Multitone DMT in either direction upstream from Customer Premise Equipment CPE to the Central Office CO and downstream from CO to CPE The most significant thermal management challenge lies in driving downstream information from CO sites to the CPE Driving xDSL information downstream suggests the need to locate many xDSL modems in a single CO site The implication is that several modems will
33. quency REV A 9 AD8016 1000000 360 100000 320 10000 280 g 1 1000 PHASE 240 9 9 5 100 200 6 1 2 40 TRANSIMPEDANCE 160 o rI 1 120 8 0 1 80 0 01 40 0 0 0 0001 0 001 0 01 0 1 1 10 100 1000 10000 FREQUENCY MHz Figure 30 Open Loop Transimpedance and Phase vs Frequency OUTPUT VOLTAGE ERROR 2mV DIV 0 1 DIV 1000 100 10 OUTPUT IMPEDANCE 0 1 0 01 0 G 2 1 Vout 2 1000 2 L Lei LL 0 1 0 Vi 0 1 Vout Vout ViN 5 0 5 10 15 20 25 30 35 40 45 TIME ns Figure 31 Settling Time 0 1 Vs X6 1 0 03 0 1 1 10 FREQUENCY MHz 100 500 Figure 32 Output Impedance vs Frequency PWDN1 PWDNO Codes 8016 200 300 400 500 600 700 800 900 TIME ns a Overload Recovery Vs 12 V 5 1000 100 0 100 Vin 2V DIV Vour 5V DIV Vout 1 1
34. twing RB 24 0 6141 15 60 0 5985 15 20 24 13 0 2992 7 60 0 2914 7 40 0 4193 10 65 2 t 0 3937 10 00 PIN 1 0 1043 2 65 0 0291 0 74 a 0 0926 2 35 0 0098 0 25 Y in 0 0500 0 0201 0 51 T 5 sala 010 127 0030033 001280309 00157040 10040 0 10 j 0 0091 0 23 i 28 Lead HTSSOP RE 28 0 386 9 80 0 382 9 70 0 378 9 60 EXPOSED PAD 0 177 4 50 0 252 0 173 4 40 6 40 0 169 4 30 5 lt 0 047 0 0256 0 65 0 041 1 05 1 20 BSC 0 039 1 00 MAX 0 031 0 80 ASHHHHHEEHHHHHHEZ 0 0118 0 30 0 030 75 0 006 0 15 P 4 EATING 0 0079 0 2 piel shld 0 000 0 00 0 0075 0 19 SEATING ORI 0 024 0 60 0 177 0 45 CONTROLLING DIMENSIONS ARE IN MILLIMETERS mm 20 DETAIL 0 1299 3 30 0 1240 3 15 0 1181 3 00 m 0 1118 0 30 0 0126 0 32 0 0090 0 23 REV 01019 1 8 00 rev A PRINTED IN U S A
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