ANALOG DEVICES AD8012 Dual 350 MHz Low Power Amplifier handbook
Contents
1. 5 5 4 Vo 0 3V p p 4 Vo 0 3V p p Rp 7500 Rp 7500 3 RL 1ko 3 RL 1ko m m 0 2 2 I I z z z 1 lt q 1 o o A 0 A o N G 1 N G 1 1 1 lt lt z G 10 z G 10 Es z G 2 z G 2 a 3 4 4 5 5 1 10 100 500 1 10 100 500 FREQUENCY MHz FREQUENCY MHz Figure 34 Frequency Response Vs 5 V Figure 37 Frequency Response Vs 5 V 0 5 0 4 Vo 0 3V p p G 2 0 3 Rp 7500 m RL 1ko Ma 02 Ju I z z Z 01 Z o o n 0 m N N 041 Z 2 9 0 3 0 4 0 5 0 1 1 10 100 1 10 FREQUENCY MHz FREQUENCY MHz Figure 35 Gain Flatness Vs 5 V Figure 38 Gain Flatness Vs 5 V 20 30 _ DRIVER Vo 2V p p m 40 RL z 1000 o 1 oa 50 o 60 a SIDE 1 ui 70 sz U 80 m SIDE 2 bk 90 2 a Z 100 110 Vour 2V DIV 120 OUT 0 03 0 1 1 10 100 500 FREQUENCY MHz Figure 36 Crosstalk vs Frequency Figure 39 Overdrive Recovery Vs 5 V G 2 Re 7509 R 100 Vin 3 V p p T 1us _10 REV A AD8012 THEORY OF OPERATION The AD8012 is a dual high speed CF amplifier that attains new levels of bandwidth BW power distortion and signal swing capability Its wide dynamic performance including noise is the result of both a new complementary high speed bipolar process and a new and unique arch2. 40 2 4 Vout 2V p p 50 Rp 7500 2nd o o a a T 7 60 4 H H te te S 7 ji n N a a 3rd 80 90 10 100 ik 10 100 ik RL Q RL Q Figure 16 Distortion vs Load Resistance Vs 5 V Figure 19 Distortion vs Load Resistance Vs 5 V Frequency 500 kHz Frequency 500 kHz 40 40 3rd 3rd RL 1000 RL 1000 2nd us RL 1000 8 60 2 k s 3 ne 1000 z 2 2nd SETER o grd na S RL 1kO te z 8 2 a 80 a 80 a 2nd G 2 A G 2 RL 1kO Vout 2V p p 3rd Vout 2V p p Rp 7500 RL 1kQ Rp 7500 100 100 1 10 20 1 10 20 FREQUENCY MHz FREQUENCY MHz Figure 17 Distortion vs Frequency Vs 5 V Figure 20 Distortion vs Frequency Vs 5 V G 2 Vo 0 3V p p Rp 7500 R lt 1000 Vs 5V NORMALIZED GAIN dB NORMALIZED GAIN dB 0 1 1 10 100 1 10 FREQUENCY MHz FREQUENCY MHz Figure 18 Gain Flatness Vs 5 V Figure 21 Gain Flatness Vs 5 V REV A 7 AD8012 Vo 0 3V p p A Rp 7500 RL
3. 20mV 5ns Figure 5 100 mV Step Response G 2 Vs t2 5 V or Figure 8 100 mV Step Response G 1 Vs t2 5 V or 45 V R lt 1kO 5V R 1kQ 1V 10ns Figure 6 4 V Step Response G 2 Vs 5 V R 1 kQ Figure 9 4 V Step Response G 1 Vs 5 V R 1kQ NOTE Vs 2 5 V operation is identical to Vs 5 V single supply operation REV A 5 AD8012 Figure 10 100 mV Step Response G 2 Vs 2 5 Vor 5 V Rp 1000 Figure 11 2 V Step Response G 2 Vs 2 5 V R 100Q Figure 12 4 V Step Response G 2 Vs 5 V R 1009 NOTE Vs 2 5 V operation is identical to Vg 5 V single supply operation S S Figure 13 100 mV Step Response G 1 Vs 2 5 V or 5 V R 1009 Figure 14 2 V Step Response G 1 Vs 2 5 V R 1009 1V Figure 15 4 V Step Response G 10ns 1 Vs 5 V R 100Q REV A AD8012
4. Figure 41 Time Domain Representation of a HDSL Signal Many of the elements of a classic differential line driver are shown in the HDSL line driver in Figure 42 6 V peak to peak differential signal is applied to the input The differential gain of the amplifier 142 Rx R6 is set to 2 so the resulting differential output signal is 12 V p p s is normal in telephony applications a transformer galvani cally isolates the differential amplifier from the line In this case a 1 1 turns ratio is used In order to correctly terminate the line it is necessary to set the output impedance of the amplifier to be equal to the impedance of the line being driven 135 Q in this case Because the transformer has a turns ratio of 1 1 the im pedance reflected from the line is equal to the line impedance of 135 Q Razr Rimr Turns Ratio As a result two 66 5 Q resistors correctly terminate the line 12 TO RECEIVER CIRCUITRY UP TO 12 000 FEET 6V p p 1350 1 1 1 1 TO GAIN 2 RECEIVER CIRCUITRY Figure 42 Differential for HDSL Applications The immediate effect of back termination is that the signal from the amplifier is halved before being applied to the line This doubles the power the amplifier must deliver However the back termination resistors also play an important second role Full duplex data transmission systems like HDSL simulta neously transmit data in both directions As a result the signal
5. 8 LEAD microSOIC 0 5 MAXIMUM POWER DISSIPATION Watts 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE C Figure 3 Plot of Maximum Power Dissipation vs Temperature for AD8012 ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8012 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING om ts ESD SENSITIVE DEVICE ORDERING GUIDE Temperature Package Package Brand Model Range Description Options Code AD8012AR 40 C to 85 C 8 Lead SOIC SO 8 AD8012AR REEL 40 C to 85 C 13 Tape and Reel SO 8 AD8012AR REEL7 40 C to 85 C 7 Tape and Reel SO 8 AD8012ARM 40 C to 85 C 8 Lead microSOIC RM 08 H6A AD8012ARM REEL 40 C to 85 C 13 Tape and Reel RM 08 H6A AD8012ARM REEL7 40 C to 85 C 7 Tape and Reel RM 08 H6A REV A Typical Performance Characteristics AD8012 7500 7500 7500 7500 Vour Vour Vs Vs Figure 4 Test Circuit Gain 2 Figure 7 Test Circuit Gain 1
6. 1000 a Vs 5V 2 I z lt 1 Q 0 N a 1 G 10 G 1 TRE zz G 2 3 4 5 1 10 100 500 FREQUENCY MHz Figure 22 Frequency Response Vs 5 V 9 2 6 Rp 7500 7 Ry 1000 gt 1V RMS Ves ESN m d 0 I U u 3 lt H 6 o gt me 9 D amp 5 12 o A5 18 21 1 10 100 500 FREQUENCY MHz Figure 23 Output Voltage vs Frequency Vs lt t5 V G 2V R 1009 CMRR dB 0 03 0 1 1 10 100 500 FREQUENCY MHz Figure 24 CMRR vs Frequency Vs 5 V 45 V NORMALIZED GAIN dB OUTPUT VOLTAGE dBV 5 Vo 0 3V p p Rp 7500 RL 1000 Vs 5V G 10 G 1 G 2 10 100 500 FREQUENCY MHz Figure 25 Frequency Response Vs 5 V 27 1VRMS 10 FREQUENCY MHz 100 500 Figure 26 Output Voltage vs Frequency Vs 5 V G 2V R 1009 PSRR dB 100k 1M 10M FREQUENCY Hz 100M 500M Figure 27 PSRR vs Frequency Vs 5 V 45 V REV A AD8012 CURRENT NOISE IN IN OUTPUT RESISTANCE Q INPUT VOLTAGE NOISE nV Hz
7. 270 350 MHz G 2 Vour lt 0 4V p p RL 1kQ 95 150 MHz G 2 Vour lt 0 4 V p p R 100 Q 90 MHz 0 1 dB Bandwidth Vout lt 0 4 V p p Rp 1 kQ 100 Q 40 23 MHz Large Signal Bandwidth Vout 4 V p p 75 MHz Slew Rate Vour 4 V p p 2 250 V us Rise and Fall Time Vour 2 V p p 3 ns Settling Time 0 1 Voyr 2 V p p 20 ns 0 02 Voyr 2 V p p 35 ns Overdrive Recovery 2x Overdrive 60 ns NOISE HARMONIC PERFORMANCE Distortion Vour 2 V p p G 2 2nd Harmonic 500 kHz Ry 1 kQ 100 Q 89 73 dBc 5 MHz Ri 1 kQ 100 18 62 dBc 3rd Harmonic 500 kHz Ri 1 kQ 100 Q 84 72 dBc 5 MHz Ri 1 kQ 100 66 52 dBc Output IP3 500 kHz Af 10 kHz Ry 1 kQ 100 30 40 dBm IMD 500 kHz Af 10 kHz Ri 1 kQ 100 Q 79 77 dBc Crosstalk 5 MHz R 100 Q 70 dB Input Voltage Noise f 10 kHz 2 5 nV VHz Input Current Noise f 10 kHz Input Input 15 pANHz Differential Gain f 3 58 MHz Ry 150 Q 1 kQ G 2 0 02 0 02 Differential Phase f 3 58 MHz R 150 Q 1 kQ G 2 0 3 0 06 Degrees DC PERFORMANCE Input Offset Voltage 1 5 4 mV Tun T max 5 mV Open Loop Transimpedance Vout 2 V Ry 100 Q 240 500 ko Tun IMax 200 kQ INPUT CHARACTERISTICS Input Resistance Input 450 ko Input Capacitance Input 2 3 pF Input Bias Current Input Input 3 12 HA Input Input Tyn I max 15 HA Common Mode Rejection Ratio Vom 2 5 V 556 60 dB Input Common Mode Voltage Range 3 8 4 1 V OUTPUT CHARACTERISTICS Output Resista
8. C NOTES IStresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device in free air at 25 C 8 Lead SOIC Package ja 155 C W 8 Lead microSOIC Package 0ja 200 C W CAUTION MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8012 is limited by the associated rise in junction temperature The maxi mum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in de vice failure The output stage of the AD8012 is designed for maximum load current capability As a result shorting the output to common can cause the AD8012 to source or sink 500 mA To ensure proper operation it is necessary to observe the maximum power derating curves Direct connection of the output to either power supply rail can destroy the device 2 0 a 5 a o
9. on the line and across the back termination resistors is the com posite of the transmitted and received signal The termination resistors are used to tap off this signal and feed it to the receive circuitry Because the receive circuitry knows what is being transmitted the transmitted data can be subtracted from the digitized composite signal to reveal the received data Driving a line with a differential signal offers a number of ad vantages compared to a single ended drive Because the two outputs are always 180 degrees out of phase relative to one another the differential signal output is double the output am plitude of either of the op amps As a result the differential amplifier can have a peak to peak swing of 16 V each op amp can swing to 4 V even though the power supply is 5 V In addition to this even order harmonics 2nd 4th 6th etc of the two single ended outputs tend to cancel out one another so the Total Harmonic Distortion quadratic sum of all harmonics decreases compared to the single ended case even as the signal amplitude is doubled This is particularly advantageous for the case of the second harmonic As it is very close to the funda mental filtering becomes difficult In this application the THD is dominated by the third harmonic which is 65 dB below the carrier i e Spurious Free Dynamic Range 65 dBc Differential line driving also helps to preserve the integrity of the transmitted signal i
10. 8 MHz Differential Gain R 150 Q 1 kO 0 03 0 03 Differential Phase R 150 Q 1 kQ 0 4 0 08 Degrees DC PERFORMANCE Input Offset Voltage 1 3 mV Tmmn T max 4 mV Open Loop Transimpedance Vout 2 V p p Ry 100 Q 200 400 ko Tun T max 150 ko INPUT CHARACTERISTICS Input Resistance Input 450 ko Input Capacitance Input 2 3 pF Input Bias Current Input Input 3 12 HA Input Input Tyn T max 15 HA Common Mode Rejection Ratio Vcy z 1 5 V to 3 5 V 56 60 dB Input Common Mode Voltage Range 1 5 to 3 5 1 2 to 3 8 V OUTPUT CHARACTERISTICS Output Resistance G 2 0 1 Q Output Voltage Swing 1 to 4 0 9 to 4 2 V Output Current Tun Tuax 50 100 mA Short Circuit Current 500 mA POWER SUPPLY Supply Current Amp 1 55 1 75 mA Tun T max 1 85 mA Operating Range Single Supply 3 12 V Power Supply Rejection Ratio 58 60 dB Specifications subject to change without notice REV A AD8012 ABSOLUTE MAXIMUM RATINGS Supply Voltage ss Fosses h 12 6 V Internal Power Dissipation Small Outline Package R 0 8 W microSOIC Package RM 0 6 W Input Voltage Common Mode V Differential Input Voltage 2 5 V Output Short Circuit Duration ae O AE LA wee Observe Power Derating Curves Storage Temperature Range RM R 65 C to 125 C Operating Temperature Range A Grade 40 C to 85 C Lead Temperature Range Soldering 10 sec 300
11. INPUT CURRENT NOISE pA Hz 1 10 ik 1 FREQUENCY MHz FREQUENCY Hz Figure 28 Output Resistance vs Frequency Figure 31 Noise vs Frequency Tz dBO PHASE Degrees PEAK TO PEAK OUTPUT AT 5MHz lt 1 THD V 5 1E 03 1E 04 1E 05 1E 06 1E 07 1E 08 1E 09 3 4 5 6 7 8 9 10 11 FREQUENCY Hz TOTAL SUPPLY VOLTAGE Volts Figure 29 Open Loop Transimpedance and Phase vs Figure 32 Output Swing vs Supply Frequency SWING V p p OUTPUT VOLTAGE ERROR 0 1 Div 1 A LOAD 0 t 0 Figure 30 Output Swing vs Load Figure 33 Settling Time Vs 5 V REV A 9 AD8012
12. ZS AD 8012 H N ANALOG DEVICES Dual 350 MHz Low Power Amplifier AD8012 FEATURES Low Power 1 7 mA Amplifier Supply Current Fully Specified for 5 V and 45 V Supplies High Output Current 125 mA High Speed 350 MHz 3 dB Bandwidth G 41 150 MHz 3 dB Bandwidth G 2 2 250 V yus Slew Rate 20 ns Settling Time to 0 1 Low Distortion 72 dBc Worst Harmonic 500 kHz R 1000 66 dBc Worst Harmonic 5 MHz R 1kQ Good Video Specifications R 1 kQ G 2 0 02 Differential Gain Error 0 06 Differential Phase Error Gain Flatness 0 1 dB to 40 MHz 60 ns Overdrive Recovery Low Offset Voltage 1 5 mV Low Voltage Noise 2 5 nV VHz Available in 8 Lead SOIC and 8 Lead microSOIC APPLICATIONS XDSL HDSL Line Driver ADC Buffer Professional Cameras CCD Imaging System Ultrasound Eguipment Digital Camera PRODUCT DESCRIPTION The AD8012 is a dual low power current feedback amplifier capable of providing 350 MHz bandwidth while using only 1 7 mA per amplifier It is intended for use in high freguency wide dynamic range systems where low distortion high speed are essential and low power is critical With only 1 7 mA of supply current the AD8012 also offers exceptional ac specs such as 20 ns settling time and 2 250 V us slew rate The video specifications are 0 02 differential gain and 0 06 degree differential phase excellent for such a low power amplifier In addition the AD8012 has a low offset of 1 5 mV T
13. he AD8012 is well suited for any application that requires high performance with minimal power The product is available in standard 8 lead SOIC or micro SOIC packages and operates over the industrial temperature range 40 C to 85 C Protected under U S Patent Number 5 537 079 REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM 40 DISTORTION dBc I o 80 10 100 1k R O Figure 1 Distortion vs Load Resistance Vs lt t5 V Frequency 500 kHz aVs LINE Np Ns TRANSFORMER Figure 2 Differential Drive Circuit for XDSL Applications One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 O Analog Devices Inc 1999 AD8012 SPEGIFIGATIONS DUAL SUPPLY er 25 c v 5 V 6 2 R 100 Re Re 750 unless otherwise noted Parameter Conditions Min Typ Max Units DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Vour lt 0 4 V p p Ri 1 kQ
14. itectural design The AD8012 basically uses a two gain stage complementary design approach versus the traditional single stage complementary mirror structure sometimes referred to as the Nelson amplifier Though twin stages have been tried before they typically consumed high power since they were of a folded cascade design much like the AD9617 This design allows for the standing or quiescent current to add to the high signal or slew current induced stages In the time domain the large signal output rise fall time and slew rate is typically controlled by the small signal BW of the amplifier and the input signal step amplitude respectively not the dc quiescent current of the gain stages with the exception of input level shift diodes Q1 Q2 Using two stages vs one also allows for a higher overall gain bandwidth product GBWP for the same power thus lower signal distortion and the ability to drive heavier external loads In addition the second gain stage also isolates divides down A3 s input reflected load drive and the nonlinearities created resulting in relatively lower dis tortion and higher open loop gain Overall when high external load drive and low ac distortion is a requirement a twin gain stage integrating amplifier like the AD8012 will provide excellent results for lower power over the Z1 R1 C1 Zi IR IFC traditional single stage complementary devices In addition being a CF amplifier closed loop BW
15. moderate dis tances via conventional telephone twisted pair wires Traditional TI El in Europe requires repeaters every 3 000 feet to 6 000 feet to boost the signal strength and allow transmission over distances of up to 12 000 feet In order to achieve repeaterless transmission over this distance an HDSL modem requires transmitted power level of 13 5 dBm assuming a line imped ance of 135 HDSL uses the Two Binary One Ouaternary line code 2B10 A sample 2B10 waveform is shown in Figure 41 The digital bit stream is broken up into groups of two bits Four analogue voltages called guaternary symbols are used to represent the four possible combinations of two bits These symbols are as signed arbitrary names 3 1 1 and 3 The corresponding voltage levels are produced by a DAC that is usually part of an Analog Front End Circuit AFEC Before being applied to the line the DAC output is low pass filtered and acquires the sinu soidal form shown in Figure 41 Finally the filtered signal is applied to the line driver The line voltages that correspond to the quaternary symbols 3 1 1 and 3 are 2 64 V 0 88 V 0 88 V and 2 64 V This gives a peak to peak line voltage of 5 28 V SYMBOL DAC NAME VOLTAGE 4 OUTPUT 43 2 64V FILTERED OUTPUT x TO LINE 1 0 88V DRIVER 1 0 88Vv 3 2 64V 1 3 1 3 3 1 3 lolo 1 PA 01 10 11 00 00 11 10 00 o1 01 11 01 00
16. n the presence of Electro Magnetic In terference EMI EMI tends to induce itself egually on to both the positive and negative signal line As a result a receiver with good common mode rejection will amplify the original signal while rejecting induced common mode EMI REV A AD8012 Choosing the Appropriate Turns Ratio for the Transformer Increasing the peak to peak output signal from the amplifier in the previous example combined with a variation in the turns ratio of the transformer can yield further enhancements to the circuit The output signal swing of the AD8012 can be increased to about 3 9 V before clipping occurs This increases the peak to peak output of the differential amplifier to 15 6 V Because the signal applied to the primary winding is now bigger the transformer turns ratio of 1 1 can be replaced with a step down turns ratio of about 1 3 1 from amplifier to line This steps the 7 8 V peak to peak primary voltage down to 6 V This is the same secondary voltage as before so the resulting power delivered to the line is the same The received signal which is small relative to the transmitted signal will however be stepped up by a factor of 1 3 Amplifying the received signal in this manner enhances its signal to noise ratio and is useful when the received signal is small compared to the to be transmitted signal The impedance reflected from the 135 Q line now becomes 228 Q 1 3 times 135 Q With a correctly
17. nce G 2 0 1 Q Output Voltage Swing 3 85 4 V Output Current Tyun T max 70 125 mA Short Circuit Current 500 mA POWER SUPPLY Supply Current Amp 1 7 1 8 mA Tym max 1 9 mA Operating Range Dual Supply 1 5 6 0 V Power Supply Rejection Ratio 58 60 dB Specifications subject to change without notice 2 REV A SINGLE SUPPLY er 25 vs 5 V G 2 R 100 O R Re 750 unless otherwise noted AD8012 Parameter Conditions Min Typ Max Units DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G z 1 Vout lt 0 4 V p p Ri 1 kQ 220 300 MHz G 2 Vour lt 0 4V p p RL 1 ko 90 140 MHz G 2 Vout lt 0 4V p p RL 100Q 85 MHz 0 1 dB Bandwidth Vout lt 0 4 V p p Rr 1 kQ 100 Q 43 24 MHz Large Signal Bandwidth Vour 2 V p p 60 MHz Slew Rate Vour 3 V p p 1 200 V us Rise and Fall Time Vour 2 V p p 2 ns Settling Time 0 1 Voyr 2 V p p 25 ns 0 02 Vour 2 V p p 40 ns Overdrive Recovery 2x Overdrive 60 ns NOISE HARMONIC PERFORMANCE Distortion Vour 2 V p p G 2 2nd Harmonic 500 kHz Ry 1 kQ 100 87 71 dBc 5 MHz R 1 kQ 100 77 61 dBc 3rd Harmonic 500 kHz Ry 1 kQ 100 89 72 dBc 5 MHz R 1 kQ 100 18 52 dBc Output IP3 500 kHz R 1 kQ 100 30 40 dBm IMD 500 kHz R 1 kQ 100 Q 77 80 dBc Crosstalk 5 MHz R 100 70 dB Input Voltage Noise f 10 kHz 2 5 nVAHz Input Current Noise f 10 kHz Input Input 15 pANHz Black Level Clamped to 2 V f 3 5
18. nverter Top Figure 48 Universal microSOIC Noninverter Top Figure 46 Universal SOIC Noninverter Bottom Figure 49 Universal microSOIC Noninverter Bottom 14 REV A AD8012 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead SOIC SO 8 0 1968 5 00 pa 890 so 8 5 0 1574 4 00 0 2440 6 20 0 1497 3 80 1 4 0 2284 5 80 PINT 0 0688 1 75 0 0196 0 50 0 0098 0 25 0 0532 1 35 0 0099 0 25 5 0 0040 0 10 Pn a gt ie o 0 0500 0 0192 0 49 a oll SEATING 1 27 5 0138 0 35 9 0098 0 25 0 0500 1 27 PLANE gsc N 9 0075 0 19 0 0160 0 41 8 Lead microSOIC RM 08 0 122 3 10 I 0 114 2 90 p 0 199 5 05 0 187 4 75 0 122 3 10 0 114 2 90 gt Fe 0 0256 0 65 BSC 0 120 3 05 0 120 3 05 7 0 112 2 84 gt 0 112 2 84 1L 0 043 1 09 0 006 0 15 y SENER 0 002 0 05 5 pe i 0 018 0 46 p gt gt le SEATING 9 008 0 20 REV A 15 0 011 0 28 0 028 0 71 PLANE 0 003 0 08 0 016 0 41 C3207a 0 12 99 PRINTED IN U S A
19. terminated line the amplifier must now drive a total load of 456 Q 1140 1140 228 Q considerably less than the original 270 Q load This reduces the drive current from the op amps by about 40 More significant however is the reduction in dynamic power consumption that is the power the amplifier must consume in order to deliver the load power Increasing the output signal so that it is as close as possible to the power rails minimizes the power consumed in the amplifier There is however a price to pay in terms of increased signal distortion Increasing the output signal of each op amp from the original 3 V to 3 9 V reduces the Spurious Free Dynamic Range SFDR from 65 dB to 50 dB measured at 500 kHz even though the overall load impedance has increased from 270 Q to 456 Q LAYOUT CONSIDERATIONS The specified high speed performance of the AD8012 requires careful attention to board layout and component selection Table I shows recommended component values for the AD8012 and Figures 44 49 show recommended layouts for the 8 lead SOIC and microSOIC packages for a positive gain Proper RF design techniques and low parasitic component selections are mandatory The PCB should have a ground plane covering all unused por tions of the component side of the board to provide a low im pedance ground path The ground plane should be removed from the area near the input pins to reduce stray capacitance Chip capacitors should be
20. used for supply bypassing see Fig ure 43 One end should be connected to the ground plane and the other within 1 8 in of each power pin An additional 4 7 UE 10 uF tantalum electrolytic capacitor should be con nected in parallel The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum Capacitance greater than 1 5 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gains Stripline design techniques should be used for long signal traces greater than about 1 in These should be designed with the proper system characteristic impedance and be properly termi nated at each end Vin Ro CHOSEN FOR CHARACTERISTIC IMPEDANCE INVERTING CONFIGURATION Vs Ro CHOSEN FOR CHARACTERISTIC IMPEDANCE NONINVERTING CONFIGURATION Figure 43 Inverting and Noninverting Configurations Table I Typical Bandwidth vs Gain Setting Resistors Small Signal 3 dB BW MHz Gain Re Re Rr Vs 5V R 1ko 1 750 Q 750 Q 53 6 Q 110 1 750 Q 49 9 Q 350 2 750 Q 750 Q 49 9 Q 150 10 750 Q 82 5 Q 49 9 Q 40 Rr chosen for 50 Q characteristic input impedance REV A 13 AD8012 z o CI tee 3 O d A D O CHELE s Ki p Eu l Figure 44 Universal SOIC Noninverter Top Silkscreen Figure 47 Universal microSOIC Noninverter Top Silkscreen Figure 45 Universal SOIC Noni
21. variations versus exter nal gain variations varying RN will be much lower compared to a VF op amp where the BW varies inversely with gain An other key attribute of this amplifier is its ability to run on a single 5 V supply due in part to its wide common mode input and output voltage range capability For 5 V supply operation the device obviously consumes half the quiescent power vs 10 V supply with little degradation in its ac and dc perfor mance characteristics See data sheet comparisons DC GAIN CHARACTERISTICS Gain stages Al A1B and A2 A2B combined provide negative feedforward transresistance gain See Figure 40 Stage A3 is a unity gain buffer which provides external load isolation to A2 Each stage uses a symmetrical complementary design A3 is also complementary though not explicitly shown This is done to reduce both second order signal distortion and overall quies cent power as discussed above In the quasi dc to low frequency region the closed loop gain relationship can be approximated as G 1 Rr Ry G Rr Ry These basic relationships above are common to all traditional operational amplifiers noninverting operation inverting operation AD8012 Figure 40 Simplified Block Diagram REV A 11 AD8012 APPLICATIONS Line Driving for HDSL High Bitrate Digital Subscriber Line HDSL is becoming popular as a means of providing full duplex data communication at rates up to 1 544 MBPS or 2 048 MBPS over
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ANALOG DEVICES AD8012 Dual 350 MHz Low Power Amplifier handbook