ANALOG DEVICES AD8010 200 mA Output Current High Speed Amplifier handbook
Contents
1. Re O MHz Vips 1 392 oo 345 950 2 374 374 305 1000 5 348 86 6 220 1000 10 499 54 9 135 650 Figure 32 Test Circuit for Table I NOTES lVo 0 2 V p p for 3 dB Bandwidth V 2 V p p for Slew Rate 5Bypassing per Figure 29 11 AD8010 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead Plastic Mini DIP N 8 0 430 10 92 gt 0 348 8 84 0 280 7 11 0 240 6 10 i 0 325 8 25 PIN 1 0 060 1 52 0 300 7 62 0 015 0 38 0 210 5 33 0 38 0 195 4 95 MAX 0 115 2 93 0 130 0 160 4 06 A Jk F G20 0 115 2 93 Fie lt 0 015 0 381 0 022 0 558 0 100 0 070 1 77 SEATIN 0 008 0 204 2 54 0 014 0 356 25 0 045 1 15 8 Lead SOIC SO 8 0 1968 5 00 0 1890 4 80 a 4 8 5 0 1574 4 00 0 2440 6 20 0 1497 m 1 4 0 2284 5 80 PIN 1 0 0688 1 75 0 0196 0 50 0 0098 0 25 0 0532 1 35 0 0099 0 25 9 0 0040 0 10 t 4 gt He je 4 A 8 f 0 0500 0 0192 0 49 o lle SEATING 1 27 60138 035 0 0098 0 25 0 0500 1 27 PLANE gsc 79 0 0075 0 19 0 0160 0 41 16 Lead Wide Body SOIC R 16 is 0 4133 10 50 i i i u 0 4193 10 65 0 2992 7 60 0 2914 7 40 0 3937 10 00 IN 1 0 1043 2 65 0 0291 0 74 0 0118 0 30 0 0926 2 35 7 0 0098 0 25 0 0040 0 10 St lt ie gt e 8 0 0500 12. 2 Vour 0 2 V p p 130 190 MHz 0 1 dB Bandwidth Vour 0 2 V p p 30 60 MHz Large Signal Bandwidth Vour 4 V p p 90 MHz Peaking Vour 0 2 V p p lt 5 MHz 0 02 dB Slew Vout 2 V p p 800 V us Rise and Fall Time Vour 2 V p p 2 0 ns Settling Time 0 1 Vour 2 V p p 25 ns NOISE HARMONIC PERFORMANCE Distortion Vout 2 V p p 2nd Harmonic 1 MHz 13 dBc 5 MHz 58 dBc 10 MHz 53 dBc 10 MHz R 39 Q 67 dBc 20 MHz 44 dBc 3rd Harmonic 1 MHz T1 dBc 5 MHz 63 dBc 10 MHz 57 dBc 10 MHz Ry 39 Q 63 dBc 20 MHz 50 dBc IMD 5 MHz Af 10 kHz 73 dBc IP3 5 MHz 42 dBm 1 dB Gain Compression 5 MHz 21 dBm Input Noise Voltage f 10 kHz 2 nVVHz Input Noise Current f 10 kHz In 3 pANHz f 20 kHz In 20 pANHz Differential Gain f 4 43 MHz Ry 150 Q 0 02 f 4 43 MHz Ry 18 75 Q 0 02 Differential Phase f 4 43 MHz Ry 150 Q 0 02 Degrees f 4 43 MHz R 18 75 Q 0 03 Degrees DC PERFORMANCE Input Offset Voltage 5 12 mV Tu TMAX 15 mV Offset Drift 10 uV C Input Bias Current 10 135 uA Tmmn Tmax 200 uA Input Bias Current 6 12 uA Tmmn Tmax 20 uA INPUT CHARACTERISTICS Input Resistance Input 125 kQ Input 12 5 Q Input Capacitance 2 75 pF Common Mode Rejection Ratio Vom 2 5 V 50 54 dB Input Common Mode Voltage Range t2 5 V Open Loop Transresistance Vout 2 5 V 300 500 kQ Turn TMAX 250 kQ OUTPUT CHARACTERISTICS Output Voltage Swing Ry 18 75 Q 2 1 2 5 V Ry 150 Q t2 7 3 0 V Output Current Rp 9Q 175 20
3. 80 70 90 80 100 0 03 0 1 1 10 100 500 0 1 1 10 100 500 FREQUENCY MHz FREQUENCY MHz Figure 15 PSRR vs Frequency Figure 18 CMRR vs Frequency 1000 G 30 ii G 2 316 0 2 100 a 31 100 45 o o PHASE E cum 4 316 90 2 gt a 3 1 0 b o a 2 10 135 1 5 z TRANSRESISTANCE p 5 0 31 3 16 180 T B 01 E 1 225 0 031 0 316 0 1 1 10 100 500 10k 100k 1M 10M 100M 1G FREQUENCY MHz FREQUENCY Hz Figure 16 Closed Loop Output Resistance vs Frequency Figure 19 Transresistance and Phase vs Frequency R 18 75 Q 2 3 0 1 G 1 20 T 1 0 z GAIN AS SHOWN G 2 2 Vo 2V p p z 1 0 R 18 750 a a 20 N N lt G 10 lt 3 0 z k gt a z S 4 0 xs 5 0 6 6 0 7 7 0 0 1 1 10 100 1000 0 1 0 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 17 Large Signal Frequency Response Vo 2 V p p Figure 20 Large Signal Frequency Response Vo 4 V p p 6 REV A AD8010 EN HN 5 B zo ete eer NB COREE MI 50 acer 3 a BINIB 2 Sea EE eo NITI BLAMEENEJE JEZSEENNEJN Figure 21 Small Signal Pulse Response G 1 Figure 24 Large Signal Pulse Response G 1 yo M te HK ALLE POPE SADU VOLTS Figure 22 Small Signal Pulse Response G 42 1 Figure 25 Large Signal Pulse Response G 2 1 1000 e eo IVERTING CUR
4. Lead SOIC Package 122 C Watt 16 Lead SOIC Package 0j 73 C Watt AD8010 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8010 is limited by the associated rise in junction tempera ture The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition tem perature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric perfor mance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in device failure While the AD8010 is internally short circuit protected this may not be sufficient to guarantee that the maximum junction temperature 150 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves 3 0 Ty 150 C 2 5 8 LEAD MINI DIP PACKAGE 2 0 16 LEAD SOIC PACKAGE WIDEBODY 1 0 8 LEAD SOIC PACKAGE e MAXIMUM POWER DISSIPATION Watts 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE C Figure 2 Plot of Maximum Power Dissipation vs Temperature ORDERING GUIDE Model Temperature Range Package Description Package Options AD8010AN 40 C to 85 C 8 Lead Plastic DIP N 8 AD8010AR 40 C to 85 C 8 Lead Plastic SOIC SO 8 AD8
5. Q differential load with low harmonic distor tion This makes it useful in designs that utilize a step up trans former to drive a twisted pair transmission line To achieve these levels of performance special precautions with respect to supply bypassing are recommended Figure 29 This configuration minimizes the contribution from high frequency supply rejection to differential gain and phase errors as well as reducing distortion due to harmonic energy in the power supplies GAIN AS SHOWN Vo 0 2V p p w 30 OVERSHOOT CAPACITIVE LOAD pF Figure 28 Capacitive Load Drive vs Series Resistor for Various Gains Driving Capacitance Loads The AD8010 was designed primarily to drive nonreactive loads If driving loads with a capacitive component is desired best frequency response is obtained by the addition of a small series resistance as shown in Figure 28 The inset figure shows the optimum value 101 Rsgnigs vs capacitive load It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll off of Rsgrigs and Cr LAYOUT CONSIDERATIONS The specified high speed performance of the AD8010 requires careful attention to board layout and component selection Proper Rg design techniques and low pass parasitic component selection are necessary The PCB should have a ground plane covering all unused por tions of the component side
6. each power pin individually to ground can have an adverse effect on the differential phase error of the circuit The cause of this is attributed to the fact that there is an internal compensation capacitor in the AD8010 that is referenced to the negative supply The recommended technique is to connect parallel bypass capacitors from the positive supply to the negative supply and then to bypass the negative supply to ground For high fre quency bypassing 0 1 uF ceramic capacitors are recommended These should be placed within a few millimeters of the power pins and should preferably be chip type capacitors The high currents that can potentially flow through the power supply pins require large bypassing capacitors These should be low inductance tantalum types and at least 47 uF The ground side of the capacitor that bypasses the negative supply should be brought to a single point ground that is the common for the returns of the outputs Figure 30 shows a circuit for making an N channel video distri bution amplifier As a practical matter the AD8010 can readily drive eight standard 150 Q video loads When driving up to 12 video loads there is minimal degradation in video performance Another important consideration when driving multiple cables is the high frequency isolation between the outputs of the cables Due to its low output impedance the AD8010 achieves better than 46 dB of output to output isolation at 5 MHz driv ing back termi
7. of the board to provide low imped ance path The ground plane should be removed from the area near the input pins to reduce the parasitic capacitance Vs Vs O AD8010 Figure 29 Standard Noninverting Closed Loop Configura tion with Recommended Bypassing Technigue The standard noninverting closed loop configuration with the recommended power supply bypassing technigue is shown in Figure 29 Ferrite beads Amidon Associates Torrance CA Part Number 43101 are used to suppress high freguency power supply energy on the DUT supply lines at the DUT C1 and C2 each represent the parallel combination of a 47 uF 16 V tanta lum electrolytic capacitor a 10 uF 10 V tantalum electrolytic capacitor and a 0 1 HE ceramic chip capacitor Connect C1 from the Vs pin to the Vs pin Connect C2 from the Vs pin to signal ground The feedback resistor should be located close to the inverting input pin in order to keep the parasitic capacitance at this node to a minimum Parasitic capacitances of less than 1 pF at the inverting input can significantly affect high speed performance Stripline design techniques should be used for long traces greater than about 3 cm These should be designed with a characteristic impedance Zo of 50 O or 75 O and be properly terminated at each end 8 REV A AD8010 APPLICATIONS Video Distribution Amplifier The AD8010 is optimized for the specific function of providing excellent video performan
8. 0 mA Short Circuit Current 240 mA Capacitive Load Drive 40 pF POWER SUPPLY Operating Range t4 5 6 0 V Quiescent Current 15 5 17 mA Twn to Tmax 20 mA Power Supply Rejection Ratio TVs 4 V to 6 V V 5 V 60 66 dB TVs 5 V Vs 4 V to 6 V 50 56 dB Specifications subject to change without notice 2 REV A ABSOLUTE MAXIMUM RATINGS Supply Voltage dew cides Glede 213000 S i ann A EIC Anu 12 6 V Internal Power Dissipation Plastic Package N Observe Power Derating Curves Small Outline Package R Observe Power Derating Curves Wide Body SOIC R 16 Observe Power Derating Curves Input Voltage Common Mode tVs Differential Input Voltage t1 2V Output Short Circuit Duration Observe Power Derating Curves Storage Temperature Range N R 65 C to 125 C Operating Temperature Range A Grade 40 C to 85 C Lead Temperature Range Soldering 10 sec 300 C NOTES IStresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device in free air 8 Lead Plastic Package a 90 C Watt 8
9. 010AR 16 40 C to 85 C 16 Lead Wide Body SOIC R 16 AD8010AR REEL REEL SOIC 13 REEL AD8010AR REEL7 REEL SOIC 7 REEL AD8010AR 16 REEL REEL SOIC 13 REEL AD8010AR 16 REEL7 REEL SOIC 7 REEL CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8010 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality REV A 3 s ESD SENSITIVE DEVICE AD8010 Typical Performance Characteristics 60 0 10 SAMPLE SIZE 300 G 2 50 f 4 43MHz PAL 0 08 18 750 DIFFERENTIAL GAIN gt o DIFFERENTIAL GAIN dG IN DIFFERENTIAL PHASE d IN 0 06 DIFFERENTIAL PHASE 0 04 PERCENTAGE OF UNITS 8 8 DIFFERENTIAL GAIN 0 02 DIFFERENTIAL PHASE Degrees 10 db db db db 0 0 0 01 0 02 0 03 0 04 0 05 0 06 0 07 0 08 0 09 0 10 0 11 0 12 0 13 1 2 4 6 8 10 12 14 16 dG Degrees NUMBER OF VIDEO LOADS Figure 3 Distribution of Differentia
10. 27 aD 0 0192 0 49 SEATING 0 0125 0 32 0 0 0157 0 40 0 0138 0 35 pL ANE 0 0091 0 23 0 23 x45 12 REV A C3208a 0 10 98 PRINTED IN U S A
11. D8010 is an ideal component choice for any application that needs a driver that will maintain signal quality when driving low impedance loads The AD8010 is offered in three package options an 8 lead DIP 16 lead wide body SOIC and a low thermal resistance 8 lead SOIC and operates over the industrial temperature range of 40 C to 85 C REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices CONNECTION DIAGRAMS 8 Lead DIP and SOIC NC NO CONNECT 16 Lead Wide Body SOIC NC NO CONNECT Vouri Vour2 Vours Voura Vours Voure Vout7 Vouts Figure 1 Video Distribution Amplifier One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1998 AD801 0 SPECIFICATIONS 25 C V 5 V G 2 R 18 75 Q Rs 150 Rr Rg 604 R 16 Rr Rg 562 N 8 Rc Re 499 R 8 Tuy 40 C Tmax 85 C unless otherwise noted Model Conditions Min Typ Max Units DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vour 0 2 V p p 180 230 MHz G
12. O AD801q U ANALOG DEVICES 200 mA Output Current High Speed Amplifier AD8010 FEATURES 200 mA of Output Current 90 Load SFDR 54 dBc O 1 MHz Differential Gain Error 0 0496 f 4 43 MHz Differential Phase Error 0 06 f 4 43 MHz Maintains Video Specifications Driving Eight Parallel 75 O Loads 0 0296 Differential Gain 0 03 Differential Phase 0 1 dB Gain Flatness to 60 MHz THD 72 dBc 9 1 MHz R 18 75 O IP3 42 dBm 5 MHz R 18 75 O 1 dB Gain Compression 21 dBm O 5 MHz R 100 230 MHz 3 dB Bandwidth G 1 R 18 75 800 V us Slew Rate R 18 75 O 25 ns Settling Time to 0 196 Available in 8 Lead DIP 16 Lead Wide Body SOIC and Thermally Enhanced 8 Lead SOIC APPLICATIONS Video Distribution Amplifier VDSL xDSL Line Driver Communications ATE Instrumentation PRODUCT DESCRIPTION The AD8010 is a low power high current amplifier capable of delivering a minimum load drive of 175 mA Signal performance such as 0 02 and 0 03 differential gain and phase error is maintained while driving eight 75 O back terminated video lines The current feedback amplifier features gain flatness to 60 MHz and 3 dB G 1 signal bandwidth of 230 MHz and only requires a typical of 15 5 mA supply current from 5 V supplies These features make the AD8010 an ideal component for Video Distribution Amplifiers or as the drive amplifier within high data rate Digital Subscriber Line VDSL and xDSL systems The A
13. RENT o INPUT VOLTAGE NOISE nV Hz INPUT CURRENT NOISE PA Hz z NONINVERTING CURRENT 10 100 1k 10k 100k 1M 10M FREQUENCY Hz FREQUENCY Hz Figure 23 Input Voltage Noise vs Frequency Figure 26 Input Current Noise vs Frequency REV A 7 AD8010 VOLTS INPUT 500mV DIV OUTPUT 1V DIV ZEN Figure 27 Overdrive Recovery G 46 OVERDRIVE RECOVERY Overdrive of an amplifier occurs when the output and or input range are exceeded The amplifier must recover from this over drive condition As shown in Figure 27 the AD8010 recovers within 35 ns from negative overdrive and within 75 ns from positive overdrive THEORY OF OPERATION The AD8010 is a current feedback amplifier optimized for high current output while maintaining excellent performance with respect to flatness distortion and differential gain phase As a video distribution amplifier the AD8010 will drive up to 12 parallel video loads 12 5 Q from a single output with 0 04 differential gain and 0 04 differential phase errors This means that unlike designs with one driver per output any output is a true reflection of the signal on all other outputs The high output current capability of the AD8010 also make it useful in xDSL applications The AD8010 can drive a 12 50 single ended or 25
14. ce when driving multiple video loads in parallel Significant power is saved and heat sinking is greatly simplified because of the ability of the AD8010 to obtain this performance when running on a 5 V supply However due to the high currents that flow when driving many parallel video loads special layout and bypassing techniques are required to assure optimal performance When designing a video distribution amplifier with the AD8010 it is very important to keep in mind where the high ac currents will flow These paths include the power supply pins of the chip along with the bypass capacitors and the return path for these capacitors the output circuits and the return path of the output current from the loads In general any loops that are formed by any of the above paths should be made as small as possible Large loops are both gen erators and receivers of magnetic fields and can cause undesired coupling of signals that lowers the performance of the amplifier Effects that have not been seen before in other op amp circuits might arise because of the high currents Most op amp circuits output at most tens of milliamps and do not require extremely tight video specifications while a video distribution amplifier can output hundreds of milliamps and require extremely low differential gain and phase errors The bypassing scheme that is used for the AD8010 requires special attention It was found that the conventional technique of bypassing
15. ine scale gain flatness will to some ex tent vary with feedback resistor tolerance It is therefore recom mended that resistors with a 196 tolerance be used if it is desired to maintain flatness over a wide range of production lots In addition resistors of different construction have different associ ated parasitic capacitance and inductance Metal film resistors were used for the bulk of the characterization for this data sheet It is possible that values other than those indicated will be opti mal for other resistor types Quality of Coaxial Cable Optimum flatness when driving a coax cable is possible only when the driven cable is terminated at each end with a resistor matching its characteristic impedance If the coax was ideal then the resulting flatness would not be affected by the length of the cable While outstanding results can be achieved using inex pensive cables it should be noted that some variation in flatness due to varying cable lengths may be experienced REV A Gain and Resistor Values Package N 8 Closed Loop 3 dB BW Slew Rate Gain Rr OQ Re O MHz Vips 1 453 co 285 900 2 374 374 255 900 5 348 86 6 200 800 10 562 61 9 120 550 Package R 16 Closed Loop 3 dB BW Slew Rate Gain Rr OQ Re O MHz Vips 1 412 co 245 900 2 392 392 220 900 5 392 97 6 160 800 10 604 66 5 95 550 Package SO 8 Closed Loop 3 dB BW Slew Rate Gain Rr OQ
16. l Gain dG and Figure 6 Differential Gain and Phase vs Number of Video Differential Phase d R 18 75 Q Loads Over Temperature 40 C to 85 C f 4 43 MHz 45 G 2 50 Vo 2V p p o 55 RL AS SHOWN s E i 60 2ND a 2 I E 65 R 18 750 E E 70 9 G 2 2 18 750 Q 75 o o tc E 80 3RD E x z s5 R 1000 2ND 90 95 1 2 3 4 5678910 20 1 10 100 FREQUENCY MHz FREQUENCY MHz Figure 4 Harmonic Distortion vs Frequency G 2 Figure 7 Two Tone 3rd Order IMD Intercept vs Frequency G 2 R 18 75 Q 6 5 7 6 4 G 2 Vo 0 2V p p 2 6 3 NUMBER OF VIDEO LOADS AS SHOWN 6 a a 6 2 m T 8 9 A 6 1 gt 6 0 a a T 2 5 9 z 1 3 o 5 8 10 5 7 12 5 6 447 7 5 5 0 1 1 10 100 500 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 5 Gain Flatness vs Frequency Over Temperature Figure 8 Gain Flatness vs Frequency vs Number of 40 C to 85 C Video Loads 4 REV A AD8010 PMEAsun 10dBm FULL SCALE GAIN 6 6 Re 500kHz TONE SPACING FROM 500kHz TO 5 5MHz WITH 4 MISSING TONES Pweasure dBm INTERMODULATION DISTORTION dBm 4 965 4 985 5 0 5 015 5 035 FREQUENCY MHz FREQUENCY MHz Figure 9 Intermodulation Distortion Figure 12 Multitone Dis
17. nated 75 Q cables Figure 30 An N Channel Video Distribution Amplifier Using An AD8010 NOTE Please see Figure 29 for Recommended Bypassing Technique REV A AD8010 Differential Line Driver Twisted pair transmission lines are more often being used for high frequency analog and digital signals Over long distances however the attenuation characteristics of these lines can degrade the performance of the transmission system To com pensate for this larger signals are transmitted which after the attenuation will still have useful signal strength The high output current of two AD8010s can be used along with a transformer to create a high power differential line driver The differential configuration effectively doubles the output swing while the step up transformer further increases the out put voltage 4990 AD8010 l 8060 AD8010 I In the circuit in Figure 31 the A device is configured as a gain of two follower while the B device is a gain of two inverter These will produce a differential output signal whose maximum value is twice the peak to peak value of the maximum output of one device For this circuit a 12 V peak to peak output can be obtained The op amps drive a 1 2 step up transformer that drives a 100 Q transmission line Since the impedance reflected back to the primary varies as the square of the turns ratio it will appear as 25 O at the primary This source terminating resistor is s
18. plit as a 12 4 O resistor at the output of each device The circuit shown is capable of delivering 12 V p p to the line and operates with a 3 dB bandwidth of 40 MHz The peak current output of either op amp is 100 mA 6 1000 1 2 6 Figure 31 High Output Differential Line Driver Using Two AD8010s NOTE Please see Figure 29 for Recommended Bypassing Technique 10 REV A AD8010 Table I 3 dB Bandwidth and Slew Rate vs Closed Loop Closed Loop Gain and Bandwidth The AD8010 is a current feedback amplifier optimized for use in high performance video and data acquisition applications Since it uses a current feedback architecture its closed loop 3 dB bandwidth is dependent on the magnitude of the feed back resistor The desired closed loop bandwidth and gain are obtained by varying the feedback resistor Rg to set the band width and varying the gain resistor Rg to set the desired gain The characteristic curves and specifications for this data sheet reflect the performance of the AD8010 using the values of Rp noted at the top of the specifications table If a greater 3 dB band width and or slew rate is required at the expense of video per formance Table I provides the recommended resistor values Figure 32 shows the test circuit and conditions used to produce Table I Effect of Feedback Resistor Tolerance on Gain Flatness Because of the relationship between the 3 dB bandwidth and the feedback resistor the f
19. tortion R 1000 FREQUENCY 5MHz G 2 AS SHOWN SEE SCHEMATIC HARMONIC DISTORTION dBc TOTAL HARMONIC DISTORTION dBc PIN RL lt FOR 1000 RL1 23 1 FOR R 18 750 10 8 6 15 100 200 300 400 500 LOAD 9 Figure 10 Total Harmonic Distortion vs Pour G 2 Figure 13 Harmonic Distortion vs Load G 1 2 1 E o 0 2V p p G 2 UMBER OF VIDEO LOADS AS SHOWN i 1 1 z a a o 2 3 a G 3 z a z 3 lt 3 o 4 GAIN AS SHOWN 5 Vo 0 2V p p gs 218750 6 27 0 1 1 10 100 1000 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 11 Small Signal Closed Loop Frequency Figure 14 Closed Loop Frequency Response vs Response R 18 75 Q Number of Video Loads REV A b AD8010 10 0 10 20 20 30 30 40 gm I 50 50 PSRR 569 60 70 PSRR
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