Home

ANALOG DEVICES AD8002 Dual 600 MHz 50 mW Current Feedback Amplifier handbook

1. 120 115 100 Rpt 500 5119 7500 lt 750 105 10 s v 100 1 POWER 0dBm tc ul 223 6mVrms 2 o O 95 6 2 E Rpr 00 3 eo SN 5 T N 9 tc 85 0 1 a 2 5 80 75 0 01 70 55 35 1 5 25 45 65 85 105 125 10 100 1M 10M 100M 1G JUNCTION TEMPERATURE C FREQUENCY Hz TPC 25 Short Circuit Current vs Temperature TPC 28 Output Resistance vs Frequency 100 100 1 BANDWIDTH SIDE 1 0 SIDE 2 E N N z i INVERTING CURRENT Vs 5V 5 2 0 1dB FLATNESS SIDE 1 0 3 amp 10 10 0 1 4 3 5 Vg 5V gt 5 0 2 5 NONINVERTING CURRENT Vs 5V SIDES o o 0 3 1000 6 5 2 Rr 5490 VOLTAGE NOISE Vg 5V 7 8 1 1 9 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY Hz FREQUENCY Hz TPC 26 Noise vs Frequency TPC 29 3 dB Bandwidth vs Frequency G 1 48 50 0 ET 52 5 PSRR 55 0 50 57 5 51 2V SPAN m m 60 0 b CMRR 5 CURVES ARE FOR WORST 52 4 62 5 CASE CONDITION WHERE t ONE SUPPLY IS VARIED 5 65 0 WHILE THE OTHER IS 53 HELD CONSTANT 67 5 54 70 0 PSRR 72 5 56 75 0 55 35 15 5 25 45 65 85 105 125 55 35 1 5 25 45 65 85 105 125 JUNCTION TEMPERATURE C JUNCTION TEMPERATURE C TPC 27 CMRR vs T
2. 2 0 6 Vin 50mV SIDE 1 3 3 1 Re 9530 1000 25 0 0 SIDE 2 gt 29 3 5 1 d 12 6 2 2 5 15 9 5 23 750 2 a 500 E 18 G 2 12 500 6810 4 2i Vg 5V 15 1000 5 24 eye 18 6 27 21 1 10 100 1G 1M 10M 100M 500M FREQUENCY Hz FREQUENCY Hz TPC 13 Frequency Response G 1 TPC 16 Large Signal Frequency Response G 2 40 9 1000 G 1 6 zin 1000 Rf 1 2100 2V p OUT 9 60 m gt mI 70 6 gt tr E 750 2ND HARMONIC 9 0 500 5 42 amp 1 21 0 15 90 18 100 27 10k 100k 1M 10M 100M 1M 10M 100M 500M FREQUENCY Hz FREQUENCY TPC 14 Distortion vs Frequency G 41 1000 TPC 17 Large Signal Frequency Response G 1 40 45 G 1 40 4 50 1000 35 60 30 G 100 Rf 10000 T m 25 F 2 70 9 2ND HARMONIC 2 20 3
3. 5 9 0 SIDE 1 4 m N 0 1 5 SIDE 2 02 6 A N 8 a5 0 3 7d z 04 8 5 2 0 5 9 1 10M 100M 1G FREQUENCY Hz Figure 1 Frequency Response Flatness 2 1V STEP Figure 2 1 V Step Response G 1 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site www analog com Fax 781 326 8703 Analog Devices Inc 2001 AD8002 SPEC 0 NS T 25 C Vs 5 V 100 75 Q unless otherwise noted Model AD8002A Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth N Package 2 750 Q 500 MHz 1 Rp 1 21 600 MHz R Package G 2 Rp 6810 500 MHz 1 Rp 953 Q 600 MHz RM Package G 2 Rg 681 Q 500 MHz 1 1 600 MHz Bandwidth for 0 1 dB Flatness N Package 2 Rp 7500 60 MHz R Package 2 Rp 6810 90 MHz RM Package 2 Rp 6810 60 MHz Slew Rate G 2 Vo 2 V Step 700 V us G 1 Vo 2 V Step 1200 V us Settling Time to 0 196 2 Vo 2 V Step 16 ns Rise and Fall Time 2 Vo 2 V Step Rg 7500 2 4 ns NOISE HARMONIC PERFORMANCE Total Harmonic Distortion fo 5 MHz 2 V p p 65 G 2 R 1000 Crosstalk Output to Output f 5 MHz 2 60 Input Voltage Noise f 10 kHz 0Q 2 0 2 Input Current Noise f 10 kHz 2 0 2 In 18
4. 2 Differential Gain Error NTSC 2 1500 0 01 Differential Phase Error NTSC G 2 1500 0 02 Degree Third Order Intercept f 10 MHz 33 dBm 1 dB Gain Compression f 10 MHz 14 dBm SFDR f 5 MHz 66 DC PERFORMANCE Input Offset Voltage 2 0 6 mV 2 0 9 mV Offset Drift 10 uV C Input Bias Current 5 0 25 35 Input Bias Current 3 0 6 0 10 Open Loop Transresistance Vo 2 5 V 250 900 kQ INPUT CHARACTERISTICS Input Resistance Input 10 MQ Input 50 Q Input Capacitance Input 1 5 pF Input Common Mode Voltage Range 3 2 V Common Mode Rejection Ratio Offset Voltage Vom 2 V 49 54 dB Input Current Vem 2 5 V 0 3 1 0 Input Current Vom 2 5 V 0 2 0 9 OUTPUT CHARACTERISTICS Output Voltage Swing 1500 254 31 V Output Current 70 mA Short Circuit Current 85 110 mA POWER SUPPLY Operating Range 3 0 6 0 Quiescent Current Both Amplifiers 10 0 11 5 mA Power Supply Rejection Ratio TVs 4 V to 6 V Vs 5 V 60 75 dB Vs 4 V to 6 V Vs 5 V 49 56 dB Input Current 0 5 2 5 Input Current 0 1 0 5 NOTES is recommended to reduce peaking and minimize input reflections at frequencies above 300 MHz However is not required Output current is limited by the maximum power di
5. 8002 OUTPUT 2 OP AMP 2 Figure 11 Differential Line Driver The current feedback nature of the op amps in addition to enabling the wide bandwidth provides an output drive of more than 3 V p p into a 20 Q load for each output at 20 MHz On the other hand the voltage feedback nature provides symmetrical high impedance inputs and allows the use of reactive compo nents in the feedback network The circuit consists of the two op amps each configured as a unity gain follower by the 511 feedback resistors between each op amp s output and inverting input The output of each op amp has 511 resistor to the inverting input of the other op amp Thus each output drives the other op amp through a unity gain inverter configuration By connecting the two amplifi ers as cross coupled inverters their outputs are freed to be equal and opposite assuring zero output common mode voltage With this circuit configuration the common mode signal of the outputs is reduced If one output moves slightly higher the nega tive input to the other op amp drives its output to go slightly lower and thus preserves the symmetry of the complementary outputs which reduces the common mode signal The common mode output signal was measured to be 50 dB at 1 MHz Looking at this configuration overall there are two high imped ance inputs the inputs of each op amp two low impedance outputs and high open loop gain If we consider th
6. 0 0040 0 10 we 14 xl 0 0 0500 1 27 seating 20192 0 49 0 0098 0 25 0 9 0500 1 27 PLANE 0 0138 0 35 0 0075 019 001800041 8 Lead pSOIC RM 8 0 122 3 10 ie 0 122 3 10 0 114 2 90 0 199 5 05 0 187 4 75 PIN1 je 0 0256 0 65 BSC 0 120 3 05 0 120 3 05 0 006 0 15 0 092 0 05 0 037 0 94 MC T 0 018 0 46 33 27 0 028 0 71 SEATING 0 008 0 20 0 011 0 28 0 71 PLANE 0 003 0 08 0 016 0 41 18 REV D Revision History AD8002 Location Data Sheet changed from REV C to REV D MAX RATINGS changed Page REV D 19 10 7 0 4770102 NI 20
7. MHz REV D 45 2 50 F4 10MHz Fo 12MHz 55 2 2F2 F Y4 60 2F4 F 1 2 2 E 5 65 70 75 80 8 7 6 5 4 3 2 101 2 3 4 5 6 INPUT POWER dBm Figure 8 Third Order IMD 10 MHz 12 MHz Operation as a Video Line Driver The AD8002 has been designed to offer outstanding perfor mance as a video line driver The important specifications of differential gain 0 01 and differential phase 0 02 meet the most exacting HDTV demands for driving one video load with each amplifier The AD8002 also drives four back terminated loads two each as shown in Figure 9 with equally impressive performance 0 01 0 07 Another important consideration is isolation between loads in a multiple load application The AD8002 has more than 40 dB of isolation at 5 MHz when driv ing two 75 Q back terminated loads 750 750 CABLE 750 CABLE Figure 9 Video Line Driver 11 8002 Driving A to D Converters the AD9058 s internal 2 V reference connected to both ADCs The AD8002 is well suited for driving high speed analog to as shown in Figure 10 reduces the number of external compo digital converters such as the AD9058 The AD9058 is a dual nents required to create a complete data acquisition system The 8 bit 50 MSPS ADC In Figure 10 the AD8002 is shown driv 20 Q resistors in series with ADC
8. small series damping resis tor 4 7 for optimum results DC Errors and Noise There are three major noise and offset terms to consider in a current feedback amplifier For offset errors refer to the equa tion below For noise error the terms are root sum squared to give a net output error In the circuit shown in Figure 5 they are input offset Vio which appears at the output multiplied by the noise gain of the circuit 1 Rz Ry noninverting input current x Ry also multiplied by the noise gain and the inverting input current which when divided between Rg and and subsequently multiplied by the noise gain always appears at the output as Ipy x The input voltage noise of the AD8002 is a low 2 nV VHz At low gains though the inverting input current noise times Rg is the dominant noise source Careful layout and device matching contribute to better offset and drift specifications for the AD8002 compared to many other current feedback amplifiers The typical performance curves in conjunction with the equations below can be used to predict the performance of the AD8002 in any application Vour Vio X 1 Igy X Ry Ip X Figure 5 Output Offset Voltage REV D 8002 Driving Capacitive Loads The AD8002 was designed primarily to drive nonreactive loads If driving loads with a capacitive component is desired best frequency response is obtained by the addition of a s
9. 02ARM REEL7 409 to 85 8 Lead uSOIC 7 REEL RM 8 HFA CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8002 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING eer ESD SENSITIVE DEVICE REV D 3 08002 Performance Characteristics 9530 1000 Vin O 3 1000 V V Tn Tr 250ps 5V 250ps 5V TPC 1 Test Circuit Gain 1 E iin V ane TPC 2 100 mV Step Response G 1 TPC 5 100 mV Step Response G 2 TPC 3 Step Response 1 TPC 6 1 Step Response G 2 4 REV D SIDE 1 0 G 2 m 1000 SIDE 2 1 Vin 50mV 9 2 o z 3 0 1 lt 0 SIDE 1 4 a N 0 1 5 SIDE 2 02 6 a 2 03 7 0 4 8 0 5 9 1 10 100 1G FREQUENCY Hz TPC 7 Frequency Response and Flatness G 2 2 1000 2ND HARMO
10. 9 549 953 681 499 1000 Re 49 9 274 576 750 54 9 10 49 9 249 549 681 54 9 10 Nominal 0 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 Rc Q 75 75 0 0 75 75 0 0 Rs Q 49 9 49 9 49 9 49 9 49 9 49 9 Rr Nominal 61 9 54 9 49 9 49 9 49 9 49 9 61 9 54 9 49 9 49 9 49 9 49 9 Small Signal BW MHz 270 380 410 600 500 170 17 250 410 410 600 500 170 17 0 1 dB Flatness MHz 45 80 130 35 60 24 3 50 100 100 35 90 24 3 AD8002ARM SOIC Gain Component 10 2 1 1 2 10 100 499 499 590 1000 681 499 1000 Rg Q 49 9 249 590 681 54 9 10 Rar Nominal Q 49 9 49 9 49 9 49 9 49 9 49 9 49 9 Rc Q 75 75 0 0 Rs 49 9 49 9 49 9 Rz Nominal Q M 61 9 49 9 49 9 49 9 49 9 49 9 Small Signal BW MHz 270 400 410 600 450 170 19 0 1 dB Flatness MHZ 60 100 100 35 70 35 3 Rc is recommended to reduce peaking and minimizes input reflections at frequencies above 300 MHz However is not required 214 REV D 8002 INVERTER DIP ANALOG DEVICES INVERTER SOIC INVERTER wSOIC 9 MINI SO INUERTER REV D Rotl ec NONINVERTER DIP NONINUERTER DIP DIP INVERTER c ANALOG 2 DEVICES ANALOG AN
11. ALOG DEVICES DEVICES SRF NONINVERTER SOIC fe 4 Rt 50 NONINUERTER o 686 ANALOG DEVICES U U ANALOG DEVICES NONINVERTER 5 Figure 14 Board Layout Silkscreen 15 8002 INVERTER DIP DIP NONINVERTER INVERTER SOIC SOIC NONINVERTER INVERTER asd i SOIC p SOIC Figure 15 Board Layout Component Layer 16 REV D 8002 DIP NONINVERTER DIP INVERTER SOIC NONINVERTER SOIC INVERTER NONINVERTER uSOIC Figure 16 Board Layout Solder Side Looking through the Board REV D 17 8002 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead Plastic DIP N 8 0 430 10 92 0 348 8 84 8 5 0 280 7 11 2 0 240 6 10 1 4 1 Te 0 325 8 25 0 100 2 54 0 300 7 62 BSC 0 060 1 52 0 210 0 015 0 38 0 195 4 95 0 115 2 93 0 130 0 160 4 06 3 30 0 115 2 93 OON 0 015 0 381 0 022 0 558 0 070 1 77 SEATING 0 008 0 204 0 014 0 356 0 045 1 15 PLANE Lead SOIC SO 8 0 1968 5 00 01890 8 5 0 1574 4 00 0 2440 6 20 0 1497 3 80 1 0 2284 5 80 1 PIN 1 7 0 0500 1 27 0 0196 0 50 BSC gt 025 4 0 0688 1 75 0 0098 0 25 3 3 0 0532 1 35
12. ANALOG DEVICES Dual 600 MHz 50 mW Current Feedback Amplifier AD8002 FEATURES Excellent Video Specifications 150 0 G 2 Gain Flatness 0 1 dB to 60 MHz 0 01 Differential Gain Error 0 02 Differential Phase Error Low Power 5 5 mA Amp Max Power Supply Current 55 mW High Speed and Fast Settling 600 MHz 3 dB Bandwidth G 1 500 MHz 3 dB Bandwidth G 2 1200 V ps Slew Rate 16 ns Settling Time to 0 1 Low Distortion 65 dBc THD f 5 MHz 33 dBm Third Order Intercept F 10 MHz 66 dB SFDR f 5 MHz 60 dB Crosstalk f 5 MHz High Output Drive Over 70 mA Output Current Drives Up to Eight Back Terminated 75 Loads Four Loads Side While Maintaining Good Differential Gain Phase Performance 0 01 0 17 Available 8 Lead Plastic DIP SOIC and pSOIC Packages APPLICATIONS A to D Driver Video Line Driver Differential Line Driver Professional Cameras Video Switchers Special Effects RF Receivers PRODUCT DESCRIPTION The AD8002 is a dual low power high speed amplifier designed to operate on 5 V supplies The AD8002 features unique trans impedance linearization circuitry This allows it to drive video loads with excellent differential gain and phase performance on only 50 mW of power per amplifier The AD8002 is a current feedback amplifier and features gain flatness of 0 1 dB to 60 MHz while offering differential gain and phase error of 0 01 and 0 02 This makes the AD8002 ideal for prof
13. NIC 3RD HARMONIC DISTORTION dBc 100 110 10k 100k 1M FREQUENCY Hz 10M 100M NORMALIZED FREQUENCY RESPONSE dB TPC 8 Distortion vs Frequency 2 1000 DISTORTION dBc 10k 100k 1M FREQUENCY Hz 10M 100M TPC 9 Distortion vs Frequency 2 1 REV D AD8002 20 Vin 30 1000 Vg 5 0V OUTPUT SIDE 1 40 F G 42 Rf 7500 50 a 60 OUTPUT SIDE 2 E 70 7 80 90 100 110 120 100k 1M 10M 100M FREQUENCY Hz TPC 10 Crosstalk Output to Output vs Frequency NOTES SIDE 1 Viy 8mV div RTO SIDE 2 1V STEP RTO 400mV div TPC 11 Pulse Crosstalk Worst Case 1 V Step 0 02 2 BACK TERMINATED 2 0 01 LOADS 750 2 0 00 001 1 0 02 LOAD 1500 2 BACK TERMINATED LOADS 750 0 08 9 8 0 06 04 1 BACK TERMINATED LOAD 1500 lt 0 02 0 00 TPC 12 Differential Gain and Differential Phase per Amplifier 8002
14. RD HARMONIC Gul tr 6 45 Rf 4990 90 10 5 100 0 110 5 10k 100k 1M 10M 100M 1M 10M 100M 1G FREQUENCY Hz FREQUENCY Hz TPC 15 Distortion vs Frequency 1 1 TPC 18 Frequency Response G 10 G 100 REV D 3 0 Vout 2 8 2500 INPUT BIAS CURRENT pA REV D OUTPUT SWING Volts 1500 Vour 55 35 15 5 25 45 65 85 105 125 JUNCTION TEMPERATURE C TPC 20 Output Swing vs Temperature 55 35 15 5 25 45 65 85 105 125 JUNCTION TEMPERATURE C TPC 21 Input Bias Current vs Temperature AD8002 INPUT OFFSET VOLTAGE mV 55 35 15 5 25 45 65 85 105 125 JUNCTION TEMPERATURE C TPC 23 Input Offset Voltage vs Temperature ud 9 0 55 35 15 5 25 45 65 85 105 125 JUNCTION TEMPERATURE a a TOTAL SUPPLY CURRENT mA TPC 24 Total Supply Current vs Temperature 8002
15. e two nonin verting inputs and just the output of Op Amp 2 the structure looks like a voltage feedback op amp having two symmetrical high impedance inputs and one output The input to Op Amp 2 is the noninverting input it has the same polarity as Output 2 and the input to Amplifier 1 is the inverting input oppo site polarity of Output 2 REV D With a feedback resistor an input resistor and grounding of the input of Amp 2 a feedback amplifier is formed This configuration is just like a voltage feedback amplifier in an inverting configuration if only Output 2 is considered The addition of Output 1 makes the amplifier differential output The differential gain of this circuit is The term is the gain of the overall op amp configuration and is the same as for an inverting op amp except for the polarity If Output 1 is used as the output reference the gain is posi tive The 1 term is the noise gain of each individual op amp in its noninverting configuration The resulting architecture offers several advantages First the gain can be changed by changing a single resistor Changing either Rr or Rg will change the gain as in an inverting op amp circuit For most types of differential circuits more than one resistor must be changed to change gain and still maintain good CMR Reactive elements can be used in the feedback network This is in contrast to current feedback amplifiers t
16. empera ture The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition tem perature of the plastic approximately 150 C Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in device failure While the AD8002 is internally short circuit protected this may not be sufficient to guarantee that the maximum junction temperature 150 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves 2 0 PLASTIC DIP PACKAGE 8 LEAD SOIC PACKAGE 15 lt o o a 1 0 a 5 8 LEAD SOIC 2 0 5 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE Figure 3 Plot of Maximum Power Dissipation vs Temperature ORDERING GUIDE Model Temperature Range Package Description Package Option Brand Code AD8002AN 409 to 85 C 8 Lead PDIP N 8 Standard AD8002AR 40 C to 85 C 8 Lead SOIC SO 8 Standard AD8002AR REEL 409 to 85 C 8 Lead SOIC 13 REEL SO 8 Standard AD8002AR REEL7 409 to 85 C 8 Lead SOIC 7 REEL SO 8 Standard AD8002ARM 409 to 85 C 8 Lead uSOIC RM 8 HFA AD8002ARM REEL 409 to 85 C 8 Lead uSOIC 13 REEL RM 8 HFA AD80
17. emperature TPC 30 PSRR vs Temperature 8 REV OUTPUT VOLTAGE dB 8002 CMRR dB 1M 10M 100M FREQUENCY Hz TPC 31 CMRR vs Frequency i HH N ons TPC 32 2 V Step Response G 7 5760 Coan pop db WIESEN WEN NUN JL D ela 5760 POs TPC 33 100 mV Step Response G 1 REV D PSRR dB 90 30k 100k 1M 10M 100M 500M FREQUENCY Hz TPC 34 PSRR vs Frequency Idt L dpi wom VTT ane TPC 35 2 V Step Response 6 5490 irs ie I 0 Ev E TPC 36 100 mV Step Response 8002 THEORY OF OPERATION A very simple analysis can put the operation of the AD8002 a current feedback amplifier in familiar terms Being a current feedback amplifier the AD8002 s open loop behavior is expressed as transimpedance AVo AI or Tz The open loop transim pedance behaves just as the open loop voltage gain of a voltage feedback amplifier that is it has a large dc value and decreases at roughly 6 dB octave in frequency Since the Ry is proportional to 1 g the equivalent voltage gain is just Tz x Zm where the gm in q
18. essional video electronics such as cameras and video switchers Additionally the AD8002 s low distortion and fast settling make it ideal for buffer high speed A to D converters The AD8002 offers low power of 5 5 mA amplifier max Vs 5 V and can run on a single 12 V power supply while capable of delivering over 70 mA of load current It is offered in an 8 lead plastic DIP SOIC and uSOIC package These features make this amplifier ideal for portable and battery powered applications where size and power are critical REV D Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM 8 Lead Plastic DIP SOIC and 5 The outstanding bandwidth of 600 MHz along with 1200 V us of slew rate make the AD8002 useful in many general purpose high speed applications where dual power supplies of up to 6 V and single supplies from 6 V to 12 V are needed The AD8002 is available in the industrial temperature range 409 to 85 C 1 SIDE 1 2 iu m 1000 SIDE 2 79 m Vin 50mV 5 20 o o Z
19. hat restrict the use of reactive elements in the feedback The circuit described requires about 0 9 pF of capacitance in shunt across Rg in order to optimize peaking and realize a 3 dB bandwidth of more than 200 MHz peaking exhibited by the circuit is very sensitive to the value of this capacitor Parasitics in the board layout on the order of tenths of picofarads will influence the frequency response and the value required for the feedback capacitor so a good lay out is essential The shunt capacitor type selection is also critical A good micro wave type chip capacitor with high Q was found to yield best performance The part selected for this circuit was a muRata Erie part number MA280R9B The distortion was measured at 20 MHz with a V p p input and 100 Q load on each output For Output 1 the distortion is 37 dBc and 41 dBc for the second and third harmonics respectively For Output 2 the second harmonic is 35 dBc and the third harmonic is 43 dBc OUTPUT dB 1M 10M 100M 1G FREQUENCY Hz Figure 12 Differential Driver Frequency Response 132 8002 Layout Considerations The specified high speed performance of the AD8002 requires careful attention to board layout and component selection Proper Rg design techniques and low parasitic component selec tion are mandatory The PCB should have a ground plane cove
20. inputs are used to help the ing the inputs of the AD9058 which are configured for 0 V to2 V AD8002s drive the 10 pF ADC input capacitance The AD8002 ranges Bipolar input signals are buffered amplified 2x and adds only 100 mW to the power consumption while not limit offset by 1 0 V into the proper input range of the ADC Using ing the performance of the circuit ENCODE 74 04 p ENCODEA ENCODE ANALOG 2740 O INA 0 5V 15 D74 MSB L AD9058 LEAD Dyg LSB ANALOG 2740 INB O 0 5V 1 2 A soo AD8002 15 m RZ1 RZ2 2 0000 8 PKG 4 19 21 25 27 42 Figure 10 AD8002 Driving a Dual A to D Converter 12 REV D 8002 Single Ended to Differential Driver Using AD8002 The two halves of an AD8002 can be configured to create a single ended to differential high speed driver with a 3 dB bandwidth in excess of 200 MHz as shown in Figure 11 Although the individual op amps are each current feedback the overall architecture yields a circuit with attributes normally associated with voltage feedback amplifiers while offering the speed advan tages inherent in current feedback amplifiers In addition the gain of the circuit can be changed by varying a single resistor Rp which is often not possible in a dual op amp differential driver 0 5 1 5pF OUTPUT 1
21. mall series resistance as shown in Figure 6 9090 5 Figure 6 Driving Capacitive Loads Figure 7 shows the optimum value for versus capacitive load It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll off of lt and 40 30 gt 20 10 0 0 5 10 15 20 25 pF Figure 7 Recommended vs Capacitive Load Communications Distortion is a key specification in communications applications Intermodulation distortion IMD is a measure of the ability of an amplifier to pass complex signals without the generation of spurious harmonics The third order products are usually the most problematic since several of them fall near the fundamen tals and do not lend themselves to filtering Theory predicts that the third order harmonic distortion components increase in power at three times the rate of the fundamental tones The specification of third order intercept as the virtual point where fundamental and harmonic power are equal is one standard mea sure of distortion performance Op amps used in closed loop applications do not always obey this simple theory At a gain of two the AD8002 has performance summarized in Figure 8 Here the worst third order products are plotted versus input power The third order intercept of the AD8002 is 33 dBm at 10
22. nce and inductance Surface mount resistors were used for the bulk of the characterization for this data sheet It is not recommended that leaded components be used with the AD8002 10 Printed Circuit Board Layout Considerations As expected for a wideband amplifier PC board parasitics can affect the overall closed loop performance Of concern are stray capacitances at the output and the inverting input nodes If a ground plane is to be used on the same side of the board as the signal traces a space 5 mm min should be left around the signal lines to minimize coupling Additionally signal lines connecting the feedback and gain resistors should be short enough so that their associated inductance does not cause high frequency gain errors Line lengths on the order of less than 5 mm are recommended If long runs of coaxial cable are being driven dispersion and loss must be considered Power Supply Bypassing Adequate power supply bypassing can be critical when optimiz ing the performance of a high frequency circuit Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier s response In addition if large current transients must be delivered to the load bypass capacitors typically greater than 1 will be required to provide the best settling time and lowest distortion A parallel combina tion of 4 7 and 0 1 is recommended Some brands of electrolytic capacitors will require a
23. ring all unused por tions of the component side of the board to provide a low impedance ground path The ground plane should be removed from the area near the input pins to reduce stray capacitance Inverting Configuration Chip capacitors should be used for supply bypassing see Figure Ns 13 One end should be connected to the ground plane and the cs other within 1 8 in of each power pin An additional large tanta 10pF lum electrolytic capacitor 4 7 uF 10 uF should be connected in A c2 c4 parallel but not necessarily so close to supply current for fast 0 1pF 10pF large signal changes at the output ace Ape The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a Supply Bypassing minimum Capacitance variations of less than 1 pF at the invert ing input will significantly affect high speed performance Stripline design techniques should be used for long signal traces greater than about 1 in These should be designed with a characteristic impedance of 50 or 75 and be properly termi nated at each end SEE TABLEI Noninverting Configuration Figure 13 Inverting and Noninverting Configurations Table I Recommended Component Values AD8002AN DIP AD8002AR SOIC Gain Gain Component 10 2 1 1 2 10 100 10 2 1 1 2 10 100 Rg 499 549 576 1210 750 499 1000 499 49
24. ssipation in the package See the power derating curves Specifications subject to change without notice Ape REV D ABSOLUTE MAXIMUM RATINGS Supply Voltage vue PIPER PXUDE ae 132 V Internal Power Dissipation Plastic DIP Package N 1 3 W Small Outline Package R 0 9 W uSOIC Package 0 6 W Input Voltage Common Mode tVs Differential Input Voltage 1 2V Output Short Circuit Duration M ea Rice ane A Observe Power Derating Curves Storage Temperature Range N R RM 65 C to 125 C Operating Temperature Range A Grade 40 C to 85 C Lead Temperature Range Soldering 10sec 300 C NOTES 1 1 above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device in free air 8 Lead Plastic DIP Package 90 C W 8 Lead SOIC Package 05 155 C W 8 Lead uSOIC Package 0j 200 C W AD8002 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8002 is limited by the associated rise in junction t
25. uestion is the trans conductance of the input stage This results in a low open loop input impedance at the inverting input a now familiar result Using this amplifier as a follower with gain Figure 4 basic analysis yields the following result Vo _ ox Tz 5 Vin Tz S Gx 1 1 1 500 R2 IN 8 4 Recognizing that x lt lt for low gains it can be seen to the first order that bandwidth for this amplifier is independent of gain G Considering that additional poles contribute excess phase at high frequencies there is a minimum feedback resistance below which peaking or oscillation may result This fact is used to determine the optimum feedback resistance In practice parasitic capacitance at the inverting input terminal will also add phase in the feedback loop so picking an optimum value for can be difficult Achieving and maintaining gain flatness of better than 0 1 dB at frequencies above 10 MHz requires careful consideration of several issues Choice of Feedback and Gain Resistors The fine scale gain flatness will to some extent vary with feedback resistance It therefore is recommended that once optimum resistor values have been determined 1 tolerance values should be used if it is desired to maintain flatness over a wide range of production lots In addition resistors of different construction have different associated parasitic capacita

ANALOG DEVICES AD8002 Dual 600 MHz 50 mW Current Feedback Amplifier handbook

Contents

Download Pdf Manuals

Related Search

Related Contents