ANALOG DEVICES AD8002 Dual 600 MHz 50 mW Current Feedback Amplifier handbook
Contents
1. 100 Rpr 500 Rr 7500 Rc 750 10 F ys 5 0V POWER OdBm LU 223 6mVrms 2 G 2 lt a 5 Rpr 00 N S 0 1 0 01 10k 100k 1M 10M 100M 1G FREQUENCY Hz Figure 31 Output Resistance vs Frequency 1 3dB BANDWIDTH SIDE 1 0 40 2 SIDE 2 E ta 0 1 2 is 0 1dB FLATNESS SIDE 1 ul 0 3 0 0 1 A a Vg 5V C mr E 0 2 vi 50mV SIDE 2 5 3 G 1 E 0 3 R 1000 3 Rr 5490 7 8 9 1M 10M 100M 1G FREQUENCY Hz Figure 32 3 dB Bandwidth vs Frequency G 1 50 0 52 5 PSRR 55 0 57 5 2V SPAN 60 0 CURVES ARE FOR WORST 62 5 CASE CONDITION WHERE ONE SUPPLY IS VARIED 65 0 WHILE THE OTHER IS HELD CONSTANT 67 5 70 0 PSRR 72 5 75 0 15 5 25 45 65 85 JUNCTION TEMPERATURE C 105 125 Figure 33 PSRR vs Temperature REV C AD8002 10 20 c l E 30 5 o 40 Vg 5 0V 50 SIDE 2 Ri 1000 Vin 200mV 60 90 1M 10M 100M S 30k 100k 1M 10M 100M 500M FREQUENCY Hz FREQUENCY Hz Figure 34 CMRR vs Frequency Figure 37 PSRR vs Frequency BEEN ENEEJER MIN Rg 5760 lo 5492. OUTPUT dB 1M 10M 100M 1G FREQUENCY Hz Figure 48 Differential Driver Frequency Response 13 AD8002 Layout Considerations The specified high speed performance of the AD8002 requires careful attention to board layout and component selection Proper Rg design techniques and low parasitic component selec tion are mandatory The PCB should have a ground plane covering all unused por tions of the component side of the board to provide a low im pedance ground path The ground plane should be removed from the area near the input pins to reduce stray capacitance Inverting Configuration Chip capacitors should be used for supply bypassing see Figure Vs 49 One end should be connected to the ground plane and the ci cs other within 1 8 in of each power pin An additional large 0 1pF 10pF 4 7 uF 10 uF tantalum electrolytic capacitor should be con ER Je 4 nected in parallel but not necessarily so close to supply current 0 1pF 10pF for fast large signal changes at the output EE as o The feedback resistor should be located close to the inverting A input pin in order to keep the stray capacitance at this node to a Supply Bypassing minimum Capacitance variations of less than 1 pF at the invert ing input will significantly affect high speed performance Stripline design techniques should be used for long signal trace
3. lt i o0 SIDE 1 42 D 2 ul N 0 1 5 i a E lt os SIDE 2 58 E N Z 0 3 7 2 0 4 8 5 0 5 9 1M 10M 100M 1G FREQUENCY Hz Figure 1 Frequency Response and Flatness G 2 Figure 2 1 V Step Response G 1 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 O Analog Devices Inc 1999 AD8002 SPEC FI CATI 0 NS O T 25 C Vs 5 V R 100 O Re 75 Q unless otherwise noted Model AD8002A Conditions Min Typ Max Units DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth N Package G 2 Rp 750 Q 500 MHz G 1 Rp 1 21 KQ 600 MHz R Package G 2 Rp 681 Q 500 MHz G 1 Rp 953 Q 600 MHz RM Package G 2 Rp 681 Q 500 MHz G 41 Re 1 KO 600 MHz Bandwidth for 0 1 dB Flatness N Package G 2 Bez 750 Q 60 MHz R Package G 2 R 681 Q 90 MHz RM Package G 2 Rg 681 Q 60 MHz Slew Rate G 2 Vo 2 V Step 700 Vis G 1 Vo 2V Step 1200 Vis Settling Time to 0 1 G 2 Vo 2 V Step 16 ns Rise amp Fall Time G 2 Vo 2 V Step Rp 750 Q 2 4 ns NOISE HARMONIC PERFORMANCE Total Harmonic Distortion fe 5 MHz Vo 2 V p p 65 dBc G 2 Rr 100 Q Crosstalk Output to Output f 5 MHz G 2 60 dB Input Voltage Noise f 10kHz R 00 2 0 nV VHz Input Current Noise f 10 kHz In 2 0 pA VHz In 18 pA VHz Differential Gain Error NTSC G 2
4. 70 5 a o o ul o N 0 1 su O 80 a 02 SIDE 2 68 90 o N Z 03 7 2 100 0 4 85 110 z 0 5 9 120 1M 10M 100M 1G 100k 1M 10M 100M FREQUENCY Hz FREQUENCY Hz Figure 10 Frequency Response and Flatness G 2 Figure 13 Crosstalk Output to Output vs Frequency 50 60 8 70 Ee I 2 80 tc S b 90 100 110 10k 100k 1M 10M 100M NOTES SIDE 1 Vy 0V 8mV div RTO FREQUENCY Hz SIDE 2 1V STEP RTO 400mV div Figure 11 Distortion vs Frequency G 2 R 100 Q Figure 14 Pulse Crosstalk Worst Case 1 V Step 60 0 02 2 BACK TERMINATED z 0 01 LOADS 759 70 z lt H 0 00 L A E an 7 m 80 2 1 BACK TERMINATED 002 G 2 LOAD 1500 z Rp 7500 9 go NTSC 2 BACK TERMINATED t LOADS 750 g 2 0 08 E a 100 z 0 06 L aa 1 BACK TERMINATED 110 a 0 0 LOAD 1500 lt 0 02 L 120 E 0 00 10k 100k 1M 10M 100M 1 2 3 4 5 6 7 8 9 10 1 FREQUENCY Hz IRE Figure 12 Distortion vs Frequency 2 R 1 kQ Figure 15 Differential Gain and Differential Phase per Amplifier REV C b AD8002 2 Vin 50mV G 1 1 F Rp 9530 SIDE RL 1000 0 SIDE2 1 m Ee I z 2 lt S 750 3 500 500 A 9530 5 ETIN Pu Ez 6 1M 10M 100M 1G FREQUENCY Hz Figure 16 Frequency Response G 1 40 lt c 2V p p 2ND HARMONIC DISTORTION dBc 8
5. Rc is recommended to reduce peaking and minimizes input reflections at frequencies above 300 MHz However Rc is not required 14 REV C AD8002 INVERTER DIP ANALB DEVICES INVERTER SOIG INVERTER BSOIC o o HiNI S INUERTER REV C BIP INVERTER D a RHRLOG DEUICES ANALOG GEVICES KS IRt a l INL o o END 0 ANALOG DEVICES 15 NONINVERTER DIP R e o u WOHIHUERTER DIP ANALOB DEVICES NONINVERTER B Ag SOIC c o Rt s HOHINUERYER ANALOG DEVICES NONINVERTER BSOIC Figure 50 Board Layout Silkscreen AD8002 jam NONINVERTER INVERTER wm DIP DIP INVERTER solc sl solic NONINVERTER INVERTER stem l SOIC p SOIC Figure 51 Board Layout Component Layer 16 NONINVERTER REV C AD8002 INVERTER DIP NONINVERTER DIP INVERTER NONINVERTER SOIC SOIC INVERTER BSOIC NONINVERTER BSOIC Figure 52 Board Layout Solder Side Looking Through the Board REV C 17 AD8002 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead Plastic DIP N 8 0 430 10 92 0 348 8 84 i 0 280 7 11 0 240 6 10 PIN 1 0 325 8 25 0 300 7 62 0 060 1 52 0 210 0 015 0 38 0 195 4 95 inv 0 115 2 93 0 130 0 160 4 06 3 30 0 115 2 93 MIN he 0 015 0 381 0 022 0 558 0 070 1 77 SEATING 0 008 0 204 0 014 0 356 0 045 1 15 P
6. Rr 150 Q 0 01 Differential Phase Error NTSC G 2 Rr 150 Q 0 02 Degree Third Order Intercept f 10 MHz 33 dBm 1 dB Gain Compression f 10 MHz 14 dBm SFDR f 5 MHz 66 dB DC PERFORMANCE Input Offset Voltage 2 0 6 mV Offset Drift 10 uV c Input Bias Current 5 0 25 TUA Tmn Tmax 35 TUA Input Bias Current 3 0 6 0 tA Tun Tmax 10 TUA Open Loop Transresistance Vo 2 5 V 250 900 kQ Tmn Tmax 175 KO INPUT CHARACTERISTICS Input Resistance Input 10 MQ Input 50 Q Input Capacitance tInput 1 5 pF Input Common Mode Voltage Range 3 2 V Common Mode Rejection Ratio Offset Voltage Vom 2 5 V 49 54 dB Input Current Vem 2 5 V Tum T Max 0 3 1 0 uA V Input Current Vom 2 5 V Tum T Max 0 2 0 9 HA V OUTPUT CHARACTERISTICS Output Voltage Swing Rr 150Q 2 7 3 1 V Output Current2 70 mA Short Circuit Current2 85 110 mA POWER SUPPLY Operating Range 3 0 6 0 V Quiescent Current Both Amplifiers Tun Tmax 10 0 11 5 mA Power Supplv Rejection Ratio Vs 4 V to 6 V Vs 5 V 60 75 dB Vs 4 V to 6 V Vs 5 V 49 56 dB Input Current Tu T Max 0 5 2 5 HA V tInput Current Tmn Tmax 0 1 0 5 HA V NOTES IRc is recommended to reduce peaking and minimize input reflections at frequencies above 300 MHz However Rcis not required Output current is limited by the maximum power dissipation in the package See the power derating curves Specifications subject to change without notice 292 REV C ABSOLUTE MAXIMUM RATIN
7. not cause high frequency gain errors Line lengths on the order of less than 5 mm are recommended If long runs of coaxial cable are being driven dispersion and loss must be considered Power Supply Bypassing Adequate power supply bypassing can be critical when optimiz ing the performance of a high frequency circuit Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier s response In addition if large current transients must be delivered to the load then bypass capacitors typically greater than 1 uF will be required to provide the best settling time and lowest distortion A parallel combination of 4 7 uF and 0 1 uF is recommended Some brands of electrolytic capacitors will require a small series damping resistor 4 7 Q for optimum results DC Errors and Noise There are three major noise and offset terms to consider in a current feedback amplifier For offset errors refer to the equa tion below For noise error the terms are root sum squared to give a net output error In the circuit below Figure 41 they are input offset Vio which appears at the output multiplied by the noise gain of the circuit 1 Rg Rj noninverting input current Ign x Ry also multiplied by the noise gain and the inverting input current which when divided between R and Ry and sub sequently multiplied by the noise gain always appears at the output as Ign x Rr The input voltage noise of the AD8002 is a lo
8. 0 3RD HARMON IC 100 10k Figure 17 Distortion vs Frequency G 1 R 100 Q 40 100k 1M FREQUENCY 10M Hz 100M 2ND HARMONIC 3RD HAR MONIC DISTORTION dBc 100 10 10k Figure 18 Distortion vs Frequency G 1 R 1 kQ 100k 1M FREQUENCY 10M Hz 100M 6 3 0 gt sa i 1 6 4 D d a 9 S E z SE 15 18 21 1M 10M 100M 500M FREQUENCY Hz Figure 19 Large Signal Frequency Response G 2 INPUT OUTPUT LEVEL dBV 27 1M 10M 100M 500M FREQUENCY Hz Figure 20 Large Signal Frequency Response G 1 GAIN dB 1M 10M 100M 1G FREQUENCY Hz Figure 21 Frequency Response G 10 G 100 REV C AD8002 G 2 2V STEP Rf 7500 OUTPUT SWING Volts 2 5 55 35 15 5 25 45 65 85 105 125 JUNCTION TEMPERATURE C Figure 23 Output Swing vs Temperature INPUT BIAS CURRENT pA 55 35 15 5 25 45 65 85 105 1
9. 0 Rc 500 Hati O EN 5760 5490 EN EUH qm vum FE REISER NS anes I spes W L MJ ages T IT 1 po n OTT TL Re 0n Tt mak Pawl E L ss Figure 36 100 mV Step Response G 1 Figure 39 100 mV Step Response G REV C _9_ AD8002 THEORY OF OPERATION A very simple analysis can put the operation of the AD8002 a current feedback amplifier in familiar terms Being a current feedback amplifier the AD8002 s open loop behavior is ex pressed as transimpedance AVo AI in or Tz The open loop transimpedance behaves just as the open loop voltage gain of a voltage feedback amplifier that is it has a large dc value and decreases at roughly 6 dB octave in frequency Since the Ry is proportional to 1 gm the equivalent voltage gain is just Tz x gy where the gy in question is the trans conductance of the input stage This results in a low open loop input impedance at the inverting input a now familiar result Using this amplifier as a follower with gain Figure 40 basic analysis yields the following result T S T T S Gx Ry RI Rin 1 gm 50 Q Figure 40 Recognizing that G x Rin lt lt RI for low gains it can be seen to the first order that bandwidth for this amplifier is independent of gain G Considering that additional poles contribute excess phase at high frequencies there is a minimum feedback resistance below which peaking or oscillation may result This fact is used to determine the optim
10. 25 JUNCTION TEMPERATURE C Figure 24 Input Bias Current vs Temperature REV C IT ROR 0 EN DIV E da Figure 25 Long Term Settling Time INPUT OFFSET VOLTAGE mV 2 55 35 15 5 25 45 65 85 105 125 JUNCTION TEMPERATURE C Figure 26 Input Offset Voltage vs Temperature 11 5 10 0 TOTAL SUPPLY CURRENT mA 55 35 15 5 25 45 65 85 105 125 JUNCTION TEMPERATURE C Figure 27 Total Supply Current vs Temperature AD8002 120 105 100 95 90 85 80 75 70 55 35 15 5 25 4 65 85 105 125 q o SHORT CIRCUIT CURRENT mA JUNCTION TEMPERATURE C Figure 28 Short Circuit Current vs Temperature 100 100 N INVERTING CURRENT Vs 5V E l ul o 10 10 9 u NONINVERTING CURRENT Vs 5V z VOLTAGE NOISE Vs 5V 1 1 10 100 1k 10k 100k FREQUENCY Hz Figure 29 Noise vs Frequency CMRR dB 15 5 25 45 65 85 JUNCTION TEMPERATURE C Figure 30 CMRR vs Temperature NOISE CURRENT pA Hz PSRR dB
11. B band width in excess of 200 MHz as shown in Figure 47 Although the individual op amps are each current feedback the overall architecture yields a circuit with attributes normally associated with voltage feedback amplifiers while offering the speed advan tages inherent in current feedback amplifiers In addition the gain of the circuit can be changed by varying a single resistor Rg which is often not possible in a dual op amp differential driver Cc 0 5 1 5pF o OUTPUT 1 o OUTPUT 2 p OP AMP 2 AD8002 Figure 47 Differential Line Driver The current feedback nature of the op amps in addition to enabling the wide bandwidth provides an output drive of more than 3 V p p into a 20 Q load for each output at 20 MHz On the other hand the voltage feedback nature provides symmetri cal high impedance inputs and allows the use of reactive compo nents in the feedback network The circuit consists of the two op amps each configured as a unity gain follower by the 511 Q Ra feedback resistors between each op amp s output and inverting input The output of each op amp has a 511 Q Rg resistor to the inverting input of the other op amp Thus each output drives the other op amp through a unity gain inverter configuration By connecting the two amplifiers as cross coupled inverters their outputs are freed to be equal and opposite assuring zero output common mode voltage With this circuit configuration the common mo
12. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in device failure While the AD8002 is internally short circuit protected this may not be sufficient to guarantee that the maximum junction temperature 150 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves 2 0 PLASTIC DIP PACKAGE o 8 LEAD SOIC PACKAGE l 1 15 lt a N eo B 10 e n z 2 05 gt lt 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE C Figure 3 Plot of Maximum Power Dissipation vs Temperature ORDERING GUIDE Model Temperature Range Package Description Package Option Brand Code AD8002AN 40 C to 85 C 8 Lead PDIP N 8 Standard AD8002AR 40 C to 85 C 8 Lead SOIC SO 8 Standard AD8002AR REEL 40 C to 85 C 8 Lead SOIC 13 REEL SO 8 Standard AD8002AR REEL7 40 C to 85 C 8 Lead SOIC 7 REEL SO 8 Standard AD8002ARM 40 C to 85 C 8 Lead uSOIC RM 8 HFA AD8002ARM REEL 40 C to 85 C 8 Lead uSOIC 13 REEL RM 8 HFA AD8002ARM REEL7 40 C to 85 C 8 Lead uSOIC 7 REEL RM 8 HFA CAUTION ESD electrostatic discharge sensitive device Electrostatic charges a
13. GS Supply Volfage ees bee ee ee ates eats 12 6V Internal Power Dissipation Plastic DIP Package N 1 3 W Small Outline Package R 0 9 W uSOIC Package RM 0 6 W Input Voltage Common Mode tVs Differential Input Voltage 1 2V Output Short Circuit Duration Ena canada isa EE Observe Power Derating Curves Storage Temperature Range N R RM 65 C to 125 C Operating Temperature Range A Grade 40 C to 85 C Lead Temperature Range Soldering 10 sec 300 C NOTES IStresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device in free air 8 Lead Plastic DIP Package 64 90 C W 8 Lead SOIC Package Du 155 C W 8 Lead uSOIC Package 614 200 C W AD8002 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8002 is limited by the associated rise in junction tempera ture The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition tem perature of the plastic approximately 150 C
14. LANE 8 Lead SOIC SO 8 0 1968 5 00 pa 890 a k 8 5 0 1574 4 00 0 2440 6 20 0 1497 3 80 i 4 0 2284 5 80 i Je Ge Moss SCH 0 0196 0 50 BSC gt 0 0089 0 25 9 0 0688 1 75 0 0098 0 25 v 0 0532 1 35 0 0040 0 10 4 el ee 8 la SEATING 0 0192 0 49 0 0098 0 25 O 9 0500 1 27 DANE 0 0138 0 35 0 0075 0 19 0 0160 0 41 8 Lead pSOIC RM 8 0 122 3 10 m SE 0 122 3 10 0 114 2 90 gu PIN 1 0 199 5 05 0 187 4 75 0 0256 0 65 BSC 0 120 3 05 0 120 3 05 E exa T 0 006 0 15 Y 1095 0 56 043 1 09 0 002 kiwi E SEATING PLAN 0 008 0 20 0 037 0 94 Y Es Le 0 011 0 28 2 0 028 0 71 0 003 0 08 0 016 0 41 0 018 0 46 18 REV C C2004b 0 7 99 PRINTED IN U S A
15. U 0 AD8004 OO ANALOG DEVICES Dual 600 MHz 50 mW Current Feedback Amplifier AD8002 FEATURES Excellent Video Specifications R 150 O G 2 Gain Flatness 0 1 dB to 60 MHz 0 01 Differential Gain Error 0 02 Differential Phase Error Low Power 5 5 mA Amp Max Power Supply Current 55 mW High Speed and Fast Settling 600 MHz 3 dB Bandwidth G 1 500 MHz 3 dB Bandwidth G 2 1200 V ps Slew Rate 16 ns Settling Time to 0 1 Low Distortion 65 dBc THD fc 5 MHz 33 dBm 3rd Order Intercept F 10 MHz 66 dB SFDR f 5 MHz 60 dB Crosstalk f 5 MHz High Output Drive Over 70 mA Output Current Drives Up to Eight Back Terminated 75 O Loads Four Loads Side While Maintaining Good Differential Gain Phase Performance 0 01 0 17 Available in 8 Lead Plastic DIP SOIC and pSOIC Packages APPLICATIONS A to D Driver Video Line Driver Differential Line Driver Professional Cameras Video Switchers Special Effects RF Receivers PRODUCT DESCRIPTION The AD8002 is a dual low power high speed amplifier de signed to operate on 5 V supplies The AD8002 features unique transimpedance linearization circuitry This allows it to drive video loads with excellent differential gain and phase per formance on only 50 mW of power per amplifier The AD8002 is a current feedback amplifier and features gain flatness of 0 1 dB to 60 MHz while offering differential gain and phase error of 0 01 and 0 02 This makes the AD8002 id
16. ch individual op amp in its noninverting configuration The resulting architecture offers several advantages First the gain can be changed by changing a single resistor Changing either Rp or Rg will change the gain as in an inverting op amp circuit For most types of differential circuits more than one resistor must be changed to change gain and still maintain good CMR Reactive elements can be used in the feedback network This is in contrast to current feedback amplifiers that restrict the use of reactive elements in the feedback The circuit described requires about 0 9 pF of capacitance in shunt across Ry in order to opti mize peaking and realize a 3 dB bandwidth of more than 200 MHz The peaking exhibited by the circuit is very sensitive to the value of this capacitor Parasitics in the board layout on the order of tenths of picofarads will influence the frequency response and the value required for the feedback capacitor so a good layout is essential The shunt capacitor type selection is also critical A good micro wave type chip capacitor with high Q was found to yield best performance The part selected for this circuit was a muRata Erie part no MA280R9B The distortion was measured at 20 MHz with a 3 V p p input and a 100 Q load on each output For Output 1 the distortion is 37 dBc and A1 dBc for the second and third harmonics respectively For Output 2 the second harmonic is 35 dBc and the third harmonic is 43 dBc
17. cts are usually the most problematic since several of them fall near the fundamen tals and do not lend themselves to filtering Theory predicts that the third order harmonic distortion components increase in power at three times the rate of the fundamental tones The specification of third order intercept as the virtual point where fundamental and harmonic power are equal is one standard measure of distortion performance Op amps used in closed loop applications do not always obey this simple theory At a gain of two the AD8002 has performance summarized in Fig ure 44 Here the worst third order products are plotted vs input power The third order intercept of the AD8002 is 33 dBm at 10 MHz REV C THIRD ORDER IMD dBc 8 7 6 5 4 3 2 10 1 2 3 4 5 6 INPUT POWER dBm Figure 44 Third Order IMD F 10 MHz F 12 MHz Operation as a Video Line Driver The AD8002 has been designed to offer outstanding perfor mance as a video line driver The important specifications of differential gain 0 0196 and differential phase 0 02 meet the most exacting HDTV demands for driving one video load with each amplifier The AD8002 also drives four back terminated loads two each as shown in Figure 45 with equally impressive performance 0 0196 0 07 Another important consideration is isolation between loads in a multiple load application The AD8002 has more than 40 dB of isolat
18. de signal of the outputs is reduced If one output moves slightly higher the negative input to the other op amp drives its output to go slightly lower and thus preserves the symmetry of the comple mentary outputs which reduces the common mode signal The common mode output signal was measured to be 50 dB at 1 MHz Looking at this configuration overall there are two high imped ance inputs the inputs of each op amp two low impedance outputs and high open loop gain If we consider the two nonin verting inputs and just the output of Op Amp 2 the structure looks like a voltage feedback op amp having two symmetrical high impedance inputs and one output The input to Op Amp 2 is the noninverting input it has the same polarity as Output 2 and the input to Amplifier 1 is the inverting input oppo site polarity of Output 2 REV C With a feedback resistor Re an input resistor Rg and grounding of the input of Op Amp 2 a feedback amplifier is formed This configuration is just like a voltage feedback amplifier in an inverting configuration if only Output 2 is considered The addition of Output 1 makes the amplifier differential output The differential gain of this circuit is The Rg Rg term is the gain of the overall op amp configuration and is the same as for an inverting op amp except for the polar ity If Output 1 is used as the output reference then the gain is positive The 1 Ra Rg term is the noise gain of ea
19. eal for professional video electronics such as cameras and video switchers Addition ally the AD8002 s low distortion and fast settling make it ideal for buffer high speed A to D converters The AD8002 offers low power of 5 5 mA amplifier max Vs 5 V and can run on a single 12 V power supply while ca pable of delivering over 70 mA of load current It is offered in an 8 lead plastic DIP SOIC and uSOIC package These features make this amplifier ideal for portable and battery powered appli cations where size and power is critical REV C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM 8 Lead Plastic DIP SOIC and SOIC The outstanding bandwidth of 600 MHz along with 1200 V us of slew rate make the AD8002 useful in many general purpose high speed applications where dual power supplies of up to 6 V and single supplies from 6 V to 12 V are needed The AD8002 is available in the industrial temperature range of 40 C to 85 C spe 14440 8 G 2 al BE m RL 1000 SIDE 2 2 d Vin 50mV 20 o o u Z 01 3 gt
20. ion at 5 MHz when driv ing two 75 Q back terminated loads 1 2 AD8002 Figure 45 Video Line Driver 11 AD8002 Driving A to D Converters ADC Using the AD9058 s internal 2 V reference connected The AD8002 is well suited for driving high speed analog to to both ADCs as shown in Figure 46 reduces the number of digital converters such as the AD9058 The AD9058 is a dual external components required to create a complete data 8 bit 50 MSPS ADC In the circuit below the AD8002 is shown acquisition system The 20 Q resistors in series with ADC in driving the inputs of the AD9058 which are configured for O V puts are used to help the AD8002s drive the 10 pF ADC input to 2 V ranges Bipolar input signals are buffered amplified capacitance The AD8002 only adds 100 mW to the power 2x and offset by 1 0 V into the proper input range of the consumption while not limiting the performance of the circuit T OpF ENCODE A ENCODE B VREFA BI ANALOG aid INA O 2740 0 5V AINA E e VINT E a 15 0 1pF VREFA I E VREF B D74 MSB AD9058 J LEAD Dog LSB ANALOG 2740 INB O 0 5V ANB COMP RZ1 RZ2 2 0000 SIP 8 PKG 25 27 42 Figure 46 AD8002 Driving a Dual A to D Converter 12 REV C AD8002 Single Ended to Differential Driver Using an AD8002 The two halves of an AD8002 can be configured to create a single ended to differential high speed driver with a 3 d
21. s greater than about 1 in These should be designed with a characteristic impedance of 50 Q or 75 Q and be properly termi nated at each end SEE TABLE Noninverting Configuration Figure 49 Inverting and Noninverting Configurations Table I Recommended Component Values AD8002AN DIP AD8002AR SOIC Gain Gain Component 10 2 1 1 2 10 100 10 2 1 1 2 10 100 Re O 499 549 576 1210 750 499 1000 499 499 549 953 681 499 1000 Rg Q 49 9 274 576 750 54 9 10 49 9 249 549 681 54 9 10 Ber Nominal Q 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 Re Q 75 75 lo 0 75 75 lo 0 Rs Q 49 9 49 9 49 9 49 9 49 9 49 9 Ry Nominal Q 61 9 54 9 49 9 49 9 49 9 49 9 61 9 54 9 49 9 49 9 49 9 49 9 Small Signal BW MHz 270 380 410 600 500 170 17 250 410 410 600 500 170 17 0 1 dB Flatness MHz 45 80 130 35 60 24 3 50 100 100 35 90 24 3 AD8002ARM pSOIC Gain Component 10 2 1 1 2 10 100 Rg Q 499 499 590 1000 681 499 1000 Rg Q 49 9 249 590 681 54 9 10 Rpr Nominal 2 49 9 49 9 49 9 49 9 49 9 49 9 49 9 Rc Q 75 75 l0 0 R Q 49 9 49 9 49 9 R4 Nominal Q 61 9 49 9 49 9 49 9 49 9 49 9 Small Signal BW MHz 270 400 410 600 450 170 19 0 1 dB Flatness MHz 60 100 100 35 70 35 3
22. s high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8002 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality LN ESD SENSITIVE DEVICE REV C AD8002 RL 1000 V O TRT 250ps 5V Figure 4 Test Circuit Gain 1 nu Figure 6 1 V Step Response G 1 Vin O RL 1000 PULSE GENERATOR V TR T 250ps I RRRES Figure 8 100 mV Step Response G 2 EN M HER C SGE HRS RIS KIS B paka NN RN NEN SCOT NN 9962 Ku C ae Figure 9 1 V Step Response G 2 REV C AD8002 1 20 m Vin 4dBV IDE 1 0 v 30 gt Fi 1000 OUTPUT SIDE 1 G 2 ul Vs 5 0V m RL 1000 SIDE 2 19 nd m Vin 50mV Rf 7500 28 50 o ul D ul CG Ki Z o 3 L 00 OUTPUT SIDE 2 a o d o SIDE 1 A
23. um feedback resistance Rg In practice parasitic capacitance at the inverting input terminal will also add phase in the feedback loop so picking an optimum value for Rg can be difficult Achieving and maintaining gain flatness of better than 0 1 dB at frequencies above 10 MHz requires careful consideration of several issues Choice of Feedback and Gain Resistors The fine scale gain flatness will to some extent vary with feed back resistance It therefore is recommended that once opti mum resistor values have been determined 1 tolerance values should be used if it is desired to maintain flatness over a wide range of production lots In addition resistors of different con struction have different associated parasitic capacitance and inductance Surface mount resistors were used for the bulk of the characterization for this data sheet It is not recommended that leaded components be used with the AD8002 10 Printed Circuit Board Layout Considerations As to be expected for a wideband amplifier PC board parasitics can affect the overall closed loop performance Of concern are stray capacitances at the output and the inverting input nodes If a ground plane is to be used on the same side of the board as the signal traces a space 5 mm min should be left around the signal lines to minimize coupling Additionally signal lines connecting the feedback and gain resistors should be short enough so that their associated inductance does
24. w 2 nV VHz At low gains though the inverting input current noise times Rg is the dominant noise source Careful layout and device matching contribute to better offset and drift specifica tions for the AD8002 compared to many other current feedback amplifiers The typical performance curves in conjunction with the equations below can be used to predict the performance of the AD8002 in any application R Rp Vour Vio x 1 E Igy X Ry x 1 E Ig x Rr Figure 41 Output Offset Voltage REV C AD8002 Driving Capacitive Loads The AD8002 was designed primarily to drive nonreactive loads If driving loads with a capacitive component is desired best frequency response is obtained by the addition of a small series resistance as shown in Figure 42 The accompanying graph 9090 RsERIES Figure 42 Driving Capacitive Loads shows the optimum value for Raps vs capacitive load It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll off of Rsenies and Cr 40 30 a l H 20 U e e 10 0 iI 0 5 10 15 20 25 CL pF Figure 43 Recommended Rsepies vs Capacitive Load Communications Distortion is a key specification in communications applications Intermodulation distortion IMD is a measure of the ability of an amplifier to pass complex signals without the generation of spurious harmonics The third order produ
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ANALOG DEVICES AD8002 Dual 600 MHz 50 mW Current Feedback Amplifier handbook