ANALOG DEVICES AD8001 800 MHz 50 mW Current Feedback Amplifier handbook
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1. 5962 9459301 ANALOG DEVICES 800 MHz 50 mW Current Feedback Amplifier AD8001 FEATURES Excellent Video Specifications 150 2 Gain Flatness 0 1 dB to 100 MHz 0 01 Differential Gain Error 0 025 Differential Phase Error Low Power 5 5 mA Max Power Supply Current 55 mW High Speed and Fast Settling 880 MHz 3 dB Bandwidth 6 1 440 MHz 3 dB Bandwidth G 2 1200 V s Slew Rate 10 ns Settling Time to 0 1 Low Distortion 65 dBc THD f 5 MHz 33 dBm 3rd Order Intercept 10 MHz 66 dB SFDR f 5 MHz High Output Drive 70 mA Output Current Drives Up to Four Back Terminated Loads 75 O Each While Maintaining Good Differential Gain Phase Performance 0 05 0 25 APPLICATIONS A to D Driver Video Line Driver Professional Cameras Video Switchers Special Effects RF Receivers PRODUCT DESCRIPTION The AD8001 is a low power high speed amplifier designed to operate on 5 V supplies The AD8001 features unique GAIN dB 12 10M 100M 1G FREQUENCY Hz Figure 1 Frequency Response of AD8001 REV C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise2. AD8001 Evaluation Board ordering information please refer to the Ordering Guide The An evaluation board for the AD8001 is available that has been layout of the evaluation board can be used as shown or serve as carefully laid out and tested to demonstrate that the specified a guide for a board layout high speed performance of the device can be realized For n E E n n 50 HONINUERTER 6 5009 T Figure 52 Evaluation Board Layout Figure 50 Evaluation Board Figure 51 Evaluation Board Layout Component Side Silkscreen Top Solder Side REV C 15 AD8001 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead Plastic DIP 8 Lead Cerdip N 8 Q 8 0 430 10 92 0 005 0 13 0 055 1 4 0 348 8 84 F 0 280 7 11 0 240 6 10 0 310 7 87 PINT 0 220 5 59 dicic 0 325 8 25 254 0 300 7 62 0 100 2 54 BSC 0 060 1 52 0 320 8 13 T Um 0 405 10 29 MAX 0 320 8 13 0 210 0 015 0 38 0 195 4 95 esie 0 290 7 37 5 33 0 115 2 93 0 060 1 52 MAX RAR 0 130 0 200 5 08 0 015 0 38 0 160 4 06 3 30 MAX 0 115 2 93 SATZ E 035503331 OON E MIN 0 200 5 0 59 0 022 0 558 0 070 1 77 SEATING 0 008 0 204 0 125 MIN R Tonn 0 014 0 356 0 045 1 15 SEATING 7
3. 0 015 0 38 0 356 1 15 0 023 0 58 0 070 1 78 PLANE 15 0 008 0 20 0 014 0 36 0 030 0 76 0 8 Lead Plastic SOIC 5 Lead Plastic Surface Mount SOT 23 SO 8 RT 5 0 1968 5 00 0 1181 300 am 0 1102 2 80 8 5 0 157444 00 0 2440 6 20 0 0669 1 70 0 1181 3 00 0 1497 3 80 410 2284 5 80 0 0590 1 50 0 1024 2 60 A a 0 0500 1 27 0 0196 0 50 pint 7 BSC 0 0099 0 25 lt 45 0 0374 0 95 BSC 0 0688 1 75 0 0748 1 90 0 0098 0 25 y 0 0532 1 35 _ BSC 0 0040 0 10 Barba s 0 0079 0 20 seating 0 0192 0 49 0 0098 0 25 0 0 0512 1 30 0 0571 1 45 0 0031 0 08 PLANE 0 0138 0 35 0 0075 019 0 0160 0 41 0 0354 0 90 y 0 0374 0 95 gt 10 0 0059 0 15 0 0197 0 50 SEATING 0 0 0217 0 55 4maa am PLANE tated 0 0019 0 05 0 0138 0 35 0 0138 0 35 16 REV 1886 0 12 99 PRINTED IN U S A
4. ANALOG 3240 1 3kQ 6490 08001 T ANALOG 3240 821 822 2 0000 SIP 8 PKG VREF A VnEF B 4 19 21 25 27 42 to both ADCs as shown in Figure 48 reduces the number of external components required to create a complete data acquisition system The 20 0 resistors in series with ADC in puts are used to help the AD8001s drive the 10 pF ADC input capacitance The AD8001 only adds 100 mW to the power consumption while not limiting the performance of the circuit ENCODE B VREF A Vs VREF B AD9058 J LEAD Doa LSB 74ACT 273 74ACT 273 CLOCK Figure 48 AD8001 Driving a Dual A to D Converter REV C AD8001 Layout Considerations The specified high speed performance of the AD8001 requires careful attention to board layout and component selection Proper Rg design techniques and low parasitic component selec tion are mandatory The PCB should have a ground plane covering all unused por tions of the component side of the board to provide a low im pedance ground path The ground plane should be removed from the area near the input pins to reduce stray capacitance Chip capacitors should be used for supply bypassing see Figure 49 One end should be connected to the ground plane and the other within 1 8 inch of each power pin An additional large 4 7 10 tantalum electrolytic capacitor should be con nected in p
5. temperature 150 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves 2 0 Ty 150 C o 8 LEAD 215 8 LEAD PLASTIC DIP PACKAGE 1 5 SOIC PACKAGE lt eo eo 81 0 gt 0 5 5 LEAD SOT 23 5 PACKAGE 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE Figure 3 Plot of Maximum Power Dissipation vs Temperature ORDERING GUIDE Temperature Package Package Brand Model Range Description Option Code AD8001AN 40 C to 85 8 Lead Plastic DIP N 8 AD8001AQ 55 C to 125 C 8 Lead Cerdip Q 8 AD8001AR 40 to 85 8 Lead SOIC SO 8 AD8001AR REEL 40 to 85 13 Tape and REEL SO 8 AD8001AR REEL7 40 to 85 7 Tape and REEL SO 8 AD8001ART REEL 40 to 85 C 13 Tape and REEL RT 5 HEA AD8001ART REEL7 40 to 85 C 7 Tape and REEL RT 5 HEA AD8001ACHIPS 40 to 85 C Die Form 5962 9459301MPA 55 C to 125 C 8 Lead Cerdip Q 8 AD8001R EB 2 SOIC Evaluation Board G 2 NOTES Standard Military Drawing Device Refer to Evaluation Board section CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD8001 features prop
6. result This fact is used to determine the optimum feedback resistance In practice parasitic capacitance at Pin 2 will also add phase in the feedback loop so picking an optimum value can be difficult Fig ure 42 illustrates this problem Here the fine scale 0 1 dB div flatness is plotted vs feedback resistance These plots were taken using an evaluation card which is available to customers so that these results may readily be duplicated see Evaluation Board section 10 Achieving maintaining gain flatness of better than 0 1 dB at frequencies above 10 MHz requires careful consideration of several issues 1M 100k 10k Tz 0 1k 100 10 100k 1M 10M 100M 1G FREQUENCY Hz Figure 41 Transimpedance vs Frequency 6980 7500 OUTPUT dB 0 9 1M 10M 100M FREQUENCY Hz Figure 42 0 1 dB Flatness vs Frequency Choice of Feedback and Gain Resistors Because of the above mentioned relationship between the band width and feedback resistor the fine scale gain flatness will to some extent vary with feedback resistance It therefore is recommended that once optimum resistor values have been determined 1 tolerance values should be used if it is desired to maintain flatness over a wide range of production lots In a
7. 0 E 5 50 o o 40 30 20 10 3 INPUT OFFSET VOLTAGE mV Figure 39 Input Offset Voltage Distribution PERCENT AD8001 THEORY OF OPERATION very simple analysis can put the operation of the AD8001 a current feedback amplifier in familiar terms Being a current feedback amplifier the AD8001 s open loop behavior is ex pressed as transimpedance AVo AI m or Tz The open loop transimpedance behaves just as the open loop voltage gain of a voltage feedback amplifier that is it has a large dc value and decreases at roughly 6 dB octave in frequency Since the Ry is proportional to 1 gy the equivalent voltage gain is just Tz X gy where the gy in question is the trans conductance of the input stage This results in a low open loop input impedance at the inverting input a now familiar result Using this amplifier as a follower with gain Figure 40 basic analysis yields the following result T S VN 5 Gx Ry Rl 6 15 Rw 500 Recognizing that G x lt lt RI low gains it can be seen to the first order that bandwidth for this amplifier is independent of gain G This simple analysis in conjunction with Figure 41 can in fact predict the behavior of the AD8001 over a wide range of conditions Figure 40 Considering that additional poles contribute excess phase at high frequencies there is a minimum feedback resistance below which peaking or oscillation may
8. 00 n 800 2 1000 I 600 5 z dis Vs 5V 2 Rep 4 400 6 R PACKAGE 200 9 12 0 10M 100M 16 500 600 700 800 900 1000 FREQUENCY Hz VALUE OF FEEDBACK RESISTOR Figure 10 Frequency Response 2 Figure 13 3 dB Bandwidth vs Rp 0 1 50 5V SUPPLIES Rr 6980 0 1 60 Vout 2V 1000 0 2 1 L pere 2 m 5 0 3 70 2 5 E 2 2 04 p rz 1000 2ND HARMONIC Vin 50mV a 05 80 0 6 g 3RD HARMONIC tc 0 7 o0 0 8 0 9 100 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY Hz FREQUENCY Hz Figure 11 0 1 dB Flatness Package for Package Add Figure 14 Distortion vs Frequency 1000 50 Q to Rp 50 8 0 08 2 5V SUPPLIES P 0 06 Vout 2V 60 S od 2 BACK TERMINATED 8 aus LOADS 750 1 0 02 70 2 2ND HARMONIC 0 00 amp 0 5 1 BACK TERMINATED 80 LOAD 1500 a o 0 02 z 59 90 D _ 1 AND 2 BACK TERMIN 0 01 LOADS 1500 AND 7 E 5 0 00 100 0 01 110 0 02 10k 100k 1M 10M 100M 0 RE 100 FREQUENCY Hz Figure 12 Distortion vs Frequency R 1 kQ Figure 15 Differential Gain and Differential Phase REV C 5 AD8001 Vin 26dB
9. 10 4700 Figure 22 Frequency Response 10 100 1M 10M 100M FREQUENCY Hz 1G 3 35 3 25 3 15 2 ore 1500 o 305 Vg 5V 295 5 2 85 Vour a 2 75 500 Vs 5V 2 65 2 55 60 40 20 0 20 40 60 80 Figure 23 Output Swing vs Temperature JUNCTION TEMPERATURE C 100 1 EN INPUT BIAS CURRENT pA 1 20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE 140 Figure 24 Input Bias Current vs Temperature REV C AD8001 2 0 DEVICE 1 1 6 DEVICE 2 gt E N INPUT OFFSET VOLTAGE mV e DEVICE 3 60 40 20 0 20 40 60 80 100 Figure 25 Input Offset vs Temperature 5 8 5 6 5 4 5 2 5 0 SUPPLY CURRENT mA 4 8 4 6 4 4 60 40 20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE C Figure 26 Supply Current vs Temperature SINK Isc SHORT CIRCUIT CURRENT mA 85 60 40 20 0 20 40 60 80 100 JUNC
10. 9 1M 10M 100M 1G FREQUENCY Hz Figure 32 3 dB Bandwiath vs Frequency 1 52 5 55 0 SPSR 57 5 60 0 3V SPAN m 62 5 CURVES ARE WORST 65 0 CASE CONDITION WHERE o ONE SUPPLY IS VARIED WHILE THE OTHER IS nop HELD CONSTANT 725 PSRR 75 0 77 5 60 0 50 2 4 60 80 100 JUNCTION TEMPERATURE C Figure 33 PSRR vs Temperature REV C CMRR dB 40 10M 100M 1G FREQUENCY Hz Figure 34 CMRR vs Frequency OUTPUT dB 10M 100M 1G FREQUENCY Hz Figure 35 3 dB Bandwidth vs Frequency G 2 Figure 36 100 mV Step Response 6 1 REV C AD8001 30 20 CURVES ARE FOR WORST CASE CONDITION WHERE 10 ONE SUPPLY IS VARIED WHILE THE OTHER IS 0 HELD CONSTANT ta 9 10 tc 20 PSRR a 30 PSRR PSRR 40 Rf 9090 G 2 50 60 1M 10M 100M 1G FREQUENCY Hz Figure 37 PSRR vs Frequency 100 90 H 3 WAFER LOTS COUNT 895 MEAN 1 37 STD DEV 1 13 70 MIN 2 45 MAX 4 69 6
11. TION TEMPERATURE Figure 27 Short Circuit Current vs Temperature AD8001 Tz TRANSRESISTANCE 0 60 40 Tz 20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE C Figure 28 Transresistance vs Temperature NVERTING CURRENT Vs NOISE VOLTAGE nV VHz 10 100 1k 10k 100k FREQUENCY Hz Figure 29 Noise vs Frequency 48 49 CMRR 50 51 ta 2 CMRR 52 53 2 5V SPAN 54 55 56 60 20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE Figure 30 CMRR vs Temperature 100 NOISE CURRENT pA VHz 1k 100 e 10 1 5 1 H H 0 1 G 2 Re 9090 H 0 01 10k 100k 1M 10M 100M FREQUENCY Hz Figure 31 Output Resistance vs Frequency 5760 0 E 6490 2 83 ae Rr 7500 5 4 1000 Vin 50mV 2 5 5 6 7 8
12. arallel but not necessarily so close to supply current for fast large signal changes at the output The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum Capacitance variations of less than 1 pF at the invert ing input will significantly affect high speed performance Stripline design techniques should be used for long signal traces greater than about 1 in These should be designed with a characteristic impedance of 50 Q or 75 Q and be properly termi nated at each end Inverting Configuration Supply Bypassing Noninverting Configuration Figure 49 Inverting and Noninverting Configurations for Evaluation Boards Table I Recommended Component Values AD8001AN DIP AD8001AR SOIC AD8001ART SOT 23 5 Gain Gain Gain Component 1 1 2 10 100 1 2 10 100 1 1 2 10 100 Rg 649 1050 750 470 1000 604 953 681 470 1000 845 1000 768 470 1000 0 649 750 51 10 604 681 51 10 845 768 51 10 Nominal 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 49 9 0 0 0 0 Rr Nominal 54 9 49 9 49 9 49 9 49 9 54 9 49 9 49 9 49 9 49 9 54 9 49 9 49 9 49 9 49 9 Small Signal 340 880 460 260 20 370 710 440 260 20 240 795 380 260 20 BW MHz 0 1 dB Flatness 105 70 105 130 100 120 110 300 145 14
13. ddition resistors of different construction have different associ ated parasitic capacitance and inductance Surface mount resis tors were used for the bulk of the characterization for this data sheet It is not recommended that leaded components be used with the AD8001 REV C AD8001 Printed Circuit Board Layout Considerations As to be expected for a wideband amplifier PC board parasitics can affect the overall closed loop performance Of concern are stray capacitances at the output and the inverting input nodes If a ground plane is to be used on the same side of the board as the signal traces a space 5 mm min should be left around the signal lines to minimize coupling Additionally signal lines connecting the feedback and gain resistors should be short enough so that their associated inductance does not cause high frequency gain errors Line lengths on the order of less than 5 mm are recommended If long runs of coaxial cable are being driven dispersion and loss must be considered Power Supply Bypassing Adequate power supply bypassing can be critical when optimiz ing the performance of a high frequency circuit Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier s response In addition if large current transients must be delivered to the load then bypass capacitors typically greater than 1 will be required to provide the best settling time and lowest distortion A para
14. ed vs input power The third order intercept of the AD8001 is 33 dBm at 10 MHz THIRD ORDER IMD dBc 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 INPUT POWER Figure 46 Third Order 10 MHz Fz 12 MHz 12 Operation a Video Line Driver The AD8001 has been designed to offer outstanding perfor mance as a video line driver The important specifications of differential gain 0 01 and differential phase 0 025 meet the most exacting demands for driving one video load The AD8001 also drives up to two back terminated loads as shown in Figure 47 with equally impressive performance 0 0196 0 07 Another important consideration is isolation between loads in a multiple load application The AD8001 has more than 40 dB of isolation at 5 MHz when driving two 75 Q back terminated loads Vs 0 001 Figure 47 Video Line Driver REV C AD8001 Driving A to D Converters The AD8001 is well suited for driving high speed analog to digital converters such as the AD9058 The AD9058 is a dual 8 bit 50 MSPS ADC In the circuit below the AD8001 is shown driving the inputs of the AD9058 which are configured for 0 V to 2 V ranges Bipolar input signals are buffered amplified 2 and offset by 1 0 V into the proper input range of the ADC Using the AD9058 s internal 2 V reference connected ENCODE O 6490 AD8001 5
15. ide Web Site http www analog com Fax 781 326 8703 O Analog Devices Inc 1999 10800 SPEC ONS Q T 25 C Vs 5 V 100 unless otherwise noted Model 08001 Conditions Min Typ Max Units DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth N Package 2 lt 0 1 dB Peaking Rp 750 Q 350 440 MHz 1 lt 1 dB Peaking Rp 1 650 880 MHz R Package 2 lt 0 1 dB Peaking Rz 681 Q 350 440 MHz 1 lt 0 1 dB Peaking Rp 845 Q 515 715 MHz RT Package 2 lt 0 1 dB Peaking Rp 768 Q 300 380 MHz 1 lt 0 1 dB Peaking Rp 1 575 795 MHz Bandwidth for 0 1 dB Flatness N Package 2 750 Q 85 110 MHz R Package 2 Rg 6810 100 125 MHz RT Package 2 Rg 768 Q 120 145 MHz Slew Rate 2 Vo 2 V Step 800 1000 V us G 1 Vo 2 V Step 960 1200 V us Settling Time to 0 1 G 1 Vo 2 V Step 10 ns Rise and Fall Time 2 Vo 2 V Step Rp 649 Q 1 4 ns NOISE HARMONIC PERFORMANCE Total Harmonic Distortion fo 5 MHz Vo 2 V p p 65 2 1009 Input Voltage Noise f 10 kHz 2 0 nV AHz Input Current Noise 10 kHz In 2 0 pA VHz In 18 pA VHz Differential Gain Error NTSC G 2 Rp 1500 0 01 0 025 Differential Phase Error NTSC 2 1500 0 025 0 04 Degree Third Order Intercept f 10 MHz 33 dBm 1 dB Gain Compression f 10 MHz 14 dBm SFDR f 5 MHz 66 DC PERFORMANCE In
16. ing Curves Storage Temperature Range 65 C to 125 Operating Temperature Range A Grade 40 to 85 Lead Temperature Range Soldering 10 sec 300 C NOTES IStresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Specification is for device in free air 8 Lead Plastic DIP Package 64 90 C W 8 Lead SOIC Package 155 C W 8 Lead Cerdip Package 110 C W 5 Lead SOT 23 5 Package 260 C W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8001 is limited by the associated rise in junction tempera ture The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition tem perature of the plastic approximately 150 C Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in device failure While the AD8001 is internally short circuit protected this may not be sufficient to guarantee that the maximum junction
17. llel combination of 4 7 uF and 0 1 F is recommended Some brands of electrolytic capacitors will require a small series damping resistor 4 7 for optimum results DC Errors and Noise There are three major noise and offset terms to consider in a current feedback amplifier For offset errors refer to the equa tion below For noise error the terms are root sum squared to give a net output error In the circuit below Figure 43 they are input offset Vio which appears at the output multiplied by the noise gain of the circuit 1 noninverting input current Ry also multiplied by the noise gain and the inverting input current which when divided between and and sub sequently multiplied by the noise gain always appears at the output as The input voltage noise of the AD8001 is a low 2 nV VHz At low gains though the inverting input current noise times Rg is the dominant noise source Careful layout and device matching contribute to better offset and drift specifica tions for the AD8001 compared to many other current feedback amplifiers The typical performance curves in conjunction with the equations below can be used to predict the performance of the AD8001 in any application R R Vour Vio xl i tdg X Ry x 14 Ip Figure 43 Output Offset Voltage REV C Driving Capacitive Loads The AD8001 was designed primarily to drive nonreactive loads If driving loads with a capacitive c
18. m m 9090 1 o 100M 1G 3G FREQUENCY Hz Figure 16 Frequency Response 1 1 0 Rr 6490 1 E 9530 1 5 4 G 1 gt 5 1000 Vin 50mV 6 7 9 2M 10M 100M 1G FREQUENCY Hz Figure 17 Flatness Package 1 for N Package Add 100 Q to Re 40 1 50 Vout 2V 60 m 2 70 2ND HARMONIC E t 80 o a 90 3RD HARMONIC 100 110 100k 1M 10M 100M FREQUENCY Hz Figure 18 Distortion vs Frequency 1 1000 N PACKAGE 900 N I 1 800 PACKAGE lt 4 700 8 Vin 50mV f 1000 600 1 500 600 700 800 900 1000 60 VALUE OF FEEDBACK RESISTOR Rp 2 Figure 19 3 dB Bandwidth vs Hg G 1 1000 G 1 Vout 2V 1100 70 DISTORTION dBc 80 100 1M FREQUENCY Hz 10M 100M Figure 20 Distortion vs Frequency R 100 Q OUTPUT dBV 10M FREQUENCY Hz 100M Figure 21 Large Signal Frequency Response 1 REV C Rr 10000
19. omponent is desired best frequency response is obtained by the addition of a small series resistance as shown in Figure 44 The accompanying graph shows the optimum value for Rsgrs vs capacitive load It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll off of RSERIES and 9090 RSERIES Figure 44 Driving Capacitive Loads 40 30 1 820 e 10 0 0 5 10 15 20 25 pF Figure 45 Recommended vs Capacitive Load 11 AD8001 Communications Distortion is a key specification in communications applications Intermodulation distortion IMD is a measure of the ability of an amplifier to pass complex signals without the generation of spurious harmonics The third order products are usually the most problematic since several of them fall near the fundamen tals and do not lend themselves to filtering Theory predicts that the third order harmonic distortion components increase in power at three times the rate of the fundamental tones The specification of third order intercept as the virtual point where fundamental and harmonic power are equal is one standard measure of distortion performance Op amps used in closed loop applications do not always obey this simple theory At a gain of two the AD8001 has performance summarized in Fig ure 46 Here the worst third order products are plott
20. put Offset Voltage 2 0 5 5 mV Offset Drift 10 Input Bias Current 5 0 25 T Max 35 Input Bias Current 3 0 6 0 10 Open Loop Transresistance Vo 2 5 250 900 INPUT CHARACTERISTICS Input Resistance Input 10 MQ Input 50 Q Input Capacitance Input 1 5 pF Input Common Mode Voltage Range 3 2 Common Mode Rejection Ratio Offset Voltage Vom 2 5 V 50 54 dB Input Current Vom 2 5 V Tum T Max 0 3 1 0 Input Current Vom 2 5 Tum 0 2 0 7 OUTPUT CHARACTERISTICS Output Voltage Swing 1500 2 7 3 1 Output Current 37 50 50 70 mA Short Circuit Current 85 110 mA POWER SUPPLY Operating Range t3 0 t6 0 V Quiescent Current T Max 5 0 5 5 mA Power Supply Rejection Ratio V 4 to 6 V Vs 5 V 60 75 dB Vs 4V to 6 V Vs 5 V 50 56 dB Input Current T Max 0 5 2 5 Input Current Tu T Max 0 1 0 5 Specifications subject to change without notice REV C AD8001 ABSOLUTE MAXIMUM RATINGS Supply Voltage ue ib te Geese Gee 12 6V Internal Power Dissipation Plastic DIP Package N 1 3 Small Outline Package R 0 9 W SOT 23 5 Package RT 0 5 W Input Voltage Common Mode tVs Differential Input Voltage 1 2 Output Short Circuit Duration etur Observe Power Derat
21. rietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING ESD SENSITIVE DEVICE REV 3 AD8001 8060 0 001 CSA 404 COMM SIGNAL ANALYZER 1000 HP8133A ULSE GENERATOR TR Tr 50ps Figure 4 Test Circuit Gain 2 RES 81 Figure 6 2 Step Response 6 1 Figure 7 2 V Step Response 2 9090 0 001 OUT TEKTRONIX CSA 404 COMM SIGNAL ANALYZER VNO R 1000 LeCROY 9210 oQ 0 001 pF GENERATOR 350ps Figure 8 Test Circuit Gain 1 Figure 9 100 mV Step Response 6 1 REV C AD8001 9 1000 Vg 5V 6 Rfg 82
22. under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAMS 8 Lead DIP N 8 Q 8 5 Lead and SOIC SO 8 SOT 23 5 08001 transimpedance linearization circuitry This allows it to drive video loads with excellent differential gain and phase perfor mance on only 50 mW of power The AD8001 is a current feedback amplifier and features gain flatness of 0 1 dB to 100 MHz while offering differential gain and phase error of 0 01 and 0 025 This makes the AD8001 ideal for professional video electronics such as cameras and video switchers Additionally the AD8001 s low distortion and fast settling make it ideal for buffer high speed A to D converters The AD8001 offers low power of 5 5 mA max Vs 5 V and can run on a single 12 V power supply while being capable of delivering over 70 mA of load current These features make this amplifier ideal for portable and battery powered applications where size and power are critical The outstanding bandwidth of 800 MHz along with 1200 V us of slew rate make the AD8001 useful in many general purpose high speed applications where dual power supplies of up to 6 V and single supplies from 6 V to 12 V are needed The AD8001 is available in the industrial temperature range of 40 C to 85 C Figure 2 Transient Response of AD8001 2 V Step 2 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World W
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ANALOG DEVICES AD8001 800 MHz 50 mW Current Feedback Amplifier handbook