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MOTOROLA MC68HC912DG128 Technical Data

1. 1 2 128 M clock Prescaler 16 bit Freerunning 16 bit load register main timer 21 48 16 Mclock 9 Prescaler pe moais 0 RESET 4 r Comparator PTO lt Pinlogic 4 fe c ccc cc cc Y Delay counter EDGO p gt TCO capture compare register __ PACO y 2 FCOH hold register PAOH hold register z 0 RESET Comparator PT1 4 Pinlogic mmn tee6cc0c002 Y gt Delay counter EDGi p gt TC1 capture compare register L PAC1 i e C1H hold register PA1H hold register l 0 RESET lt q r Comparator PT2 4 d9 Pinlogic mm fz Y Delay counter EDG2 p gt TC2 capture compare register l PAC2 Y y m C2H hold register PA2H hold register 2 Qiu RESET 7 lt q Comparator PT3 4 Pinlogic mmr paassa crc ce Y Delay counter EDGS p gt TC3 capture compare register l PAC3 r y E C3H hold register PA3H hold register E Da Comparator PT4 _ Pin logic EDGA 1 CC re LATQ BUFEN p gt 1C4 capture compare register queue mode MUX EDG0 r Lg Read TC3H PA Comparator hold register PT5 lt
2. ITSTO Interrupt Test Register 0 0018 Bit 7 6 5 4 3 2 1 Bit 0 ITE6 ITE8 ITEA ITEC ITEE ITFO ITF2 ITF4 RESET 0 0 0 0 0 0 0 0 ITST1 Interrupt Test Register 1 0019 Bit 7 6 5 4 3 2 1 Bit 0 ITD6 ITD8 ITDA ITDC ITDE ITEO ITE2 ITE4 RESET 0 0 0 0 0 0 0 0 ITST2 Interrupt Test Register 2 001A Bit 7 6 5 4 3 2 1 Bit 0 ITC6 ITC8 ITCA ITCC ITCE ITDO ITD2 ITD4 RESET 0 0 0 0 0 0 0 0 ITST3 Interrupt Test Register 3 001B Bit 7 6 5 4 3 2 1 Bit 0 ITB6 ITB8 ITBA ITBC ITBE ITCO ITC2 ITC4 RESET 0 0 0 0 0 0 0 0 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA For More Information On This Product Resets and Interrupts Go to www freescale com 139 Freescale Semiconductor Inc Resets and Interrupts 9 7 Resets 9 7 1 Power On Reset 9 7 2 External Reset Technical Data There are four possible sources of reset Power on reset POR and external reset on the RESET pin share the normal reset vector The computer operating properly COP reset and the clock monitor reset each has a vector Entry into reset is asynchronous and does not require a clock but the MCU cannot sequence out of reset without a system clock A positive transition on Vpp causes a power on reset POR An external voltage level detector or other external reset circuits are the usual source of reset in a system The POR circ
3. 8g e 9 zo PNE X lt 6 55828 Peace 2222 99 EET TT egizg9ta99goQgomumm t5uoououuo 5 uUiEa DC 0 0 0 0 tC r cC r 0o 0 0 0 n0 0 0 0 0 0 0 0 25 SELSSSSSB8SSNSSSSSSSSSRESSSESR PW2 PP2 TE I Toto mme oa crum 84 PAD17 AN17 PW1 PP1 12 O 83 PAD07 AN07 PWO PPO C 3 82 PAD16 AN16 IOCO PTO L 4 81 PADOG ANOG IOC1 PT1 15 80 PAD15 AN15 IOC2 PT2 16 79 1 PADOS ANOS IOC3 PT3 L7 78 PAD14 AN14 KWJ7 PJ7 L8 77 PADO4 ANO4 KWJ6 PJ6 9 76 PAD13 AN13 KWJ5 PJ5 L 10 75 PADO3 ANO3 KWJ4 PJ4 E 11 74 PAD12 AN12 Vpp C412 73 PADO2 ANO2 PK3 13 72 PAD11 AN11 Vss 14 MC68HC912DG128 71 PADO1 ANO1 IOCA PTA J 15 112TQFP 70 PAD10 AN10 IOC5 PT5 1 16 69 PADOO ANOO IOCG PT6 17 68 1 Vaio IOC7 PT7 J 18 67 Vang KWJ3 PJ3 L 19 66 Vss KWJ2 PJ2 20 65 Vpp KWJ1 PJ1 L 21 64 PA7 ADDR15 DATA15 DATA7 KWJO PJO C 22 63 PA6 ADDR14 DATA14 DATAG SMODN TAGHI BKGD C7 23 62 1 PAB ADDR13 DATA13 DATAS ADDRO DATAO PBO C 24 61 PA4 ADDR12 DATA12 DATA4 ADDR1 DATA1 PB1 25 60 PA3 ADDR11 DATA11 DATA3 ADDR2 DATA2 PB2 C 26 59 PA2 ADDR10 DATA10 DATA2 ADDR3 DATA3 PB3 C 27 58 PA1 ADDR9 DATAQ DATA1 ADDR4 DATA4 PB4 128 o noto Onoon Noro onoo o a o wo oL PAADDRS DATA DATAO CN C CO CO co co C50 CO sb sb b E cb c cB CM CE SE O01 LO 0 40 0 40 0 d amp a amp mrfreiiuuuu om rzssi urszszrir riuiuiit Bees oo eo eer b gt eS Wee
4. PORTJ Port J Register 0028 Bit 7 6 5 4 3 2 1 Bit 0 PORT PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJO KWU KWJ7 KWJ6 KWJ5 KWJ4 KWJ3 KWJ2 KWJ1 KWJO RESET Read and write anytime Bit 7 6 5 4 3 2 1 Bit 0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PHO KWU KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWHO RESET PORTH Port H Register 0029 Read and write anytime Bit 7 6 5 4 3 2 1 Bit 0 DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJO RESET 0 0 0 0 0 0 0 0 DDRJ Port J Data Direction Register 002A Data direction register J is associated with port J and designates each pin as an input or output Read and write anytime DDRJ 7 0 Data Direction Port J 0 Associated pin is an input 1 Associated pin is an output Technical Data MC68HC912DG128 Rev 3 0 148 I O Ports with Key Wake up MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc I O Ports with Key Wake up Key Wake up and Port Registers Bit 7 6 5 4 3 2 1 Bit 0 DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDHO RESET 0 0 0 0 0 0 0 0 DDRH Port H Data Direction Register 002B Data direction register H is associated with port H and designates each pin as an input or output Read and write anytime DDRH 7 0 Data Direction Port H 0 Associated pin is an input 1 Associated pin is an output
5. Bit 7 6 5 4 3 2 1 Bit 0 Name PK7 0 0 0 PK3 PK2 PK1 PKO PORTK DDK7 0 0 0 DDK3 DDK2 DDK1 DDKO DDRK 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 PIX2 PIX1 PIXO PPAGE 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES COMCRO 0 0 0 0 0 LOOPB WUPM CLKSRC COMCR 1 SJW1 SJWO BRP5 BRP4 BRP3 BRP2 BRP1 BRPO COBTRO SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 COBTR1 WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF CORFLG WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE CORIER 0 ABTAK2 ABTAK1 ABTAKO 0 TXE2 TXE1 TXEO COTFLG 0 ABTRQ2 ABTRQ ABTRQO 0 TXEIE2 TXEIE1 TXEIEO COTCR 0 0 IDAM1 IDAMO 0 IDHIT2 IDHIT1 IDHITO COIDAC Unimplemented Reserved RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERRO CORXERR TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERRO COTXERR AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO COIDARO AC7 AC6 AC5 ACA AC3 AC2 AC1 ACO COIDAR1 AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO COIDAR2 AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO COIDAR3 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO COIDMRO AM7 AM6 AM5 AM4 AMS3 AM2 AM1 AMO COIDMR1 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO COIDMR2 AM7 AM6 AM5 AM4 AMS3 AM2 AM1 AMO COIDMR3 AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO COIDAR4 AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO COIDAR5 AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO COIDAR6 AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO COIDAR7 AM7 AM6 AM5 AM4 AMS3 AM2 AM1 AMO COI
6. Bit 7 6 5 4 3 2 1 Bit 0 Name AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO C1IDAR7 AM7 AM6 AM5 AMA AM3 AM2 AM1 AMO C1IDMR4 AM7 AM6 AM5 AMA AM3 AM2 AM1 AMO C1IDMR5 AM7 AM6 AM5 AMA AM3 AM2 AM1 AMO C1IDMR6 AM7 AM6 AM5 AMA AM3 AM2 AM1 AMO C1IDMR7 Unimplemented 4 Reserved 0 0 0 0 0 0 PUPCAN RDPCAN PCTLCAN1 PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 TxCAN RxCAN PORTCAN1 DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 0 0 DDRCAN 1 FOREGROUND RECEIVE BUFFER 1 RxFG1 TRANSMIT BUFFER 10 Tx10 TRANSMIT BUFFER 11 Tx11 TRANSMIT BUFFER 12 Tx12 Unimplemented Reserved px 1 Port A port B and data direction registers DDRA DDRB are not in map in expanded and peripheral modes Reserved or unimplemented bits Table 4 1 Register Map Sheet 10 of 10 3 Registers also not in map in peripheral mode 4 Data read at these locations is undefined 5 Port K and DDRK not in the map in peripheral and expanded modes with EMK set Technical Data MC68HC912DG128 Rev 3 0 73 Registers For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Technical Data MC68HC912DG128 Rev 3 0 74 Registers MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC912DG128 5 1 Contents 5 2 Introduction Section 5 Operating Modes BE MENU serrer e
7. flag Bit 7 6 5 4 3 2 1 Bit 0 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 RESET 0 0 0 0 0 0 0 0 ATDOTESTH ATD1TESTH ATD Test Register Bit 7 6 5 4 3 2 1 Bit 0 SAR1 SARO RST TSTOUT TST3 TST2 TST1 TSTO RESET 0 0 0 0 0 0 0 0 ATDOTESTL ATD1TESTL ATD Test Register 0069 01E9 The test registers control various special modes which are used during manufacturing The test register can be read or written only in the special modes In the normal modes reads of the test register return zero and writes have no effect SAR 9 0 SAR Data Reads of this byte return the current value in the SAR Writes to this byte change the SAR to the value written Bits SAR 9 0 reflect the ten SAR bits used during the resolution process for a 10 bit result MC68HC912DG128 Rev 3 0 Technical Data Analog to Digital Converter 307 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Analog to Digital Converter RST Module Reset Bit When set this bit causes all registers and activity in the module to assume the same state as out of power on reset except for ADPU bit in ATDCTL2 which remains set allowing the ATD module to remain enabled TSTOUT Multiplex Output of TST 3 0 Factory Use TST 3 0 Test Bits 3 to 0 Reserved Selects one of 16 reserved factory testing modes Bit 7 6 5 4 3 2 1 Bit 0 PADx7 PADx6 PADx5 PA
8. KWIEJ Key Wake up Port J Interrupt Enable Register 002C Bit 7 6 5 4 3 2 1 Bit 0 KWIEJ7 KWIEJ6 KWIEJ5 KWIEJ4 KWIEJ3 KWIEJ2 KWIEJ1 KWIEJO RESET 0 0 0 0 0 0 0 0 Read and write anytime KWIEJ 7 0 Key Wake up Port J Interrupt Enables 0 Interrupt for the associated bit is disabled 1 Interrupt for the associated bit is enabled Bit 7 6 5 4 3 2 1 Bit 0 KWIEH7 KWIEH6 KWIEH5 KWIEH4 KWIEH3 KWIEH2 KWIEH1 KWIEHO RESET 0 0 0 0 0 0 0 0 KWIEH Key Wake up Port H Interrupt Enable Register 002D Read and write anytime KWIEH 7 0 Key Wake up Port H Interrupt Enables MC68HC912DG128 Rev 3 0 0 Interrupt for the associated bit is disabled 1 Interrupt for the associated bit is enabled Technical Data MOTOROLA I O Ports with Key Wake up For More Information On This Product Go to www freescale com 149 Freescale Semiconductor Inc I O Ports with Key Wake up KWIFJ Key Wake up Port J Flag Register 002bE Bit 7 6 5 4 3 2 1 Bit 0 KWIFJ7 KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJO RESET 0 0 0 0 0 0 0 0 Read and write anytime Each flag is set by an active edge on its associated input pin This could be a rising or falling edge based on the state of the KWPu register To clear the flag write one to the corresponding bit in KWIFJ Initialize this register after initializing KWPJ so that illegal flags ca
9. 0000 REGISTERS gogrp MAPPABLE TO ANY 2K SPACE 0000 0400 0800 2K bytes EEPROM gorer MAPPABLE TO ANY 4K SPACE 0800 1000 2000 2000 8K bytes RAM garrr MAPPABLE TO ANY 8K SPACE 4000 s000 16K Fixed Flash EEPROM 16K Page Window 8000 8000 Eight 16K Flash EEPROM pages A000 BFFF Protected BOOT BFFF at odd programing pages s CO00 16K Fixed Flash EEPROM FFFF E000 FFFF Protected BOOT L FF00 BDM EEE LD it acti NORMAL EXPANDED SPECIAL SINGLE CHIP SINGLE CHIP Figure 5 1 Memory Map after reset The following diagram illustrates the memory paging scheme MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Operating Modes 93 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes 0000 0400 0800 1000 2000 4000 16K Flash Unpaged PS One 16K Page accessible at a time selected by PPAGE value 0 to 7 K s8000 00 Flash 32K 01 Flash 32K 10Flash32K N 11 Flash 32K Nn ZR mum anda 1 3 6 7 16K Flash l Paged mE mE mE i 8K Boot 8K Boot 8K Boot 8K Boot C000 d This 32K Flash 16K Flash accessible as E000 Unpaged pages 6 amp 7 and as unpaged 4000 7FFF amp SEEFF VECTORS C000 FFFF NORMAL SINGLE CHIP Figure 5 2 Memory Paging Technical Data MC68HC912DG128 Rev 3 0 94 Operating Modes MOTOROLA For More information On This Product Go to
10. Data Movement IPIPE 1 0 Captured at Rising Edge of E Clock IPIPE 1 0 Mnemonic Meaning 0 0 No Movement 0 1 LAT Latch Data From Bus 1 0 ALD Advance Queue and Load From Bus 1 1 ALL Advance Queue and Load From Latch Execution Start IPIPE 1 0 Captured at Falling Edge of E Clock IPIPE 1 0 Mnemonic Meaning 0 0 No Start 0 1 INT Start Interrupt Sequence 1 0 SEV Start Even Instruction 1 1 SOD Start Odd Instruction 1 Refers to data that was on the bus at the previous E falling edge 2 Refers to bus cycle starting at this E falling edge Program information is fetched a few cycles before it is used by the CPU In order to monitor cycle by cycle CPU activity it is necessary to externally reconstruct what is happening in the instruction queue Internally the MCU only needs to buffer the data from program fetches For system debug it is necessary to keep the data and its associated address in the reconstructed instruction queue The raw signals required for reconstruction of the queue are ADDR DATA R W ECLK and status signals IPIPE 1 0 The instruction queue consists of two 16 bit queue stages and a holding latch on the input of the first stage To advance the queue means to move the word in the first stage to the second stage and move the word from either the holding latch or the data bus input buffer into the first stage To start even or odd instruction means to execute the opcod
11. bytes Bit 7 6 5 4 3 2 1 Bit 0 RESET 0 0 0 0 0 0 0 0 ATDOCTLO ATD1CTLO Reserved 0060 01E0 Writes to this register will abort current conversion sequence READ any time WRITE any time Bit 7 6 5 4 3 2 1 Bit 0 RESET 0 0 ATDOCTL1 ATD1CTL1 Reserved 0061 01E1 WRITE Write to this register has no meaning READ Special Mode only MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Analog to Digital Converter 299 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter Bit 7 6 5 4 3 2 1 Bit 0 ADPU AFFC AWAI 0 0 0 ASCIE ASCIF RESET 0 0 0 0 0 0 0 0 ATDOCTL2 ATD1CTL2 ATD Control Register 2 0062 01E2 The ATD control register 2 and 3 are used to select the power up mode interrupt control and freeze control Writes to these registers abort any Current conversion sequence Read or write anytime except ASCIF bit which cannot be written Bit positions ATDCTL2 4 2 and ATDCTL3 7 2 are unused and always read as zeros ADPU ATD Disable 0 Disables the ATD including the analog section for reduction in power consumption 1 Allows the ATD to function normally Software can disable the clock signal to the A D converter and power down the analog circuits to reduce power consumption When reset to zero the ADPU bit aborts any conversion sequenc
12. Bit 7 6 5 4 3 2 1 Bit 0 0 Bit 6 5 4 3 2 1 Bit 0 RESET 0 0 0 0 0 0 0 0 PWPRES PWM Prescale Counter 0043 PWPRES is a free running 7 bit counter Read anytime Write only in special mode SMOD 1 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 RESET 0 0 0 0 0 0 0 0 PWSCALO PWM Scale Register 0 0044 MC68HC912DG128 Rev 3 0 Read and write anytime A write will cause the scaler counter PWSCNTO to load the PWSCALO value unless in special mode with DISCAL 1 in the PWTST register PWM channels 0 and 1 can select clock SO scaled as its input clock by setting the control bit PCLKO and PCLK1 respectively Clock SO is generated by dividing clock A by the value in the PWSCALO register 1 and dividing again by two When PWSCALO FF clock A is divided by 256 then divided by two to generate clock SO Technical Data MOTOROLA Pulse Width Modulator 199 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pulse Width Modulator Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 RESET 0 0 0 0 0 0 0 0 PWSCNTO PWM Scale Counter 0 Value 0045 PWSONTO is a down counter that upon reaching 00 loads the value of PWSCALO Read any time Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 RESET 0 0 0 0 0 0 0 0 PWSCAL1 PWM Scale Register 1 0046 Read and write anytime A write will cause
13. MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Appendix CGM Practical Aspects For More Information On This Product Go to www freescale com 413 Freescale Semiconductor Inc Appendix CGM Practical Aspects Table 20 2 Suggested 8MHz Synthesis PLL Filter Elements Acquisition Mode ME SYNR ME Co nF Ro kO Cp nF Bandwidth E IE 0 614 0C 7 98 1000 0 43 100 1 2 157 0 614 0C 7 98 47 2 4 7 5 5 157 0 614 0C 7 98 10 4 3 1 0 12 157 0 614 0C 7 98 3 3 7 5 0 33 21 157 0 8 09 8 00 2200 0 27 220 0 9 201 0 8 09 8 00 100 1 2 10 4 4 201 0 8 09 8 00 22 2 4 2 2 9 3 201 0 8 09 8 00 4 7 5 6 0 47 20 1 201 1 07 8 00 2200 0 22 220 1 251 1 07 8 00 100 1 0 10 4 8 251 1 07 8 00 2 2 2 2 2 10 4 251 1 07 8 00 4 7 4 7 0 47 22 5 251 1 6 05 8 00 3300 0 15 330 1 1 402 1 6 05 8 00 100 0 82 10 6 2 402 1 6 05 8 00 33 1 5 3 3 10 7 402 1 6 05 8 00 10 2 7 1 0 19 5 402 2 03 8 00 4700 0 1 470 1 502 2 03 8 00 220 0 51 22 4 6 502 2 03 8 00 47 1 0 4 7 10 502 2 03 8 00 10 2 4 1 0 21 8 502 2 66 02 8 00 2200 0 12 220 1 7 668 2 66 02 8 00 220 0 43 22 5 3 668 2 66 02 8 00 47 1 0 4 7 11 6 668 2 66 02 8 00 10 2 1 0 25 1 668 4 01 8 00 2200 0 1 220 2 1 1005 4 01 8 00 330 0 27 33 5 4 1005 4 01 8 00 100 0 51 10 9 7 1005 4 01 8 00 22 1 0 2 2 20 8 1005 Technical Data MC68HC912DG128 Rev 3 0 414 Appendix CG
14. 0012 Bit 7 6 5 4 3 2 1 Bit 0 EE15 EE14 EE13 EE12 0 0 0 EEON 0 0 0 0 0 0 0 1 Technical Data EE 15 12 Internal EEPROM map position These bits specify the upper four bits of the 16 bit EEPROM address Normal modes write once special modes write anytime Read anytime EEON internal EEPROM On Enabled This bit is forced to one in single chip modes Read or write anytime 0 Removes the EEPROM from the map 1 Places the on chip EEPROM in the memory map at the address selected by EE 15 12 MC68HC912DG128 Rev 3 0 84 Operating Modes For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Operating Modes Internal Resource Mapping 5 5 4 Flash EEPROM mapping through internal Memory Expansion The Page Index register or PPAGE provides memory management for the MC68HC912DG128 PPAGE consists of three bits to indicate which physical location is active within the windows of the MC68HC912DG128 The MC68HC912DG128 has a user s program space window a register space window for Flash module registers and a test program space window The user s program page window consists of 16K Flash EEPROM bytes One of eight pages is viewed through this window for a total of 128K accessible Flash EEPROM bytes On the MC68HC912DG128 the register space window consists of a 4 byte register block One of four pages is viewed through this window for each of the
15. 152 Section 11 Clock Functions mE o 22 ce ecco eet a TERES UR Aree abantnseecdws 155 TLZ NG adc seterasei nispet deme cheese iA 155 11 3 Clock Sources eoe audor BA RR RR RAS 156 11 4 Phase Locked Loop PLL 2 sasaaactaumle e ERI LERGR 157 11 5 Acquisition and Tracking Modes illsssss 159 11 6 Limp Home and Fast STOP Recovery modes 161 11 7 System Clock Frequency formulas llus 179 The Clock Divider Chains iruosiiskewnssgebepbiceser th us 180 11 9 Computer Operating Properly COP 184 11 10 Real Time Interrupt oso ci cece debis besrco E e bemad 184 11 11 Glock Monitor oeceaeesee RR Rm mS 184 11 12 Glock Function Registers 220c2c cceasex ts ur URaR 185 Section 12 Pulse Width Modulator 123 COMM uus end ue E La ED Rod wd ER anager 191 12 2 JIBntrodicliole a ssuencekmRscumESGAS RA ERES EE ER Ra 191 MC68HC912DG128 Rev 3 0 10 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 12 3 12 4 13 1 13 2 13 3 13 4 13 5 14 1 14 2 14 8 14 4 14 5 14 6 15 1 15 2 15 3 15 4 15 5 15 6 15 7 MC68HC912DG128 Rev 3 0 Table of Contents PWM Register Description v d d do RR RR CR eo dedi 195 PWM Boundary Cases ci 6 deve deen ERO EORR RR Rene ad 206 Section 13 Enhanced Capture Timer gon MT Pp erpPITC PP 207 iln m 207 En
16. NOTE SDBUG12is a P amp E Micro Product It can be obtained from P amp E from their web site http www pemicro com for approximately 100 Third party tools http www mcu motsps com dev tools 3rd index htm MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA General Description 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 1 5 MC68HC912DG128 Block Diagram VFP 128K byte flash EEPROM velar 8K byte RAM 2K byte EEPROM CPU12 VRHO VRH1 VRH1 ATDO vRLO ATD1 vRL1 VRL1 VDDA VDDA VDDA VSSA VSSA PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PORT ADO Single wire Periodic interrupt l WI even background COP watchdog debug module Clock monitor Enhanced Breakpoints capture XFC Clock timer VDDPLL PLL Generation VSSPLL module EXTAL XTAL RESET SDI MISO SDO MOSI PEO XIRQ Lite PEt IRQ integration PE2 RW _ module PE3 LSTRB LIM PE4 ECLK PE5 MODA PE6 MODB PE7 VDD x2 P X O LO xt CO QN CO T Q 10 s CO QU 7 O EErzrraxit daaa dda VSS we ost lreLE TOo DEG ZEGEE ErmrrcrccT Ooaoaaaoaao Power for internal circuitry aqgqqgqaag 22229998 29200000 TITILL pir Sr a ch ate ete a oe VDDXx2 NN OFNT A Wide SEEZKELS CLLALAES VSSXx2 bus EEEEEEPEE geegaacae Ia EINA aAdaaoagag oooaoaaaao eee een Power for I O drivers
17. Time segment 1 TSEG1 and time segment 2 TSEG2 are programmable as shown in Table 17 7 Table 17 7 Time segment values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 TSEG22 TSEG21 TSEG20 Time segment 2 0 0 0 0 1 Tq clock cycle 0 0 0 1 Tq clock cycle 0 0 0 1 2 Tq clock cycles 0 0 1 2 Tq clock cycles 0 0 1 0 3 Tq clock cycles 0 0 1 1 4 Tq clock cycles j 1 1 1 8 Tq clock cycles 1 1 1 1 16 Tq clock cycles 1 In this case PHASE SEG1 must be at least two time quanta Technical Data MC68HC912DG128 Rev 3 0 342 MSCAN Controller MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MSCAN Controller Programmer s Model of Control Registers The bit time is determined by the oscillator frequency the baud rate prescaler and the number of time quanta Tq clock cycles per bit as shown above Presc value CGMCANCLK NOTE The CBTR1 register can only be written if the SFTRES bit in CMCRO is set BitTime enumber of TimeQuanta 17 13 6 msCAN12 Receiver Flag Register CRFLG All bits of this register are read and clear only A flag can be cleared by writing a 1 to the corresponding bit position A flag can only be cleared when the condition which caused the setting is no more valid Writing a 0 has no effect on the flag setting Every flag has an associated interrupt enable flag in the CRIER registe
18. REGISTER TMSK2 pi PR2 PR1 PRO MCEN R Prescaled MCLK 4 Oxx REGISTER MCCTL BITS MCPR1 MCPRO 0 0 MODULUS e X 3 e DOWN 4 0 1 COUNTER 29 1 0 REGISTER PACTL BITS PAEN CLK1 CLKO 1 1 1 1 0 1 1 1 0 PULSE ACC PACLK 256 e LOW BYTE 1 411 PACLK 65536 pi PAOV Technical Data PACLK GATE 1 LOGIC PAMOD PULSE ACC HIGH BYTE Figure 11 8 Clock Chain for ECT MC68HC912DG128 Rev 3 0 182 Clock Functions For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Clock Functions Clock Divider Chains PCLK 5 BIT MODULUS TO ATDO COUNTER PRO PR4 2 and ATD1 2 REGISTER SPOBR Ene SPR1 SPRO SPI BS BIT RATE 2 0 0 1 x MSCAN E 3 SYSCLK 2 0 1 1 EZ ECLK 2 1 0 0 w4 E3 CLKSW BDM BIT CLOCK 2 1 0 1 BCLK ZS e Receive Detect falling edge BKGD IN count 12 ECLKs Sample input 2 1 1 0 SYNCHRONIZER Transmit 1 Detect falling edge E3 4 count 6 ECLKs while output is 29 1 1 1 high impedance Drive out 1 E n E cycle pulse high high imped BKGD DIRECTION 200 output again Transmit 0 Detect falling edge Drive out low count 9
19. 389 19 6 Analog Converter Characteristics Operating 390 19 7 ATD AC Characteristics Operating 391 19 8 ATD Maximum PFIaUDDS auae ak d ERR kan 391 19 9 EEPROM Characteristics a sanwasuueke Rar n ERR RR Ru 392 18 10 Flash EEPROM Characteristics auaa e eee 392 19 11 Pulse Width Modulator Characteristics 394 19 12 Control TINY uiuis daa e p an ded doa ete e die 395 19 13 Peripheral Port TMG uoa decksoudolbodoka ici deo oclo deae 400 19 14 Multiplexed Expansion Bus Timing 401 15009 OFI TN dra eq ed d ad redde Dice ed RI diera en d ac a 403 19 16 CGM CDSraglen s WDR aoo oe SE RE eR 406 19 17 ACRES cade acd dao d wd E eke ee REN dedi OR c d 406 19 18 msCAN12 Wake up Time from Sleep Mode 406 20 1 Suggested 8MHz Synthesis PLL Filter Elements Wit 4g dos TETUTTSTITOOQO IT 2002 riri ee ee 413 20 2 Suggested 8MHz Synthesis PLL Filter Elements DADOUISIBO MOE dca aco ae ordeo pO ER AGO eed 414 22 1 BED SON 6 ce ga da E RUE RC IRE eC RERO CR 431 22 2 2K byte EEPROM Block Protection 433 zc Erase Secs dadadau 6d hd a eh db ded HOD dedos 434 22 4 Shadow word MAING o oo clea wade cedure deiciwans 436 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA List of Tables 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables Technical Data MC68HC912DG128 Rev 3
20. E Clock Frequency at Frequency at SRRZ PRI IRPO Divisor E Clock 4 MHz E Clock 8 MHz 0 0 0 2 2 0 MHz 4 0 MHz 0 0 1 4 1 0 MHz 2 0 MHz 0 1 0 8 500 kHz 1 0 MHz 0 1 1 16 250 kHz 500 KHz 1 0 0 32 125 kHz 250 KHz 1 0 1 64 62 5 kHz 125 KHz 1 1 0 128 31 3 kHz 62 5 KHz 1 1 1 256 15 6 kHz 31 3 KHz MC68HC912DG128 Rev 3 0 Technical Data 269 MOTOROLA Multiple Serial Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multiple Serial Interface Bit 7 6 5 4 3 2 1 Bit 0 SPIF WCOL 0 MODF 0 0 0 0 RESET 0 0 0 0 0 0 0 0 SPOSR SPI Status Register Technical Data 00D3 Read anytime Write has no meaning or effect SPIF SPI Interrupt Request SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SPOSR register with SPIF set followed by an access read or write to the SPI data register WCOL Write Collision Status Flag The MCU write is disabled to avoid writing over the data being transferred No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error Automatically cleared by a read of the SPOSR with WCOL set followed by an access read or write to the SPODR register 0 No write collision 1 Indicates that a serial transfer was in progress when the MCU tried to
21. 208 Enhanced Capture Timer MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Enhanced Capture Timer Introduction T1 2 128 16 bit Free running M clock 39 Prescaler I SD 16 bit load register main timer 1 4 8 16 16 bit modulus M clock Prescaler down counter 0 RESET at Comparator PTO d39 Pinlogic 4 rz7 7 PST Y gt Delay counter EDGO p gt TCO capture compare register L PACO ne Y 5 T COH hold register PAOH hold register 0 RESET na Comparator PT1 Pinlogic 4 p 777027020 Y gt Delay counter EDGI TC1 capture compare register p PACI ITC1H hold register PA1H hold register 0 RESET m Comparator PT2 lt Pinlogic 4 222222 Y
22. 388 Electrical Specifications For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Electrical Specifications Tables of Data Table 19 4 Supply Current Vpp 5 0 Vdc 10 Vss 0 Vdc Ta T to Ty unless otherwise noted Characteristic Symbol 8 MHz Unit Maximum total supply current RUN Single chip mode DD 60 mA Expanded mode 100 mA WAIT All peripheral functions shut down Single chip mode Wipp 15 mA Expanded mode 20 mA STOP S Single chip mode no clocks DD 200 uA Table 19 5 ATD DC Electrical Characteristics Vpp 5 0 Vdc 10 Vss 0 Vdc Ta T to Ty ATD Clock 2 MHz unless otherwise noted Characteristic Symbol Min Max Unit Analog supply voltage VDDA 4 5 5 5 V Analog supply currentNormal operation IDDA 1 0 mA Reference voltage low VRL Vssa Vpopa 2 Reference voltage high VRH Vppa 2 VppA Vner differential reference voltage VRH VRL 4 5 5 5 V Input voltage ViNDC Vssa VpDA V Input current off channel lorF 100 nA Reference supply current IREF 250 uA Input capacitanceNot Sampling CiNN 10 pF Sampling Cins 15 pF 1 Accuracy is guaranteed at Vay Vg 5 0V 10 2 To obtain full scale full range results Vssa lt VnL lt ViNDC lt VRH lt VDpDA 3 Maximum leakage occurs at maximum operating temperature Current decreases by approximately one half for each 10 C
23. 430 Appendix MC68HC912DG128A EEPROM For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Appendix MC68HC912DG128A EEPROM EEPROM Control Registers Table 22 1 EEDIV Selection Osc Freq Osc Period Divide Factor EEDIV 16 Mhz 62 5ns 560 0230 8 Mhz 125ns 280 0118 4 Mhz 250ns 140 008C 2 Mhz 500ns 70 0046 1 Mhz ius 35 0023 500 Khz 2us 18 0012 250 Khz 4us 9 0009 EEMCR EEPROM Module Configuration 00F0 Bit 7 6 5 4 3 2 1 Bit 0 NOBDML NOSHW RESERVED 1 EESWAI PROTLCK DMY RESET e e 1 1 0 0 1 Bits 4 and 5 have test functions and should not be programmed 2 Loaded from SHADOW word Bits 7 4 are loaded at reset from the EEPROM SHADOW word NOTE The bits 5 and 4 are reserved for test purposes These locations in SHADOW word should not be programmed otherwise some locations of regular EEPROM array will not be more visible NOBDML Background Debug Mode Lockout Disable 0 2 The BDM lockout is enabled 1 The BDM lockout is disabled Loaded from SHADOW word at reset Read anytime Write anytime in special modes SMODN 0 NOSHW SHADOW Word Disable 0 The SHADOW word is enabled and accessible at address 0FCO 0FC1 1 Regular EEPROM array at address 0FCO 0FC1 Loaded from SHADOW word at reset Read anytime Write anytime in special modes SMODN 0 When
24. 181 11 8 SGC Chain f r BASE osaaca a bare eee ek eens CR 182 11 9 Clock Chain for MSCAN SPI ATDO ATD1 and BDM 183 12 1 Block Diagram of PWM Left Aligned Output Channel 192 12 2 Block Diagram of PWM Center Aligned Output Channel 193 12 3 PWM Clock Sources coc etek tk ERR d RR Ri i Ra Renta 194 13 1 Timer Block Diagram in Latch Mode 209 13 2 Timer Block Diagram in Queue Mode 210 19 3 8 Bit Pulse Accumulators Block Diagram 211 13 4 16 Bit Pulse Accumulators Block Diagram 212 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA List of Figures 15 For More Information On This Product Go to www freescale com Technical Data Freescale Semiconductor Inc List of Figures Block Diagram for Port7 with Output compare Pulse BODIE Puoi dog gea cae Oe ew nee Fe Rer ie dt plc Gi od 213 C3F COF Interrupt Flag Setting 213 Multiple Serial Interface Block Diagram 250 Serial Communications Interface Block Diagram 251 Serial Peripheral Interface Block Diagram 263 SPI Glock Format D CPHA UD Luosadcxa xo C E eed en 264 SPI Clock Format 1 CPHA Dioses kkkakbasau Rr 265 Normal Mode and Bidirectional Mode 266 Hz Block LET BET am kind ian on dene dade boe bae 275 IIC Transmission Signals os iccuesch rrr ara rmn 276 IIC Clock Synchronization iu su sux ede
25. Pin logic enese see mp CJ Sip ee e c er gt p gt TC5 capture compare register ED MUX G1 L Read TC2H hold register m r Comparator PT6 lt Pin logic EDGG fe as eee p gt TC6 capture compare register Lp p MU Read TC1H gt poe hold register E Comparator gt PT7 lt Pin logic ebayer See ees Read TCOH gt p gt TC7 capture compare register hold register MUX EDG3 gt Figure 13 2 Timer Block Diagram in Queue Mode Technical Data MC68HC912DG128 Rev 3 0 210 Enhanced Capture Timer For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Enhanced Capture Timer Introduction Load holding register and reset pulse accumulator L 0 EDGO 8 bit PACO PACNO PTO M Edge detector Delay counter PAOH holding register Interrupt gt 0 EDG1 8 bit PAC1 PACN1 PT1 Edge detector Delay counter gt PA1H holding register e a 0 s EDG2 8 bit PAC2 PACN2 as PT2 Edge detector gt Delay counter g
26. A 16 bit register in the CPU The PC register holds the address of the next instruction or operand that the CPU will use pull An instruction that copies into the accumulator the contents of a stack RAM location The stack RAM address is in the stack pointer pullup A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply pulse width The amount of time a signal is on as opposed to being in its off state pulse width modulation PWM Controlled variation modulation of the pulse width of a signal with a constant frequency push An instruction that copies the contents of the accumulator to the stack RAM The stack RAM address is in the stack pointer PWM period The time required for one complete cycle of a PWM waveform RAM Random access memory All RAM locations can be read or written by the CPU The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off RC circuit A circuit consisting of capacitors and resistors having a defined time constant read To copy the contents of a memory location to the accumulator register A circuit that stores a group of bits reserved memory location A memory location that is used only in special factory test modes Writing to a reserved location has no effect Reading a reserved location returns an unpredictable value reset To force a d
27. When the PUPE bit in the PUCR register is set PE 7 3 2 1 0 are pulled up PE 7 3 2 0 are active pull up devices PUPCR is not in the address map in peripheral mode Neither port E nor DDRE is in the map in peripheral mode neither is in the internal map in expanded modes with EME set MC68HC912DG128 Rev 3 0 52 Pinout and Signal Descriptions MOTOROLA For More Information On This Product Go to www freescale com 3 5 4 Port H 3 5 5 Port J Freescale Semiconductor Inc Pinout and Signal Descriptions Port Signals Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced drive level RDRIV can be written once after reset RDRIV is not in the address map in peripheral mode Refer to Bus Control and Input Output Port H pins are used for key wake ups that can be used with the pins configured as inputs or outputs The key wake ups are triggered with either a rising or falling edge signal KWPH An interrupt is generated if the corresponding bit is enabled KWIEH If any of the interrupts is not enabled the corresponding pin can be used as a general purpose I O pin Refer to I O Ports with Key Wake up Register DDRH determines whether each port H pin is an input or output Setting a bit in DDRH makes the corresponding bit in port H an output clearing a bit in DDRH makes the corresponding bit in port H an input The default reset state of DDRH is all zeros Register KWPH not only determine
28. 1 Use these commands only for reading writing to BDM locations The BDM firmware ROM and BDM registers are not normally in the HC12 MCU memory map Since these locations have the same addresses as some of the normal application memory map there needs to be a way to decide which physical locations are being accessed by the hardware BDM commands This gives rise to needing separate memory access commands for the BDM locations as opposed to the normal application lo cations In logic this is accomplished by momentarily enabling the BDM memory resources just for the access cycles of the READ BD and WRITE BD commands This logic allows the debugging system to unobtrusively access the BDM locations even if the application program is running out of the same memory area in the normal application memory map The second type of BDM commands are firmware commands implemented in a small ROM within the HC12 MCU The CPU must be in background mode to execute firmware commands The usual way to get to background mode is by the hardware command BACKGROUND The BDM ROM is located at FF20 to FFFF while BDM is active There are also seven bytes of BDM registers located at FF00 to FF06 when BDM is active The CPU executes code in the BDM firmware to perform the requested operation The BDM firmware watches for serial commands and executes them as they are received The firmware commands are shown in Table 18 3 Technical Data MC68HC912DG128 Rev 3 0 362 De
29. Freescale Semiconductor Inc Appendix MC68HC912DG128A EEPROM EEPROM Programmer s Model A steady internal self time clock is required to provide accurate counts to meet EEPROM progranverase requirements This clock is generated via by a programmable 10 bit prescaler register Automatic program erase termination is also provided In ordinary situations with crystal operating properly the steady internal self time clock is derived from the input clock source EXTALi The divider value is as in EEDIVH EEDIVL In limp home mode where the oscillator has malfunctioned or is unavailable the self time clock is derived from the PLL with approximately 1 MHz frequency with a predefined divider value of 0023 Program erase operation is not guaranteed in limp home mode The clock switching function is only applicable for permanent loss of crystal condition so the program erase will also not be guaranteed when the loss of crystal condition is intermittent It is strongly recommended that the clock monitor is enabled to ensure that the program erase operation will be shutdown in the event of loss of crystal with a clock monitor reset or switch to a limp home mode clock This will prevent unnecessary stress on the emulated EEPROM during oscillator failure MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Appendix MC68HC912DG128A EEPROM 429 For More Information On This Product Go to www freescale com Freescale Semiconductor I
30. MOTOROLA Freescale Semiconductor Inc Electrical Specifications Tables of Data Table 19 14 Multiplexed Expansion Bus Timing Vpp 5 0 Vdc 10 Vss 0 Vac Ta T to Ty unless otherwise noted Num Characteristic 2 3 4 Delay Symbol edid Unit Min Max Frequency of operation E clock frequency fo 0 004 8 0 MHz 1 Cycle timeteye 1 fo toye 0 125 250 us 2 Pulse width E lowPWg teyo 2 delay 4 PWe 58 ns 3 Pulse width E high PWg teyc 2 delay 2 PW H 60 ns 5 Address delay timetap tcyc 4 delay 27 tap 58 ns 7 Address valid time to ECLK risetay PWg tap tay 0 ns 8 Multiplexed address hold timetyay teyo 4 delay 18 MAH 13 ns 9 Address Hold to Data Valid tAHDS 20 10 Data Hold to High Ztpyz tap 20 tpuz 38 11 Read data setup time tpsR 25 ns 12 Read data hold time tpHR 10 ns 13 Write data delay time tppw 47 ns 14 Write data hold time tpuw 20 ns 15 Write data setup time tpsw PWg tppw tosw 13 ns 16 Read write delay timetgyp teyo 4 delay 18 tRWD 49 ns 17 Read write valid time to E risetawy PWg tRwp trwv 9 ns 18 Read write hold time tRWH 20 ns 19 Low strobe 9 delay timet gp tey 4 delay 18 tLsp 49 ns 20 Low strobe valid time to E riset sy PWg tj gp tLsv 9 ns 21 Low strobe hold time tLsH 20 ns
31. NT interrupt control Two 8 bit ports with key wake up interrupt Clock generation Phase locked loop clock frequency multiplier Limp home mode in absence of external clock Slow mode divider Low power 0 5 to 16 MHz crystal oscillator reference clock e 112 Pin TQFP package Up to 66 general purpose I O lines plus up to 18 input only lines e 8MHz operation at 5V Development support Single wire background debug mode BDM On chip hardware breakpoints Technical Data MC68HC912DG128 Rev 3 0 26 General Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Ordering Information 1 4 Ordering Information Table 1 1 Device Ordering Information Temperature Package Voltage Frequency Order Number Range Designator 0 to 70 C 68HC912DG128PV8 112 Pin TQFP 40 to 85 C C 68HC912DG128CPV8 Single Tray 4 5V 5 5V 8 MHz 60 Pcs 40 to 105 C V 68HC912DG128VPV8 40 to 125 C M 68HC912DG128MPV8 Important M temperature operation is available only for single chip modes Table 1 2 Development Tools Ordering Information Description Name Order Number MCUez Free from World Wide Web M68SDIL 8 5V M68DIL12 SDIL MCUez Serial Debug Interface SDI SDBUG12 Evaluation board EVB M68EVB912DG128 EVB only M68KIT912DG128 EVB SDIL12
32. No External E Clock Normal single chip write once special single chip write anytime all other modes write never Read anytime In peripheral mode E is an input and in all other modes E is an output 0 PE4 is the external E clock pin subject to the following limitation In single chip modes to get an E clock output signal it is necessary to have ESTR 0 in addition to NECLK 0 A 16 bit write to PEAR and MODE registers can configure all three bits in one operation 1 PE4 is a general purpose I O pin Technical Data MC68HC912DG128 Rev 3 0 102 Bus Control and Input Output MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bus Control and Input Output Registers LSTRE Low Strobe LSTRB Enable Normal write once Special write anytime EXCEPT the first time Read anytime This bit has no effect in single chip modes or normal expanded narrow mode 0 PE3 is a general purpose I O pin 1 PES is configured as the LSTRB bus control output provided the MCU is not in single chip or normal expanded narrow modes LSTRB is used during external writes After reset in normal expanded mode LSTRB is disabled If needed it should be enabled before external writes External reads do not normally need LSTRB because all 16 data bits can be driven even if the MCU only needs 8 bits of data In normal expanded narrow mode this pin is reset to an output
33. Y C ID accepted Filter O hit D Figure 17 3 32 bit Maskable Identifier Acceptance Filters ID28 IDRO 1D21 ID20 IDR1 1D15 ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDRO ID3 ID2 IDR1 IDE y y AM7 CIDMRO AMO AM7 CIDMR1 AMO Y Y AC7 CIDARO ACO AC7 CIDAR1 ACO Y Y C ID accepted Filter 0 hit Y Y AM7 CIDMR2 AMO AM7 CIDMR3 AMO Y AC7 CIDAR2 ACO AC7 CIDAR3 ACO Y Y ID accepted Filter 1 hit D Figure 17 4 16 bit Maskable Acceptance Filters MC68HC912DG128 Rev 3 0 MSCAN Controller For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MSCAN Controller Identifier Acceptance Filter ID28 IDRO 1D21 1D20 IDR1 1 D15 ID14 IDR2 D7 ID6 IDR3 RTR ID10 IDRO D3 ID2 IDR1 IDE Y AM7 CIDMRO AMO Y AC7 CIDARO ACO Y 1p accepted Filter 0 hit Y AM7 CIDMR1 AMO Y AC7 CIDAR1 ACO Y iD accepted Filter 1 hit Y AM7 CIDMR2 AMO Y AC7 CIDAR2 ACO Y ip accepted Filter 2 hit Y AM7 CIDMR3 AMO Y AC7 CIDAR3 ACO Figure 17 5 8 bit Maskable Acceptance Filters The identifier acceptance registers CIDARO 7 define the acceptable patterns of the standard or extended identifier ID10 I
34. gt Delay counter EDG TC2 capture compare register L PAC2 ITC2H hold register PA2H hold register 0 RESET Ps Comparator PT3 J Pinlogic p 4 frr c crc ccc a Y gt Delay counter EDGS TC3 capture compare register p PACS m C3H hold register PA3H hold register x PT4 Pin logi n Comparator e 4 dM Pinlogic eye t0077020207722 EDG4 p gt TC4 capture compare register ar DE MUX ICLAT LATQ BUFEN lt EDG0 gt m force latch Fi Comparator PT5 4 Pin logic EDG5 F P EEE ers a CRE bis NUX p gt TC5 capture compare register Write 0000 EDG1 gt to modulus counter hx Comparator LATQ PT6 Pin logic epee f a scd xA mcs eee MDC latch enable p gt TC6 capture compare register EDG2 MUR a Comparator PT7 4 Pin logic EDGr ont qp uso Tee nm eme TC7 capture compare register MUX EDG3 gt Figure 13 1 Timer Block Diagram in Latch Mode MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Enhanced Capture Timer 209 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Enhanced Capture Timer
35. lt 10 11 BIT SHIFT REG TxD BUFFER SCxDRL WAKE UP LOGIC SCxSR1 INT STATUS SCxCR2 SCI CTL 2 SCxCR1 SCI CTL 1 INT REQUEST LOGIC Figure 14 2 Serial Communications Interface Block Diagram MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Multiple Serial Interface 251 For More Information On This Product Go to www freescale com 14 4 1 Data Format Freescale Semiconductor Inc Multiple Serial Interface The serial data format requires the following conditions An idle line in the high state before transmission or reception of a message A start bit logic zero transmitted or received that indicates the start of each character Data that is transmitted or received least significant bit LSB first A stop bit logic one used to indicate the end of a frame A frame consists of a start bit a character of eight or nine data bits anda stop bit A BREAK is defined as the transmission or reception of a logic zero for one frame or more This SCI supports hardware parity for transmit and receive 14 4 2 SCI Baud Rate Generation Technical Data The basis of the SCI baud rate generator is a 13 bit modulus counter This counter gives the generator the flexibility necessary to achieve a reasonable level of independence from the CPU operating frequency and still be able to produce stand
36. 0 0 0 0 0 0 0 This register controls the operation of the Flash EEPROM array BOOTP cannot be changed when the LOCK control bit in the FEELCK register is set or if ENPE in the FEECTL register is set BOOTP Boot Protect The boot blocks are located at E000 FFFF and A000 BFFF for odd program pages for each Flash EEPROM module Since boot programs must be available at all times the only useful boot block is at E000 FFFF location All paged boot blocks can be used as protected program space if desired 0 Enable erase and program of 8K byte boot block 1 Disable erase and program of 8K byte boot block Technical Data MC68HC912DG128 Rev 3 0 110 Flash Memory For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Flash Memory Flash EEPROM Registers FEETST Flash EEPROM Module Test Register 00F6 Bit 7 6 5 4 3 2 1 Bit 0 FSTE GADR HVT FENLV FDISVFP VTCK STRE MWPR RESET 0 0 0 0 0 0 0 0 In normal mode writes to FEETST control bits have no effect and always read zero The Flash EEPROM module cannot be placed in test mode inadvertently during normal operation FSTE Stress Test Enable 0 Disables the gate drain stress circuitry 1 Enables the gate drain stress circuitry GADR Gate Drain Stress Test Select 0 Selects the drain stress circuitry 1 Selects the gate stress circuitry HVT
37. 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 Freescale Semiconductor Inc Bit 7 6 5 4 3 2 1 Bit 0 Name Bit 7 6 5 4 3 2 1 Bit 0 PACN2 Bit 7 6 5 4 3 2 1 Bit 0 PACN1 Bit 7 6 5 4 3 2 1 Bit 0 PACNO MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPRO MCCTL MCZF 0 0 0 POLF3 POLF2 POLF1 POLFO MCFLG 0 0 0 0 PASEN PA2EN PA1EN PAOEN ICPAR 0 0 0 0 0 0 DLY1 DLYO DLYCT NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVWO ICOVW SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ ICSYS 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 TCBYP 0 TIMTST PT7 PT6 PT5 PT4 PT3 PT2 PT1 PTO PORTT DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDTO DDRT 0 PBEN 0 0 0 0 PBOVI 0 PBCTL 0 0 0 0 0 0 PBOVF 0 PBFLG Bit 7 6 5 4 3 2 1 Bit 0 PA3H Bit 7 6 5 4 3 2 1 Bit 0 PA2H Bit 7 6 5 4 3 2 1 Bit 0 PA1H Bit 7 6 5 4 3 2 1 Bit 0 PAOH Bit 15 14 13 12 11 10 9 Bit 8 MCCNTH Bit 7 6 5 4 3 2 1 Bit 0 MCCNTL Bit 15 14 13 12 11 10 9 Bit 8 TCOH Bit 7 6 5 4 3 2 1 Bit 0 TCOH Bit 15 14 13 12 11 10 9 Bit 8 TC1H Bit 7 6 5 4 3 2 1 Bit 0 TC1H Bit 15 14 13 12 11 10 9 Bit 8 TC2H Bit 7 6 5 4 3 2 1 Bit 0 TC2H Bit 15 14 13 12 11 10 9 Bit 8 TC3H Bit 7 6 5 4 3 2 1 Bit 0 TC3H BTST BSPL BRLD SBR12 SBR11 SBR10 SBHR9 SBR8 SCOBDH SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBRO SCOBDL LOOPS WOMS RSRC M WAKE ILT PE PT SCOCR1 TIE TCIE RIE ILIE TE RE RWU SBK SCOCR2 TDRE TC RDRF IDLE OR NF FE PF SCOSR1
38. 162 MIFCONIBUBD aa ER cine RUE qo AR CIR UE CC RR EO AE CI COR A 297 16 3 Functional Description 1uusasesacesa ke KREH bar ok o eg ae 298 16 4 ATD Registers aod ood PRORA DGRGR eie PR de di pop Hl d 299 16 5 ATD Mode DIO c ada ERAZARAKAeXR E EROR P4 FORD Rn 310 The MC68HC912DG128 has two identical ATD modules identified as ATDO and ATD1 Except for the Vppa and Vssa Analog supply voltage all pins are duplicated and indexed with 0 or 1 in the following description An x indicates either O or 1 The ATD module is an 8 channel 10 bit or 8 bit multiplexed input successive approximation analog to digital converter It does not require external sample and hold circuits because of the type of charge redistribution technique used The ATD converter timing can be synchronized to the system P clock The ATD module consists of a 16 word 32 byte memory mapped control register block used for control testing and configuration MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Analog to Digital Converter 297 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter VRH RC DAC ARRAY V j REFERENCE AND COMPARATOR RLX amp VDD SUPPLY Nx7 PADx7 Nx6 PADx6 Nx5 PADx5 Nx4 PADx4 Nx3 PADx3 Nx2 PADx2 Nx1 PADx1 Nx0 PADx0 gt wn o D gt iw ANALOG MUX AND SAMPLE BUFFER AMP gt iw n2
39. EEPROM Charge Pump Clock 0 System clock is used as clock source for the internal charge pump Internal RC oscillator is stopped 1 Internal RC oscillator drives the charge pump The RC oscillator is required when the system bus clock is lower than fppoc Read and write anytime EEPROT EEPROM Block Protect 00F1 Bit 7 6 5 4 3 2 1 Bit 0 SHPROT 1 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROTO RESET 1 1 1 1 1 1 1 1 Prevents accidental writes to EEPROM Read anytime Write anytime if EEPGM 0 and PROTLCK 0 SHPROT SHADOW Byte Protection 0 The SHADOW byte can be programmed and erased 1 The SHADOW byte is protected from being programmed and erased BPROT 5 0 EEPROM Block Protection 0 Associated EEPROM block can be programmed and erased 1 Associated EEPROM block is protected from being programmed and erased Table 8 1 2K byte EEPROM Block Protection Bit Name Block Protected Block Size BPROT5 0800 to 0BFF 1024 Bytes BPROT4 0C00 to 0DFF 512 Bytes BPROT3 0E00 to 0EFF 256 Bytes BPROT2 0F00 to 0F7F 128 Bytes BPROT1 0F80 to 0FBF 64 Bytes BPROTO 0FCO to 0FFF 64 Bytes MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA EEPROM Memory 129 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EEPROM Memory EETST EEPROM Test 00F2 Bit 7 6
40. entered by a breakpoint only if an internal signal from the BDM indicates background debug mode is enabled BKDBE will be used as an enable for the second address only breakpoint e Breakpoints are not allowed if the BDM mode is already active Active mode means the CPU is executing out of the BDM ROM e BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM This is important because even if the ENABLE bit in the BDM is negated the CPU actually does execute the BDM ROM code It checks the ENABLE and returns if not set If the BDM is not serviced by the monitor then the breakpoint would be re asserted when the BDM returns to normal CPU flow There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled 18 5 2 Breakpoint Registers Breakpoint operation consists of comparing data in the breakpoint address registers BRKAH BRKAL to the address bus and comparing data in the breakpoint data registers BRKDH BRKDL to the data bus The breakpoint data registers can also be compared to the address bus The scope of comparison can be expanded by ignoring the least significant byte of address or data matches The scope of comparison can be limited to program data only by setting the BKPM bit in breakpoint control register 0 To trace program flow setting the BKPM bit causes address comparison of program data only Control bits are also available that allow checking read write mat
41. 0002 This register determines the primary direction for each port A pin when functioning as a general purpose l O port DDRA is not in the on chip map in expanded and peripheral modes Read and write anytime 0 Associated pin is a high impedance input 1 Associated pin is an output MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Bus Control and Input Output For More Information On This Product Go to www freescale com 97 Freescale Semiconductor Inc Bus Control and Input Output Single Chip PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO RESET EE Expanded ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDRO amp Periph DATA DATA6 DATAS DATA4 DATA3 DATA2 DATA1 DATAO Expanded ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDRO narrow PORTB Port B Register 0001 Bits PB 7 0 are associated with addresses ADDR 7 0 and DATA 7 0 except in narrow mode respectively When this port is not used for external addresses such as in single chip mode these pins can be used as general purpose I O DDRB determines the primary direction of each pin This register is not in the on chip map in expanded and peripheral modes Read and write anytime Bit 7 6 5 4 3 2 1 Bit 0 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDBO RESET 0 0 0 0 0 0 0 0 DDRB Port B Data Direction Register 0003 This register determines the primary direction for each port B pin when
42. 00E3 TCF IAAS IBB IBAL 0 SRW IBIF RXAK IBSR 00E4 D7 D6 D5 D4 D3 D2 D1 DO IBDR 00E5 0 0 0 RDPIB 0 0 0 PUPIB IBPURD 00E6 PIB7 PIB6 PIB5 PIB4 PIB3 PIB2 PIB1 PIBO PORTIB 00E7 DDRIB7 DDRIB6 DDRIB5 DDRIB4 DDRIB3 DDRIB2 DDRIB1 DDRIBO DDRIB eee Unimplemented 4 Reserved 00FO NOBDML NOSHB 1 Reserved EESWAI PROTLCK EERC EEMCR 00F1 SHPROT 1 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROTO EEPROT 00F2 EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0 EETST 00F3 BULKP 0 0 BYTE ROW ERASE EELAT EEPGM EEPROG 00F4 0 0 0 0 0 0 0 LOCK FEELCK 00F5 0 0 0 0 0 0 0 BOOTP FEEMCR 00F6 FSTE GADR HVT FENLV FDISVFP VTCK STRE MWPR FEETST 00F7 0 0 0 FESWAI SVFP ERAS LAT ENPE FEECTL 00F8 MTO7 MTO6 MT05 MT04 MT03 MT02 MTO1 MTOO MTSTO 00F9 MTOF MTOE MTOD MTOC MTOB MTOA MTO9 MT08 MTST1 00FA MT17 MT16 MT15 MT14 MT13 MT12 MT11 MT10 MTST2 00FB MT1F MT1E MT1D MT1C MT1B MT1A MT19 MT18 MTST3 Table 4 1 Register Map Sheet 6 of 10 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Registers 69 For More Information On This Product Go to www freescale com Address 00FC 00FD 00FE 00FF 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 010D 010E 010F 0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 011A 011B 011C 011D 011E 011F 0120 013C 013D 013E 013F Freescale Semiconductor Inc
43. 11FEE32K is located from addresses 4000 to 7FFF and from C000 to FFFF The other three 32K Flash EEPROM arrays OOFEE32K 01FEE32K and 10FEE32K are mapped through a 16K byte program page window located from addresses 8000 to BFFF The page window has eight 16K byte pages The last two pages also map the physical location of the fixed 32K Flash EEPROM array 11FEE32K In expanded modes the Flash EEPROM arrays are turned off See Operating Modes MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Flash Memory 109 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory 7 7 Flash EEPROM Registers Each 32K byte Flash EEPROM module has a set of registers The register space 00F4 00F7 is in a register space window of four pages Each register page of four bytes maps the register space for each Flash module and each page is selected by the PPAGE register See Operating Modes FEELCK Flash EEPROM Lock Control Register 00F4 RESET Bit 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 In normal modes the LOCK bit can only be written once after reset LOCK Lock Register Bit 0 Enable write to FEEMCR register 1 Disable write to FEEMCR register FEEMCR Flash EEPROM Module Configuration Register RESET Bit 7 6 5 4 3 0 0 0 0 0 0
44. 127 8 5 EEPROM Control Registers annaa aana rd hh en 128 The MC68HC912DG128 EEPROM nonvolatile memory is arranged in a 16 bit configuration The EEPROM array may be read as either bytes aligned words or misaligned words Access times are one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations Programming is by byte or aligned word Attempts to program or erase misaligned words will fail Only the lower byte will be latched and programmed or erased Programming and erasing of the user EEPROM can be done in all modes Each EEPROM byte or aligned word must be erased before programming The EEPROM module supports byte aligned word row 32 bytes or bulk erase all using the internal charge pump The EEPROM module has hardware interlocks which protect stored data from corruption by accidentally enabling the program erase voltage Programming voltage is derived from the internal Vpp supply with an internal charge pump MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA EEPROM Memory 125 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EEPROM Memory 8 3 Future EEPROM Support CAUTION Technical Data Design is underway to introduce an improved EEPROM module with integrated state machine to simplify programming and erase This will be introduced on the 68HC912DG128A together with 5V programming Flash EEPROM Appendix MC68HC91
45. COP See computer operating properly module COP CPU See central processor unit CPU CPU12 The CPU of the MC68HC12 Family CPU clock Bus clock select bits BCSP and BCSS in the clock select register CLKSEL determine which clock drives SYSCLK for the main system including the CPU and buses When EXTALi drives the SYSCLK the CPU or bus clock frequency f is equal to the EXTALI frequency divided by 2 CPU cycles A CPU cycle is one period of the internal bus clock normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal The length of time required to execute an instruction is measured in CPU clock cycles CPU registers Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map The CPU always has direct access to the information in these registers The CPU registers in an M68HC12 are A 8 bit accumulator B 8 bit accumulator D 16 bit accumulator formed by concatenation of accumulators A and B e IX 16 bit index register e Y 16 bit index register SP 16 bit stack pointer PC 16 bit program counter e CCR 8 bit condition code register MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Glossary 443 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc cycle time The period of the operating frequency toyc 1 fop D See a
46. Condition to set the flag RERRIF 128 REC lt 255 amp BOFFIF 3 Condition to set the flag TERRIF 128 TEC 255 amp BOFFIF Technical Data MC68HC912DG128 Rev 3 0 344 MSCAN Controller MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MSCAN Controller Programmer s Model of Control Registers OVRIF Overrun Interrupt Flag This flag is set when a data overrun condition occurs If not masked an Error interrupt is pending while this flag is set 0 No data overrun has occurred 1 A data overrun has been detected RXF Receive Buffer Full The RXF flag is set by the msCAN12 when a new message is available in the foreground receive buffer This flag indicates whether the buffer is loaded with a correctly received message After the CPU has read that message from the receive buffer the RXF flag must be handshaken cleared in order to release the buffer A set RXF flag prohibits the exchange of the background receive buffer into the foreground buffer If not masked a Receive interrupt is pending while this flag is set 0 The receive buffer is released not full 1 The receive buffer is full A new message is available WARNING To ensure data integrity no registers of the receive buffer shall be read while the RXF flag is cleared NOTE The CHFLG register is held in the reset state when the SFTRES bit in CMCRO is set 17 13 7 msCAN12
47. Pinout and Signal Descriptions Signal Descriptions 3 4 15 Clock generation module test CGMTST The CGMTST pin PE6 is the output of the clocks tested when CGMTE bit is set in PEAR register The PIPOE bit must be cleared for the clocks to be tested Table 3 2 Signal Description Summary Pin Pin Name joo Number Description 112 pin EXTAL F 47 Crystal driver and external clock input pins On reset all the device clocks XTAL 48 are derived from the EXTAL input frequency XTAL is the crystal output An active low bidirectional control signal RESET acts as an input to RESET 46 initialize the MCU to a known start up state and an output when COP or clock monitor causes a reset ADDR 7 0 UT PB 7 0 31 24 External bus pins share function with general purpose I O ports A and B In single chip modes the pins can be used for I O In expanded modes ADDR 15 8 the pins are used for the external buses DATA 15 8 PA 7 0 64 57 p DBE PE7 36 Data bus control and in expanded mode enables the drive control of external buses during external reads ECLK PE7 36 Inverted E clock used to latch the address CAL is the output of the Slow Mode programmable clock divider SLWCLK and is used as a calibration reference for functions such as GAE PET i time of day It is overridden when DBE function is enabled It always has a 5096 duty CGMTST PE6 37 Clock generation module test output MODB Stat
48. The PWM function is enabled with the PWEN register Enabling PWM pins takes precedence over the general purpose port When pulse width modulation is not in use the port pins may be used for general purpose l O Register DDRP determines pin direction of port P when used for general purpose I O When DDRP bits are set the corresponding pin is configured for output On reset the DDRP bits are cleared and the corresponding pin is configured for input When the PUPP bit in the PWCTL register is set all input pins are pulled up internally by an active pull up device Pull ups are disabled after reset Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels Levels are at normal drive capability after reset The PWCTL register can be read or written anytime after reset Refer to Pulse Width Modulator Port S is the 8 bit interface to the standard serial interface consisting of the two serial communications interfaces SCI1 and SCIO and the serial peripheral interface SPI subsystems Port S pins are available for general purpose I O when standard serial functions are not enabled Port S pins serve several functions depending on the various internal control registers If WOMS bit in the SCOCR1register is set the P channel drivers of the output buffers are disabled wire or mode for pins 0 through 3 If SWOM bit in the SPOCR1 register is set the P channel drivers of the output buffers are disabled
49. W 1 x is 4 5 6 or 7 depending on which buffer RxFG Tx0 Tx1 or Tx2 respectively 17 12 2 Identifier Registers IDRn The identifiers consist of either 11 bits ID10 IDO for the standard or 29 bits ID28 IDO for the extended format ID10 28 is the most significant bit and is transmitted first on the bus during the arbitration procedure The priority of an identifier is defined to be highest for the smallest binary number SRR Substitute Remote Request This fixed recessive bit is used only in extended format It must be set to 1 by the user for transmission buffers and will be stored as received on the CAN bus for receive buffers IDE ID Extended This flag indicates whether the extended or standard identifier format is applied in this buffer In the case of a receive buffer the flag is set as being received and indicates to the CPU how to process the buffer identifier registers In the case of a transmit buffer the flag indicates to the msCAN12 what type of identifier to send 0 Standard format 11 bit 1 Extended format 29 bit MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA MSCAN Controller 335 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MSCAN Controller RTR Remote transmission request This flag reflects the status of the Remote Transmission Request bit in the CAN frame In the case of a receive b
50. Writing a1 to this bit clears the flag if TFFCA 0 Writing a zero has no effect Any access to the MCCNT register will clear the MCZF flag in this register when TFFCA bit in register TSCR 86 is set MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Enhanced Capture Timer For More Information On This Product Go to www freescale com 235 BIT 7 Freescale Semiconductor Inc Enhanced Capture Timer POLF3 POLFO First Input Capture Polarity Status These are read only bits Write to these bits has no effect Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read Each POLFx corresponds to a timer PORTx input 0 The first input capture has been caused by a falling edge 1 The first input capture has been caused by a rising edge RESET 6 5 4 3 2 1 BIT O 0 0 0 0 PASEN PA2EN PA1EN PAOEN 0 0 0 0 0 0 0 0 ICPACR Input Control Pulse Accumulators Control Register Technical Data 00A8 The 8 bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PATCL A0 is cleared If PAEN is set PASEN and PA2EN have no effect The 8 bit pulse accumulators PAC1 and PACO can be enabled only if PBEN in PBTCL BO is cleared If PBEN is set PA1EN and PAQEN have no effect Read any time Write any time PAxEN 8 Bit Pulse Accumulator x Enable 0 8 Bit Pulse Accumul
51. execution resumes after a delay of 4096 XCLK cycles NOTE The external clock signal should stabilise within the 4096 reset counter cycles Use of DLY 0 is not recommended due to this requirement MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Clock Functions 167 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Functions 11 6 5 Executing the STOP instruction without Limp Home mode clock monitor enabled NOLHM 1 CME 1 DLY X If the NOLHM bit and the CME or FCME bits are set a clock monitor failure is detected when a STOP instruction is executed and the MCU resets via the clock monitor reset vector 11 6 6 STOP exit in Limp Home mode with Delay CAUTION Technical Data NOLHM 0 CME X DLY 1 If the NOLHM bit is cleared then the CME or FCME bit is masked when a STOP instruction is executed to prevent a clock monitor failure When coming out of STOP mode the MCU goes into limp home mode where CME and FCME signals are asserted When using a crystal oscillator anormal STOP exit sequence requires the DLY bit to be set to allow for the crystal stabilization period With the 13 stage counter clocked by the VCO at fycomin following a delay of 4096 XCLK cycles at the limp home frequency if the clock monitor indicates the presence of an external clock the limp home mode is de asserted and the MCU exits STOP normally using EXTALi clock Where the crystal s
52. wire or mode for pins 4 through 7 The open drain control affects both the serial and the general purpose outputs If the RDPS bit in the SPOCR2 register is set Port S pin drive capabilities are reduced If PUPS bit in the SPOCR2 register is set a pull up device is activated for each port S pin programmed as a general purpose input If the pin is programmed as a general purpose output the pull up is disconnected from the pin regardless of the state of PUPS bit See Multiple Serial Interface MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Pinout and Signal Descriptions 57 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pinout and Signal Descriptions 3 5 14 Port T Technical Data This port provides eight general purpose I O pins when not enabled for input capture and output compare in the timer and pulse accumulator subsystem The TEN bit in the TSCR register enables the timer function The pulse accumulator subsystem is enabled with the PAEN bit in the PACTL register Register DDRT determines pin direction of port T when used for general purpose I O When DDRT bits are set the corresponding pin is configured for output On reset the DDRT bits are cleared and the corresponding pin is configured for input When the PUPT bit in the TMSK register is set all input pins are pulled up internally by an active pull up device Pull ups are disabled after reset Setting the
53. 0 22 List of Tables MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC912DG128 1 1 Contents 1 2 Introduction Section 1 General Description QVE MUNDI LEER REPRE d Ww Y base R Fe RD ad SOR 23 EE 00 o v cnn ce eee tetas one ened 24 1 4 Ordering BIOS uario hoa ae C nC debo e d a 27 5 4MOBBHOBT2DG128 Block Diagram i e ooa 28 The MC68HC912DG128 microcontroller unit MCU is a 16 bit device composed of standard on chip peripherals including a 16 bit central processing unit CPU12 128K bytes of flash EEPROM 8K bytes of RAM 2K bytes of EEPROM two asynchronous serial communication interfaces SCI a serial peripheral interface SPI an inter IC interface I2C an enhanced capture timer ECT two 8 channel 10 bit analog to digital converters ATD a four channel pulse width modulator PWM and two CAN 2 0 A B software compatible modules MSCAN 12 System resource mapping clock generation interrupt control and bus interfacing are managed by the lite integration module LIM The MC68HC912DG128 has full 16 bit data paths throughout however the external bus can operate in an 8 bit narrow mode so single 8 bit wide memory can be interfaced for lower cost systems The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements In addition to the I O ports available in each modu
54. 0 222 Enhanced Capture Timer MOTOROLA For More Information On This Product Go to www freescale com RESET Freescale Semiconductor Inc Enhanced Capture Timer Timer Registers Bit 7 6 5 4 3 2 1 Bit 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 TCTL3 Timer Control Register 3 Bit 7 6 5 4 3 2 1 Bit 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDGOB EDGOA 0 0 0 0 0 0 0 0 RESET TCTL4 Timer Control Register 4 RESET TMSK1 Timer Interrupt Mask 1 Read or write anytime EDGnB EDGnA Input Capture Edge Control These eight pairs of control bits configure the input capture edge detector circuits Table 13 2Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge rising or falling Bit 7 6 5 4 3 2 1 Bit 0 C7I C l C5I CAI C3I C2l Cil col 0 0 0 0 0 0 0 0 Read or write anytime MC68HC912DG128 Rev 3 0 008A 008B 008C Technical Data MOTOROLA Enhanced Capture Timer For More Information On This Product Go to www freescale com 223 Freescale Semiconductor Inc Enhanced Capture Timer The bits in TMSK1 correspond bit for bit with the bits in the TFLG1 status register If cleared the corresponding flag is
55. 11 10 Bit 8 Bit 7 6 5 4 3 2 Bit 0 TCO Timer Input Capture Output Compare Register 0 0090 0091 Bit 7 6 5 4 3 2 Bit 0 Bit 15 14 13 12 11 10 Bit 8 Bit 7 6 5 4 3 2 Bit 0 TC1 Timer Input Capture Output Compare Register 1 0092 0093 Bit 7 6 5 4 3 2 Bit 0 Bit 15 14 13 12 11 10 Bit 8 Bit 7 6 5 4 3 2 Bit 0 TC2 Timer Input Capture Output Compare Register 2 0094 0095 Bit 7 6 5 4 3 2 Bit 0 Bit 15 14 13 12 11 10 Bit 8 Bit 7 6 5 4 3 2 Bit 0 TC3 Timer Input Capture Output Compare Register 3 0096 0097 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Enhanced Capture Timer 227 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Enhanced Capture Timer Bit 7 6 5 4 3 2 Bit 0 Bit 15 14 13 12 11 10 Bit 8 Bit 7 6 5 4 3 2 Bit 0 TC4 Timer Input Capture Output Compare Register 4 0098 0099 Bit 7 6 5 4 3 2 Bit 0 Bit 15 14 13 12 11 10 Bit 8 Bit 7 6 5 4 3 2 Bit 0 TC5 Timer Input Capture Output Compare Register 5 009A 009B Bit 7 6 5 4 3 2 Bit 0 Bit 15 14 13 12 11 10 Bit 8 Bit 7 6 5 4 3 2 Bit 0 TC6 Timer Input Capture Output Compare Register 6 009C 009D Bit 7 6 5 4 3 2 Bit 0 Bit 15 14 13 12 11 10 Bit 8 Bit 7 6 5 4 3 2 Bit 0 TC7 Timer Input Capture Output Compare Register 7 009E 009F Depending on the TIOS bit for th
56. 128 21 37 1920 257 18 80 9 38 1280 129 19 96 9 39 1536 129 1A 112 17 3A 1792 257 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Inter IC Bus 283 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Inter IC Bus Table 15 2 IIC Divider and SDA Hold values IBC5 0 SCL Divider SDA Hold IBC5 0 SCL Divider SDA Hold hex clocks clocks hex clocks clocks 1B 128 17 3B 2048 257 1C 144 25 3C 2304 385 1D 160 25 3D 2560 385 1E 192 33 3E 3072 513 1F 240 33 3F 3840 513 IBCR IIC Bus Control Register 00E2 Bit 7 6 5 4 3 2 1 Bit 0 IBEN IBIE MS SL Tx Rx TXAK RSTA 0 IBSWAI RESET 0 0 0 0 0 0 0 0 Read and write anytime IBEN IIC Bus Enable This bit controls the software reset of the entire IIC module 0 The module is reset and disabled This is the power on reset situation When low the IIC system is held in reset but registers can still be accessed 1 The IIC system is enabled This bit must be set before any other IBCR bits have any effect If the IIC module is enabled in the middle of a byte transfer the interface behaves as follows slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected Master mode will not be aware that the bus is busy hence if a start cycle is initiated then the current bus cycle may become corrupt
57. 267 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Multiple Serial Interface CPOL CPHA SPI Clock Polarity Clock Phase These two bits are used to specify the clock format to be used in SPI operations When the clock polarity bit is cleared and data is not being transferred the SCK pin of the master device is low When CPOL is set SCK idles high See Figure 14 4 and Figure 14 5 SSOE Slave Select Output Enable The SS output feature is enabled only in the master mode by asserting the SSOE and DDS7 LSBF SPI LSB First enable 0 Data is transferred most significant bit first 1 Data is transferred least significant bit first Normally data is transferred most significant bit first This bit does not affect the position of the MSB and LSB in the data register Reads and writes of the data register will always have MSB in bit 7 SPOCR2 SPI Control Register 2 00D1 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 PUPS RDPS SPSWAI SPCO RESET 0 0 0 0 1 0 0 0 Read or write anytime PUPS Pull Up Port S Enable 0 No internal pull ups on port S 1 All port S input pins have an active pull up device If a pin is programmed as output the pull up device becomes inactive RDPS Reduce Drive of Port S 0 Port S output drivers operate normally 1 All port S output pins have reduced drive capability for lower power and less noise SPSWAI Ser
58. 32 768 ms 8 196 ms 2 048 ms 0 1 1 215 263 44 ms 65 536 ms 16 384 ms 4 096 ms 1 0 0 216 526 88 ms 131 72 ms 32 768 ms 8 196 ms 1 0 1 217 1 05 s 263 44 ms 65 536 ms 16 384 ms 1 1 0 218 2 11s 526 88 ms 131 72 ms 32 768 ms 1 1 1 219 4 22s 1 05s 263 44 ms 65 536 ms Bit 7 6 5 4 3 2 1 Bit 0 RTIF 0 0 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 RTIFLG Real Time Interrupt Flag Register 0015 RTIF Real Time Interrupt Flag This bit is cleared automatically by a write to this register with this bit set 0 Time out has not yet occurred 1 Set when the time out period is met Technical Data MC68HC912DG128 Rev 3 0 186 Clock Functions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Functions Clock Function Registers Bit 7 6 5 4 3 2 1 Bit 0 CME FCME FCMCOP WCOP DISR CR2 CR1 CRO RESET 0 1 0 0 0 0 1 1 1 Normal RESET 0 1 0 0 0 1 1 1 1 Special COPCTL COP Control Register 0016 CME Clock Monitor Enable Read and write anytime If FCME is set this bit has no meaning nor effect 0 Clock monitor is disabled Slow clocks and stop instruction may be used 1 Slow or stopped clocks including the stop instruction will cause a clock reset sequence or limp home mode See Limp Home and Fast STOP Recovery modes On reset CME is 1 if VDDPLL is high CME is 0 if VDDPLL is low NOTE The VDDPLL dependent reset operation is not impleme
59. 32K flash module register blocks of MC68HC912DG128 The test mode program page window consists of 32K Flash EEPROM bytes One of the four 32K byte arrays is viewed through this window for a total 128K accessible Flash EEPROM bytes This window is only available in special mode for test purposes and replaces the user s program page window MC68HC912DG128 has a five pin port Port K for emulation and for general purpose I O Three pins are used to emulate the three page indices PPAGE bits and one pin is used as an emulation chip select When these four pins are not used for emulation they serve as general purpose l O pins The fifth Port K pin is used as a general purpose I O pin 5 5 5 Program space expansion There are 128K bytes of Flash EEPROM With a 64K byte address space the PPAGE register is needed to perform on chip memory expansion A program space window of 16K byte pages is located from 8000 to BFFF Three page indices are used to point to one of eight different 16K byte pages They can be viewed as expanded addresses x16 x15 and x14 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Operating Modes 85 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Table 5 3 Program space Page Index Page Index 2 Page Index 1 Page Index 0 PPAGE bit 2 PPAGE bit 1 PPAGE pito os rogram space Page Flash array 0 0 0 16K byte Pa
60. 418 Appendix CGM Practical Aspects MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC912DG128 Section 21 Appendix MC68HC912DG128A Flash 21 1 Contents 21 2 Introduction 212 MORE era er da e REOR eo AD b CROIRE ORAE CORNER 419 ELS TI La d dede iranin oca ae ERR EROR e dedu 420 21 4 Flash EEPROM Control Block isus sas rc RR r4 RR 420 21 5 Flash EEPROM BITRISL paz ob CORO ER CCCII CR 420 21 6 Flash EEPROM Registers asuaaes eb EEX Fh es R s 421 mde c a eens ce end ets TTE 423 21 8 Programming the Flash EEPROM 424 21 9 Erasing the Flash PEPROM icc ceee cede eedeuehwenews 425 21 10 Stop or Wait Mode 00 02 eee 425 The four Flash EEPROM array modules OOFEE32K 01FEE32K 10FEE32K and 11FEE32K for the 68HC912DG128A serve as electrically erasable and programmable non volatile ROM emulation memory The modules can be used for program code that must either execute at high speed or is frequently executed such as operating system kernels and standard subroutines or they can be used for static data which is read frequently The Flash EEPROM module is ideal for program storage for single chip applications allowing for field reprogramming MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Appendix MC68HC912DG128A Flash 419 For More Information On This Product Go to www freescale com Freescale Semi
61. 5 4 3 2 1 Bit 0 EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0 RESET 0 0 0 0 0 0 0 0 Read anytime Write in special modes only SMODN 0 These bits are used for test purposes only In normal modes the bits are forced to zero EEODD Odd Row Programming 0 Odd row bulk programming erasing is disabled 1 Bulk program erase all odd rows EEVEN Even Row Programming 0 Even row bulk programming erasing is disabled 1 Bulk program erase all even rows MARG Program and Erase Voltage Margin Test Enable 0 Normal operation 1 Program and Erase Margin test This bit is used to evaluate the program erase voltage margin EECPD Charge Pump Disable 0 Charge pump is turned on during program erase 1 Disable charge pump EECPRD Charge Pump Ramp Disable Known to enhance write erase endurance of EEPROM cells 0 Charge pump is turned on progressively during program erase 1 Disable charge pump controlled ramp up EECPM Charge Pump Monitor Enable 0 Normal operation Ta 1 Output the charge pump voltage on the IRQ Vpp pin Technical Data MC68HC912DG128 Rev 3 0 130 EEPROM Memory MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EEPROM Memory EEPROM Control Registers EEPROG EEPROM Control 00F3 Bit 7 6 5 4 3 2 1 Bit 0 BULKP 0 0 BYTE ROW ERASE EELAT EEPGM RESET 1 0 0 0 0 0 0 0 BULKP Bulk Era
62. AM6 AM5 AM4 AM3 AM2 AM1 AMO CIDMR5 R 0HD W AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO CIDMR6 R 01E W AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO CIDMR7 R Soir W AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO RESET AM7 AMO Acceptance Mask Bits If a particular bit in this register is cleared this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected The message is accepted if all such bits match If a bit is set it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit NOTE The CIDMRO 7 registers can only be written if the SFTRES bit in CMCRO is set Technical Data MC68HC912DG128 Rev 3 0 352 MSCAN Controller MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MSCAN Controller 17 13 15 msCAN12 Port CAN Control Register PCTLCAN Bit 7 6 5 4 3 2 1 Bit 0 PCTLCAN R 0 0 0 0 0 0 013D W PUPCAN RDPCAN RESET 0 0 0 0 0 0 0 0 The following bits control pins 7 through 2 of Port CAN when they are implemented externally PUPCAN Pull Up Enable Port CAN 0 Pull mode disabled for Port CAN 1 Pull mode enabled for Port CAN RDPCAN Reduced Drive Port CAN 0 R
63. ATDxCTL5 occurs RES10 10 bit Mode 0 8 bit operation 1 10 bit operation SMP1 SMPO Select Sample Time Used to select one of four sample times after the buffered sample and transfer has occurred Table 16 2 Final Sample Time Selection SMP1 SMPO Final Sample Time 0 0 2 A D clock periods 0 1 4 A D clock periods 1 0 8 A D clock periods 1 1 16 A D clock periods Technical Data MC68HC912DG128 Rev 3 0 302 Analog to Digital Converter MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter ATD Registers PRS4 PRS3 PRS2 PRS1 PRSO Select Divide By Factor for ATD P Clock Prescaler The binary value written to these bits 1 to 31 selects the divide by factor for the modulo counter based prescaler The P clock is divided by this value plus one and then fed into a 2 circuit to generate the ATD module clock The divide by two circuit insures symmetry of the output clock signal Clearing these bits causes the prescale value default to one which results in a 2 prescale factor This signal is then fed into the 2 logic The reset state divides the P clock by a total of four and is appropriate for nominal operation at 2 MHz Table 16 3 shows the divide by operation and the appropriate range of system clock frequencies Table 16 3 Clock Prescaler Values Prescale Total D
64. BKGD or TAGHI after reset 3 4 7 Single Wire Background Mode Pin BKGD Technical Data The BKGD pin receives and transmits serial background debugging commands A special self timing protocol is used The BKGD pin has an active pull up when configured as an input BKGD has no pull up control Refer to Development Support MC68HC912DG128 Rev 3 0 46 Pinout and Signal Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pinout and Signal Descriptions Signal Descriptions 3 4 8 External Address and Data Buses ADDR 15 0 and DATA 15 0 External bus pins share functions with general purpose I O ports A and B In single chip operating modes the pins can be used for I O in expanded modes the pins are used for the external buses In expanded wide mode ports A and B are used for multiplexed 16 bit data and address buses PA 7 0 correspond to ADDR 15 8 DATA 15 8 PB 7 0 correspond to ADDR 7 O DATA T7 0 In expanded narrow mode ports A and B are used for the16 bit address bus and an 8 bit data bus is multiplexed with the most significant half of the address bus on port A In this mode 16 bit data is handled as two back to back bus cycles one for the high byte followed by one for the low byte PA 7 0 correspond to ADDR 15 8 and to DATA 15 8 or DATA 7 0 depending on the bus cycle The state of the address pins should be latched at the rising edg
65. Channels 2 and 3 are separate 8 bit PWMs 1 Channels 2 and 3 are concatenated to create one 16 bit PWM channel CONO1 Concatenate PWM Channels 0 and 1 When concatenated channel 0 becomes the high order byte and channel 1 becomes the low order byte Channel 0 output pin is used as the output for this 16 bit PWM bit O of port P Channel 1 clock select control bits determine the clock source Channel 1 output pin becomes a general purpose l O 0 Channels 0 and 1 are separate 8 bit PWMs 1 Channels 0 and 1 are concatenated to create one 16 bit PWM channel PCKA2 PCKAO Prescaler for Clock A Clock A is one of two clock sources which may be used for channels 0 and 1 These three bits determine the rate of clock A as shown in Table 12 1 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Pulse Width Modulator 195 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pulse Width Modulator PCKB2 PCKBO Prescaler for Clock B Clock B is one of two clock sources which may be used for channels 2 and 3 These three bits determine the rate of clock B as shown in Table 12 1 Table 12 1 Clock A and Clock B Prescaler RESET PCKA2 PCKA1 PCKAO Value of PCKB2 PCKB1 PCKBO Clock A B 0 0 0 P 0 0 1 Pi2 0 1 0 P4 0 1 1 P 8 1 0 0 P 16 1 0 1 P 32 1 1 0 P 64 1 1 1 P 7128 Bit 7 6 5 4
66. Data MC68HC912DG128 Rev 3 0 120 Flash Memory MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory Erasing the Flash EEPROM START ERASE TURN ON Vep CLEAR MARGIN FLAG CLEAR ERASE PULSE COUNTER ngp WRITE PPAGE SET ERAS SET LAT WRITE TO ARRAY L SETENPE je DELAY FOR DURATION OF ERASE PULSE tePuLsE CLEAR ENPE SET MARGIN FLAG A DELAY BEFORE VERIFY tvERAsE IS INCREMENT MARGIN FLAG nep COUNTER SET NO READ ARRAY YES DECREMENT nep COUNTER ARRAY ERASED YES YES ARRAY ERASED YES CLEAR LAT TURN OFF Vep ARRAY ERASED ARRAY FAILED TO ERASE Figure 7 2 Erase Sequence Flow MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Flash Memory 121 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory 7 11 Program Erase Protection Interlocks The Flash EEPROM program and erase mechanisms provide maximum protection from accidental programming or erasure The voltage required to program erase the Flash EEPROM Vrp is supplied via an external pin If Vep is not present no programming erasing will occur Furthermore th
67. FEECTL register is set BOOTP Boot Protect The boot blocks are located at E000 FFFF and A000 BFFF for odd program pages for each Flash EEPROM module Since boot programs must be available at all times the only useful boot block is at E000 FFFF location All paged boot blocks can be used as protected program space if desired 0 Enable erase and program of 8K byte boot block 1 Disable erase and program of 8K byte boot block MC68HC912DG128 Rev 3 0 Technical Data Appendix MC68HC912DG128A Flash 421 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Appendix MC68HC912DG128A Flash FEECTL Flash EEPROM Control Register 00F7 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 FEESWAI HVEN 0 ERAS PGM RESET 0 0 0 0 0 0 0 0 This register controls the programming and erasure of the Flash EEPROM FEESWAI Flash EEPROM Stop in Wait Control 0 Do not halt Flash EEPROM clock when the part is in wait mode 1 Halt Flash EEPROM clock when the part is in wait mode HVEN High Voltage Enable This bit enables the charge pump to supply high voltages for program and erase operations in the array HVEN can only be set if either PGM or ERAS are set and the proper sequence for program or erase is followed 0 Disables high voltage to array and charge pump off 1 Enables high voltage to array and charge pump on ERAS Erase Control
68. Freescale Semiconductor Inc Pulse Width Modulator PWM Register Description Bit 7 6 5 4 3 2 1 Bit 0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PPO PWM PWM3 PWM2 PWMI PWMO RESET E PORTP Port P Data Register 0056 PORTP can be read anytime PWM functions share port P pins 3 to 0 and take precedence over the general purpose port when enabled When configured as input a read will return the pin level Port P 7 4 will read as zero because there are no available external pins When configured as output a read will return the latched output data Port P 7 4 will read the last value written A write will drive associated pins only if configured for output and the corresponding PWM channel is not enabled After reset all pins are general purpose high impedance inputs Bit 7 6 5 4 3 2 1 Bit 0 DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDPO RESET 0 0 0 0 0 0 0 0 DDRP Port P Data Direction Register 0057 DDRP determines pin direction of port P when used for general purpose I O Read and write anytime DDRP 7 4 Data Direction Port P pin 7 4 Serve as memory locations since there are no corresponding port pins DDRP 3 0 Data Direction Port P pin 3 0 0 I O pin configured as high impedance input 1 I O pin configured for output MC68HC912DG128 Rev 3 0 Technical Data Pulse Width Modulator 205 For More Information On This P
69. Go to www freescale com Freescale Semiconductor Inc Appendix MC68HC912DG128A EEPROM EEPROM Control Registers If BYTE 1 only the location specified by the address written to the programming latches will be erased The operation will be a byte or an aligned word erase depending on the size of written data ERASE Erase Control 0 EEPROM configuration for programming 1 EEPROM configuration for erasure Read anytime Write anytime if EEPGM 0 Configures the EEPROM for erasure or programming Unless BULKP is set erasure is by byte aligned word row or bulk EELAT EEPROM Latch Control 0 EEPROM set up for normal reads 1 EEPROM address and data bus latches set up for programming or erasing Read anytime Write anytime except when EEPGM 1 or EEDIV 0 BYTE ROW ERASE and EELAT bits can be written simultaneously or in any sequence EEPGM Program and Erase Enable 0 Disables program erase voltage to EEPROM 1 Applies program erase voltage to EEPROM The EEPGM bit can be set only after EELAT has been set When EELAT and EEPGM are set simultaneously EEPGM remains clear but EELAT is set The BULKP AUTO BYTE ROW ERASE and EELAT bits cannot be changed when EEPGM is set To complete a program or erase cycle when AUTO bit is clear two successive writes to clear EEPGM and EELAT bits are required before reading the programmed data When AUTO bit is set EEPGM is automatically cleared after the program
70. Inc Technical Data MC68HC912DG128 Section 3 Pinout and Signal Descriptions 3 1 Contents 3 2 Pin Assignments in 112 pin QFP 2 case ceesse arra 37 Bo Power Supply PINE oo aqoa ace ac ea E HD oes 40 B SUM Descriptions Lia ones nese ERE DIE EORR SERE 42 39 PO ae Lag ed aue do ac n Ete E Re Rl edo bc arua 51 3 2 Pin Assignments in 112 pin QFP The MC68HC912DG128 is available in a 112 pin thin quad flat pack TQFP Most pins perform two or more functions as described in the Signal Descriptions Figure 3 2 shows pin assignments In expanded narrow modes the lower byte data is multiplexed with higher byte data through pins 57 64 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Pinout and Signal Descriptions 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pinout and Signal Descriptions
71. Introduction Section 19 Electrical Specifications 192 InWOQOHOHD sk acicr c d dor ent o Oe e e ERE ORE HEC ee 385 199 Tabl s ol SE uana cre oko ox aod ee Bowed aca c ak aae 386 The MC68HC912DG128 microcontroller unit MCU is a16 bit device composed of standard on chip peripherals including a 16 bit central processing unit CPU12 128 Kbyte flash EEPROM 8K byte RAM 2K byte EEPROM two asynchronous serial communications interfaces SCI a serial peripheral interface SPI an 8 channel 16 bit timer two16 bit pulse accumulators and 16 bit down counter ECT two 10 bit analog to digital converter ADC a four channel pulse width modulator PWM an IIC interface module and two MSCAN modules The chip is the first 16 bit microcontroller to include both byte erasable EEPROM and flash EEPROM on the same device System resource mapping clock generation interrupt control and bus interfacing are managed by the Lite integration module LIM The MC68HC912DG128 has full 16 bit data paths throughout however the multiplexed external bus can operate in an 8 bit narrow mode so single 8 bit wide memory can be interfaced for lower cost systems This section contains the most accurate electrical information for the MC68HC912DG128 microcontroller available at the time of publication The following characteristics are contained in this document MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Electrical Specifications 385 For More Infor
72. KWIFJ 002F KWIFH7 KWIFH6 KWIFH5 KWIFH4 KWIFH3 KWIFH2 KWIFH1 KWIFHO KWIFH 0030 KWPJ7 KWPJ6 KWPJ5 KWPJ4 KWPJ3 KWPJ2 KWPJ1 KWPJO KWPJ 0031 KWPH7 KWPH6 KWPH5 KWPH4 KWPH3 KWPH2 KWPH1 KWPHO KWPH 0032 0 0 0 0 0 0 0 0 Reserved 0033 0 0 0 0 0 0 0 0 Reserved nes Unimplemented Reserved 0038 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYNO SYNR 0039 0 0 0 0 0 REFDV2 REFDV1 REFDVO REFDV 003A TSTOUT7 TSTOUT6 TSTOUT5 TSTOUTA TSTOUT3 TSTOUT2 TSTOUT1 TSTOUTO CGTFLG 003B LOCKIF LOCK 0 0 0 0 LHIF LHOME PLLFLG 003C LOCKIE PLLON AUTO ACQ 0 PSTP LHIE NOLHM PLLCR 003D 0 BCSP BCSS 0 0 MCS 0 0 CLKSEL 003E 0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDVO SLOW 003F OPNLE TRK TSTCLKE TST4 TST3 TST2 TST1 TSTO CGTCTL 0040 CON23 CONO1 PCKA2 PCKA1 PCKAO PCKB2 PCKB1 PCKBO PWCLK 0041 PCLK3 PCLK2 PCLK1 PCLKO PPOL3 PPOL2 PPOL1 PPOLO PWPOL 0042 0 0 0 0 PWENS PWEN2 PWEN1 PWENO PWEN 0043 0 Bit 6 5 4 3 2 1 Bit 0 PWPRES 0044 Bit 7 6 5 4 3 2 1 Bit 0 PWSCALO 0045 Bit 7 6 5 4 3 2 1 Bit 0 PWSCNTO 0046 Bit 7 6 5 4 3 2 1 Bit 0 PWSCAL1 0047 Bit 7 6 5 4 3 2 1 Bit 0 PWSONT 1 0048 Bit 7 6 5 4 3 2 1 Bit 0 PWONTO 0049 Bit 7 6 5 4 3 2 1 Bit 0 PWONT 1 004A Bit 7 6 5 4 3 2 1 Bit 0 PWCNT2 004B Bit 7 6 5 4 3 2 1 Bit 0 PWONT3 004C Bit 7 6 5 4 3 2 1 Bit 0 PWPERO Table 4 1 Register Map Sheet 2 of 10 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Registers 65 For More Info
73. Li g s bz PC 311 Extemal PRI a be ebd tinite p bac eke dedo raa es 312 Message Storage Leia is bi waa CR Oe Io ca pol a PR 313 Identifier Acceptance Filter 00005 318 Ni aid oer oe SERO OECD NE EU E EE ee d22 Protocol Violation Protection s da Xaraaked a e e 324 Low Power Modes ais onde ede ea 08 CROCI ERE Poe aeo 325 ii c4 TTE 329 dec 4l coo CUP cR 329 Memory MaMe a ib e d dd RO ud ER EG p ede E ES ER 332 Programmer s Model of Message Storage 332 Programmer s Model of Control Registers 338 Section 18 Development Support dac e NATAT ET 1 ET T oT 355 Introduction a ennaa naaa 355 Mel ucBon QUEUE s siue P pRPER sige ReRPIGS E WERE d 355 Background Debug Mode Lislsssullsssus 357 MC68HC912DG128 Rev 3 0 12 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents To DORON Sea e OT TOLLIT TIT 375 186 insituchon TOO oui rhe 4a ob es ER ORC ON 4C eR ned 382 Section 19 Electrical Specifications 19 1 XODIBIB sedi Evo EDAD RC use dwinake A Udo 385 19 2 JIBlrodcliolk sa ssec kem Ress EGGARG RE ERES EE RES 385 19 3 Tables of Data i cszsuuuuRuRR RR RR RE Rm RERO 386 Section 20 Appendix CGM Practical Aspects 20 1 COMIS boo cece Rue me RR ASEE S RERRRES ERE RR 407 202 rodul aao prae daccie DEP dL Ee P ddr EWebd
74. MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MC68HC912DG128 12 1 Contents 12 2 Introduction Section 12 Pulse Width Modulator 122 Wee S a d E debat pe o qo RUP CA V Reka 191 12 3 PWM Register Description n sakura darn ee ones 195 12 4 PWM Boundary Cases na dera Y Fa ORC 206 The pulse width modulator PWM subsystem provides four independent 8 bit PWM waveforms or two 16 bit PWM waveforms or a combination of one 16 bit and two 8 bit PWM waveforms Each waveform channel has a programmable period and a programmable duty cycle as well as a dedicated counter A flexible clock select scheme allows four different clock sources to be used with the counters Each of the modulators can create independent continuous waveforms with software selectable duty rates from 0 percent to 100 percent The PWM outputs can be programmed as left aligned outputs or center aligned outputs The period and duty registers are double buffered so that if they change while the channel is enabled the change will not take effect until the counter rolls over or the channel is disabled If the channel is not enabled then writes to the period and or duty register will go directly to the latches as well as the buffer thus ensuring that the PWM output will always be either the old waveform or the new waveform not some variation in between A change in duty or period
75. MSCAN Controller 17 13 3 msCAN12 Module Control Register CMCR1 Bit 7 6 5 4 3 2 1 Bit 0 CMCR1 R 0 0 0 0 0 LOOPB WUPM CLKSRC 0101 W es RESET 0 0 0 0 0 0 0 0 LOOPB Loop Back Self Test Mode When this bit is set the msCAN12 performs an internal loop back which can be used for self test operation the bit stream output of the transmitter is fed back to the receiver internally The RxCAN input pin is ignored and the TxCAN output goes to the recessive state 1 The msCAN 12 behaves as it normally does while transmitting and treats its own transmitted message as a message received from a remote node In this state the msCAN12 ignores the bit sent during the ACK slot of the CAN frame Acknowledge field to ensure proper reception of its own message Both transmit and receive interrupts are generated 0 Normal operation 1 Activate loop back self test mode WUPM Wake Up Mode This flag defines whether the integrated low pass filter is applied to protect the msCAN12 from spurious wake ups see Programmable Wake Up Function 0 msCAN12 will wake up the CPU after any recessive to dominant edge on the CAN bus 1 msCAN12 will wake up the CPU only in the case of dominant pulse on the bus which has a length of at least approximately Twup CLKSRC msCAN12 Clock Source This flag defines which clock source the msCAN12 module is driven from only for system with CGM module see Clock System
76. Mode A single full feature breakpoint which causes the part to enter background debug mode BDM mode may be entered by a breakpoint only if an internal signal from the BDM indicates background debug mode is enabled e Breakpoints are not allowed if the BDM mode is already active Active mode means the CPU is executing out of the BDM ROM e BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM This is important because even if the ENABLE bit in the BDM is negated the CPU actually does execute the BDM ROM code It checks the ENABLE and returns if not set If the BDM is not serviced by the monitor then the breakpoint would be re asserted when the BDM returns to normal CPU flow e There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled 18 5 1 3 BDM Dual Address Mode Technical Data Dual address only breakpoints each of which cause the part to enter background debug mode In the dual mode each address breakpoint is affected consistent across modes by the BKPM bit the BKALE bit and the BKxRW and BKxRWE bits In dual address mode the BKDBE becomes an enable for the second address breakpoint The BKSZ8 bit will have no effect when in a dual address mode BDM mode may be MC68HC912DG128 Rev 3 0 376 Development Support MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Development Support Breakpoints
77. Mode MOMI or SISO In bidirectional mode the SPI uses only one serial data pin for external device interface The MSTR bit decides which pin to be used The MOSI pin becomes serial data I O MOMI pin for the master mode and the MISO pin becomes serial data I O SISO pin for the slave mode The direction of each serial I O pin depends on the corresponding DDRS bit When SPE 1 Master Mode Slave Mode MSTR 1 MSTR 0 Serial Out gt MO Serial In Sl DDRS4 SPI DDRS5 SPI Normal Serial In r MI Serial Out gt SO Mode Serial Out gt MO Serial In Sl DDS4 SPI Biss SPI J Serial In MI Serial Out gt SO SWOM enables open drain output SWOM enables open drain output Serial Out gt MOMI Serial In PS5 DDRS4 SPI DDRS5 SPI Bidirectional REA PS4 Serial Out gt SISO Mode SPC0 1 Serial Out gt MOMI Serial In PS5 DDS4 SPI DDS5 SPI Serial In PS4 Serial Out gt SISO SWOM enables open drain output PS4 becomes GPIO SWOM enables open drain output PS5 becomes GPIO Figure 14 6 Normal Mode and Bidirectional Mode Technical Data MC68HC912DG128 Rev 3 0 266 Multiple Serial Interface MOTOROLA For More Information On This Product Go to www freescale com Freescale
78. More Information On This Product Go to www freescale com Address 0000 0001 0002 0003 0004 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 0023 0024 Freescale Semiconductor Inc Bit 7 6 5 4 3 2 1 Bit 0 Name PA7 PA6 PA5 PA4 PA3 PA2 PA PAO PORTA PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PORTB DDA7 DDA6 DDAS5 DDA4 DDA3 DDA2 DDA1 DDAO DDRA DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDBO DDRB 0 0 0 0 0 0 0 0 Reserved PE7 PE6 PE5 PE4 PE3 PE2 PE1 PEO PORTE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 0 0 DDREO NDBE CGMTE PIPOE NECLK LSTRE RDWE CALE DBENE PEAR SMODN MODB MODA ESTR IVIS EBSWAI EMK EME MODE PUPK PUPJ PUPH PUPE 0 0 PUPB PUPA PUCR RDPK RDPJ RDPH RDPE 0 0 RDPB RDPA RDRIV 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 Reserved RAM15 RAM14 RAM13 0 0 0 0 0 INITRM REG15 REG14 REG13 REG12 REG11 0 0 MMSWAI INITRG EE15 EE14 EE13 EE12 0 0 0 EEON INITEE ROMTST NDRF RFSTR1 RFSTRO EXSTR1 EXSTRO ROMHM ROMON MISC RTIE RSWAI RSBCK Reserved RTBYP RTR2 RTR1 RTRO RTICTL RTIF 0 0 0 0 0 0 0 RTIFLG CME FCME FCMCOP WCOP DISR CR2 CR1 CRO COPCTL Bit 7 6 5 4 3 2 1 Bit 0 COPRST ITE6 ITE8 ITEA ITEC ITEE ITFO ITF
79. NOSHW cleared the regular EEPROM array bytes at address 0FCO and 0FC1 are not visible The SHADOW word is accessed instead for both read and program erase operations Bits 7 4 from MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Appendix MC68HC912DG128A EEPROM 431 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix MC68HC912DG128A EEPROM NOTE NOTE Technical Data the high byte of the SHADOW word 0FCO are loaded to EEMCR 7 4 Bits 1 0 from the high byte of the SHADOW word 0FCO are loaded to EEDIVH 1 0 Bits 7 0 from the low byte of the SHADOW word 0FC1 are loaded to EEDIVL 7 0 BULK program erase only applies if SHADOW word is enabled Bit 6 from high byte of SHADOW word should not be programmed in order to have the full EEPROM array visible EESWAI EEPROM Stops in Wait Mode 0 The module is not affected during WAIT mode 1 The module ceases to be clocked during WAIT mode Read and write anytime The EESWAI bit should be cleared if the WAIT mode vectors are mapped in the EEPROM array PROTLCK Block Protect Write Lock 0 Block protect bits and bulk erase protection bit can be written 1 Block protect bits are locked Read anytime Write once in normal modes SMODN 1 set and clear any time in special modes SMODN 0 DMY Dummy bit Read and write anytime MC68HC912DG128 Rev 3 0 432 Appendix MC68HC912DG128A E
80. OL7 OM6 OL6 OM5 OL5 OM4 OL4 RESET 0 0 0 0 0 0 0 0 TCTL1 Timer Control Register 1 0088 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Enhanced Capture Timer 221 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Enhanced Capture Timer Bit 7 6 5 4 3 2 1 Bit 0 OM3 OL3 OM2 OL2 OM1 OL1 OMO OLO RESET 0 0 0 0 0 0 0 0 TCTL2 Timer Control Register 2 0089 Read or write anytime OMn Output Mode OLn Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCn compare When either OMn or OLn is one the pin associated with OCn becomes an output tied to OCn regardless of the state of the associated DDRT bit NOTE Toenable output action by OMn and OLn bits on the timer port the corresponding bit in OC7M should be cleared Table 13 1 Compare Result Output Action OMn OLn Action Timer disconnected from output pin logic Toggle OCn output line Clear OCn output line to zero Set OCn output line to one O O O To operate the 16 bit pulse accumulators A and B PACA and PACB independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits lOSn 1 OMn 0 and OLn 0 OC7V7 or OC7MO in the OC7M register must also be cleared Technical Data MC68HC912DG128 Rev 3
81. PAD11 PAD10 PORTAD1 01FO Bit 15 14 13 12 11 10 9 Bit 8 ADR10H 01F1 Bit 7 Bit 6 0 0 0 0 0 0 ADR10L 01F2 Bit15 14 13 12 11 10 9 Bit 8 ADR11H 01F3 Bit 7 Bit 6 0 0 0 0 0 0 ADR11L 01F4 Bit15 14 13 12 11 10 9 Bit 8 ADR12H 01F5 Bit 7 Bit 6 0 0 0 0 0 0 ADR12L 01F6 Bit15 14 13 12 11 10 9 Bit 8 ADR13H 01F7 Bit 7 Bit 6 0 0 0 0 0 0 ADR13L 01F8 Bit15 14 13 12 11 10 9 Bit 8 ADR14H 01F9 Bit 7 Bit 6 0 0 0 0 0 0 ADR14L 01FA Bit15 14 13 12 11 10 9 Bit 8 ADR15H 01FB Bit 7 Bit 6 0 0 0 0 0 0 ADR15L 01FC Bit15 14 13 12 11 10 9 Bit 8 ADR16H 01FD Bit 7 Bit 6 0 0 0 0 0 0 ADR16L 01FE Bit15 14 13 12 11 10 9 Bit 8 ADR17H 01FF Bit 7 Bit 6 0 0 0 0 0 0 ADR17L Table 4 1 Register Map Sheet 8 of 10 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Registers 71 For More Information On This Product Go to www freescale com Address 0200 02FF 0300 0301 0302 0303 0304 0305 0306 0307 0308 0309 030D 030E 030F 0310 0311 0312 0313 0314 0315 0316 0317 0318 0319 031A Freescale Semiconductor Inc Bit 7 6 5 4 3 2 1 Bit 0 Name Unimplemented Reserved 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES C1MCRO 0 0 0 0 0 LOOPB WUPM CLKSRC CIMCR1 SJW1 SJWO BRP5 BRP4 BRP3 BRP2 BRP1 BRPO C1BTRO SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG
82. Pin Name aoe Number Description 112 pin XIRQ PEO 56 Provides a means of requesting asynchronous nonmaskable interrupt requests after reset initialization During reset this pin determines special or normal operating mode After SMODN o reset single wire background interface pin is dedicated to the BKGD 23 i a background debug function Pin function TAGHI used in instruction TAGHI tagging See Development Support IX 2 0 PK 2 0 109 111 Page Index register emulation outputs ECS PK7 108 Emulation Chip select PW 3 0 PP 3 0 112 1 3 Pulse Width Modulator channel outputs SS PS7 96 Slave select output for SPI master mode input for slave mode or master mode SCK PS6 95 Serial clock for SPI system SDO MOSI PS5 94 Master out slave in pin for serial peripheral interface SDI MISO PS4 93 Master in slave out pin for serial peripheral interface TxD1 PS3 92 SCI transmit pin RxD1 PS2 91 SCI1 receive pin TxDO PS1 90 SCIO transmit pin RxDO PSO 89 SCIO receive pin IoC 7 0 PT 7 0 18 15 7 4 Pins used for input capture and output compare in the timer and pulse accumulator subsystem 84 82 80 7 AN1 7 0 PAD1 7 0 8 76 74 72 Analog inputs for the analog to digital conversion module 1 70 83 81 79 7 ANO 7 0 PADO 7 0 7 75 73 71 Analog inputs for the analog to digital conversion module 0 69 TxCAN1 102 MSCAN1 transmit pin RxCAN1 103 MSCAN1 receive pin TxCANO 104 MSCANO transmit pin RxCANO 105 MSCANO receive pin SCL PIB
83. RDPP Reduced Drive of Port P 0 All port P output pins have normal drive capability 1 All port P output pins have reduced drive capability PUPP Pull Up Port P Enable 0 All port P pins have an active pull up device disabled 1 All port P pins have an active pull up device enabled PSBCK PWM Stops while in Background Mode 0 Allows PWM to continue while in background mode 1 Disable PWM input clock when the part is in background mode Bit 7 6 5 4 3 2 1 Bit 0 DISCR DISCP DISCAL 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 PWTST PWM Special Mode Register Test 0055 Read anytime but write only in special mode SMODN 0 These bits are available only in special mode and are reset in normal mode DISCR Disable Reset of Channel Counter on Write to Channel Counter 0 2 Normal operation Write to PWM channel counter will reset channel counter 1 Write to PWM channel counter does not reset channel counter DISCP Disable Compare Count Period 0 Normal operation 1 In left aligned output mode match of period does not reset the associated PWM counter register DISCAL Disable Load of Scale Counters on Write to the Associated Scale Registers 0 Normal operation 1 Write to PWSCALO and PWSCAL1 does not load scale counters Technical Data MC68HC912DG128 Rev 3 0 204 Pulse Width Modulator MOTOROLA For More Information On This Product Go to www freescale com
84. Receiver Interrupt Enable Register CRIER Bit 7 6 5 4 3 2 1 Bit 0 CRIER R s0105 lw WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE RESET 0 0 0 0 0 0 0 0 WUPIE Wake up Interrupt Enable 0 No interruptis generated from this event 1 A wake up event results in a wake up interrupt RWRNIE Receiver Warning Interrupt Enable 0 No interruptis generated from this event 1 A receiver warning status event results in an error interrupt MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA MSCAN Controller 345 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MSCAN Controller TWRNIE Transmitter Warning Interrupt Enable 0 No interruptis generated from this event 1 A transmitter warning status event results in an error interrupt RERRIE Receiver Error Passive Interrupt Enable 0 No interruptis generated from this event 1 A receiver error passive status event results in an error interrupt TERRIE Transmitter Error Passive Interrupt Enable 0 No interruptis generated from this event 1 A transmitter error passive status event results in an error interrupt BOFFIE BUSOFF Interrupt Enable 0 No interruptis generated from this event 1 A BUSOFF event results in an error interrupt OVRIE Overrun Interrupt Enable 0 No interruptis generated from this event 1 An overrun event results in an error
85. Registers 148 10 4 Key Wake Up Input Filter 152 The MC68HC912DG128 offers 16 additional I O ports with key wake up capability The key wake up feature of the MC68HC912DG128 issues an interrupt that will wake up the CPU when it is in the STOP or WAIT mode Two ports are associated with the key wake up function port H and port J Port H and port J wake ups are triggered with a rising or falling signal edge For each pin which has an interrupt enabled there is a path to the interrupt request signal which has no clocked devices when the part is in stop mode This allows an active edge to bring the part out of stop Digital filtering is included to prevent pulses shorter than a specified value from waking the part from STOP An interrupt is generated when a bit in the KWIFH or KWIFJ register and its corresponding KWIEH or KWIEJ bit are both set All 16 bits pins share the same interrupt vector Key wake ups can be used with the pins configured as inputs or outputs Default register addresses as established after reset are indicated in the following descriptions For information on re mapping the register block refer to Operating Modes MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA I O Ports with Key Wake up 147 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc I O Ports with Key Wake up 10 3 Key Wake up and Port Registers
86. Stress Test High Voltage Status 0 High voltage not present during stress test 1 High voltage present during stress test FENLV Enable Low Voltage 0 Disables low voltage transistor in current reference circuit 1 Enables low voltage transistor in current reference circuit FDISVFP Disable Status Vep Voltage Lock When the Vep pin is below normal programming voltage the Flash module will not allow writing to the LAT bit the user cannot erase or program the Flash module The FDISVFP control bit enables writing to the LAT bit regardless of the voltage on the Vpp pin 0 Enable the automatic lock mechanism if Vep is low 1 Disable the automatic lock mechanism if Vep is low MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Flash Memory 111 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Flash Memory Technical Data VTCK V Check Test Enable When VTCK is set the Flash EEPROM module uses the Vrpp pin to control the control gate voltage the sense amp time out path is disabled This allows for indirect measurements of the bit cells program and erase threshold If Vep lt Vzggy breakdown voltage the control gate will equal the Vep voltage If Vep gt Vzprx the control gate will be regulated by the following equation Vcontrol gate Vzpgny 0 44 x Vep Vzgnk 0 V1 test disable 1 V4 test enable STRE Spare Test Row Enable The spare test
87. Technical Data MC68HC912DG128 9 1 Contents 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 9 10 9 2 Introduction Section 9 Resets and Interrupts e a a eso QE de Ron pere ere he hehe T 133 Maskable interrupts coc o eee en he eRe eo e a 134 Latching of Interrupts 2d crack P 4 diede OR IR EUR oos 134 Interrupt Control and Priority Registers 135 Interrupt test registers Lipari ra IO CR ee eer dans ER 138 ico e 137 Effects UL RESel Lor ken dar wol do EU du pod dolo dox 138 Register Stacking ce aodio ed oe ERECTO edd e RE 140 Important User Information lllllllssesssn 142 CPU12 exceptions include resets and interrupts Each exception has an associated 16 bit vector which points to the memory location where the routine that handles the exception is located Vectors are stored in the upper 128 bytes of the standard 64K byte address map The six highest vector addresses are used for resets and non maskable interrupt sources The remainder of the vectors are used for maskable interrupts and all must be initialized to point to the address of the appropriate service routine MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Resets and Interrupts 133 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resets and Interrupts 9 2 1 Exception Priority A hardware priority hierarchy determines which reset or interru
88. Used in conjunction with the BKDBE bit which should be set 0 High byte of data bus bits 15 8 are compared to BRKDH 1 High byte is not used in comparisons BKMBL Breakpoint Mask Low Disables the matching of the low byte of data when in full breakpoint mode Used in conjunction with the BKDBE bit which should be set 0 Low byte of data bus bits 7 0 are compared to BRKDL 1 Low byte is not used in comparisons MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Development Support 379 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Development Support BK1RWE R W Compare Enable Enables the comparison of the R W signal to further specify what causes a match This bit is NOT useful in program breakpoints or in full breakpoint mode This bit is used in conjunction with a second address in dual address mode when BKDBE 1 0 R W is not used in comparisons 1 R W is used in comparisons BK1RW R W Compare Value When BK1RWE 1 this bit determines the type of bus cycle to match 0 A write cycle will be matched 1 A read cycle will be matched BKORWE R W Compare Enable Enables the comparison of the R W signal to further specify what causes a match This bit is not useful in program breakpoints 0 R W is not used in the comparisons 1 R W is used in comparisons BKORW R W Compare Value When BKORWE 1 this bit determines the type of bus
89. Z J A 0 10 T PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0 46 pot SEATING T PLANE le MILLIMETERS T DIM MN MAX A 20 000 BSC Ai 10 000 BSC B 20 000 BSC Bi 10 000 BSC C 1 600 Ct 0 050 0 150 C2 1350 1 450 D 0270 0 370 E 0450 0 750 F 0 270 0 330 G 0 650 BSC J 0 090 0 170 K 0 500 REF 0 25 P 0 325 BSC I R1 0 100 0 200 GAGE PLANE R2 0 100 0 200 S 22 000 BSC si 11 000 BSC v 22 000 BSC vi 11 000 BSC Y 0 250 REF H 1 000 REF AA 0 090 0 160 0 o 8 91 CR RR d VIEW AB e2 11 13 e3 1 13 Figure 3 2 112 pin QFP Mechanical Dimensions case no 987 MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Pinout and Signal Descriptions 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pinout and Signal Descriptions 3 3 Power Supply Pins Power and ground pins are described below and summarized in Table 3 1 3 3 1 Internal Power Vpp and Ground Vss Power is supplied to the MCU through Vpp and Vss Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them
90. address mode 0 BRKDL will not be used to compare to the address bus 1 BRKDL will be used to compare to the address bus BKOALE Breakpoint 0 Range Control Valid in all modes 0 BRKAL will not be used to compare to the address bus 1 BRKAL will be used to compare to the address bus Technical Data MC68HC912DG128 Rev 3 0 378 Development Support MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Development Support Breakpoints Table 18 10 Breakpoint Address Range Control RESET BK1ALE BKOALE Address Range Selected 0 Upper 8 bit address only for full mode or dual mode BKPO 1 Full 16 bit address for full mode or dual mode BKPO 0 Upper 8 bit address only for dual mode BKP1 1 Full 16 bit address for dual mode BKP1 Bit 7 6 5 4 3 2 1 Bit 0 0 BKDBE BKMBH BKMBL BK1RWE BK1RW BKORWE BKORW 0 0 0 0 0 0 BRKCT1 Breakpoint Control Register 1 0021 This register is read write in all modes BKDBE Enable Data Bus Enables comparing of address or data bus values using the BRKDH L registers 0 The BRKDH L registers are not used in any comparison 1 The BRKDH L registers are used to compare address or data depending upon the mode selections BKEN1 0 BKMBH Breakpoint Mask High Disables the comparing of the high byte of data when in full breakpoint mode
91. as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded 3 3 2 External Power Vppx and Ground Vssx External power and ground for I O drivers Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded 3 3 3 Vpp4 Vssa Provides operating voltage and ground for the analog to digital converter This allows the supply voltage to the ATD to be bypassed independently Connecting Vppa to Vpp if the ATD modules are not used will not result in an increase of power consumption 3 3 4 Analog to Digital Reference Voltages Vnu Vni VRHo Veto reference voltage high and low for ATD converter 0 Vrui Vai reference voltage high and low for ATD converter 1 If the ATD modules are not used leaving Vay connected to Vpp will not result in an increase of power consumption Technical Data MC68HC912DG128 Rev 3 0 40 Pinout and Signal Descriptions MOTOROLA For More Information On This Product Go to www freescale com 3 3 5 Vpppri VssPLL 3 3 6 XFC 3 3 7 Vep NOTE Freescale Semiconductor Inc Pinout and Signal Descriptions Power Supply Pins Provides operating voltage and ground for the Phase Locked Loop This allows the supply voltage to the PLL to be bypassed independentl
92. can be forced into immediate effect by writing the new value to the duty and or period registers and then writing to the counter This causes the counter to reset and the new duty and or period values to be latched In addition since the counter is readable it is MC68HC912DG128 Rev 3 0 Technical Data MOTOROLA Pulse Width Modulator 191 For More information On This Product Go to www freescale com Freescale Semiconductor Inc Pulse Width Modulator possible to know where the count is with respect to the duty value and software can be used to make adjustments by turning the enable bit off and on The four PWM channel outputs share general purpose port P pins Enabling PWM pins takes precedence over the general purpose port When PWM channels are not in use the port pins may be used for discrete input output CLOCK SOURCE ECLK or Scaled ECLK CENTR 0 T5 FROM PORT P UP DOWN DATA REGISTER GATE gt PWCNTx m CLOCK EDGE SYNC RESET 8 BIT COMPARE PWDTYx gt s Q MUX MUX Q TO PIN 8 BIT COMPARE R i DRIVER gt PWPERx e SBO PWENx SYNC PPOL 0 PPOL 1 r PWDTY C PWPRER Figure 12 1 Block Diagram of PWM Left Aligned Output Channel Technical Data MC68HC912DG128 Rev 3 0 192 Pulse
93. cece eee ggrrzzizgiuuc gt gt jg ud Z z glg zlej ES ERE EISE Ssg P BOs na ES tc cc cc aa oc 888 28 LLAI nir Figure 3 1 MC68HC912DG128 Pin Assignments in 112 pin QFP Technical Data MC68HC912DG128 Rev 3 0 38 Pinout and Signal Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pinout and Signal Descriptions Pin Assignments in 112 pin QFP 4X O 020 T E M N 4X 28 TIPS 0 20 IT MN PIN 1 112 85 IDENT ON nannnnannnnnnnannnnnnnnn zd 1 OQ EU VIEW Y p l E E 7 L E M BUM 28 ES 57 PO TEL Y 2 J 0 13 amp T M N N SECTION J1 J1 34 A1 ROTATED 90 COUNTERCLOCKWISE HO S1 4 e A gt NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 DATUMS L M AND N TO BE DETERMINED AT SEATING PLANE DATUM T 4 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE DATUM T 5 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE VIEW AB PROTRUSION IS 0 25 PER SIDE DIMENSIONS A AND B INCLUDE MOLD MISMATCH 6 DIMENSION D DOES NOT INCLUDE DAMBAR x 112X PROTRUSION ALLOWABLE DAMBAR
94. cycle to match on 0 Write cycle will be matched 1 Read cycle will be matched Table 18 11 Breakpoint Read Write Control BK1RWE BK1RW BKORWE BKORW Read Write Selected 0 x R W is don t care for full mode or dual mode BKPO 1 0 R W is write for full mode or dual mode BKPO 1 1 R W is read for full mode or dual mode BKPO 0 X R W is don t care for dual mode BKP1 1 0 R W is write for dual mode BKP1 1 1 R W is read for dual mode BKP1 Technical Data MC68HC912DG128 Rev 3 0 380 Development Support MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Development Support Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 RESET 0 0 0 0 0 0 0 0 BRKAH Breakpoint Address Register High Byte 0022 These bits are used to compare against the most significant byte of the address bus Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 RESET 0 0 0 0 0 0 0 0 BRKAL Breakpoint Address Register Low Byte 0023 These bits are used to compare against the least significant byte of the address bus These bits may be excluded from being used in the match if BKOALE 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 RESET 0 0 0 0 0 0 0 0 BRKDH Breakpoint Data Register High Byte 0024 These
95. deed eee dew 280 Flow Chart of Typical IIC Interrupt Routine 295 Analog to Digital Converter Block Diagram 298 The CAN SIS 2 dedezsad eR Re WE dE d ndr enr d ndr 313 User Model for Message Buffer Organization 316 32 bit Maskable Identifier Acceptance Filters 320 16 bit Maskable Acceptance Filters 320 8 bit Maskable Acceptance Filters 321 SLEEP Request Acknowledge Cycle 327 Clocking Ge dues tima aenak eae oes E A 329 Segments within the Bit Time 0 331 CAN Standard Compliant Bit Time Segment Settings 331 msc ANTZ Memory Mab wc ica deciatuencesenes a Odes 332 Message Buffer Organization 20 5 333 Receive Transmit Message Buffer Extended Identifier 334 Standard Identifier Mapping 0 335 Identifier Acceptance Registers 1st bank 351 Identifier Acceptance Registers 2nd bank 451 Identifier Mask Registers 1st bank 352 Identifier Mask Registers 2nd bank 352 BDM Host to Target Serial Bit Timing 359 BDM Target to Host Serial Bit Timing Logic 1 359 BDM Target to Host Serial Bit Timing Logic 0 360 Veo Conditioning LAU s i324 ub arduo e 3 1 rd ecies 393 Vep Operating PaDG ucdassakun d wk A hd Rd aa de hex Ran 394 jug 65 656 meat cpm 395 P
96. drain MC68HC912DG128 Rev 3 0 358 Development Support MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Development Support Background Debug Mode BKGD pin during host to target