ANALOG DEVICES ADP3166* 5-Bit Programmable 2- 3- 4-Phase Synchronous Buck Controller handbook
Contents
1. nmr X tgp X Ossr loc XVcc 18 Also shown is the standby dissipation factor Ico X Voc for the driver For the ADP3418 the maximum dissipation should be less than 400 mW For our example with 7 mA 22 8 nC and Qgsr 34 3 nC we find 265 mW in each driver which is below the 400 mW dissipation limit See the ADP3418 data sheet for more details REV 0 ADP3166 Ramp Resistor Selection The ramp resistor is used for setting the size of the internal PWM ramp The value of this resistor is chosen to provide the best combination of thermal balance stability and transient response The following expression is used for determining the optimum value 1 Rp 3x Ap X Rps XCR 0 2 x 600nH 19 R 381 S 3x5x4 2mW x 5pF where is the internal ramp amplifier gain Ap is the current balancing amplifier gain Rps is the total low side MOSFET on resistance and is the internal ramp capacitor value The closest standard 196 resistor value is 383 kQ The internal ramp voltage magnitude can be calculated using _ Ag X 1 D XVyjp VR X fw 0 2x 1 0 125 x1 5 V 20 R 0 41V 383 kQ x5 pF 330 kHz The size of the internal ramp can be made larger or smaller If it is made larger stability and transient response will improve but thermal balance will degrade Conversely if the ramp is made smaller thermal balance will improve at the s2. 5 o 4 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 0 50 100 150 200 250 300 MASTER CLOCK FREQUENCY MHz RT VALUE TPC 1 Supply Current vs Master Clock Frequency TPC 2 Master Clock Frequency vs CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the ADP3166 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING A SENSITIVE DEVICE REV 0 ADP3166 ADP3166 Te ADP3166 3 5 BIT CODE 4 6 CROWBAR 10kQ 200kQ 100nF AVfe FB 14 RAMPADJ ILIMIT 15 Test Circuit 1 Closed Loop Output Voltage Accuracy Test Circuit 3 Positioning Voltage Test Circuit ADP3166 12V 39kQ 1kQ CSCOMP 1V os 7 40 Test Circuit 2 Positioning Amplifier Vos Test Circuit REV 0 B5 ADP3166 PIN CONFIGURATION RU 28 1 166 VIDO TOP VIEW Not to Scale 14 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Function 1 5 VID4 VIDO Voltage Identification DAC Inputs These five pins are pulled up to an internal reference providing a logic 1 if l
3. ADP3168 0 ANALOG DEVICES 9 Bit Programmable 2 3 4 Phase Synchronous Buck Controller ADP3166 FEATURES Selectable 2 3 or 4 Phase Operation at up to 1 MHz per Phase Differential Sensing Error 1 over Temperature Logic Level PWM Outputs for Interface to External High Power Drivers Active Current Balancing between Output Phases Built in Power Good Blanking Supports On the Fly VID Code Changes 5 Bit Digitally Programmable 0 8 V to 1 55 V Output Short Circuit Protection with Programmable Latch Off Delay Overvoltage Protection Crowbar Logic Output APPLICATIONS Desktop PC Power Supplies Next Generation AMD Processors VRM Modules GENERAL DESCRIPTION The ADP3166 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance AMD processors It uses an internal 5 bit DAC to read a voltage identification VID code directly from the pro cessor which is used to set the output voltage between 0 8 V and 1 55 V The ADP3166 also uses a multimode PWM architecture to drive the logic level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency The phase relationship of the output signals can be programmed to provide 2 3 or 4 phase operation allowing for the construction of up to four complementary buck switch ing stages The ADP3166 includes prog
4. Table I VID Code vs Output Voltage VIDA VID3 VID2 VID1 VIDO V 1 1 1 1 1 No CPU 1 1 1 1 0 0 800 1 1 1 0 1 0 825 1 1 1 0 0 0 850 1 1 0 1 1 0 875 1 1 0 1 0 0 900 1 1 0 0 1 0 925 1 1 0 0 0 0 950 1 0 1 1 1 0 975 1 0 1 1 0 1 000 1 0 1 0 1 1 025 1 0 1 0 0 1 050 1 0 0 1 1 1 075 1 0 0 1 0 1 100 1 0 0 0 1 1 125 1 0 0 0 0 1 150 0 1 1 1 1 1 175 0 1 1 1 0 1 200 0 1 1 0 1 1 225 0 1 1 0 0 1 250 0 1 0 1 1 1 275 0 1 0 1 0 1 300 0 1 0 0 1 1 325 0 1 0 0 0 1 350 0 0 1 1 1 1 375 0 0 1 1 0 1 400 0 0 1 0 1 1 425 0 0 1 0 0 1 450 0 0 0 1 1 1 475 0 0 0 1 0 1 500 0 0 0 0 1 1 525 0 0 0 0 0 1 550 Output Voltage Differential Sensing The ADP3166 combines differential sensing with a high accu racy VID DAC and reference and a low offset error amplifier to maintain a worst case specification of 1 differential sensing error over its full operating output voltage and temperature range The output voltage is sensed between the FB and FBRTN pins FB should be connected through a resistor to the regulation point usually the remote sense pin of the micropro cessor FBRTN should be connected directly to the remote sense ground point The internal VID DAC and precision refer ence are referenced to FBRTN which has a minimal current of 100 to allow accurate remote sensing The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage Output Current Sensing The
5. Figure 5 Transient Setting Waveform 21 For load release see Figure 5 if VTRANREL is larger than Vypani refer to Figure 4 there is not enough output capacitance Either more capacitance is needed or it is necessary to make the inductor values smaller if inductors are changed it is necessary to start design over using the spreadsheet and this tuning guide LAYOUT AND COMPONENT PLACEMENT THERMISTOR SWITCH NODE PLANES 12V CONNECTOR INPUT POWER PLANE ri WOOO POWER PLANE KEEP OUT AREA Figure 6 Layout Recommendations KEEP OUT AREA General Recommendations The following guidelines are recommended for optimal performance of a switching regulator in a PC system Key layout issues are illustrated in Figure 6 18 For good results at least a four layer PCB is recommended This should allow the needed versatility for control circuitry interconnections with optimal placement power planes for ground input and output power and wide interconnection traces in the rest of the power delivery current paths Keep in mind that each square unit of 1 ounce copper trace has a resistance of 0 53 mQ at room temperature Whenever high currents must be routed between PCB lay ers vias should be used liberally to create several parallel current paths so that the resistance and inductance intro duced by these current paths is minimized and the via current rating is n
6. ponent parasitic effects see the Tuning Procedure section The compensation values can then be solved using the following C _ Rop XT 47 D _ 3xl9mQx8 70us _ 30 36 0mQx2 00kQ 099 PF T _ 1 3145 Cp 17 655 pF 2 00kQ R 31 T _ 1 315 655 Rg 2 00kQ P 62 16 Choosing the closest standard values for these components yields Cy 680 pF 7 32 680 Crp 18 pF Figure 3 shows the typical transient response using the compen sation values Cry Selection and Input Current di dt Reduction In continuous inductor current mode the source current of the high side MOSFET is approximately a square wave with a duty ratio equal to n X Vour V and an amplitude one nth of the maximum output current To prevent large voltage transients a low ESR input capacitor sized for the maximum rms current must be used The maximum rms capacitor current is given by Icrus DX Io X nxD I 0 125x 56A x 1 1 9 05A ES 0 x X11 1 M CRIS 3x 125 Note that the capacitor manufacturer s ripple current ratings are often based on only 2 000 hours of life This makes it advisable REV 0 ADP3166 to further derate the capacitor or to choose a capacitor rated at a higher temperature than required Several capacitors may be placed in parallel to meet size or height requirements in the design In this example the input capacitor b
7. 10 sec 300 C Vapor Phase 00 S6C cese s rere alate Ne 215 Infrared 15 S66 sae Y RADO EY Yu 220 CROWBAR PWMI to PWM4 0 3 V to 5 5 V Stresses above those listed under Absolute Maximum Ratings may cause perma SW1 to SW4 5 V to 25 V nent damage to the device This is a stress rating only Functional operation of the All Other Inputs and Outputs 0 3 V to VCC 0 3 V device at these or any other conditions above those listed in the operational Operating Ambient Temperature Range 0 to 85 sections of this specification is not implied Exposure to absolute maximum rating OMEN conditions for extended periods may affect device reliability Absolute maximum Operating Junction Temperature 125 ly individually onl bination Unl herwi ified all 2 E ratings apply individually only not in combination Unless otherwise specified a Storage Temperature Range 65 C to 150 other voltages are referenced to GND COEM d EHEMALS 100 C W ORDERING GUIDE Temperature Package Quantity Model Range Options per Reel ADP3166JRU REEL7 0 C to 85 C RU 28 TSSOP 28 1000 ADP3166JRU REEL 0 C to 85 C RU 28 TSSOP 28 2500 4 25 C 4 PHASE OPERATION lt x o 0 2 2 3 t 2 5 o x gt 8
8. AMPLIFIER Offset Voltage Vos csA CSSUM CSREF see Test Circuit 2 3 3 mV Input Bias Current Ipras csA 20 100 nA Gain Bandwidth Product GBW sa 20 MHz Slew Rate 10 50 V us Input Common Mode Range CSSUM and CSREF 0 3 V Positioning Accuracy See Test Circuit 3 76 80 84 mV Output Voltage Range 100 uA 0 05 3 3 V Output Current 500 uA CURRENT BALANCE CIRCUIT Common Mode Range Vsw x cM 600 200 mV Input Resistance Rswoo SW X 0V 24 30 36 Input Current Iswx SW X 0V 5 7 9 uA Input Current Matching Alswoo SW X 0V 5 5 CURRENT LIMIT COMPARATOR Output Voltage Normal Mode EN 22V 2 9 3 3 1 V In Shutdown EN lt 0 8 V 100 uA 400 mV Output Current Normal Mode EN gt 2 V Roumrr 250 kQ 12 uA Maximum Output Current EN gt 2V 60 Current Limit Threshold Voltage Vcr VcSREF Rium 250 kQ 105 125 145 mV Current Limit Setting Ratio Vculmiwrr 10 4 mV uA Latch Off Delay Threshold In current limit 1 7 1 8 1 9 V Latch Off Delay Time tsET DLY Rpgray 250 Cpgray 4 7 nF 600 Us REV 0 ADP3166 Parameter Symbol Conditions Min Typ Max Unit SOFT START Output Current Soft Start Mode Ipgray ss During start up DELAY 2 8 V 15 20 25 uA Soft Start Delay Time tpELAY SS 250 kQ CpELAY 4 7 nF 350 Us VID Code 01111 ENABLE INP
9. Res 1 6 mQ 150 100 0 145 520 Next use Equation 6 to solve for Ge zo S000 1 6mQ x 100 kQ 12 It is best to have a dual location for Cos in the layout so stan dard values can be used in parallel to get as close to the value desired For this example choosing Cc to be a 1 5 nF and 2 2 nF in parallel is a good choice For best accuracy should be 10 capacitor The closest standard 1 value for is 147 KQ Inductor DCR Temperature Correction With the inductor s DCR being used as the sense element and copper wire being the source of the DCR one needs to com pensate for temperature changes of the inductor s winding Fortunately copper has a well known temperature coefficient of 0 39 C If Rcs is designed to have an opposite and equal percentage change in resistance to that of the wire it will cancel the tem perature variation of the inductor s DCR Due to the nonlinear nature of NTC thermistors resistors Rcs and Rcs see Figure 2 are needed to linearize the NTC and produce the desired tem perature tracking PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW SIDE MOSFET TO TO SWITCH Vour N NODES SENSE ADP3166 CSCOMP KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES Figure 2 Temperature Compensation Circuit Values The following procedure and expressions will yield values to use f
10. circuit has caused the output voltage to drop below the PWRGD threshold then a soft start cycle is initiated The latch off function can be reset by either removing and reapplying VCC to the ADP3166 or by pulling the EN pin low for a short time T o disable the short circuit latch off function the external resistor to ground should be left open and a large greater than 1 resistor should be connected from to DELAY This prevents the DELAY capacitor from discharging so the 1 8 V threshold is never reached The resistor will have an impact on the soft start time because the current through it will add to the internal 20 current source During startup when the output voltage is below 200 mV a secondary current limit is active This is necessary because the voltage swing of CSCOMP cannot go below ground This sec ondary current limit controls the internal COMP voltage to the PWM comparators to 2 V This will limit the voltage drop across the low side MOSFETs through the current balance circuitry REV 0 ADP3166 Dynamic VID The ADP3166 incorporates the ability to dynamically change the VID input while the controller is running This allows the output voltage to change while the supply is running and sup plying current to the load This is commonly referred to as VID on the fly OTF A VID OTF can occur under either light load or heavy load conditions The processor signals the controller by changing the VID inputs i
11. mV Maximum dynamic output voltage error E Vpggg 70 mV Error voltage allowed for controller and ripple Vgggg t20mV Maximum output current Io 56 Maximum output current step 24 Static output droop resistance Ro based on 2 No load output voltage set at upper output voltage limit Von VsERR VRERR 1 530 V b Full load output voltage set at lower output voltage limit Vor Vserr Vrerr 1 470 Ro Vont Von Io 1 530 V 1 470 V 56A 1 1 mQ Dynamic output droop resistance based on 2 Output current step to no load with output voltage set at upper output dynamic voltage limit Vrerr 1 550 V b Output voltage prior to load change at lour AIo Vor Alo X Ro 1 504 V Rop Vourp 1 550 V 1 504 V 24A 1 9 mQ Number of phases n 3 Switching frequency per phase 330 kHz Setting the Clock Frequency The ADP3166 uses a fixed frequency control architecture The frequency is set by an external timing resistor Rr The clock frequency and the number of phases determine the switching frequency per phase which relates directly to switching losses and the sizes of the inductors and input and output capacitors With n 3 for three phases a clock frequency of 990 kHz sets the switching frequency of each phase to 330 kHz which represents a practical trade off between t
12. use lower gate capacitance devices The conduction loss of the main MOSFET is given by the fol lowing where RDS MF is the on resistance of the MOSFET 2 2 Pour DX i X Rps ur 17 Typically for main MOSFETs one wants the highest speed low Ciss device but these usually have higher on resistance One must select a device that meets the total power dissipation about 1 5 W for a single D PAK when combining the switch ing and conduction losses For our example we have selected an Infineon IPD12NO3L as the main MOSFET three total 3 with a Criss 1460 pF max and Rpsmry 14 max at T 120 C and an Infineon IPDO6N03L as the synchronous MOSFET six total nsp 6 with 2370 pF max and 8 4 mQ max at T 120 C The synchronous MOSFET CISS is less than 3000 pF satisfy ing that requirement Solving for the power dissipation per MOSFET at 56 A and Ig 6 6 A yields 647 mW for each synchronous MOSFET and 1 26 W for each main MOSFET These numbers work well considering there is usually more PCB area available for each main MOSFET versus each syn chronous MOSFET One last thing to look at is the power dissipation in the driver for each phase This is best described in terms of the Og for the MOSFETs and is given by the following where is the total gate charge for each main MOSFET and is the total gate charge for each synchronous MOSFET
13. will cause excessive power losses while too small a value will lead to increased measurement error good rule is to have the DCR be about 1 to 1 1 2 times the static droop resistance Ro For our example we are using an inductor with a DCR of 1 6 mQ Designing an Inductor Once the inductance and DCR are known the next step is either to design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals It is also important to have the inductance and DCR tolerance specified to keep the accuracy of the system controlled Using 20 for the inductance and 8 for the DCR at room temperature are rea sonable tolerances that most manufacturers can meet The first decision in designing the inductor is to choose the core material There are several possibilities for providing low core loss at high frequencies Two examples are the powder cores e g Kool Mu from Magnetics Inc or Micrometals and the gapped soft ferrite cores e g 3F3 or 3F4 from Philips Low frequency powdered iron cores should be avoided due to their high core loss especially when the inductor value is relatively low and the ripple current is high The best choices for a core geometry are closed loop types such as pot cores PQ U and E cores or toroids A good compromise between price and performance are cores with a toroidal shape There are many useful references for quickly designing a power inductor such a
14. 00 us with a setting error of 3 Solving for the bulk capacitance yields 600 nH x24 A C gt 50 uF 1 63 mF X MIN i 7 600nH x TO0mV x 1 100ms 1 5 x3x3 5x1 1m 700mV x600nH 2 1 50mF 20 4 where 3 5 Using eight 820 OSCONS with a typical ESR of 12 mQ each yields Cx 6 56 mF with an Ry 1 5 One last check should be made to ensure that the ESL of the bulk capacitors Lx is low enough to limit the initial high fre quency transient spike This is tested using La gt 2 Rae 14 Ly 22x50mF x1 9mW 361pH 13 ADP3166 In this example Lx is 375 pH for the eight OSCON capacitors which basically satisfies this limitation If the Lx of the chosen bulk capacitor bank is too large the number of capacitors must be increased One should note for this multimode control technique all ceramic designs can be used as long as the conditions of Equations 12 13 and 14 are satisfied Power MOSFETs For this example the N channel power MOSFETs have been selected for one high side switch and two low side switches per phase The main selection parameters for the power MOSFETs are Vasra Qo Criss and The minimum gate drive voltage the supply voltage to the ADP3418 dictates whether standard threshold or logic level threshold MOSFETs must be used With 710 V logic level threshold MOSFETs Vesan lt 2 5 V are recomme
15. 66 THEORY OF OPERATION The ADP3166 combines a multimode fixed frequency PWM control with multiphase logic outputs for use in 2 3 and 4 phase synchronous buck CPU core supply power converters The internal 5 bit VID DAC conforms to AMD s Hammer family power specifications Multiphase operation is important for producing the high currents and low voltages demanded by today s microprocessors Handling the high currents in a single phase converter would place high thermal demands on the components in the system such as the inductors and MOSFETs The multimode control of the ADP3166 ensures a stable high performance topology for e Balancing currents and thermals between phases e High speed response at the lowest possible switching frequency and output decoupling Minimizing thermal switching losses due to lower frequency operation Tight load line regulation and accuracy High current output from having up to 4 phase operation Reduced output ripple utilizing multiphase cancellation Immunity to board layout Ease of use and design due to independent component selection Flexibility in operation for tailoring design to low cost or high performance Number of Phases The number of operational phases and their phase relationship are determined by internal circuitry that monitors the PWM outputs Normally the ADP3166 operates as a 4 phase PWM controller Grounding the PWM 4 pin programs 3 phase opera tion and groundi
16. ADP3166 provides a dedicated current sense amplifier CSA to monitor the total output current for proper voltage positioning versus load current and for current limit detection Sensing the load current at the output gives the total average current being delivered to the load which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low side MOSFET ADP3166 This amplifier can be configured several ways depending on the objectives of the system Output inductor ESR sensing without thermistor for lowest cost Output inductor ESR sensing with thermistor for improved accuracy with tracking of inductor temperature e Sense resistors for highest accuracy measurements The positive input of the CSA is connected to the CSREF pin which is connected to the output voltage The inputs to the amplifier are summed together through resistors from the sensing element such as the switch node side of the output inductors to the inverting input CSSUM The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor The current information is then given as the difference of CSREF CSCOMP This difference signal is used internally to offset the VID DAC for voltage position
17. ND T 0 C to 85 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit ERROR AMPLIFIER Accuracy Veg 0 8 V Output Referenced to FBRTN CSSUM CSCOMP 0 792 0 800 0 808 V See Test Circuit 1 1 175 V Output Referenced to FBRTN CSSUM CSCOMD 1 163 1 175 1 187 V See Test Circuit 1 1 55 V Output Referenced to FBRTN CSSUM CSCOMD 1 535 1 55 1 566 V See Test Circuit 1 Line Regulation AV pB 10 14 0 05 Input Bias Current 13 15 5 17 uA FBRTN Current IFBRTN 100 200 uA Output Current FB forced to Vou 3 500 Bandwidth Product GBW rr COMP FB 20 MHz Slew Rate 10 pF 50 V us VID INPUTS Input Low Voltage Vir vip 0 8 V Input High Voltage Vini 2 V Input Current VID X 0V 20 26 uA Pull Up Resistance Ryp 100 120 KQ Internal Pull Up Voltage 2 0 2 4 2 65 V VID Transition Delay Time VID code change to FB change 400 ns No CPU Detection Turn Off VID code change to 11111 to 400 ns Delay Time PWM going low OSCILLATOR Frequency Range fosc 0 25 4 MHz Frequency Variation PHASE 25 250 4 phase 160 200 240 kHz Ta 25 115 4 phase 400 kHz 25 75 4 phase 600 kHz Output Voltage Ver 100 kQ to GND 1 9 2 0 2 1 V Timing Resistor Value 500 RAMPADJ Voltage Vrampapy RAMPADJ FB 50 50 RAMPADJ Input Current Range Irampapy 0 50 CURRENT SENSE
18. Rpu new mw 36 17 8 Repeat Steps 6 and 7 to check the loadline and repeat the adjustments if necessary 9 Once finished with dc loadline adjustment do not change 18 Rex Resi Resa or for the rest of the procedure 10 Measure the output ripple at no load and at full load with a scope and make sure that it is within spec AC Loadline Setting Remove the dc load from the circuit and hook up the dynamic load Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 us div Set the dynamic load for a transient step of about 24 A at 1 kHz with 50 duty cycle Measure the output waveform it might be necessary to use a dc offset on scope to see the waveform Try to use a vertical scale of 100 mV div or finer The waveform should look something like Figure 3 Use the horizontal cursors to measure Vacprp and Vpcpgp as shown DO NOT MEASURE THE UNDERSHOOT OR OVERSHOOT THAT HAPPENS IMMEDI AFTER THE STEP th EU 1 E 47 VpcpRP ys J m ER Y Figure 3 AC Loadline Waveform If the Vacprp and are different by more than a few millivolts use the following to adjust It might be necessary to parallel different values to get the right one since there are limited standard capacitor values available It is a good idea to have locations for
19. The first step is to set Cp y for the soft start ramp This ramp is generated with a 20 pA internal current source The value of Rp will have a second order impact on the soft start time because it sinks part of the current source to ground However as long as is kept greater than 200 this effect is minor The value for Cp can be approximated using 4 Iss 2xRpry Cory 20 4 2 where 155 is the desired soft start time Assuming an Rp y of 390 and a desired a soft start time of 3 ms Cpry is 36 nF The closest standard value for Ces is 39 nF Once Cp y has been chosen Rp y can be calculated for the current limit latch off time using 1 96 xt Rpry BT 3 If the result for Rp is less than 200 kQ then a smaller soft start time should be considered by recalculating the equation for or a longer latch off time should be used In no case should Rpry be less than 200 In this example a delay time of 8 ms makes 402 The closest standard 5 value is 390 Inductor Selection The choice of inductance for the inductor determines the ripple current in the inductor Less inductance leads to more ripple current which increases the output ripple voltage and conduc tion losses in the MOSFETs but allows using smaller size inductors and for a specified peak to peak transient deviation less total output capacitance Conversely a higher inductance means lower ri
20. UT Input Low Voltage VLEN 0 8 V Input High Voltage VIH EN 2 V Input Current 1 1 uA POWER GOOD COMPARATOR Undervoltage Threshold Vpwrepiuv Relative to nominal DAC output 200 300 400 mV Overvoltage Threshold VpwRGD OV Relative to nominal DAC output 200 300 400 mV Output Low Voltage Vor PwRGD IpwRGD sINK 4mA 150 400 mV Off State Leakage Current Vesrer Vpac 50 uA Delay Time VID Code Changing 100 250 us VID Code Static 400 ns CROWBAR COMPARATOR Crowbar Trip Point V CROWBAR 2 0 2 1 2 2 V Crowbar Reset Point 300 400 500 mV Crowbar Response Time tCROWBAR Overvoltage to PWM Low 400 ns Overvoltage to CRWBR High 400 ns Output Voltage Low VoL CROWBAR IcRowBAR SINK 100 100 500 mV Output Voltage High VoH CROWBAR IcRowBAR SOURCE 100 4 0 5 0 PWM OUTPUTS Output Voltage Low VorL wM IpwM sINK 400 160 500 mV Output Voltage High IPWM SOURCE 400 uA 4 0 5 0 V SUPPLY DC Supply Current Icc 7 10 mA UVLO Threshold Voltage rising 6 5 6 9 7 3 V UVLO Hysteresis 0 7 0 9 1 1 V NOTES All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control SQC Guaranteed by design not tested in production Specifications subject to change without notice REV 0 ADP3166 ABSOLUTE MAXIMUM RATINGS VCC 0 3 V to 15 V FBRTN 0 3 V to 0 3 V VIDO to EN DELAY ILIMIT CSCOMP RT COMP Lead Temperature Soldering
21. V the COMP pin bias voltage Vgj4s is 1 2 V and the current balancing amplifier gain is 5 Using Vg of 0 48 V and Rpsmax of 4 2 mQ low side on resistance at 150 C we find a per phase limit of 74 A This limit can be adjusted by changing the ramp voltage But make sure not to set the per phase limit lower than the average per phase current There is also per phase initial duty cycle limit determined by V Bias Dmax 24 T 24 For this example the maximum duty cycle is found to be 0 55 Feedback Loop Compensation Design Optimized compensation of the ADP3166 allows the best pos sible response of the regulator s output to a load change The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is optimized over the widest possible frequency range including dc and equal to the droop resistances Ro and Rop With the output impedance the output voltage will respond in proportion with the load current this ensures the optimal output positioning and allows the minimization of the output decoupling With the multimode feedback structure of the ADP3166 one needs to set the feedback compensation to make the converter s output impedance work in parallel with the output decoupling to meet this goal There are several poles and zeros created by the output inductor and decoupling capacitors output filte
22. acrifice of transient response and stability The factor of three in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability transient response and thermal balance COMP Pin Ramp There is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input Vr Ro Rop x 1 21 nX fsw X Cx X Ro X Rop Ver For this example the overall ramp signal is found to be 0 48 V Current Limit Set Point To select the current limit set point we need to find the resistor value for The current limit threshold for the ADP3166 is set with a V source Vr across Ry zy with a gain of 10 4 mV uA can be found using the following XVm X Ro 2 REV 0 For values of Rzym greater than 500 the current limit may be lower than expected so some adjustment of may be needed Here I is the average current limit for the output of the sup ply For our example choosing 75 A for we find to be 378 for which we choose 374 as the nearest 1 value The per phase current limit described earlier has its limit deter mined by the following I 27 Ir PHLIM Ap X NS 2 23 For the ADP3166 the maximum COMP voltage is 3 3
23. ank is formed by 12 three 2200 uF 16 V Nichicon capacitors with a ripple current rating of 3 5 A each 11 13 To reduce the input current di dt to below the recommended maximum of 0 1 A us an additional small inductor L gt 1 uH 14 15 A should be inserted between the converter and the sup ply bus That inductor also acts as a filter between the converter and the primary power source 15 ES Resanew X 35 Var TUNING PROCEDURE FOR ADP3166 1 Build a circuit based on compensation values computed from the design spreadsheet 2 Hook up the dc load to the circuit turn it on and verify its operation Also check for jitter at no load and full load DC Loadline Setting 3 Measure the output voltage at no load Verify that it is within tolerance 4 Measure the output voltage at full load cold Vg co p Let the board set for a 10 minutes at full load and measure output Vg If there is a change of more than a few millivolts adjust Rcs and Rcs using Equations 35 and 37 5 Repeat Step 4 until the cold and hot voltage measurements remain the same 6 Measure the output voltage from no load to full load using 5 A steps Compute the loadline slope for each change and 16 then average them to get the overall loadline slope Romeras 7 If Romeras is off by more than 0 05 mQ from Ro use Equa tion 36 to adjust the Rpy values Romeras
24. ce which is based on the number and type of capacitor to be used The best location for ceramics is inside the socket Others can be placed along the outer edge of the socket as well REV 0 Combined ceramic values of 30 to 100 uF are recommended usually made up of multiple ceramic capacitors Select the num ber of ceramics and find the total ceramic capacitance Cz Next there is an upper limit imposed on the total amount of bulk capacitance Cx when one considers the VID on the fly voltage stepping of the output voltage step Vy in time ty with error of Vggg and a lower limit based on meeting the critical capacitance for load release for a given maximum load step AIo Lx C m LLI L I 9 0 ee z 90 L Cx max 5 V V xK a x lit ty X 1 VID Vy L Verr here I where V V To meet the conditions of these expressions and transient response the ESR of the bulk capacitor bank Rx should be less than or equal to the dynamic droop resistance If the is larger than the system will not meet the VID on the fly specification and may require the use of a smaller inductor or more phases and may have to increase the switch ing frequency to keep the output ripple the same For our example a combination of MLCC capacitors Cz 50 uF was used The VID on the fly step change is from 1 5 V to 0 8 V making Vy 700 mV in 1
25. d switching noise energy EMI and conduction losses in the board Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise related operational problems in the power converter control circuitry The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs including all interconnecting PCB traces and planes The use of short and wide interconnection traces is especially critical in this path for two reasons it minimizes the inductance in the switching loop which can cause high energy ringing and it accommodates the high current demand with minimal voltage loss e Whenever a power dissipating component e g a power MOSFET is soldered to a PCB the liberal use of vias both directly on the mounting pad and immediately surrounding it is recommended Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board To further improve thermal performance the largest possible pad area should be used e The output power path should also be routed to encompass a short distance The output power path is formed by the cu
26. e time to switch off the synchronous should not exceed the nonoverlap dead time of the MOSFET driver 40 ns typical for the ADP3418 The output impedance of the driver is about 2 and the typical MOSFET input gate resistances are about 1 Q to 2 Q so a total gate capacitance of less than 6000 pF should be adhered to Since there are two MOSFETs in parallel we should limit the input capacitance for each synchro nous MOSFET to 3000 pF The high side main MOSFET must be able to handle two main power dissipation components conduction and switching losses The switching loss is related to the amount of time it 14 takes for the main MOSFET to turn on and off and to the current and voltage that are being switched Basing the switch ing speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance the following expression pro vides an approximate value for the switching loss per main MOSFET where ny is the total number of main MOSFETs x Ps ur 7 2X few x 700 EO x Rg x xCiss 16 MF Here Rg is the total gate resistance 2 Q for the ADP3418 and about 1 for typical high speed switching MOSFETs making Rg 3 and Cyss is the input capacitance of the main It is interesting to note that adding more main MOSFETs does not really help the switching loss per MOSFET since the additional gate capacitance slows down switching The best thing to reduce switching loss is to
27. eft open When in normal operation mode the DAC output programs the FB regulation voltage from 0 8 V to 1 55 V Leaving VID4 through VIDO open results in the ADP3166 going into a No CPU mode shutting off its PWM outputs 6 CROWBAR Crowbar Output This logic level output can be used to control an external device to short the 12 V supply to ground to protect the CPU from overvoltage if CSREF exceeds 2 1 V 7 FBRTN Feedback Return VID DAC and error amplifier reference for remote sensing of the output voltage 8 FB Feedback Input Error amplifier input for remote sensing of the output voltage A resistor between this pin and the output voltage sets the no load offset point 9 COMP Error Amplifier Output and Compensation Point 10 PWRGD Power Good Output Open drain output that pulls to GND when the output voltage is outside of the proper operating range 11 EN Power Supply Enable Input Pulling this pin to GND disables the PWM outputs 12 DELAY Soft Start Delay and Current Limit Latch Off Delay Setting Input A resistor and capacitor connected between this pin and GND sets the soft start ramp up time and the overcurrent latch off delay time 13 RT Frequency Setting Resistor Input external resistor connected between this pin and GND sets the oscil lator frequency of the device 14 RAMPADJ PWM Ramp Current Input resistor from the converter input voltage to this pin sets the internal PWM ramp 15 ILIMIT Current Limit Set Point Enable Ou
28. he switching losses and the sizes of the output filter components Figure 1 shows that to achieve a 990 kHz oscillator frequency the correct value for is 200 kQ Alternatively the value for Ry can be calculated using 1 nx x 5 83 pF Ar 1 5 where 5 83 pF and 1 5 are internal IC component values For good initial accuracy and frequency stability it is recom mended to use a 1 resistor ADP3166 SEE THEORY OF OPERATION SECTION FOR DESCRIPTION OF OPTIONAL Rew RESISTORS 2200pF 16V x 3 NICHICON PW SERIES c9 47 02 C8 i ADP3418 100nF D2 Q1 1N4148WS IPD12NO3L L2 820pF 2 5V x 8 OSCON SERIES 600nH 1 6mO 12mQ ESR EACH Q3 IPDOGNOSL Q2 10kF x 5MLCC IPDO6NO3L AROUND SOCKET U3 12 ADP3418 00nF ue a4 IPD12NO3L L3 600nH 1 6mO IPDOGNOS3L Q5 IPDOGNOSL U4 7 Q7 IPD12NO3L 100 5 Q9 IPDO6NO3L Qs IPDOGNOS3L 5 SI 8 FROM CPU 5 s lt Rcsi Rcs2 35 7 73 2kO CSCOMP 5 E CSSUM Figure 1 56 AMD K8 CPU Supply Circuit 10 Vcc coRE 0 8V 1 55V O Vcc coRE RTN REV 0 ADP3166 Soft Start and Current Limit Latch Off Delay Times Because the soft start and current limit latch off delay functions share the DELAY pin these two parameters must be considered together
29. ing and as a differential input for the current limit comparator To provide the best accuracy for the sensing of current the CSA has been designed to have a low offset input voltage Also the sensing gain is determined by external resistors so that it can be made extremely accurate Active Impedance Control Mode For controlling the dynamic output voltage droop as a function of output current a signal proportional to the total output cur rent at the CSCOMP pin can be scaled to be equal to the droop impedance of the regulator times the output current This droop voltage is then used to set the input control voltage to the sys tem The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be This differs from previous implementations and allows enhanced feed forward response Voltage Control Mode A high gain bandwidth voltage mode error amplifier is used for the voltage mode control loop The control input voltage to the positive input is set via the VID 5 bit logic code according to the voltages listed in Table I This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current commonly known as active voltage position ing The output of the amplifier is the COMP pin which sets the termination voltage for the internal PWM ramps The negative input FB is tied to the output sense location with a resi
30. lls down the output as the reverse current builds up in the inductors If the output overvoltage is due to a short of the high side MOSFET this action current limits the input supply or blow its fuse protect ing the microprocessor from destruction The CROWBAR output can be used to signal an external input crowbar or other protection circuit Output Enable and UVLO The input VCC must be higher than the UVLO threshold and the EN pin must be higher than its logic threshold for the ADP3166 to begin switching IF UVLO is less than the threshold or the EN pin is a logic low the ADP3166 is disabled This holds the PWM outputs at ground shorts the DELAY capacitor to ground and holds the ILIMIT pin at ground In the application circuit the ILIMIT pin should be connected to the OD pins of the ADP3418 drivers Because ILIMIT is grounded this disables the drivers such that both DRVH and DRVL are grounded This feature is important to prevent dis charging of the output capacitors when the controller is shut off If the driver outputs were not disabled a negative voltage could be generated on the output due to the high current discharge of the output capacitors through the inductors REV 0 APPLICATION INFORMATION The design parameters for a typical AMD K8 compliant CPU application are as follows Input voltage Vi 12 V VID setting voltage Vyp 1 500 V Duty cycle D 0 125 Maximum static output voltage error t Vsggg 50
31. n multiple steps from the start code to the finish code This change can be either positive or negative When a VID input changes state the ADP3166 detects the change and blanks the DAC for a minimum of 400 ns This time is to prevent a false code due to logic skew while the six VID inputs are changing Additionally the first VID change initiates the PWRGD blanking function for a minimum of 100 to prevent a false PWRGD event Each VID change will reset the internal timer Power Good Monitoring The power good comparator monitors the output voltage via the CSREF pin The PWRGD pin is an open drain output whose high level when connected to a pull up resistor indicates that the output voltage is within the nominal limits specified previ ously based on the VID voltage setting PWRGD will go low if the output voltage is outside of this specified range PWRGD is blanked during a VID OTF event for a period of 100 us to prevent false signals during the time the output is changing Output Crowbar As part of the protection for the load and output components of the supply the PWM outputs are driven low turning on the low side MOSFETs and the CROWBAR logic output goes high when the output voltage exceeds the upper power good threshold This crowbar action releases once the output volt age has fallen back within specifications if no other faults are present The release threshold is approximately 400 mV Turning on the low side MOSFETs pu
32. nded The maximum output current Io determines Rps ow requirement for the low side synchronous MOSFETs With the ADP3166 currents are balanced between phases thus the current in each low side MOSFET is the output current divided by the total number of MOSFETs nsr With conduction losses being dominant the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase Ig and average total output current 2 2 i g D 2 12 al NSF lt Knowing the maximum output current being designed for and the maximum allowed power dissipation one can find the required for the MOSFET For D PAK MOSFETs up to an ambient temperature of 50 C a safe limit for Psp is 1 W to 1 5 W at 120 junction temperature Thus for our example 56 A maximum we find Rps sr per MOSFET lt 10 mQ This Rps sr is also at a junction temperature of about 120 C so we need to make sure we account for this when making this selection For our example we selected two lower side MOSFETs at 7 each at room temperature which gives 8 4 mQ at high temperature Another important factor for the synchronous MOSFET is the input capacitance and the feedback capacitance The ratio of the feedback to input needs to be small less than 10 is recom mended to prevent accidental turn on of the synchronous MOSFETs when the switch node goes high Also th
33. ng the PWM3 and PWM4 pins programs 2 phase operation When the ADP3166 is enabled the controller outputs a voltage that is approximately 550 mV An inter nal comparator checks each pin s voltage versus a threshold of 400 mV If the pin is grounded it will be below the threshold and the phase will be disabled The output impedance of the PWM pin is approximately 5 kO Any external pull down resis tance connected to the PWM pin should not be less than 25 kQ to ensure proper operation The phase detection is made during the first two clock cycles of the internal oscillator After this time if the PWM output was not grounded it will switch between 0 V and 5 V If the PWM output was grounded it will remain off The PWM outputs are logic level devices intended for driving external gate drivers such as the ADP3418 Since each phase is monitored independently operation approaching 100 duty cycle is possible Also more than one output can be on at a time for overlapping phases Master Clock Frequency The clock frequency of the ADP3166 is set with an external resistor connected from the RT pin to ground The frequency follows the graph in TPC 1 To determine the frequency per phase the clock is divided by the number of phases in use If PWMMA is grounded divide the master clock by 3 for the frequency of the remaining phases If PWM3 and PWMA are grounded divide by 2 If all phases are in use divide by 4 REV 0
34. or Res and the thermistor value at 25 C for a given Rcs value 1 Select an NTC based on type and value Since we do not have a value yet start with a thermistor with a value close to Res The NTC should also have an initial tolerance of better than 5 2 Based on the type of NTC find its relative resistance value at two temperatures The temperatures to use that work well are 50 and 90 We will call these resistance values A A is 50 25 B 18 5 Note that the NTC s relative value is always 1 at 25 C 3 Next find the relative value of Res required for each of these temperatures This is based on the percentage change needed which we will initially make 0 39 We will call these rj is 1 1 TC X 25 and is 1 1 TC X 25 where 0 0039 T 50 and 90 REV 0 ADP3166 4 Compute the relative values for Rcs 2 and Rry using A B xnxn Ax 1 B xr Bx 1 A xn R s Ax 1 B xn Bx 1 A xr A B 1 Ros 1 n 1 mn Rog 8 1 Ry 1 1 1 5 Calculate rry X Ros then select the closest value of thermistor available Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one ee Rry ACTUAL 9 RTH CALCULATED 6 Finally calculate values for R
35. ort Circuit Protection The ADP3166 compares a programmable current limit set point to the voltage on the output of the current sense amplifier at the CSCOMP pin The level of current limit is set with the resistor from the ILIMIT pin to ground During normal operation the voltage on ILIMIT is 3 V The current through the external resistor is internally scaled to give a current limit threshold of 10 4 mV uA If the difference in voltage between CSREF and CSCOMP drops below the current limit threshold the internal current limit amplifier will control the internal COMP voltage to maintain the average output current at the limit After the limit is reached the 3 V pull up on the DELAY pin is disconnected and the external delay capacitor is discharged through the external resistor A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1 8 V The current limit latch off delay time is therefore set by the RC time constant discharging from 3 V to 1 8 V The Applications section discusses the selection of Rp y based on the Cp y that has been chosen Because the controller continues to cycle the phases during the latch off delay time if the short is removed before the 1 8 V threshold is reached the controller will return to normal operation The recovery characteristic depends on the state of PWRGD If the output voltage is within the PWRGD window the controller resumes normal operation However if short
36. os and Rcs using the following Res Reg X k X Reg Reg Res X 1 k k X Res For this example Rcs has been chosen to be 100 so we start with a thermistor value of 100 Looking through available 0603 size thermistors we find a Vishay NTHS0603N01N1003JR NTC thermistor with A 0 3602 and B 0 09174 From these we compute Rcs 0 3796 Rcs 0 7195 and Rry 1 0751 Solving for yields 107 51 so we choose 100 mak ing 0 9302 Finally we find Rcs and Reg to be 35 3 and 73 9 kQ Choosing the closest 1 resistor values yields a choice of 35 7 and 73 2 Output Offset AMD specification requires that at no load the nominal output voltage of the regulator be offset to a higher value than the nominal voltage corresponding to the VID code The offset is set by a con stant current source flowing out of the FB pin and flowing through The value of can be found using Equation 11 10 Vons Trp 1 11 SEV cv uU 15 pA The closest standard 1 resistor value is 2 00 Selection The required output decoupling for the regulator is typically recommended by AMD for various processors and platforms One can also use some simple design guidelines to determine what is required These guidelines are based on having both bulk and ceramic capacitors in the system The first thing is to select the total amount of ceramic capaci tan
37. ot exceeded If critical signal lines including the output voltage sense lines of the ADP3166 must cross through power circuitry it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier An analog ground plane should be used around and under the ADP3166 for referencing the components associated with the controller This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it The components around the ADP3166 should be located close to the controller with short traces The most important traces to keep short and away from other traces are the FB and CSSUM pins Refer to Figure 6 for more details on layout for the CSSUM node The output capacitors should be connected as close as possible to the load or connector that receives the power e g a microprocessor core If the load is distributed the capacitors should also be distributed and generally in pro portion to where the load tends to be more dynamic Avoid crossing any signal lines over the switching power path loop described below REV 0 ADP3166 Power Circuitry e The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiate
38. pple current and reduced conduction losses but requires larger size inductors and more output capacitance for the same peak to peak transient deviation In any multiphase converter a practical value for the peak to peak inductor ripple current is less than 50 of the maximum dc current in the same inductor Equation 4 shows the relationship between the induc tance oscillator frequency and peak to peak ripple current in the inductor Equation 5 can be used to determine the mini mum inductance based on a given output ripple voltage _ Vip x 1 D z gt x 1 nx D i Jsw XVRIPPLE Solving Equation 5 for a 10 mV p p output ripple voltage yields 1 5V x1 9mQx 1 0 375 330 kHz x10mV 540nH REV 0 If the ripple voltage is less than that designed for the inductor can be made smaller until the ripple value is met This will allow opti mal transient response and minimum output decoupling The smallest possible inductor should be used to minimize the number of output capacitors 600 nH inductor is a good choice for a starting point and it gives a calculated ripple cur rent of 6 6 A The inductor should not saturate at the peak current of 22 A and should be able to handle the sum of the power dissipation caused by the average current of 18 7 A in the winding and the core loss Another important factor in the inductor design is the DCR which is used for measuring the phase currents A large DCR
39. r that need to be compensated for 15 ADP3166 The first step is to compute the time constants for all of the poles and zeros in the system Ap X Rps Rr Ro Rop X Lx 1 nx D xVer nx Cx X Ro X X Vyp 1 6 mQOx0 48 V 1 1 mQ 1 9 mQ x 600 nH 1 0 375 x 0 48 3x1 5 4 L5V 3x6 56 mF x l l mQx1 9 mQx1 5V E R 236 0 mQ L Rop R C R R OD a X x OD Rop x Ry 6 56 x 1 9 m0 0 6mo 372 19 0 6 T 8 70 us T Rx R Rop XCx 27 1 5 MQ 0 6 1 9 mQ x 6 56 mF 1 31us m Ap X Rps yr XR 5 4 2 28 ae RE 1 5 Vx36 0 mQ 2 T Cy XCz X Rop Cy x Ro R Cz x Rop 2 T 6 56 mF x50 mF x1 9 137 ns 6 56 mF x 1 9 mQ 0 6 mQ 50 mF 1 9 29 where for the ADP3166 R is the PCB resistance from the bulk T 137ns capacitors to the ceramics and where Rp is the total low side Crp CR 3331Q 18 7 pF 33 A MOSFET on resistance per phase For this example Ap is 5 Ver equals 0 48 V R is approximately 0 6 mQ assuming a 4 layer motherboard and Lx is 375 pH for the eight OSCON capacitors type three compensator on the voltage feedback is adequate for proper compensation of the output filter The expressions that follow are intended to yield an optimal starting point for the design some adjustments may be necessary to account for PCB and com
40. rammable no load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient The ADP3166 also provides accurate and reliable short circuit protection adjustable current limiting and a delayed power good output that accommodates on the fly output volt age changes requested by the CPU ADP3166 is specified over the commercial temperature range of 0 to 85 and is available in a 28 lead TSSOP package Patent pending REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM vcc RAMPADJ RT D ADP3166 UVLO SHUTDOWN a AND BIAS RESET 2 3 4 PHASE DRIVER LOGIC CURRENT BALANCING CIRCUIT RESET RESET CROWBAR CURRENT LIMIT CIRCUIT FBRTN VID2 VID1 VIDO One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD P31 66 SPEC 0 NS 12 V FBRTN G
41. rrent path through the inductor the output capacitors and the load e For best EMI containment a solid power ground plane should be used as one of the inner layers extending fully under all the power components Signal Circuitry e The output voltage is sensed and regulated between the FB pin and the FBRTN pin which connects to the signal ground at the load To avoid differential mode noise pickup in the sensed signal the loop area should be small Therefore the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller e The feedback traces from the switch nodes should be con nected as close as possible to the inductor The CSREF signal should be connected to the output voltage at the inductor nearest to the controller REV 0 19 ADP3166 OUTLINE DIMENSIONS 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 Dimensions shown in millimeters i ye COPLANARITY 0 19 SEATING 09 0 10 PLANE 0 09 0 45 COMPLIANT TO JEDEC STANDARDS MO 153AE 20 REV 0 03589 0 4 03 0
42. s e Magnetic Designer Software Intusoft http www intusoft com e Designing Magnetic Components for High Frequency DC DC Converters McLyman Kg Magnetics ISBN 1 883107 00 8 11 ADP3166 Selecting a Standard Inductor The following companies can provide design consultation and deliver power inductors optimized for high power applications upon request e Coilcraft 847 639 6400 http www coilcraft com Coiltronics 561 752 5000 http www coiltronics com e Sumida Electric Company 510 668 0660 http www sumida com e Vishay Intertechnology 402 563 6866 http www vishay com Output Droop Resistance The design requires that the regulator output voltage measured at the CPU pins drops when the output current increases The specified voltage drop corresponds to the static output droop resistance Ro The output current is measured by summing together the voltage across each inductor and then passing the signal through a low pass filter This summer filter is the CS amplifier configured with resistors Rpg x summers and Rcs and Ces filter The output resistance of the regulator is set by the following equations where Rz is the DCR of the output inductors x Rr Rexx 6 L ye REX Ras One has the flexibility of choosing either or It is best to select Rcs equal to 100 and then solve for by rearranging Equation 6 R RI
43. stor Rg and is used for sensing and controlling the output voltage at this point A current source from the FB pin flowing through is used for setting the no load offset voltage from the VID voltage The no load voltage will be positive with respect to the VID DAC The main loop compensation is incorporated in the feedback network between FB and COMP Soft Start The power on ramp up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground The RC time constant also determines the current limit latch off time as explained in the following section In UVLO or when EN is a logic low the DELAY pin is held at ground After the UVLO threshold is reached and EN is a logic high the DELAY capacitor is charged up with an internal 20 1A current source The output voltage follows the ramping voltage on the DELAY pin limiting the inrush current The soft start time depends on the value of VID DAC and Cp y with a secondary effect from Rp y Refer to the Applications section for detailed information on setting Cpj y When the PWRGD threshold is reached the soft start cycle is stopped and the DELAY pin is pulled up to 3 V This ensures that the output voltage is at the VID voltage when the PWRGD signals to the system that the output voltage is good If EN is taken low or if VCC drops below UVLO the DELAY capacitor is reset to ground to be ready for another soft start cycle Current Limit and Sh
44. tput A resistor from this pin to GND sets the current limit threshold of the converter This pin is actively pulled low when the ADP3166 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high side and low side outputs should go low 16 CSREF Current Sense Reference Voltage Input The voltage on this pin is used as the reference for the current sense amplifiers and the Power Good and Crowbar functions This pin should be connected to the com mon point of the output inductors 17 CSSUM Current Sense Summing Node Resistors from each switch node to this pin sum the average inductor cur rents together to measure the total output current 18 CSCOMP Current Sense Compensation Point A resistor and capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time 19 GND Ground All internal biasing and the logic output signals of the device are referenced to this ground 20 23 SW4 SW1 Current Balance Inputs Inputs for measuring the current level in each phase The SW pins of unused phases should be grounded 24 27 PWMA PWMI Logic Level PWM Outputs Each output is connected to the input of an external MOSFET driver such as the ADP3413 or ADP3418 Connecting the and or PWM 4 outputs to GND will cause that phase to turn off allowing the ADP3166 to operate as a 2 3 or 4 phase controller 28 VCC Supply Voltage for the Device 6 REV 0 ADP31
45. two capacitors in the layout for this Repeat Steps 11 to 13 and repeat adjustments if neces sary Once complete do not change Ces for the rest of the procedure Set the dynamic load step to maximum step size do not use a step size larger than needed and verify that the output waveform is square meaning Vacprp and Vpcprp are equal 1 R CS2 NEW Resor 1 xR R R x R R Fuse CSI OLD 25 CS2 OLD CS2 NEW CS1 OLD TH 25 C Cs NEW Vos G8 REV 0 17 ADP3166 Initial Transient Setting 19 With dynamic load still set at maximum step size expand scope time scale to see 2 is div to 5 us div The waveform may have two overshoots and one minor undershoot see Figure 5 Here is the final desired static value Figure 4 Transient Setting Waveform 20 Ifthe overshoots are larger than desired try making the following adjustments in this order Note if these adjust ments do not change the response you are limited by the output decoupling Check the output response each time a change is made as well as the switching nodes to make sure it is still stable a Make the ramp resistor larger by 25 Rgawp b For increase CB or switching frequency For increase RA and decrease by 25 VTRANREL
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ANALOG DEVICES ADP3166* 5 Bit Programmable 2 3 4 Phase Synchronous Buck Controller handbook