ANALOG DEVICES ADP3159/ADP3179 4-Bit Programmable Synchronous Buck Controllers handbook
Contents
1. The converter onlv operates at the nominal operating frequencv at the above specified Vour and at light load At higher values of Vout or under heavy load the operating frequency decreases due to the parasitic voltage drops across the power devices The actual minimum frequency at Vour 1 7 V is calculated to be 195 kHz see Equation 3 where Roscownsr is the resistance of the high side MOSFET estimated value 14 mQ RoscomLsr is the resistance of the low side MOSFET estimated value 6 mQ Rsense is the resistance of the sense resistor estimated value 4 mQ R_ is the resistance of the inductor estimated value 3 mQ Inductance Selection The choice of inductance determines the ripple current in the inductor Less inductance leads to more ripple current which increases the output ripple voltage and the conduction losses in the MOSFETs but allows using smaller size inductors and for a specified peak to peak transient deviation output capacitors with less total capacitance Conversely a higher inductance means lower ripple current and reduced conduction losses but requires larger size inductors and more output capacitance for the same peak to peak transient deviation The following equation shows the relationship between the inductance oscillator frequency peak to peak ripple current in an inductor and input and output voltages pe Vour X torr 4 Th RIPPLE For 4 A peak to peak ripple current which correspond2. LL cece eee eee een ene e nes 2 Edit to ERROR AMPLIFIER section 0000 eee 2 Addition to ORDERING GUIDE e ta Goede able whl a te tay us is 3 Edits to the On board Linear Regulator Controllers section 0 000 5 Edits tosPigute 3 tes escheat A A and a diced Ae is eae eee eon 6 Editst Eguat on 24 22 2 secu O Gates hates cache A dia da 10 Edits to Feedback Compensation for Active Voltage Positioning section 000 10 Editto Equatoni27 l kpkoi A dl g ud irene o be aed da da A cle ta 11 Addition of new text to Linear Regulators section ce eee eee nr 11 REV A 15 V LO L L O6LZOD W S N NI GILNIHd 16
3. controlled by the ADP3159 The linear regulator controllers have been designed so that they remain active even when the switching controller is in UVLO mode to ensure that the output voltages of the linear regulators will track the 3 3 V supply as required by Intel design specifica tions By diode ORing the VCC input of the IC to the 5 VSB and 12 V supplies as shown in Figure 3 the switching output will be disabled in standby mode but the linear regulators will begin conducting once VCC rises above about 1 V During start up the linear outputs will track the 3 3 V supply up until they reach their respective regulation points regardless of the state of the 12 V supply Once the 12 V supply has exceeded the 5 VSB supply by more than a diode drop the controller IC will track the 12 V supply Once the 12 V supply has risen above the UVLO value the switching regulator will begin its start up sequence Table I Output Voltage vs VID Code VID3 VID2 VID1 VIDO VOUT NOM 1 1 1 1 1 30 V 1 1 1 0 1 35 V 1 1 0 1 1 40 V 1 1 0 0 1 45 V 1 0 1 1 1 50 V 1 0 1 0 1 55 V 1 0 0 1 1 60 V 1 0 0 0 1 65 V 0 1 1 1 1 70 V 0 1 1 0 1 75 V 0 1 0 1 1 80 V 0 1 0 0 1 85 V 0 0 1 1 1 90 V 0 0 1 0 1 95 V 0 0 0 1 2 00 V 0 0 0 0 2 05 V REV A ADP3159 ADP3179 APPLICATION INFORMATION Specifications for a Design Example The design parameters for a tvpical 750 MHz Pentium III appli cation shown in Figure 3 are as follows Input Vol
4. i e loose dc load regulation is inherently required to allow improved transient containment i e to achieve tighter ac load regulation That is the dc load regulation is intentionally sacrificed but kept within specification in order to minimize the number of capacitors required to contain the load transients produced by the CPU Figure 6 Adding Overcurrent Protection to the Linear Regulator Linear Regulators The two linear regulators provide a low cost convenient and versatile solution for generating additional supply rails The maximum output load current is determined by the size and thermal impedance of the external N channel power MOSFET that is placed in series with the supply The output voltage is sensed at the LRFB pin and compared to an internal reference voltage in a negative feedback loop which keeps the output voltage in regulation If the load is reduced or increased the MOSFET drive will also be reduced or increased by the controller IC to provide a well regulated 2 5 accurate output voltage The LRFB threshholds of the ADP3159 are internally set at 2 5 V LRFB1 and 1 8 V LRFB2 while the LRFB pins of the ADP3179 are compared to an internal 1 V reference This allows the use of an external resistor divider network to program the linear regulator output voltage The correct resistor values for setting the output voltage of the linear regulators in the ADP3179 can be determined using Ry RL Vourar Vir
5. Rubycon capaci tors is 2 6 mF while the equivalent capacitance is 5 mF The capacitance is safely above the critical value RsenseE The value of Rsense is based on the maximum required output current The current comparator of the ADP3159 has a mini mum current limit threshold of 69 mV Note that the 69 mV value cannot be used for the maximum specified nominal cur rent as headroom is needed for ripple current and tolerances REV A ADP3159 ADP3179 The current comparator threshold sets the peak of the inductor current yielding a maximum output current Io which equals twice the peak inductor current value less half of the peak to peak inductor ripple current From this the maximum value of Rsensg is calculated as Rsense lt Ves o1 ain emi 4mQ oe Iicewrtzey 15 A 1 9A 8 2 In this case 4 mQ was chosen as the closest standard value Once Rsensk has been chosen the output current at the point where current limit is reached lovrcci can be calculated using the maximum current sense threshold of 87 mV I Vos cL MAX IL RIPPLE OUT CL Rsense 2 9 287mV 384 4 4 9 4 m4 2 At output voltages below 450 mV the current sense threshold is reduced to 54 mV and the ripple current is negligible There fore at dead short the output current is reduced to 54 mV 4 mQ Iovrcse 13 5A 10 To safely carry the current under maximum load conditions the sense resistor must have a power rating of a
6. at least Pors Rs loa 1 2W 67 The maximum linear regulator MOSFET junction temperature with a shorted output is Ty max Ta Oc X Vin X Lomax Tmax 50 C 1 4 C W x 3 3V x2 2 4 60 0 38 which is within the maximum allowed by the MOSFET s data sheet specification The maximum MOSFET junction tempera ture at nominal output is Tinom Ta 4 0 c X Vin Vour X locnom Tinom 50 C 1 4 C W x 3 3V 2 5 V x2 A 52 C 39 This example assumes an infinite heatsink The practical limita tion will be based on the actual heatsink used 12 LAYOUT AND COMPONENT PLACEMENT GUIDELINES The following guidelines are recommended for optimal perfor mance of a switching regulator in a PC system General Recommendations 1 For best results a four layer PCB is recommended This should allow the needed versatility for control circuitry interconnections with optimal placement a signal ground plane power planes for both power ground and the input power e g 5 V and wide interconnection traces in the rest of the power delivery current paths 2 Whenever high currents must be routed between PCB layers vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded 3 Tfcritical signal lines including the voltage and current sense lines of the controller IC must cross through po
7. mal load transient response with the minimum number of output capacitors Cycle by Cycle Operation During normal operation when the output voltage is regulated the voltage error amplifier and the current comparator are the main control elements During the on time of the high side MOSFET the current comparator monitors the voltage between the CS and CS pins When the voltage level between the two pins reaches the threshold level the DRVH output is switched to ground which turns off the high side MOSFET The timing capacitor CT is then charged at a rate determined by the off time controller While the timing capacitor is charging the DRVL output goes high turning on the low side MOSFET When the voltage level on the timing capacitor has charged to the upper threshold voltage level a comparator resets a latch The output of the latch forces the low side drive output to go low and the high side drive output to go high As a result the low side switch is turned off and the high side switch is turned on The sequence is then repeated As the load current increases the output volt age starts to decrease This causes an increase in the output of the voltage error amplifier which in turn leads to an increase in the current comparator threshold thus tracking the load current To prevent cross conduction of the external MOSFETs feedback is incorporated to sense the state of the driver output pins Before the low side drive output can go hi
8. 14 Sa e lea The maximum rms current of the low side MOSFET is i ETA NI Invanzev X IL PEAK Trika Ikmsisr 4 DrsF max X 3 13 1 A 13 1 A4X16 1 4 16 1 4 15 Irmsrsr 4 54 X 3 10 8 Arms The Rpson for each MOSFET can be derived from the allowable dissipation If 10 of the maximum output power is allowed for MOSFET dissipation the total dissipation will be Powers 0 1X Vour X Iovrimax 2 26 W 16 Allocating half of the total dissipation for the high side MOSFET and half for the low side MOSFET and assuming that switching losses are small relative to the dc conduction losses the required minimum MOSFET resistances will be Rosconyusr S 15 mQ 17 TA BER a7 P 1 13 W Rpsconiisr E Zos 10 mQ 18 Note that there is a trade off between converter efficiency and cost Larger MOSFETs reduce the conduction losses and allow higher efficiency but increase the system cost If efficiency is not a major concern a Vishay Siliconix SUB45N03 13L Rps on 10 mQ nominal 16 mQ worst case for the high side and a Vishav Siliconix SUB75N03 07 Rps on 6 mQ nominal 10 mQ worst case for the low side are good choices The high side MOSFET dissipation is Vin X Incpraxy X Qe X fun 2xIg 19 5V x15 Ax70 nC x195 kHz _ 25 97 19 2x1A4 2 Pousr Irmsusr X Rps on Ppusr 8 8 42 X16 MQ 4 where the second term represents the turn off loss of the MOSFET In the second term Qg is the gate charge
9. ET is turned off and by virtue of its essentially nonexistent reverse recovery time Whenever a power dissipating component e g a power MOSFET is soldered to a PCB the liberal use of vias both directly on the mounting pad and immediately sur rounding it is recommended Two important reasons for this are improved current rating through the vias if it is a current path and improved thermal performance especially if the vias extend to the opposite side of the PCB where a plane can more readily transfer the heat to the air 10 The output power path though not as critical as the switch 11 ing power path should also be routed to encompass a small area The output power path is formed by the current path through the inductor the current sensing resistor the out put capacitors and back to the input capacitors For best EMI containment the ground plane should extend fully under all the power components These are the input capacitors the power MOSFETs and Schottky diode the inductor the current sense resistor any snubbing elements that might be added to dampen ringing and the output capacitors Signal Circuitry 12 The output voltage is sensed and regulated between the 13 13 GND pin which connects to the signal ground plane and the CS pin The output current is sensed as a voltage and regulated between the CS pin and the CS pin In order to avoid differential mode noise pickup in those sensed sign
10. ETAA D P3150fitiii Fes ANALOG DEVICES A Bit Programmable Synchronous Buck Controllers ADP3159 ADP3179 FEATURES Optimally Compensated Active Voltage Positioning with Gain and Offset Adjustment ADOPT for Superior Load Transient Response Complies with VRM 8 4 Specifications with Lowest System Cost 4 Bit Digitally Programmable 1 3 V to 2 05 V Output N Channel Synchronous Buck Driver Two On Board Linear Regulator Controllers Total Accuracy 0 8 Over Temperature High Efficiency Current Mode Operation Short Circuit Protection Power Good Output Overvoltage Protection Crowbar Protects Micro processors with No Additional External Components APPLICATIONS Core Supply Voltage Generation for Intel Pentium III Intel Celeron GENERAL DESCRIPTION The ADP3159 and ADP3179 are highly efficient output syn chronous buck switching regulator controllers optimized for converting a 5 V main supply into the core supply voltage required by high performance processors These devices use an internal 4 bit DAC to read a voltage identification VID code directly from the processor which is used to set the output voltage between 1 3 V and 2 05 V They use a current mode constant off time architecture to drive two N channel MOSFETs at a programmable switching frequency that can be optimized for regulator size and efficiency The ADP3159 and ADP3179 also use a unique supplemental regulation technique called Analog Devices Opti
11. Frequency Using TPC 4 Power On Start Up Waveform MOSFETs of Figure 3 TEK RUN i y TRIG D 25 20 KI l g T 15 a a L o li 10 a 2 zZz 5 0 CH1 5 00V By MERE 5 00V By M 1 004s A CH1 f 5 90V 0 5 o 0 5 ip y 2 6500ns OUTPUT ACCURACY of Nominal TPC 2 Gate Switching Waveforms Using MOSFETs of TPC 5 Output Accuracy Distribution Figure 3 TEK RUN TRIG D CH1 2 00V By gE 200V Bwm 1 00ns A CH1 f 5 88V Hi v 150 000us TPC 3 Driver Transition Waveforms Using MOSFETs of Figure 3 4 REV A ADP3159 ADP3179 ADP3159 ADP3179 4 BIT CODE s LRDRV1 COMP 13 Figure 1 Closed Loop Output Voltage Accuracv Test Circuit ADP3159 ADP3179 NC NO CONNECT Figure 2 Linear Regulator Output Voltage Accuracy Test Circuit THEORY OF OPERATION The ADP3159 and ADP3179 use a current mode constant off time control technique to switch a pair of external N channel MOSFETs in a synchronous buck topology Constant off time operation offers several performance advantages including that no slope compensation is required for stable operation A unique feature of the constant off time control technique is that since the off time is fixed the converter s switching frequency is a function of the ratio of input voltage to output voltage The fixed off time is programmed by the value of an external capacitor connected to the CT pin The on time varies in such a way t
12. Ra Roomp The nearest 1 value of 10 5 kQ was chosen for Rg _ 78 7 kQX9 2 kQ 78 7 kQ 9 2 kQ Rg 10 4 kQ 27 K E L RIPPLE k Rsense X z2 mi Vent Voc 2 Em X RroraL amp m RroraL 2X gm Room 3 8 A 4mQ x25 1 174 12V K x 28 2 2 2 mmhox9 1kQ 2 2 mmhox9 1kQ 2x2 2 mmhox130 kQ 4 7x107 I x Rsense X Vin V RIPPLE X AXsEnsE X My In Vvip Vent Vento 2 X tp X Rsense X m f 29 Vari 1V 28 AXAMAX23 _ 5V 17V 75 ng 4 mx 25 1 174V 29 2 1 5 nH R nXI Vouros Vovremax Viw E ae Vym X kvip 5mQx3 8 A 30 Vouros 40 mV 1 7V x5x109 22 mV Finally the compensating capacitance is determined from the equality of the pole frequency of the error amplifier gain and the zero frequency of the impedance of the output capacitor Cour X ESR _ 5mF x 4 8 mQ C je 9 1kQ 2 6nF 31 RroraL GD The closest standard value for Coc is 2 7 nF Trade Offs Between DC Load Regulation and AC Load Regulation Casual observation of the circuit operation e g with a voltmeter would make it appear that the dc load regulation appears to be rather poor compared to a conventional regulator see Figure 4 This would be especially noticeable under very light or very REV A heavy loads where the voltage is positioned near one of the extremes of the regulation window rather than near the nominal center value It must be noted and understood that this low gain characteristic
13. als their loop areas should be small Thus the CS trace should be routed atop the signal ground plane and the CS and CS traces should be routed as a closely coupled pair CS should be over the signal ground plane as well The CS and CS traces should be Kelvin connected to the current sense resistor so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage It is desir able to have the ADP3159 close to the output capacitor bank and not in the output power path so that any voltage drop between the output capacitors and the GND pin is minimized and voltage regulation is not compromised ADP3159 ADP3179 OUTLINE DIMENSIONS Dimensions shown in inches and mm 20 Lead TSSOP RU 20 0 260 6 60 0 252 6 40 An A H Aa Mi LI 0 177 4 50 0 169 4 30 0 256 6 50 0 246 6 25 PIN17 0 006 0 15 0 0433 1 10 0 002 0 05 MAX LA i gt He mi 8 SEATING 0 0256 0 65 0 0118 0 30 9 0079 0 20 0 0 028 0 70 PLANE 0 0075 0 19 59035 0 090 0 020 0 50 14 REV A ADP3159 ADP3179 Revision Historv Location Page Global change from ADP3159 to ADP3159 ADP3179 Data Sheet changed from REV 0 to REV A Edits to GENERAL DESCRIPTION ini e b a e b je ae aa A e e we ed A a A e ek 1 Edits to FUNC TIONAL BLOCK DIAGRAM A rin a a a eh l DA 1 Addition to LINEAR REGULATORS section of the SPECIFICATIONS
14. ance Ryp 20 30 kQ Internal Pull Up Voltage 5 0 5 4 5 7 V OSCILLATOR Off Time Ta 25 C CT 200 pF 3 5 4 0 4 5 us CT Charge Current Icr Ta 25 C Vour in Regulation 130 150 170 pA Ta 25 C Vout 0V 25 35 45 HA ERROR AMPLIFIER Output Resistance Rocerr 1 mQ Transconductance amp m ERR 2 05 2 2 2 35 mmho Output Current lore FB Forced to Voyr 3 625 HA Maximum Output Voltage Vcomrmax FB Forced to Voyr 3 3 0 V Output Disable Threshold VCOMP OFF 600 750 900 mV 3 dB Bandwidth ERR COMP Open 500 kHz CURRENT SENSE Threshold Voltage Vesa FB Forced to Vour 3 69 78 87 mV FB lt 0 45 V 35 45 54 mV 0 8 V lt COMP lt 1V 1 5 mV Input Bias Current Tests Ics CS CS Vour 0 5 5 HA Response Time tcs CS CS gt 87 mV to DRVH 50 ns Going Low OUTPUT DRIVERS Output Resistance Rowrvxy I 50 mA 6 Q Output Transition Time tr tF C 3000 pF 80 ns LINEAR REGULATORS Feedback Current I RFB X 0 3 1 HA LRI Feedback Voltage VLRFB 1 ADP3159 Figure 2 VCC 4 5 V to 12 6 V 2 44 2 5 2 56 V ADP3179 Figure 2 VCC 2 4 5 V to 12 6 V 0 97 1 0 1 03 V LR2 Feedback Voltage VLRFB 2 ADP3159 Figure 2 VCC 4 5 V to 12 6 V 1 75 1 8 1 85 V ADP3179 Figure 2 VCC 2 4 5 V to 12 6 V 0 97 1 0 1 03 V Driver Output Voltage Virprv VCC 4 5 V Virre 0 V 4 2 V POWER GOOD COMPARATOR Undervoltage Threshold Vrwecbquw of Nominal DAC Voltage 75 80 85 Undervoltage Hysteresis of Nominal DAC Voltage 5 Overvoltage Thres
15. gh the high side drive output must be low Likewise the high side drive output is unable to go high while the low side drive output is high Power Good The ADP3159 has an internal monitor that senses the output voltage and drives the PWRGD pin of the device This pin is an open drain output whose high level when connected to a pull up resistor indicates that the output voltage has been within a 20 regulation band of the targeted value for more than 500 ms The PWRGD pin will go low if the output is outside the regulation band for more than 500 ms Output Crowbar An added feature of using an N channel MOSFET as the syn chronous switch is the ability to crowbar the output with the same MOSFET If the output voltage is 20 greater than the targeted value the controller IC will turn on the lower MOSFET which will current limit the source power supply or blow its fuse pull down the output voltage and thus save the microprocessor from destruction The crowbar function releases at approximately 50 of the nominal output voltage For example if the output is programmed to 1 5 V but is pulled up to 1 85 V or above the crowbar will turn on the lower MOSFET If in this case the output is pulled down to less than 0 75 V the crowbar will release allowing the output voltage to recover to 1 5 V if the fault condition has been removed 5 ADP3159 ADP3179 ADP3159 ADP3179 fijNc U1 5V O 2 vipo O FROM CPU e roko
16. h N channel MOSFET The voltage at DRVH swings from GND to VCC 20 IGND Ground Reference GND should have a low impedance path to the source of hte svnchronous MOSFET ORDERING GUIDE Temperature LDO Package Package Model Range Voltage Description Option ADP3159JRU 0 C to 70 C 2 5V 1 8V Thin Shrink Small Outline RU 20 ADP3179JRU 0 C to 70 C Adjustable Thin Shrink Small Outline RU 20 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the ADP3159 and the ADP3179 feature proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Wa ESD SENSITIVE DEVICE REV A 3 ADP3159 ADP3179 Ivpical Performance Characteristics TEK RUN i 5 1 TRIG D 60 50 a E 1 40 E LU E T 30 o gt a a 20 2 no 10 0 0 100 200 300 400 500 600 700 800 CH1 5 00V By SRE 500mV By M 10 0ms A CH1 f 5 90V OSCILLATOR FREQUENCY kHz gt y 0 00000 s TPC 1 Supply Current vs Operating
17. hat a regulated output voltage is maintained as described below in the cycle by cycle operation The on time does not vary under fixed input supply conditions and it varies only slightly as a func tion of load This means that the switching frequency remains fairly constant in a standard computer application Active Voltage Positioning The output voltage is sensed at the CS pin A voltage error amplifier gm amplifies the difference between the output voltage and a programmable reference voltage The reference voltage is programmed to between 1 3 V and 2 05 V by an inter nal 4 bit DAC that reads the code at the voltage identification VID pins Refer to Table I for output voltage vs VID pin code information A unique supplemental regulation technique called REV A Analog Devices Optimal Positioning Technology ADOPT adjusts the output voltage as a function of the load current so that it is always optimally positioned for a load transient Stan dard passive voltage positioning sometimes recommended for use with other architectures has poor dynamic performance which renders it ineffective under the stringent repetitive tran sient conditions specified in Intel VRM documents Consequently such techniques do not allow the minimum possible number of output capacitors to be used ADOPT as used in the ADP3159 and ADP3179 provides a bandwidth for transient response that is limited only by parasitic output inductance This yields opti
18. hold Vrweepncov of Nominal DAC Voltage 115 120 125 Overvoltage Reset Point of Nominal DAC Voltage 40 50 60 Output Voltage Low VOLPWRGD IpwRGD SINK 1mA 250 500 mV Response Time 250 ns SUPPLY DC Supply Current Icc 7 9 mA UVLO Threshold Voltage VuvLo 6 75 7 25 V UVLO Hysteresis 0 8 1 1 2 V NOTES 1AJI limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control SQC Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs Specifications subject to change without notice REV A ADP3159 ADP3179 PIN FUNCTION DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS VGG sar eaten ities 0 3 V to 15 V l r DRVH DRVL LRDRVI LRDRV2 0 3 Vto VCC 0 3V Pin Mnemonic Function All Other Inputs and Outputs 0 3 V to 10 V 1 19 NC No Connection Op erating Ambient Temperature Range 0 C to TOG 2 5 VID3 VID2 Voltage Identification DAC Inputs These Operating Junction Temperature eae 129 VID1 VIDO pins are pulled up to an internal reference Storage Temperature Range 65 C to 150 C providing a Logic One if left open The Oya CA A A A A ME MA ME MA OK AS ai wen pine gee ee 143 C W DAC output programs the FB regulation Lead Temperature Soldering 10 sec 300 C voltage from 1 3 V to 2 05 V Vapor Phase 60 sec 6 215 C 6 PWRGD o drai it hat sinak vhent Infra
19. l O vec 16 POWER q LRFB2 GOOD C2 3 3V 68pF p 78 7kO c15 R2 1uF E 10kQ Q1 SUB45N03 13L ViR1 6 2 5V 2A ci L 1004F T D2 MBROS2LT1 O5V STANDBV D3 MBROS2LT1 012V C6 L2 T 1pF 19H l 5V Cc7 C8 bafer T 22pF T 1000uF I 1000F SUB45N03 13L R12 10004 Fx5 4m0 24m EACH VCC CORE o 1 30V TO L1 2 05V 1 7KH 15A Qs kalb E dur SUB75N03 07 gt C17 C18 C19 C20 C21 C11 C16 1pF SUB45N03 13L Figure 3 15 A Pentium III Application Circuit On board Linear Regulator Controllers The ADP3159 and ADP3179 include two linear regulator controllers to provide a low cost solution for generating additional supply rails In the ADP3159 these regulators are internally set to 2 5 V LRI and 1 8 V LR2 with 2 5 accuracy The ADP3179 is designed to allow the outputs to be set externally using a resistor divider The output voltage is sensed by the high input impedance LRFB x pin and compared to an internal fixed reference The LRDRV x pin controls the gate of an external N channel MOSFET resulting in a negative feedback loop The only addi tional components required are a capacitor and resistor for stability Higher output voltages can be generated by placing a resistor divider between the linear regulator output and its respective LRFB pin The maximum output load current is determined by the size and thermal impedance of the external power MOSFET that is placed in series with the supply and
20. mal Position ing Technology ADOPT to enhance load transient performance Active voltage positioning results in a dc dc con verter that meets the stringent output voltage specifications for high performance processors with the minimum number ADOPT is a trademark of Analog Devices Inc Pentium is a registered trademark of Intel Corporation Celeron is a trademark of Intel Corporation REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM vec cT DRVH 3 DRVL VID DAC A O VID3 VID2 VID1 VIDO of output capacitors and smallest footprint Unlike voltage mode and standard current mode architectures active voltage positioning adjusts the output voltage as a function of the load current so it is always optimally positioned for a system tran sient The devices also provide accurate and reliable short circuit protection and adjustable current limiting They also include an integrated overvoltage crowbar function to protect the microprocessor from destruction in case the core supply exceeds the nominal programmed voltage by more than 20 The ADP3159 and ADP3179 contain two fixed output vol
21. nce The capaci tance must be large enough that the voltage across the capacitor which is the sum of the resistive and capacitive voltage deviations does not deviate beyond the initial resistive deviation while the inductor current ramps up or down to the value corresponding to the new load current The maximum allowed ESR also repre sents the maximum allowed output resistance Rour The cumulative errors in the output voltage regulation cuts into the available regulation window Vwin When considering dynamic load regulation this relates directly to the ESR When consider ing dc load regulation this relates directly to the programmed output resistance of the power converter Some error sources such as initial voltage accuracy and ripple voltage can be directly deducted from the available regulation window while other error sources scale proportionally to the amount of voltage positioning used which for an optimal design should utilize the maximum that the regulation window will allow The error determination is a closed loop calculation but it can be closely approximated To maintain a conservative design while avoiding an impractical design various error sources should be considered and summed statistically The output ripple voltage can be factored into the calculation by summing the output ripple current with the maximum output current to determine an effective maximum dynamic current change The remaining errors are summed sepa
22. oad current will initially flow through the output capacitors 10 and this will produce an output voltage deviation equal to the ESR of the output capacitor array times the load current change TEK RUN 200kS s SAMPLE WALH T CH1 100mV CH2 M250ps CH2 J 680mV Figure 4 Transient Response of the Circuit of Figure 3 100 90 80 70 60 50 EFFICIENCY 40 30 20 0 2 4 6 8 10 12 14 16 18 20 OUTPUT CURRENT A Figure 5 Efficiencv vs Load Current of the Circuit of Figure 3 To correctly implement active voltage positioning the low fre quency output impedance i e the output resistance of the converter should be made equal to the maximum ESR of the output capacitor array This can be achieved by having a single pole roll off of the voltage gain of the gm error amplifier where the pole frequency coincides with the ESR zero of the output capacitor A gain with single pole roll off requires that the gm amplifier output pin be terminated by the parallel combination of a resistor and capacitor The required resistor value can be calculated from the equation _ Room X Rrorar 1MQx9 1kQ 9 2 kQ omP Room Rn PMOL ARO 24 where Rie ni X Rsense 25x 4mQ 79120 25 Em X Recmax 2 2 mmhox5 mQ In Equations 24 and 25 Rocm is the internal resistance of the Zm amplifier nz is the division ratio f
23. put current To prevent large voltage transients a low ESR input capacitor sized for the maximum rms current must be used The maximum rms capacitor current is given by Icirms Lo y Dusk Dusk 22 15 A 40 36 0 367 7 2 A For a ZA type capacitor with 1000 uF capacitance and 6 3 V voltage rating the ESR is 24 mQ and the maximum allowable ripple current at 100 kHz is 2 A At 105 C at least four such capacitors must be connected in parallel to handle the calculated ripple current At 50 C ambient however a higher ripple cur rent can be tolerated so three capacitors in parallel are adequate The ripple voltage across the three paralleled capacitors is ESRoun D Voeunyripeie Io x Roun HSF Mc Nc X Cin X fmax 24 mQ 36 23 Farms 715 Ax j9 mV 3 3x1000 uF x195 kHz To further reduce the effect of the ripple voltage on the system supply voltage bus and to reduce the input current di dt to below the recommended maximum of 0 1 A ms an additional small inductor L gt 1 uH 10 A should be inserted between the converter and the supply bus Feedback Compensation for Active Voltage Positioning Optimized compensation of the ADP3159 allows the best pos sible containment of the peak to peak output voltage deviation Any practical switching power converter is inherently limited by the inductor in its output current slew rate to a value much less than the slew rate of the load Therefore any sudden change of l
24. rately according to the formula Vin Va Vym X 2 kym x 6 2 AOS Eh Hkg 95mV where kjip 0 5 is the initial programmed voltage tolerance from the graph of TPC 6 Recs 2 is the tolerance of the current sense resistor kosr 10 is the summed tolerance of the current sense filter components kgr 2 is the tolerance of the two termination resistors added at the COMP pin and kga 8 accounts for the IC current loop gain tolerance including the g tolerance The remaining window is then divided by the maximum output current plus the ripple to determine the maximum allowed ESR and output resistance 95mV 15443 8 A The output filter capacitor bank must have an ESR of less than 5 mQ One can for example use five ZA series capacitors from Rubycon which would give an ESR of 4 8 mQ Without ADOPT voltage positioning the ESR would need to be less than 3 mQ yielding a 50 increase to eight Rubycon output capacitors Vwin Io Loa Rewmax Rour max 5 mQ 6 Cour Checking the Capacitance As long as the capacitance of the output capacitor is above a critical value and the regulating loop is compensated with ADOPT the actual value has no influence on the peak to peak deviation of the output voltage to a full step change in the load current The critical capacitance can be calculated as follows fo xL Re XVour 7 EL AR 7 5 mQ x 1 7 Cour crir The critical capacitance for the five ZA series
25. re X Ri 32 Assuming that Ry 710 kQ Vovran 1 2 V and rearranging equation 32 to solve for Ry yields _ 10 kQ x Vourar Virre 33 gt Virre 10 kQx 1 2V 1V Ry IV 2kQ 11 ADP3159 ADP3179 Efficiencv of the Linear Regulators The efficiency and corresponding power dissipation of each of the linear regulators are not determined by the controller IC Rather these are a function of input and output voltage and load current Efficiency is approximated by the formula V n 100 x 2 34 Vin The corresponding power dissipation in the MOSFET together with anv resistance added in series from input to output is given by Pipo Vin Vour x Jour 35 Minimum power dissipation and maximum efficiency are accom plished by choosing the lowest available input voltage that exceeds the desired output voltage However if the chosen input source is itself generated by a linear regulator its power dissipation will be increased in proportion to the additional current it must now provide Implementing Current Limit for the Linear Regulators The circuit of Figure 6 gives an example of a current limit pro tection circuit that can be used in conjunction with the linear regulators The output voltage is internally set by the LRFB pin The value of the current sense resistor may be calculated as follows _540mV _ 540 mV 2 2 A Rs 250 mQ 36 Lomax The power rating of the current sense resistor must be
26. red 15 Se iii ia i ea Reus aia 220 C Pra ER re RR output voltage is in the proper operating This is a stress rating only operation beyond these limits can cause the device to range be permanently damaged Unless otherwise specified all voltages are referenced L R to GND 7 15 LREB1 Feedback connections for the linear LRFB2 regulator controllers 8 14 LRDRV1 Gate drives for the respective linear LRDRV2 regulator N channel MOSFETs 9 FB Feedback Input Error amplifier input for remote sensing of the output voltage 10 CS Current Sense Negative Node Negative PIN CONFIGURATION input for the current comparator 11 CS Current Sense Positive Node Positive RU 20 input for the current comparator The output current is sensed as a voltage at this Ne sla ajeno pin with respect to CS ke Ejes 12 CT External capacitor connected from CT to vio e lte Dave ground sets the Off time of the device vib A ADP3159 yes 13 COMP Error Amplifier Output and Compensation via s ADP3179 to vec Point The voltage at this output programs PwReD LEN TOR VIEW ps LRFB2 the output current control level between LRFB1 14 LRDRV2 CS and CS LADAVI 8 13 comp 16 JVCC Supply Voltage for the device FB e 12 cr 17 DRVL Low Side MOSFET Drive Gate drive for cs iol 11 ess the synchronous rectifier N channel NC NO CONNECT MOSFET The voltage at DRVL swings from GND to VCC 18 JDRVH High side MOSFET Drive Gate drive for the buck switc
27. res PQ U and E cores or toroids cost more but have much better EMI RFI performance A good compromise between price and performance are cores with a toroidal shape 1 Vin Lomax X CRosconyusr Rsense Ri Vovr 3 fun torr Vin Lomax X CRpsconyusr Rsense Ri Roscon tsr REV A ADP3159 ADP3179 There are many useful references for quickly designing a power inductor Table II gives some examples Table II Magnetics Design References Magnetic Designer Software Intusoft http www intusoft com Designing Magnetic Components for High Frequency DC DC Converters McLyman Kg Magnetics ISBN 1 883107 00 08 Selecting a Standard Inductor The companies listed in Table III can provide design consul tation and deliver power inductors optimized for high power applications upon request Table III Power Inductor Manufacturers Coilcraft 847 639 6400 http www coilcraft com Coiltronics 561 752 5000 http www coiltronics com Sumida Electric Companv 408 982 9660 http www sumida com Cour Selection Determining the ESR The required equivalent series resistance ESR and capacitance drive the selection of the tvpe and quantitv of the output capaci tors The ESR must be small enough to contain the voltage deviation caused bv a maximum allowable CPU transient cur rent within the specified voltage limits giving consideration also to the output ripple and the regulation tolera
28. rom the output voltage to signal of the g amplifier to the PWM comparator and g is the transconductance of the gm amplifier itself REV A ADP3159 ADP3179 Although a single termination resistor equal to Rcomp would vield the proper voltage positioning gain the dc biasing of that resistor would determine how the regulation band is centered i e offset Note that sometimes the specified regulation band is asymmetrical with respect to the nominal VID voltage With the ADP3159 the offset is already considered part of the design procedure no special provision is required To accomplish the dc biasing it is simplest to use two resistors to terminate the gm amplifier output with the lower resistor Rg tied to ground and the upper resistor Ra to the 12 V supply of the IC The values of these resistors can be calculated using Vow _ 12V En XWVourwosy K 2 2 mmho x 22 mV 4 7x107 Ra 79 1kQ 26 where K is a constant determined by internal characteristics of the ADP3159 peak to peak inductor current ripple Iprppi p and the current sampling resistor Rsgynsg K can be calculated using Equations 28 and 29 Vpyy is the resistor divider supply voltage e g the recommended 12 V supply and Vouros is the output voltage offset from the nominal VID programmed value under no load condition This offset is given by Equation 30 The closest 1 value for Ra is 78 7 kQ This value is then used to solve for Rg _ Ra X Rcomp
29. s the two FETs and the power Schottky diode if used including all interconnecting PCB traces and planes The use of short and wide interconnection traces is especially critical in this path for two reasons it minimizes the inductance in the switching loop which can cause high energy ringing and it accommodates the high current demand with minimal voltage loss REV A ADP3159 ADP3179 8 REV A A power Schottky diode 1 2 A dc rating placed from the lower MOSFET s source anode to drain cathode will help to minimize switching power dissipation in the upper MOSFET In the absence of an effective Schottky diode this dissipation occurs through the following sequence of switching events The lower MOSFET turns off in advance of the upper MOSFET turning on necessary to prevent cross conduction The circulating current in the power converter no longer finding a path for current through the channel of the lower MOSFET draws current through the inherent body drain diode of the MOSFET The upper MOSFET turns on and the reverse recovery characteristic of the lower MOSFET s body drain diode prevents the drain voltage from being pulled high quickly The upper MOSFET then conducts very large current while it momentarily has a high voltage forced across it which translates into added power dissipation in the upper MOSFET The Schottky diode minimizes this problem by carrying a majority of the circu lating current when the lower MOSF
30. s to approximately 25 of the 15 A full load dc current in an induc tor Equation 4 yields an inductance of _1 7V x3 3 us 4A L 1 4uH A 1 5 uH inductor can be used which gives a calculated ripple current of 3 8 A at no load The inductor should not saturate at the peak current of 17 A and should be able to handle the sum of the power dissipation caused by the average current of 15 A in the winding and the core loss Designing an Inductor Once the inductance is known the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals The first decision in designing the inductor is to choose the core material There are several possibilities for providing low core loss at high frequen cies Two examples are the powder cores e g Kool Mu from Magnetics Inc and the gapped soft ferrite cores e g 3F3 or 3F4 from Philips Low frequency powdered iron cores should be avoided due to their high core loss especially when the inductor value is relatively low and the ripple current is high Two main core types can be used in this application Open magnetic loop types such as beads beads on leads and rods and slugs provide lower cost but do not have a focused mag netic field in the core The radiated EMI from the distributed magnetic field may create problems with noise interference in the circuitry surrounding the inductor Closed loop types such as pot co
31. t age linear regulator controllers that are designed to drive external N channel MOSFETs The outputs are internally fixed at 2 5 V and 1 8 V in the ADP3159 while the ADP3179 provides adjustable output which is set using an external resistor divider These linear regulators are used to generate the auxiliary voltages AGP GTL etc required in most moth erboard designs and have been designed to provide a high bandwidth load transient response The ADP3159 and ADP3179 are specified over the commercial temperature range of 0 C to 70 C and are available in a 20 lead TSSOP package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2001 AD P31 59 AD P31 19 SPEC FI CATI ONS VCC 12 V T 0 C to 70 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit FEEDBACK INPUT Output Accuracy Ves 1 3 V Output Figure 1 1 289 1 3 1 311 V 1 65 V Output Figure 1 1 637 1 65 1 663 V 2 05 V Output Figure 1 2 034 2 05 2 066 V Line Regulation AVoutr VCC 10Vto 14 V 0 06 Crowbar Trip Point Vcrowsar of Nominal DAC Voltage 115 120 125 Crowbar Reset Point of Nominal DAC Voltage 40 50 60 Crowbar Response Time tcROWBAR Overvoltage to DRVL Going High 400 ns VID INPUTS Input Low Voltage ViLvm 0 6 V Input High Voltage Vivin 2 0 V Input Current vip VID X 0 V 185 250 LA Pull Up Resist
32. t least Prsovse Uo hu x RsENSE 20 Ay x4mO 1 6W a 1 Power MOSFETs Two external N channel power MOSFETs must be selected for use with the ADP3159 one for the main switch and an identical one for the synchronous switch The main selection parameters for the power MOSFETs are the threshold voltage Vascrm and the ON resistance Rps on The minimum input voltage dictates whether standard threshold or logic level threshold MOSFETs must be used For Vw gt 8 V standard threshold MOSFETs Vcserm lt 4 V may be used If Vin is expected to drop below 8 V logic level threshold MOSFETs Vasra lt 2 5 V are strongly recommended Only logic level MOSFETs with Vas ratings higher than the absolute maximum value of Vcc should be used The maximum output current lomax determines the Rpscon requirement for the two power MOSFETs When the ADP3159 is operating in continuous mode the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current For Vw 5 V and Voyr 1 65 V the maximum duty ratio of the high side FET is Dusrmax 1 fun X torr Dusrqmax 1 195 Hz x 3 3 ps 36 12 REV A The maximum duty ratio of the low side synchronous rectifier MOSFET is Disr max 1 Dusr max 54 13 The maximum rms current of the high side MOSFET is 2 2 Th VALLEY CU wattey x IL PEAK T IL PEAK IrmsHsF T x 3 2 2 14 Meee 30 13
33. tage Vm 5 V Auxiliary Input Vcc 12 V Output Voltage Vvip 1 7 V Maximum Output Current lomax 15 A Minimum Output Current lomm 1 A Static tolerance of the supply voltage for the processor core AVo 40 mV 80 mV 120 mV Transient tolerance for less than 2 us of the supply voltage for the processor core when the load changes between the minimum and maximum values with a di dt of 20 A us AVorrRANSIENT 80 mV 130 mV 210 mV Input current di dt when the load changes between the mini mum and maximum values lt 0 1 A us The above requirements correspond to Intel s published power supply requirements based on VRM 8 4 guidelines CT Selection for Operating Frequency The ADP3159 uses a constant off time architecture with torr determined by an external timing capacitor CT Each time the high side N channel MOSFET switch turns on the voltage across CT is reset to 0 V During the off time CT is discharged by a constant current of 150 uA Once CT reaches 3 0 V a new on time cycle is initiated The value of the off time is calculated using the continuous mode operating frequency Assuming a nominal operating frequency fyom of 200 kHz at an output voltage of 1 7 V the corresponding off time is Pees l Your 1 Vin Jnom 1 7V 1 1 torr 1 x 3 3 us ra zr 200 kHz z The timing capacitor can be calculated from the equation Cr torr X Icr _ 3 3 us x150 u4 150 pF eax 3V 2
34. to be removed from the gate for turn off and Ig is the gate current From the data sheet Qg is 70 nC and the gate drive current provided by the ADP3159 is about 1 A The low side MOSFET dissipation is 2 Poise Irms sr X Rpscon Poisr 10 8 A X10 mMQ 1 08 W Note that there are no switching losses in the low side MOSFET 20 ADP3159 ADP3179 Surface mount MOSFETs are preferred in CPU core converter applications due to their ability to be handled by automatic assembly equipment The TO 263 package offers the power handling of a TO 220 in a surface mount package However this package still needs adequate copper area on the PCB to help move the heat away from the package The junction temperature for a given area of 2 ounce copper can be approximated using T 814 x Pp Ta 21 assuming 074 45 C W for 0 5 in 074 36 C W for 1 in 9 1 28 C W for 2 in For 1 in of copper area attached to each transistor and an ambient temperature of 50 C Tsp 36 C W x 1 48 W 50 C 103 C TiLse 36 C W x 1 08 W 50 C 89 C All of the above calculated junction temperatures are safely below the 175 C maximum specified junction temperature of the selected MOSFETs Cin Selection and Input Current di dt Reduction In continuous inductor current mode the source current of the high side MOSFET is approximately a square wave with a duty ratio equal to Vour Vin and an amplitude of one half of the maximum out
35. wer circuitry it is best if a ground plane can be inter posed between those signal lines and the traces of the power circuitry This serves as a shield to minimize noise injection into the signals at the cost of making signal ground a bit noisier 4 The GND pin of the controller IC should connect first to a ceramic bvpass capacitor on the VCC pin and then into the power ground plane However the ground plane should not extend under other signal components including the ADP3159 itself 5 The output capacitors should also be connected as closely as possible to the load or connector that receives the power e g a microprocessor core If the load is distributed the capacitors should also be distributed and generally in proportion to where the load tends to be more dynamic It is also advised to keep the planar interconnection path short i e have input and output capacitors close together 6 Absolutely avoid crossing any signal lines over the switching power path loop described below Power Circuitry 7 The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy i e EMI Failure to take proper precaution often results in EMI problems for the entire PC system as well as noise related operational prob lems in the power converter control circuitry The switching power path is the loop formed by the current path through the input capacitor
Download Pdf Manuals
Related Search
ANALOG DEVICES ADP3159/ADP3179 4 Bit Programmable Synchronous Buck Controllers handbook