ANALOG DEVICES ADP3158/ADP3178 4-Bit Programmable Synchronous Buck Controllers handbook
Contents
1. REV A ADP3158 ADP3178 ADP3158 ADP3178 4 BIT CODE Figure 1 Closed Loop Output Voltage Accuracy Test Circuit ADP3158 ADP3178 Figure 2 Linear Regulator Output Voltage Accuracy Test Circuit THEORY OF OPERATION TheADP3158 and ADP3178 use a current mode constant off time control technique to switch a pair of external N channel MOSFET sin asynchronous buck topology C onstant off time operation offers several performance advantages including that no slope compensation is required for stable operation A unique feature of the constant off time control technique is that since the off time is fixed the converter s switching frequency is a function of the ratio of input voltage to output voltage T he fixed off time is programmed by the value of an external capaci tor connected to the CT pin T he on time varies in such a way that a regulated output voltage is maintained as described below in the cycle by cycle operation T he on time does not vary under fixed input supply conditions and it varies only slightly as a function of load T his means that the switching frequency remains fairly constant in a standard computer application Active Voltage Positioning T he output voltage is sensed at the CS pin A voltage error amplifier gm amplifies the difference between the output voltage and a programmable reference voltage T he reference voltage is programmed to between 1 3 V and 2 05 V by an inter nal 4 bit2. SUB75N03 07 Figure 3 15 A Pentium III Application Circuit T he linear regulator controllers have been designed so that they APPLICATION INFORMATION remain active even when the switching controller isin UVLO mode Specifications for a Design Example to ensure that the output voltages of the linear regulators will track T he design parameters for a typical 750 M Hz Pentium II appli the 3 3 V supply as required by Intel design specifications By cation shown in Figure 3 are as follows diode ORing the VCC input of the IC to the 5 VSB and 12 V W supplies as shown in Figure 3 the switching output will be disabled Input voltage MUY in standby mode but the linear regulators will begin conducting Auxiliary Input Vcc 12 V once VCC rises above about 1 V During start up the linear out Output Voltage Vy p 1 7 V puts will track the 3 3 V supply up until they reach their respective regulation points regardless of the state of the 12 V supply Once M aximum Output Current lo max 15 A the 12 V supply has exceeded the 5 VSB supply by more than a Minimum Output Current lo min 1 A diode drop the controller IC will track the 12 V supply Once the Static tolerance of the supply voltage for the processor core 12 V supply has risen above the UVLO value the switching regula AV 40 mV 80 mV 120 mV tor will begin its start up seguence 4 E PSA Transient tolerance for less than 2 us of the supply voltage for the pro
3. Signal Circuitry 12 The output voltage is sensed and regulated between the GND pin which connects to the signal ground plane and the CS pin The output current is sensed as a voltage and regulated between the CS pin and the CS pin In order to avoid differential mode noise pickup in those sensed signals their loop areas should be small T hus the C S trace should be routed atop the signal ground plane and the CS and CS traces should be routed as a closely coupled pair CS should be over the signal ground plane as well 13 TheCS and CS traces should be K elvin connected to the current sense resistor so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage It is desir able to have the controller IC close to the output capacitor bank and not in the output power path so that any voltage drop between the output capacitors and the GND pin is minimized and voltage regulation is not compromised OUTLINE DIMENSIONS Dimensions shown in inches and mm 16 Lead SOIC R 16A SO 16 0 3937 10 00 5 0 3859 9 80 16 0 1574 4 00 0 1497 3 80 v el Js PIN1 9 050 B a 0 2440 6 20 127 0 0688 1 75 0 2284 5 80 0 0196 0 50 SC 0 0532 1 35 0 0099 0 25 HARA 2 whe 8 0 0098 0 25 0 0192 0 49 SEATING 9 9999 0 25 0 0 0500 1
4. lo Cour rin eames 15A 7 A 2 6mF 5mox1 7 gt The critical capacitance for the five ZA series Rubycon capaci tors is 2 6 mF while the equivalent capacitance is 5 mF The capacitance is safely above the critical value REV A ADP3158 ADP3178 Rsense T he value of Rsense is based on the maximum required output current T he current comparators of the ADP3158 and ADP3178 have a minimum current limit threshold of 69 mV N ote that the 69 mV value cannot be used for the maximum specified nominal current as headroom is needed for ripple current and tolerances T he current comparator threshold sets the peak of the inductor current yielding a maximum output current l which equals twice the peak inductor current value less half of the peak to peak induc tor ripple current From this the maximum value of Reense is calculated as Vescea MIN _ 69MV O 15A 1 9A 8 Rsense lt L RIPPLE lo jp SEURIPRLE N 2 In this case 4 mQ was chosen as the closest standard value Once Rsense has been chosen the output current at the point where current limit is reached loyr c can be calculated using the maximum current sense threshold of 87 mV Veset MAX x l L RIPPLE Rsense 2 _87mV _3 8A aoa 9 4mQ 2 At output voltages below 450 mV the current sense threshold is reduced to 54 mV and the ripple current is negligible T here fore at dead short the output current is reduced to loutict 54 m
5. 27 0 0040 0 10 0 0138 0 35 PLANE 5 Ooze 949 0 0160 0 41 14 REV A Revision History ADP3158 ADP3178 Location Page Global change from ADP3158 to ADP3158 AD P3178 Change from REV Oto REV A Edits to GENERAL DESCRIPTION ci a t tua Maite deanna wag por wand on edu a osaajaa man 1 Edits to FUNCTIONAL BLOCK DIAGRAM cece ccc e al Edit to ERROR AMPLIFIER section of the SPECIFICATIONS 1 ccc an 2 Addition to LINEAR REGULATORS section of the SPECIFICATIONS aoaaa 2 Addition to ORDERING GUIDE siat ssa a and V array ad toes kod AKAA ater ada aaa ota aa t heir ante eaten AA an 3 Edits to the On board Linear Regulator Controllers section 2 0 0 eet 5 Edit to AQUA ioe ones eee H nie ede mark 6 Edits to Eguations 24 127 and lt 3 ecc id ae tana ta ana Seles detache laude ants lataa a aa MATKAA Soka Selenite 11 Addition of new text to Linear Regulators Section msn 12 REV A 15 v L0 2 9 1 681Z09 W S N NI AJINIHA 16
6. 54 13 T he maximum rms current of the high side MOSFET is 2 2 D li vaLLEY li vaLLEY XI L PEAK IL peak RMSHSF HSF MAX X 3 2 7 14 eee 69 ELA s see Kn The maximum rms current of the low side MOSFET is 2 2 Ya IL VALLEY I vartev XI L PEAK i PEAK laMsisr En Dis max X 3 2 2 15 oe 54 x ELA 13 1 A EAA Sig sans T he Rpsion for each MOSFET can be derived from the allowable dissipation If 10 of the maximum output power is allowed for MOSFET dissipation the total dissipation will be Po rers 0 1xVour Xlout max 2 26W 16 Allocating half of the total dissipation for the high side M OSFET and half for the low side MOSFET and assuming that switching losses are small relative to the dc conduction losses the required minimum MOSFET resistances will be P 1 13W R lt 15mQ DS ON HSF Ine BBA 17 P 1 13W R lt BE 10m2 DS ON LSF lisp 10 8 A 18 ADP3158 ADP3178 N ote that there is a trade off between converter efficiency and cost Larger MOSFET sreduce the conduction losses and allow higher efficiency but increase the system cost If efficiency is not a major concern a Vishay Siliconix SU B45N 03 13L Rpsion 10 mQ nominal 16 mQ worst case for the high side and a Vishay Siliconix SU B75N 03 07 Ros on 6 MQ nominal 10 mQ worst case for the low side are good choices T he high side MOSFET dissipation is p 2 R Vi
7. DAC that reads the code at the voltage identification VID pins Refer to T able for output voltage vs VID pin code information A unique supplemental regulation technique called Analog D evices Optimal Positioning T echnology ADOPT adjusts the output voltage as a function of the load current so it is always optimally positioned for a load transient Standard passive voltage positioning sometimes recommended for use with other architectures has poor dynamic performance which renders it ineffective under the stringent repetitive transient conditions specified in Intel VRM documents C onsequently REV A such techniques do not allow the minimum possible number of output capacitors to be used ADOPT as used in the ADP3158 and AD P3178 provides a bandwidth for transient response that is limited only by parasitic output inductance T his yields opti mal load transient response with the minimum number of output capacitors Cycle by Cycle Operation During normal operation when the output voltage is regulated the voltage error amplifier and the current comparator are the main control elements D uring the on time of the high side MOSFET the current comparator monitors the voltage between the CS and CS pins When the voltage level between the two pins reaches the threshold level the DRVH output is switched to ground which turns off the high side MOSFET Thetiming capacitor CT is then charged at a rate determined by the off time
8. being pulled high quickly The upper MOSFET then conducts very large current while it momentarily has a high voltage forced across it which translates into added power dissipation in the upper M OSF ET T he Schottky diode minimizes this problem by carrying a majority of the circu lating current when the lower M OSFET is turned off and by virtue of its essentially nonexistent reverse recovery time Whenever a power dissipating component e g a power MOSFET is soldered to a PCB the liberal use of vias both directly on the mounting pad and immediately sur rounding it is recommended T wo important reasons for this are improved current rating through the vias if it isa current path and improved thermal performance espe cially if the vias extend to the opposite side of thePCB where a plane can more readily transfer the heat to the air The output power path though not as critical as the switch ing power path should also be routed to encompass a small area T he output power path is formed by the current path through the inductor the current sensing resistor the out put capacitors and back to the input capacitors For best EMI containment the ground plane should extend fully under all the power components T hese are the input capacitors the power MOSFETs and Schottky diode the inductor the current sense resistor any snubbing elements that might be added to dampen ringing and the output capacitors ADP3158 ADP3178
9. calculated from the equation Rocm XRrora _ 1MQx9 1kQ Rcomp 9 2k0 AAR Room Rrora 1MQ 9 1kQ 24 where n XRsense 25x4mQ RroraL 9 1k0 ii Om X Remax 2 2 mmhox5mQ 25 In Equations 24 and 25 Rocm is the internal resistance of the gn amplifier n is the division ratio from the output voltage to signal of the gm amplifier to the PWM comparator and gm is the transconductance of the g amplifier itself Although a single termination resistor equal to Rcomp would yield the proper voltage positioning gain the dc biasing of that resistor would determine how the regulation band is centered i e offset N ote that sometimes the specified regulation band is asymmetrical with respect to the nominal VID voltage With the AD P3158 and AD P3178 the offset is already considered part of the design procedure no special provision is required To accomplish the dc biasing it is simplest to use two resistors to terminate the gm amplifier output with the lower resistor Rg tied to ground and the upper resistor Ra to the 12 V supply of the IC T he values of these resistors can be calculated using 2 Vow oe 12V Om XWout os K 2 2mmhox 22mV 4 7x107 79 1k 26 Ra REV A where K isa constant determined by internal characteristics of the ADP3158 and ADP3178 peak to peak inductor current ripple Ipippte and the current sampling resistor Rsense K can be calculated using Equations 28 and 29 Vpyy is the resis
10. controller While the timing capacitor is charging the DRVL output goes high turning on the low side MOSFET When the voltage level on the timing capacitor has charged to the upper threshold voltage level a comparator resets a latch T he output of the latch forces the low side drive output to go low and the high side drive output to go high As a result the low side switch is turned off and the high side switch is turned on T he sequence is then repeated As the load current increases the output voltage starts to decrease T his causes an increase in the output of the voltage error amplifier which in turn leads to an increase in the current comparator threshold thus tracking the load cur rent To prevent cross conduction of the external MOSFETs feedback is incorporated to sense the state of the driver output pins Before the low side drive output can go high the high side drive output must be low Likewise the high side drive output is unable to go high while the low side drive output is high Output Crowbar An added feature of using an N channel MOSFET as the syn chronous switch is the ability to crowbar the output with the same MOSFET If the output voltage is 20 greater than the targeted value the controller IC will turn on the lower MOSFET which will current limit the source power supply or blow itsfuse pull down the output voltage and thus save the microprocessor from destruction T he crowbar function releases at approxi
11. mately 50 of the nominal output voltage F or example if the output is programmed to 1 5 V but is pulled up to 1 85 V or above the crowbar will turn on the lower MOSFET If in this case the output is pulled down to less than 0 75 V the crowbar will release allowing the output voltage to recover to 1 5 V if the fault condition has been removed On board Linear Regulator Controllers The ADP3158 and AD P3178 include two linear regulator con trollers to provide a low cost solution for generating additional supply rails In the AD P3158 these regulators are internally set to 2 5 V LR1 and 1 8 V LR2 with 2 5 accuracy T he AD P3178 is designed to allow the outputs to be set externally using a resistor divider T he output voltage is sensed by the high input impedance LRF B x pin and compared to an internal fixed reference TheLRDRV x pin controls the gate of an external N channel MOSFET resulting in a negative feedback loop T he only addi tional components required are a capacitor and resistor for stability The maximum output load current is determined by the size and thermal impedance of the external power MOSFET that is placed in series with the supply 5 ADP3158 ADP3178 D2 MBRO52LT1 O5V STANDBY D3 MBRO52LT1 012V C6 Ea I 1pF 1pH z 5v C7 C8 C9 T 22uF T 1000uF T 1000pF ADP3158 ONEN 10004F x 5 o at 24m0 EACH voc CORE gt te te te fe 2 05V FROM CPU FIIT 15A C17 C18C19C20 C21 SUB45N03 13L
12. radiated switching noise energy i e EM I Failure to take proper precaution often results in EM problems for the entire PC system as well as noise related operational prob lems in the power converter control circuitry T he switching power path is the loop formed by the current path through the input capacitors the two FET s and the power Schottky REV A 10 11 13 diode if used including all interconnecting PCB traces and planes T he use of short and wide interconnection traces is especially critical in this path for two reasons it minimizes the inductance in the switching loop which can cause high energy ringing and it accommodates the high current demand with minimal voltage loss A power Schottky diode 1 2 A dc rating placed from the lower M OSFET s source anode to drain cathode will help to minimize switching power dissipation in the upper MOSFET InthebA6ONx ofan effective Schottky diode this dissipation occurs through the following sequence of switching events T he lower MOSFET turns off in advance of the upper MOSFET turning on necessary to prevent cross conduction T he circulating current in the power converter no longer finding a path for current through the channel of the lower MOSFET draws current through the inherent body drain diode of the MOSFET T he upper MOSFET turns on and the reverse recovery characteristic of the lower M OSF ET s body drain diode prevents the drain voltage from
13. 178 contain two linear regulator controllers that are designed to drive external N channel MOSFETs The outputs are internally fixed at 2 5 V and 1 8 V in the AD P3158 while the AD P3178 provides adjustable out puts that are set using an external resistor divider T hese linear regulators are used to generate the auxiliary voltages AGP GTL etc required in most motherboard designs and have been designed to provide a high bandwidth load transient response The ADP3158 and AD P3178 are specified over the commercial temperature range of 0 C to 70 C and are available in a 16 lead SOIC package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2001 ADP3 158 ADP3 178 SPECI FICATI ONS VCC 12 V T 0 C to 70 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit SWITCHING REGULATOR Output Accuracy Ves 1 3 V Output Figure 1 1 289 13 1 311 V 1 65 V Output Figure 1 1 637 1 65 1 663 V 2 05 V Output Figure 1 2 034 2 05 2 066 V Line Regulation AV out VCC 10V to 14V 0 06 Crowbar T rip Point VCROWBAR of Nominal DAC Voltage 115 120 125 Crowbar Reset Point of Nominal DAC Voltage 40 50 60 Crowbar Response T ime CROWBAR Overvoltage to DRVL Going High 400 ns VID INPUTS Input Low Voltage Vitti 0 6 V Input H igh Voltage ViH vin 2 0 V Input Current I vin VID X 0V 185 250 JA Pull U p Resistance
14. 3V 150 pF 2 3 Vin locmax X Roscon msr Rsense R Vour Tuin torr Vin lo MAX X Rosion JHSF Rsense R Ros on use T he converter only operates at the nominal operating frequency at the above specified Voy7 and at light load At higher values of Vour or under heavy load the operating frequency decreases due to the parasitic voltage drops across the power devices T he actual minimum frequency at Vout 1 7 V is calculated to be 195 kH z see Equation 3 where Rosiown use s the resistance of the high side M OSF ET estimated value 14 mQ Rosionyisr Is the resistance of the low side MOSFET estimated value 6 mQ Rsense is the resistance of the sense resistor estimated value 4 mQ R is the resistance of the inductor estimated value 3 MQ REV A Inductance Selection T he choice of inductance determines the ripple current in the inductor Less inductance leads to more ripple current which increases the output ripple voltage and the conduction losses in the MOSFETs but allows using smaller size inductors and for a specified peak to peak transient deviation output capacitors with less total capacitance C onversely a higher inductance means lower ripple current and reduced conduction losses but requires larger size inductors and more output capacitance for the same peak to peak transient deviation T he following equation shows the relationship between the inductance oscillator frequ
15. EA D P3158 H hy RS ANALOG DEVICES 4 Bit Programmable Synchronous Buck Controllers ADP3158 ADP3178 FEATURES Optimally Compensated Active Voltage Positioning with Gain and Offset Adjustment ADOPT for Superior Load Transient Response Complies with VRM Specifications with Lowest System Cost 4 Bit Digitally Programmable 1 3 V to 2 05 V Output N Channel Synchronous Buck Driver Total Accuracy 0 8 Over Temperature Two On Board Linear Regulator Controllers Designed to Meet System Power Seguencing Reguirements High Efficiency Current Mode Operation Short Circuit Protection for Switching Regulator Overvoltage Protection Crowbar Protects Micro processors with No Additional External Components APPLICATIONS Core Supply Voltage Generation for Intel Pentium III Intel Celeron GENERAL DESCRIPTION The ADP3158 and ADP3178 are highly efficient synchronous buck switching regulator controllers optimized for converting a 5 V main supply into the core supply voltage required by high performance processors T hese devices use an internal 4 bit DAC to read a voltage identification VID code directly from the processor which is used to set the output voltage between 1 3 V and 2 05 V T hey use a current mode constant off time archi tecture to drive two N channel M OSF ET sat a programmable switching freguency that can be optimized for regulator size and efficiency TheADP3158 and ADP3178 also use a unique supplemental r
16. PCB layers vias should be used liberally to create several parallel current paths so that the resistance and inductance intro duced by these current paths is minimized and the via current rating is not exceeded If critical signal lines including the voltage and current sense lines of the controller IC must cross through power circuitry it is best if a ground plane can be interposed between those signal lines and the traces of the power circuitry T his serves as a shield to minimize noise injec tion into the signals at the cost of making signal ground a bit noisier The GND pin should connect first to a ceramic bypass capacitor on the VCC pin and then into the power ground plane H owever the ground plane should not extend under other signal components including the controller IC itself T he output capacitors should also be connected as closely as possible to the load or connector that receives the power e g a microprocessor core If the load is distributed the capacitors should also be distributed and generally in proportion to where the load tends to be more dynamic It is also advised to keep the planar interconnection path short i e have input and output capacitors close together Absolutely avoid crossing any signal lines over the switching power path loop described below Power Circuitry 7 T he switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize
17. Rvip 20 30 kQ Internal Pull U p Voltage 5 0 5 4 5 7 V OSCILLATOR Off Time TA 25 C CT 200 pF 3 5 4 0 4 5 us CT Charge Current ler Ta 25 C Vout in Regulation 130 150 170 JA TA 25 C Vour 0V 25 35 45 JA ERROR AMPLIFIER Output Resistance R over 1 MQ T ransconductance Om ERR 2 05 2 2 2 35 mmho Output Current lO ERR CS Forced to Vout 3 625 JA M aximum Output Voltage VCOMP MAX CS Forced to Vout 3 3 0 V Output Disable T hreshold VCOMP OFF 600 750 900 mV 3 dB Bandwidth BW ERR COMP 0pen 500 kHz CURRENT SENSE T hreshold Voltage Ves rH CS Forced to Vout 3 69 78 87 mV CS lt 0 45 V 35 45 54 mV 0 8V lt COMP lt 1V 1 5 mV Input Bias Current lesa lcs CS CS Vout 0 5 5 JA Response T ime tes CS CS gt 87 mV to DRVH 50 ns Going Low OUTPUT DRIVERS Output Resistance RocDRV x Il 50 mA 6 Q Output T ransition Time tr tr C 3000 pF 80 ns LINEAR REGULATORS Feedback Current leo 0 3 1 JA LR1 Feedback Voltage LRFB 1 AD P3158 Figure 2 2 44 2 5 2 56 V VCC 4 5 V to 12 6 V AD P3178 Figure 2 0 97 1 0 1 03 V VCC 4 5 V to 12 6 V LR2 Feedback Voltage VLRFB 2 AD P3158 Figure 2 1 75 1 8 1 85 V VCC 4 5 V to 12 6 V AD P3178 Figure 2 0 97 1 0 1 03 V VCC 4 5 V to 12 6 V Driver Output Voltage VI RDRV X VCC 4 5 V VLRFB X 0V 4 2 V SUPPLY DC Supply Current lec 7 9 mA UVLO Threshold Voltage Vuvio 6 75 7 7 25 V UVLO Hysteresis 0 8 l 1 2 V NOTES TAII limits at temperature extremes are guaranteed
18. V loutisc Amo 13 5A 10 To Safely carry the current under maximum load conditions the sense resistor must have a power rating of at least PRsense lo xRsense 20 A x4 mQ 1 6W 11 Power MOSFETs Two external N channel power MOSFETs must be selected for use with the AD P3158 and ADP3178 one for the main switch and an identical one for the synchronous switch T he main selection parameters for the power M OSFET s are the threshold voltage Vcsiruy and the ON resistance Rpsjon J T he minimum input voltage dictates whether standard threshold or logic level threshold M OSF ET s must be used For Vin gt 8V standard threshold MOSFET s Vesen lt 4 V may be used If REV A Vin is expected to drop below 8 V logic level threshold MOSFETs Vos lt 2 5 V are strongly recommended Only logic level MOSFET swith Ves ratings higher than the absolute maximum value of Vcc should be used T he maximum output current lom ax determines the Ros ow requirement for the two power MOSFET s When the AD P3158 and ADP3178 are operating in continuous mode the simplifying assumption can be made that one of the two M OSF ET sis always conducting the average load current For Vin 5 V and Vout 1 65 V the maximum duty ratio of the high side FET is Dusecmax 1 fuin Xtore Duse max 1 195 kH z x 3 3 us 36 12 T he maximum duty ratio of the low side synchronous rectifier MOSFET is Disrimax 1 Duse max
19. also to the output ripple and the regulation tolerance T he capaci tance must be large enough that the voltage across the capacitor which is the sum of the resistive and capacitive voltage deviations does not deviate beyond the initial resistive deviation while the inductor current ramps up or down to the value corresponding to the new load current T he maximum allowed ESR also repre sents the maximum allowed output resistance Rout T he cumulative errors in the output voltage regulation cuts into the available regulation window Vwin When considering dynamic load regulation this relates directly to the ESR When consider ing dc load regulation this relates directly to the programmed output resistance of the power converter Some error sources such as initial voltage accuracy and ripple voltage can be directly deducted from the available regulation window while other error sources scale proportionally to the amount of voltage positioning used which for an optimal design should utilize the maximum that the regulation window will allow T he error determination is a closed loop calculation but it can be closely approximated T o maintain a conservative design while avoiding an impractical design various error sources should be considered and summed statistically T he output ripple voltage can be factored into the calculation by summing the output ripple current with the maximum output current to determine an effective maximum d
20. cessor core when the load changes between the a di ve WIP cogs minimum and maximum values with a di dt of 20 A us VID3 VID2 VID1 VIDO Vout nom AV o tRANSIENT 80 mV 130 mV 210 mV 1 1 1 1 1 30V Input current di dt when the load changes between the mini 1 1 1 0 1 35 V mum and maximum values lt 0 1 A us 1 1 0 1 1 40 V T he above requirements correspond to Intel s published power 1 1 0 0 1 45 V supply requirements based on VRM 8 4 guidelines 1 0 1 1 1 50 V 1 0 1 0 1 55 V 1 0 0 1 1 60 V 1 0 0 0 1 65 V 0 1 1 1 1 70 V 0 1 1 0 1 75 V 0 1 0 1 1 80 V 0 1 0 0 1 85 V 0 0 1 1 1 90 V 0 0 1 0 1 95 V 0 0 0 1 2 00 V 0 0 0 0 2 05 V 6 REV A ADP3158 ADP3178 CT Selection for Operating Freguency TheADP3158 and AD P3178 use a constant off time architecture with topp determined by an external timing capacitor CT Each time the high side N channel MOSFET switch turns on the volt age across CT is reset to 0 V During the off time CT is charged by a constant current of 150 JA Once CT reaches 3 0 V anew on time cycle is initiated T he value of the off time is calculated using the continuous mode operating frequency Assuming a nominal operating frequency fy om of 200 kH z at an output volt age of 1 7 V the corresponding off time is sour 1 t 1 x a Vin fyom 1 7V 1 1 torr 1 5V 200kHz gt gt HS The timing capacitor can be calculated from the equation c torr Xlcr _ 3 3 usx150 uA Vr
21. e core T he radiated EM I from the distributed magnetic field may create problems with noise interference in the circuitry surrounding the inductor Closed loop types such as pot cores PQ U and E cores or toroids cost more but have much better EMI RFI performance A good compromise between price and performance are cores with a toroidal shape _7 ADP3158 ADP3178 T here are many useful references for guickly designing a power inductor T able II gives some examples Table ll Magnetics Design References M agnetic Designer Software Intusoft http www intusoft com Designing M agnetic Components for High Frequency DC DC Converters M cL yman K g M agnetics ISBN 1 883107 00 08 Selecting a Standard Inductor The companies listed in T able III can provide design consul tation and deliver power inductors optimized for high power applications upon reguest Table III Power Inductor Manufacturers Coilcraft 847 639 6400 http www coilcraft com Coiltronics 561 752 5000 http www coiltronics com Sumida Electric Company 408 982 9660 http www sumida com Cour Selection Determining the ESR T he required equivalent series resistance ESR and capacitance drive the selection of the type and guantity of the output capaci tors The ESR must be small enough to contain the voltage deviation caused by a maximum allowable CPU transient cur rent within the specified voltage limits giving consideration
22. ee Figure 4 T his would be especially noticeable under very light or very heavy loads where the voltage is positioned near one of the extremes of the regulation window rather than near the nominal center value It must be noted and understood that this low gain characteristic i e loose dc load regulation is inherently required to allow improved transient containment i e to achieve tighter ac load regulation T hat is the dc load regulation is intentionally sacrificed but kept within specification in order to minimize the number of capacitors required to contain the load transients produced by the CPU ADP3158 ADP3178 LRDRV1 Figure 6 Adding Overcurrent Protection to the Linear Regulator Linear Regulators T he two linear regulators provide a low cost convenient and versatile solution for generating additional supply rails The maximum output load current is determined by the size and thermal impedance of the external N channel power MOSFET that is placed in series with the supply T he output voltage is sensed at the LRFB pin and compared to an internal reference voltage in a negative feedback loop which keeps the output voltage in regulation If the load is reduced or increased the MOSFET drive will also be reduced or increased by the controller IC to provide a well regulated 2 5 accurate output voltage TheLRFB threshold of the ADP 3158 are internally set at 2 5 V LRFB1 and 1 8 V LRFB2 while the LRFB p
23. egulation technigue called Analog D evices Optimal Positioning Technology ADOPT to enhance load transient performance Active voltage positioning results in a dc dc converter that meets the stringent output voltage specifications for high performance processors with the minimum number of output capacitors and smallest footprint U nlike voltage mode and ADOPT is a trademark of Analog D evices Inc Pentium is a registered trademark of Intel Corporation Celeron is a trademark of Intel Corporation REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM vcc CT 3 ADP3158 ADP3178 0604 VID3 VID2 VID1 VIDO standard current mode architectures active voltage positioning adjusts the output voltage as a function of the load current so it is always optimally positioned for a system transient T hey also provide accurate and reliable short circuit protection and adjustable current limiting T he devices include an integrated overvoltage crowbar function to protect the microprocessor from destruction in case the core supply exceeds the nominal programmed voltage by more than 20 The ADP3158 and ADP3
24. ency peak to peak ripple current in an inductor and input and output voltages L _ Vout x torr 4 l L RIPPLE For 4 A peak to peak ripple current which corresponds to approximately 25 of the 15 A full load dc current in an inductor Equation 4 yields an inductance of _1 7V x3 3us 7 4A L 1 4uH A 1 5 pH inductor can be used which gives a calculated ripple current of 3 8 A at no load T he inductor should not saturate at the peak current of 17 A and should be able to handle the sum of the power dissipation caused by the average current of 15 A in the winding and the core loss Designing an Inductor Once the inductance is known the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals T he first decision in designing the inductor is to choose the core material T here are several possibilities for providing low core loss at high frequen cies Two examples are the powder cores e g K ool M u from M agnetics Inc and the gapped soft ferrite cores e g 3F 3 or 3F 4 from Philips Low frequency powdered iron cores should be avoided due to their high core loss especially when the inductor value is relatively low and the ripple current is high T wo main core types can be used in this application O pen magnetic loop types such as beads beads on leads and rods and slugs provide lower cost but do not have a focused mag netic field in th
25. ge without detection Although the AD P3158 AD P3178 feature proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges T herefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING ESD SENSITIVE DEVICE REV A 3 ADP3158 ADP3178 Typical Performance Characteristics TEK RUN a TRIG D 60 50 40 30 20 SUPPLY CURRENT mA 0 100 200 300 400 500 600 700 800 OSCILLATOR FREQUENCY kHz TPC 1 Supply Current vs Operating Frequency Using MOSFETs of Figure 3 TEK RUN E x ITI J TRIG D CH1 5 00V By KIM 5 00V Byy M 1 00us A CHI 5 90V gt gt v 2 6500ps TPC 2 Gate Switching Waveforms Using MOSFETs of Figure 3 TEK RUN y TRIG D CH1 2 00V By SRL 200V By M 1 00ns A CH1 5 88V gt gt v 150 000us TPC 3 Driver Transition Waveforms Using MOSFETs of Figure 3 NUMBER OF PARTS CH1 5 00V By ROIA 500mV By M 10 0ms A CH1 5 90V E gt y 0 00000 s TPC 4 Power On Start Up Waveform 25 Ta 25 C Vout 1 65V 20 15 10 0 5 0 0 OUTPUT ACCURACY of Nominal TPC 5 Output Accuracy Distribution 5
26. ins of the AD P3178 are compared to an internal 1 V reference T his allows the use of an external resistor divider network to program the linear regulator output voltage T he correct resistor values for setting the output voltage of the linear regulators in the AD P3178 can be determined using Ry R Vout tr Virre Sa L 32 Assuming that R 10 KQ Vour r 1 2 V and rearranging E guation 32 to solve for Ry yields _ 10 KOX Vour ice Virre i Vines 33 10kQx 1 2V 1V AxN N 2 12 Efficiency of the Linear Regulators Theefficiency and corresponding power dissipation of each of the linear regulators are not determined by the controller IC Rather these are a function of input and output voltage and load current Efficiency is approximated by the formula y 100 x our 34 IN T he corresponding power dissipation in the MOSFET together with any resistance added in series from input to output is given by Pino Win Vout Xlour 35 M inimum power dissipation and maximum efficiency are accom plished by choosing the lowest available input voltage that exceeds the desired output voltage H owever if the chosen input source is itself generated by a linear regulator its power dissipation will be increased in proportion to the additional current it must now provide Implementing Current Limit for the Linear Regulators T he circuit of Figure 4 gives an example of a current limit pro tection circuit that ca
27. n X peak X Qe X fmin DHSF lrMSHSF XKRps ow 2xlc 5V x15A x70nC x195kHZ _ Jew 19 2x1A where the second term represents the turn off loss of the MOSFET In the second term Oc is the gate charge to be removed from the gate for turn off and Ig is the gate current From the data sheet Oc is 70 nC and the gate drive current provided by the ADP3159 is about 1 A The low side M OSFET dissipation is Pons 8 8 A x16mQ 4 2 Poise amsisr XRos on Porsp 10 8 A x 10 mQ 1 08 W N ote that there are no switching losses in the low side MOSFET Surface mount M OSFET s are preferred in CPU core converter applications due to their ability to be handled by automatic assembly equipment The T 0 263 package offers the power handling of a TO 220 in a surface mount package H owever this package still needs adequate copper area on the PCB to help move the heat away from the package T he junction temperature for a given area of 2 ounce copper can be approximated using Ty 0m xPo Ta 21 assuming 0 4 45 C W for 0 5 in 0 4 36 C M for 1 in 0 4 28 C W for 2 in For 1 in of copper area attached to each transistor and an ambient temperature of 50 C T msr 36 C W x 1 48 W 50 C 103 C T sr 36 C W x 1 08 W 50 C 89 C All of the above calculated junction temperatures are safely below the 175 C maximum specified junction temperature of the selected MOSFETs Cin Selection and Input Curren
28. n be used in conjunction with the linear regulators T he output voltage is internally set by the LRFB pin T he value of the current sense resistor may be calculated as follows _5340mV 540 mV R 2 2A 250 MQ 36 lo max T he power rating of the current sense resistor must be at least Poias Rs xlocmaxy 1 2W 37 T he maximum linear regulator MOSFET junction temperature with a shorted output is Tmax Ta Ox XV in Xloimax T max 50C 1 4 C MW x 3 3V x2 2 A 60 C 38 which is within the maximum allowed by the M OSFET s data sheet specification The maximum M OSFET junction tempera ture at nominal output is Trnom Ta 0x X Vin Vout Xlocnom Tywom 50 C 1 4 C W x 3 3V 2 5 V x2 A 52 C 39 T his example assumes an infinite heatsink T he practical limita tion will be based on the actual heatsink used REV A ADP3158 ADP3178 LAYOUT AND COMPONENT PLACEMENT GUIDELINES T he following guidelines are recommended for optimal perfor mance of a switching regulator in a PC system General Recommendations 1 F or best results a four layer PCB is recommended T his should allow the needed versatility for control circuitry interconnections with optimal placement a signal ground plane power planes for both power ground and the input power e g 5 V and wide interconnection traces in the rest of the power delivery current paths Whenever high currents must be routed between
29. ns for the linear regulator controllers Gate drives for the respective linear regulator N channel M OSFET s Current Sense N egative N ode N egative input for the current comparator T his pin also connects to the internal error ampli fier that senses the output voltage Current Sense Positive N ode Positive input for the current comparator T he output current is sensed as a voltage at this pin with respect to CS External capacitor connected from CT to ground sets the Off time of the device Error Amplifier Output and C ompensation Point T he voltage at this output programs the output current control level between CS and CS Supply Voltage for the device Low Side MOSFET Drive Gate drive for the synchronous rectifier N channel MOSFET T he voltage at DRVL swings from GND to VCC H igh Side MOSFET Drive Gate drive for the buck switch N channel MOSFET T he voltage at DRVH swings from GND to VCC Ground Reference GND should have a low impedance path to the source of the synchronous MOSFET ORDERING GUIDE Temperature LDO Package Package Model Range Voltage Description Option ADP3158JR 0 C to 70 C 2 5V 1 8V SO Small Outline Package R 16A SO 16 ADP3178JR 0 C to 70 C Adjustable SO Small Outline Package R 16A SO 16 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can dischar
30. t di dt Reduction In continuous inductor current mode the source current of the high side MOSFET is approximately a square wave with a duty ratio equal to Voyr V n and an amplitude of one half of the maximum output current To prevent large voltage transients a 20 10 low ESR input capacitor sized for the maximum rms current must be used T he maximum rms capacitor current is given by 2 lc ams lo Dusr Duse 15A 40 36 0 36 7 2A For a ZA type capacitor with 1000 uF capacitance and 6 3 V voltage rating the ESR is 24 mQ and the maximum allowable ripple current at 100 kHz is 2 A At 105 C at least four such capacitors must be connected in parallel to handle the calculated ripple current At 50 C ambient however a higher ripple cur rent can be tolerated so three capacitors in parallel are adequate T he ripple voltage across the three paralleled capacitors is ESRecn D sr nc Nc XCin X fmax 22 V cin ippLE lo 24 ma 36 23 3 3x1000 uF x195kHz To further reduce the effect of the ripple voltage on the system supply voltage bus and to reduce the input current di dt to below the recommended maximum of 0 1 A ms an additional small inductor L gt 1 uH 10 A should be inserted between the converter and the supply bus Feedback C ompensation for Active Voltage Positioning Optimized compensation of the AD P3158 and AD P3178 allows the best possible containment of the peak to peak o
31. tor divider supply voltage e g the recommended 12 V supply and Vout os S the output voltage offset from the nominal VID programmed value under no load condition T his offset is given by Equation 30 T he closest 1 value for Ra is 78 7 kQ This value is then used to solve for Rg Ra XRcowp _ 78 7kK0x9 2kQ R E 78 7 k 9 2 KQ 10 4kQ 27 Ra Rcomp 127 T he nearest 1 value of 10 5 kQ was chosen for R x a leimieece Rsense xM Vent __ Vec 2 Om XRrotaL Ym XRroraL 2 Ym Rocm 28 K 3 8A 4 m x25 E 1 174 W 12V 177 22 mmho x 9 1kaQ 2 2mmho x9 1kQ 2x2 2mmhox130ka 4 7 lt 10 R n Vent Vonto EPE 5 SENSE ZA o xtp x Rsense xn 29 Jaa See OF A ree wa KOKDOS 2117 1 5 pH Remax XI L RipPLE Vout os Vour max Vvio MAY 2 L Vio X Kiv 5mQx3 8A Vout os 40 mV 1 7V x5x103 22mV 30 Finally the compensating capacitance is determined from the equality of the pole frequency of the error amplifier gain and the zero frequency of the impedance of the output capacitor Cour XESR _ 5S mF x4 8mQ Coc 9 1kQ 2 6 nF 31 Rrotat T he closest standard value for C oc is 2 7 nF 11 ADP3158 ADP3178 Trade Offs Between DC Load Regulation and AC Load Regulation Casual observation of the circuit operation e g with a voltmeter would make it appear that the dc load regulation appears to be rather poor compared to a conventional regulator s
32. utput voltage deviation Any practical switching power converter is inherently limited by the inductor in its output current slew rate to a value much less than the slew rate of the load T herefore any sudden change of load current will initially flow through the output capaci tors and this will produce an output voltage deviation equal to the ESR of the output capacitor array times the load current change V C IN jRIPPLE 154 gt x 129 0 TEK RUN 200kS s SAMPLE EUCH T M 250ps 100mVW CH2 Figure 4 Transient Response of the Circuit of Figure 3 CH2 680mV REV A ADP3158 ADP3178 100 90 80 70 60 50 40 EFFICIENCY 0 2 4 6 8 10 1 14 16 18 20 OUTPUT CURRENT A Figure 5 Efficiency vs Load Current of the Circuit of Figure 3 To correctly implement active voltage positioning the low fre quency output impedance i e the output resistance of the converter should be made equal to the maximum ESR of the output capacitor array T his can be achieved by having a single pole roll off of the voltage gain of the gm error amplifier where the pole freguency coincides with the ESR zero of the output capacitor A gain with single pole roll off requires that the gm amplifier output pin be terminated by the parallel combination of a resistor and capacitor T he required resistor value can be
33. via correlation using standard Statistical Quality Control SQC Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs Specifications subject to change without notice REV A ADP3158 ADP3178 PIN FUNCTION DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS VEC r N Masa aeon EMOA J asa Ean 0 3 V to 15 V DRVH DRVL LRDRV1 LRDRV2 0 3 V to VCC 0 3V All Other Inputs and Outputs 0 3 V to 10 V Operating Ambient Temperature Range 0 C to 70 C Operating Junction Temperature 125 C Storage T emperature Range Oja T wo Layer Board soolon a 125 C W Four Layer Board 0 cece eee nn 81 C MW Lead Temperature Soldering 10 sec 300 C Vapor Phase 60 sec 0 cece ee eee 215 C Infrared 15 sec sossun eee 220 C T his is a stress rating only operation beyond these limits can cause the device to be permanently damaged U nless otherwise specified all voltages are referenced to GND PIN CONFIGURATION TOP VIEW 5 Not to Scale 12 LRFB2 Pin Mnemonic Function 1 4 15 16 VIDO VID3 LRFB1 LRFB2 LRDRVI LRDRV2 CS CS CT COMP VCC DRVL DRVH GND Voltage Identification DAC Inputs T hese pins are pulled up to an internal reference providing a Logic 1 if left open The DAC output programs the C S regulation voltage from 1 3 V to 2 05 V F eedback connectio
34. ynamic current change T he remaining errors are summed separately according to theformula Vwin Wa Vyio x2 kvip x 5 lo a lo loa 2 c RCS Kes 2 where Ky p 0 5 is the initial programmed voltage tolerance from the graph of TPC 6 krcs 2 is the tolerance of the current sense resistor kcsr 10 is the summed tolerance of the current sense filter components kar 2 is the tolerance of the two termination resistors added at the COMP pin and keg 8 accounts for the IC current loop gain tolerance including the gm tolerance The remaining window is then divided by the maximum output current plus the ripple to determine the maximum allowed ESR and output resistance F 2 as Ren 95 mV Vw 95mV lo 104 15A 3 8A T he output filter capacitor bank must have an ESR of less than 5 mQ One can for example use five ZA series capacitors from Rubycon which would give an ESR of 4 8 mQ Without ADOPT voltage positioning the ESR would need to be less than 3 ma yielding a 50 increase to eight Rubycon output capacitors 5mQ Re MAX Rour max 6 Cour Checking the Capacitance As long as the capacitance of the output capacitor is above a critical value and the regulating loop is compensated with ADOPT the actual value has no influence on the peak to peak deviation of the output voltage to a full step change in the load current The critical capacitance can be calculated as follows
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ANALOG DEVICES ADP3158/ADP3178 4 Bit Programmable Synchronous Buck Controllers handbook