ANALOG DEVICES ADP3110 Dual Bootstrapped 12 V MOSFET Driver with Output Disable handbook
Contents
1. ANALOG DEVICES Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3110 FEATURES All in one synchronous buck driver Bootstrapped high side drive One PWM signal generates both drives Anticross conduction protection circuitry Output disable control turns off both MOSFETs to float output per Intel VRM 10 specification APPLICATIONS Multiphase desktop CPU supplies Single supply synchronous buck converters GENERAL DESCRIPTION The ADP3110 is a dual high voltage MOSFET driver optimized for driving two N channel MOSFETs which are the two switches in a nonisolated synchronous buck power converter Each of the drivers is capable of driving a 3000 pF load with a 25 ns propagation delay and a 30 ns transition time One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high side gate drivers The ADP3110 includes overlapping drive protection to prevent shoot through current in the external MOSFETs The OD pin shuts off both the high side and the low side MOSFETs to prevent rapid output capacitor discharge during system shutdown The ADP3110 is specified over the commercial temperature range of 0 C to 85 C and is available in an 8 lead SOIC_N package SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM ADP3110 DELAY gt o Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no respon2. ADP3110 is disabled the low side gate is held low HIGH SIDE DRIVER The high side driver is designed to drive a floating N channel MOSFET The bias voltage for the high side driver is developed by an external bootstrap supply circuit which is connected between the BST and SW pins The bootstrap circuit comprises a diode D1 and bootstrap capacitor and Rasr are included to reduce high side gate drive voltage and limit the switch node slew rate referred to as a Boot Snap circuit see the Application Information section for more details When the ADP3110 is starting up the SW pin is at ground therefore the bootstrap capacitor charges up to VCC through D1 When the PWM input goes high the high side driver begins to turn on the high side MOSFET Q1 by pulling charge out of and As Q1 turns on the SW pin rises up to Vn forcing the BST pin to Vix Vcosr which is enough gate to source voltage to hold Q1 on To complete the cycle Q1 is switched off by pulling the gate down to the voltage at the SW pin When the low side MOSFET Q2 turns on the SW pin is pulled to ground This allows the bootstrap capacitor to charge up to VCC again The high side driver s output is in phase with the PWM input When the driver is disabled the high side gate is held low OVERLAP PROTECTION CIRCUIT The overlap protection circuit prevents both of the main power switches Q1 and Q2 from being on at th
3. 12 ADP3110 SPECIFICATIONS Voc 12 V BST 4 V to 26 V Ta 25 C unless otherwise noted Table 1 Parameter Symbol Min Typ Uni PWM INPUT Input Voltage High 2 0 Input Voltage Low 0 8 Input Current 1 1 yA Hysteresis 90 250 mV OD INPUT Input Voltage High Input Voltage Low Input Current Hysteresis Propagation Delay Times See Figure 3 See Figure 3 HIGH SIDE DRIVER Output Resistance Sourcing Current BST SW 12V Output Resistance Sinking Current sw BST to SW 12V Output Resistance Unbiased BST to SW 0V Transition Times BST to SW 12 V nF see Figure 4 BST to SW 12 V 3 nF see Figure 4 Propagation Delay Times BST to SW 12 V 3 nF see Figure 4 tpdlpava BST to SW 12 V 3 nF see Figure 4 SW Pull Down Resistance Rsw SW to PGND LOW SIDE DRIVER Output Resistance Sourcing Current Output Resistance Sinking Current PGND Output Resistance Unbiased VCC PGND Transition Times Cioap nF see Figure 4 Cioap nF see Figure 4 Propagation Delay Times tpdhorvi Cioap 3 nF see Figure 4 15 Cioap 3 nF see Figure 4 Time out Delay SW 5V 110 190 SW PGND 95 150 SUPPLY Supply Voltage Range Vcc 4 15 132 V Supply Current Isys BST 12V IN 0V 2 5 mA UVLO Voltage VCC rising 1 5 3 0 Hysteresis 350 1 All lim
4. 1622 1 Mdg quote M gt ALT 44029 1 fox 3264 esL 50005 Juzi 02 ZHdy Yo Sy 022 9H Mths met I ee HO amy aur ados 12 pier Eur d o o Out L Hu0Z ndo v1 ZONO9Q1N o 60 H T slo A 181844 oui 2 Jii root Tro ZONOLIGLN zonotrain 20 001 Hu0ZE 1 t 133005 mev NI 291 81 310 Ls 1 AW ZONOLLALN 9 vo t 3809 22 OGL 96 ASL ASLE8 0 531995 2995 OANYS VWP L HUOZE 3409 994 8 Av atiogs ZONO9G LN 10 9 OLLEdQV 2 33 zn T onun 19 7 23 m SIHIS XMAN OANYS Jui z veteUamopz 89 i Figure 6 VRD 10 x Compliant Power Supply Circuit Rev 0 Page 10 of 12 ADP3110 OUTLINE DIMENSIONS 4 8 5 4 00 0 1574 6 20 0 2440 3 80 0 1497 11 4 5 80 0 2284 1 27 0 0500 BSC 1 75 0 0688 lt 0 25 0 0099 0 25 0 0098 1 35 0 0532 0 10 0 0040 0 51 0 0201 8 COPLANARITY Skata 0 31 0 0122 0 25 0 0098 0 1 27 0 0500 NE 0 17 0 006
5. 7 0 40 0 0157 0 50 0 0196 x 45 COMPLIANT TO JEDEC STANDARDS MS 012 AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 7 8 Lead Standard Small Outline Package SOIC Narrow Body R 8 Dimensions shown in millimeters and inches ORDERING GUIDE Model Temperature Range Package Description Package Option Quantity per Reel ADP3110KRZ 0 C to 85 C Standard Small Outline Package SOIC_N R 8 N A ADP3110KRZ RL 0 to 85 Standard Small Outline Package 5 1 R 8 2500 17 Pb free part Rev 0 Page 11 of 12 ADP3110 NOTES 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www ana 0 0 com as rao DEVICES Rev 0 Page 12 of 12 WWW ZFA CN 7 150 C WWW 2 CA WALA PAK R 41662 gl XA 26 XYI 0755 83278916 83278919 010 62632888 62636888
6. OSFETs if more than one is used assume a worst case mismatch of 30 for design margin Lour is the output inductor value When producing the design there is no exact method for calculating the dV dt due to the parasitic effects in the external MOSFETs as well as the PCB However it can be measured to determine if it is safe If it appears the dV dt is too fast an optional gate resistor can be added between DRVH and the high side MOSFET This resistor slows down the dV dt but it also increases the switching losses in the high side MOSFET The ADP3110 is optimally designed with an internal drive impedance that works with most MOSFETS to switch them efficiently yet minimize dV dt However some high speed MOSFETs may require this external gate resistor depending on the currents being switched in the MOSFET Low Side Synchronous MOSFETs The low side MOSFETS are usually selected to have a low on resistance to minimize conduction losses This usually implies a large input gate capacitance and gate charge The first concern is to make sure the power delivery from the ADP3110 s does not exceed the thermal rating of the driver The next concern for the low side MOSFETS is to prevent them from inadvertently being switched on when the high side MOSFET turns on This occurs due to the drain gate Miller also specified as capacitance of the MOSFET When drain of the low side MOSFET is switched to VCC by the high side turni
7. controller data sheet for more details on MOSFET losses This usually implies a low gate resistance and low input capacitance charge device Yet there is also a significant source lead inductance that can exist this depends mainly on the MOSFET package it is best to contact the MOSFET vendor for this information The ADP3110 DRVH output impedance and the external MOSFETs input resistance determine the rate of charge delivery to the MOSFETs gate capacitance which in turn determines the switching times of the MOSFETs A large voltage spike can be generated across the source lead inductance when the high side MOSFETs switch off due to large currents flowing in the MOSFETs during switching usually larger at turn off due to ramping of the current in the output inductor This voltage spike occurs across the internal die of the MOSFETs and can lead to catastrophic avalanche The mechanisms involved in this avalanche condition can be referenced in literature from the MOSFET suppliers Rev 0 Page 8 of 12 ADP3110 The MOSFET vendor should provide a maximum voltage slew rate at drain current rating such that this can be designed around The next step is to determine the expected maximum current in the MOSFET This can be done by D MAX 7 F max 2 Lour Ipc per phase Dwax is determined for the VR controller being used with the driver Note this current gets divided roughly equally between M
8. e same time This prevents shoot through currents from flowing through both power switches and the associated losses that can occur during their on off transitions The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn off to the Q2 turn on and by internally setting the delay from the Q2 turn offto the Q1 turn on To prevent the overlap of the gate drives during the Q1 turn off and the Q2 turn on the overlap circuit monitors the voltage at the SW pin When the PWM input signal goes low Q1 begins to turn off after propagation delay Before Q2 can turn on the overlap protection circuit makes sure that SW has first gone high and then waits for the voltage at the SW pin to fall from Vin to 1 V Once the voltage on the SW pin has fallen to 1 V Q2 begins turn on If the SW pin had not gone high first then the Q2 turn on is delayed by a fixed 150 ns By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time the overlap protection circuit ensures that Q1 is off before Q2 turns on regardless of variations in temperature supply voltage input pulse width gate charge and drive current If SW does not go below 1 V after 190 ns DRVL turns on This can occur if the current flowing in the output inductor is negative and is flowing through the high side MOSFET body diode Rev 0 Page 7 of 12 ADP3110 APPLICATION INFORMATION SUPPLY CAPACITOR SELECTION For the supply inp
9. e source of the lower MOSFET 4 The Vcc bypass capacitor should be located as closely as possible to the VCC and PGND pins 5 Use vias to other layers when possible to maximize thermal conduction away from the IC The circuit in Figure 6 shows how four drivers can be combined with the ADP3181 to form a total power conversion solution for generating for an Intel CPU that is VRD 10 x compliant Figure 5 shows an example of the typical land patterns based on the guidelines given previously For more detailed layout guidelines for a complete CPU voltage regulator subsystem refer to the Layout and Component Placement section in the ADP3181 data sheet 05514 005 Figure 5 External Component Placement Example Rev 0 Page 9 of 12 ADP3110 NOILO3S NOILVH3dO 40 181640 33S SIN3NOdWOO TWNOILdO 40 NOLLdIH2S3Q V ZONOLLGIN ZONOLLGLN 519 E duy I 09091 4 49 966 53001 Out it 1 ZONO9G LN n A 4 0302 Auge I iui OM jut 3ug9 OLLEdGV Y sa I H 919 sn oss 44098 4 En pn 1824 2590 25
10. ed to the buck switching node close to the upper MOSFET s source It is the floating return for the upper MOSFET drive signal It is also used to monitor the switched voltage to prevent turn on of the lower MOSFET until the voltage is below 1 V 8 DRVH Buck Drive Output drive for the upper buck MOSFET Rev 0 Page 5 of 12 ADP3110 TIMING CHARACTERISTICS ipdlon tpdhop Figure 3 Output Disable Timing Diagram 05514 003 m tpdipRvH trprvL DRVL tpdhprvH gt gt DRVH SW Vm Ym tpdhprvL i Sw 1V Figure 4 Timing Diagram Timing is Referenced to the 90 and 10 Points Unless Otherwise Noted Rev 0 Page 6 of 12 ADP3110 THEORY OF OPERATION The ADP3110 is a dual MOSFET driver optimized for driving two N channel MOSFETs in a synchronous buck converter topology A single PWM input signal is all that is required to properly drive the high side and the low side MOSFETs Each driver is capable of driving a 3 nF load at speeds up to 500 kHz A more detailed description of the ADP3110 and its features follows Refer to Figure 1 LOW SIDE DRIVER The low side driver is designed to drive a ground referenced N channel MOSFET The bias to the low side driver is internally connected to the VCC supply and PGND When the ADP3110 is enabled the driver s output is 180 degrees out of phase with the PWM input When the
11. harge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features AVANT S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy AG electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev 0 Page 4 of 12 ADP3110 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 05514 002 Figure 2 8 Lead SOIC_N Pin Configuration Table 3 Pin Function Descriptions Pin No Mnemonic Description 1 BST Upper MOSFET Floating Bootstrap Supply A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high side MOSFET as it is switched 2 IN Logic Level PWM Input This pin has primary control of the driver outputs In normal operation pulling this pin low turns on the low side driver pulling it high turns on the high side driver 3 OD Output Disable When low this pin disables normal operation forcing DRVH and DRVL low 4 Input Supply This pin should be bypassed to PGND with 1 uF ceramic capacitor 5 DRVL Synchronous Rectifier Drive Output drive for the lower synchronous rectifier MOSFET 6 PGND Power Ground This pin should be closely connected to the source of the lower MOSFET 7 SW Switch Node Connection This pin is connect
12. its at temperature extremes are guaranteed via correlation using standard statistical quality control SQC methods Specifications apply over the full operating temperature range Ta 0 C to 85 C 3 For propagation delays tpdh refers to the specified signal going high and tpdl refers to it going low Rev 0 Page 3 of 12 ADP3110 ABSOLUTE MAXIMUM RATINGS Table 2 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress VCC 0 3 V to 15 V rating only functional operation of the device at these or any BST 0 3 V to VCC 15V other conditions above those indicated in the operational BST to SW 0 3 V to 15 V section of this specification is not implied Exposure to absolute SW maximum rating conditions for extended periods may affect DC 5 Vto 15 V device reliability Unless otherwise specified all other voltages lt 200 ns 10 V to 25 V are referenced to PGND DRVH DC SW 0 3 V to BST 0 3 V lt 200 ns SW 2 V to BST 0 3 V DRVL DC 0 3 V to VCC 0 3 V lt 200 ns 2 V to VCC 0 3 V IN OD 0 3 V to 6 5 V SOIC_N 2 Layer Board 123 C W 4 Layer Board 90 C W Operating Ambient Temperature Range 0 C to 85 C Junction Temperature Range 0 C to 150 C Storage Temperature Range 65 C to 150 C Lead Temperature Range Soldering 10 sec 300 C Vapor Phase 60 sec 215 C Infrared 15 sec 260 C ESD CAUTION ESD electrostatic disc
13. ng on at a rate dV dt the internal gate of the low side MOSFET is pulled up by an amount roughly equal to VCC x Crss Ciss It is important to make sure this does not put the MOSFET into conduction Another consideration is the nonoverlap circuitry of the ADP3110 which attempts to minimize the nonoverlap period During the state of the high side turning off to low side turning on the SW pin and the conditions of SW prior to switching are monitored to adequately prevent overlap However during the low side turn off to high side turn on the SW pin does not contain information for determining the proper switching time so the state of the DRVL pin is monitored to go below one sixth of Vcc and then a delay is added Due to the Miller capacitance and internal delays of the low side MOSFET gate one must ensure the Miller to input capacitance ratio is low enough and the low side MOSFET internal delays are not large enough to allow accidental turn on of the low side MOSFET when the high side MOSFET turns on Contact Sales for an updated list of recommended low side MOSFETs PC BOARD LAYOUT CONSIDERATIONS Use the following general guidelines when designing printed circuit boards 1 Trace out the high current paths and use short wide gt 20 mil traces to make these connections 2 Minimize trace inductance between the DRVH and DRVL outputs and the MOSFET gates 3 Connect the PGND pin of the ADP3110 as closely as possible to th
14. r is used for slew rate limiting to minimize the ringing at the switch node It also provides peak current limiting through D1 An Rasr value of 1 5 to 2 2 is a good choice The resistor needs to be able to handle at least 250 mW due to the peak currents that flow through it A small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by Vcc The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage The average forward current can be estimated by Qoare X f max 5 where fuax is the maximum switching frequency of the controller The peak surge current rating should be calculated by F PEAK R I 6 BST MOSFET SELECTION When interfacing the ADP3110 to external MOSFETs the designer should be aware of a few considerations These help to make a more robust design that minimizes stresses on both the driver and MOSFETs These stresses include exceeding the short time duration voltage ratings on the driver pins as well as the external MOSFET It is also highly recommended to use the Boot Snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs If a simple bootstrap arrangement is used make sure to include a proper snubber network on the SW node High Side Control MOSFETs The high side MOSFET is usually selected to be high speed to minimize switching losses see any ADI Flex Mode
15. sibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Figure 1 12V INDUCTOR 9 5 CONTROL LOGIC D DELAY 05514 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved ADP3110 TABLE OF CONTENTS Specifications 3 Overlap Protection Circuit siseses 7 Absolute Maximum 4 Application 8 ESD Caution tette eee mee tete 4 Supply Capacitor Selection 8 Pin Configuration and Function 5 5 Bootstrap CIrcuit eee RERCRREHERKURSEBBCE RE 8 Timing Characteristics teer th e ete Re RS 6 MOSFET Selection eoo seat to emite 8 Theory of Operation 7 Board Layout 9 eim 7 Outline Dimensions ette ide 11 Highi Side DrIVeE sissies 7 Ordering Guide 11 REVISION HISTORY 6 05 Revision 0 Initial Version Rev 0 Page 2 of
16. ut VCC of the ADP3110 a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn Use a 4 7 uF low ESR capacitor Multilayer ceramic chip MLCC capacitors provide the best combination of low ESR and small size Keep the ceramic capacitor as close as possible to the ADP3110 BOOTSTRAP CIRCUIT The bootstrap circuit uses a charge storage capacitor Css and a diode as shown in Figure 1 These components can be selected after the high side MOSFET is chosen The bootstrap capacitor must have a voltage rating that is able to handle twice the maximum supply voltage A minimum 50 V rating is recommended The capacitor values are determined using the following equations Qs C por 10 1 GATE bsri Voarg 2 VCC Vp where is the total gate charge of the high side MOSFET at is the desired gate drive voltage usually in the range of 5 V to 10 V 7 V being typical Vp is the voltage drop across D1 Rearranging Equation 1 and Equation 2 to solve for yields Qoare psr 10 x 3 BST1 VCC Vp can then be found by rearranging Equation 1 Q 10x 4 GATE For example an NTD60N02 has a total gate charge of about 12 nC at 7 V Using VCC 12 V and Vp 1 V we find 12 nF and Cas 6 8 nF Good quality ceramic capacitors should be used Ras
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ANALOG DEVICES ADP3110 Dual Bootstrapped 12 V MOSFET Driver with Output Disable handbook