ANALOG DEVICES ADP1148 ADP1148-3.3 ADP1148-5 High Efficiency Synchronous Step-Down Switching Regulators handbook
Contents
1. 1000 L 504H 800 Rsense 0 020 L 25pH 600 Rsense 0 020 1 o O 400 L 504H 200 Psense 0 050 0 0 1 2 3 4 5 Vin Vour VOLTAGE V Figure 5 Selecting Minimum Output Capacitor vs Vin Vour and Inductor lLoAp 1A CIRCUIT Figure 8 ADP1148 5 Output Voltage Change vs Input Voltage 30 VsHuTDOWN 2V SUPPLY CURRENT pA 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE V Figure 11 Supply Current in Shutdown ADP1148 ADP1148 3 3 ADP1148 5 Typical Performance Characteristics 30 80 N 5 0 2 c o A 3 3 50 w 5 2 E o a 40 N z 3 t 30 lt i 5 E Qn Qp 50nC 20 z o a q 0 20 50 80 110 140 170 200 230 260 0 4 6 OPERATING FREQUENCY kHz 0 3 0 5 1 0 1 5 2 0 2 5 3 0 3 3 3 5 4 0 4 5 5 0 Vin Vout V OUTPUT VOLTAGE V Figure 12 Operating Frequency vs Figure 13 Gate Charge Supply Figure 14 Off Time vs Vour Vin Vour Current MAXIMUM THRESHOLD SENSE VOLTAGE mV 0 25 70 85 100 TEMPERATURE C Figure 15 Current Sense Threshold Voltage 6 REV A ADP1148 ADP1148 3 3 ADP1148 5 APPLICATIONS The ADP1148 uses a current mode constant off time structure to switch a pair of exte2. and L can immedi ately be calculated Rsense 100 mV 2 50 torr 1 200 kHz x 1 5 12 2 92 us Cr 2 92 ps 1 3 x 10 220 pF L min 5 1x 10 50 3 Q 220 pF x 5 V 228 uH Assume that the M OSFET dissipations are to be limited to Py 2Pp 250 mW If T4 50 and the thermal resistance of each M OSFET is 50 C then the junction temperatures will be 63 and dp dp 0 007 x 63 25 0 27 T he required Rps oy for each MOSFET can now be calculated P ChRosion 12 x 0 25 5 x 2x 1 27 120 N ChRoscon 12 0 25 7 x 2x 1 27 85 T he P channel requirement can be met by a IRF 7204 T he N channel requirement can be met by a IRF 7404 Note that the most stringent requirement for the N channel M OSFET is with Vour 0 i e short circuit During a continuous short circuit the worst case N channel M OSFET dissipation rises to Py Isciavo X Rosco X 1 dy With the 50 sense resistor Isc avc 2 A will result increas ing the N channel dissipation to 0 45 W at die temperature of 73 C Cin will require an rms current rating of at least 1 A at tempera ture and Cour will require an ESR of 50 ma for optimum efficiency N ow allow V y to drop to its minimum value At lower input voltages the operating frequency will decrease and the P channel will be conducting most of the time causing the power dissipation to increase At 7 V the frequency shifts
3. When the voltage level on the timing capacitor has discharged to the threshold voltage level Vr 1 comparator T switches setting Flip Flop 1 T his forces the N drive to go off and the P drive output low and subsequently turns the P channel M OSFET on T he sequence is then repeated As load current increases the output voltage starts to reduce T his results in the output of the gain circuit increasing the level of the current comparator thresh old thus tracking the load current At very low load currents the power saving sequence will be interrupted by the Set of Flip Flop 2 by voltage comparator B which also monitors the voltage across Rsense When the load current decreases to half the designed inductor ripple current the voltage across Rsense Will reverse polarity When this hap pens comparator B will set the Q bar output of Flip Flop 2 which will go to logic zero state and interrupt the cycle by cycle operation and inhibit the output FET driver T he output of the power supply storage capacitor will slowly be drained by the load and the output voltage starts decreasing When this decreased voltage exceeds the Vos of comparator V this in turn will reset Flip Flop 2 and normal cycle by cycle operation will resume If the load is very small it will take a long time for Flip Flop 2 to reset and during that time the oscillator capacitor may discharge below V gt At the point at which the timing capacitor discharges below V y2 c
4. to fmin 1 Vout Vin tore 1 2 92 ps x 1 5 7 98 kHz and the P channel power dissipation increases to 120 2A 1 27 5V 7V 435 mW T his last step is needed to ensure the maximum temperature of the P channel M OSFET is not exceeded ADP1148 Adjustable Applications When an output voltage other than 3 3 V or 5 V is required the ADP1148 adjustable version is used with an external resistive divider from Vour to Veg Pin 9 T he regulated voltage is deter mined by Vout 1 25 1 R2 R1 T o prevent a stray pickup a 100 pF capacitor is suggested across R1 located closeto the ADP1148 Auxiliary Windings TheADP1148 synchronous switch removes the normal limita tion that power must be drawn from the inductor primary wind ing in order to extract power from auxiliary windings With synchronous switching auxiliary outputs may be loaded without regard to the primary output load providing that the loop re mains in continuous mode operation 10 Output Crowbar An added feature to using an N channel MOSFET as the syn chronous switch is the ability to crowbar the output with the same M OSFET Pulling the timing cap pin above 1 5 V when the output voltage is greater than the desired regulated value will turn on the N channel M OSFET and turn off the P channel M OSFET A fault condition such as an external short between Vi and Vout or an internal short of the P channel device which causes the
5. SPECIFICATIONS ELECTRI CAL C HARACTERI STICS 0 C lt Ta lt 70 C Vin 10 V Vshurown 0 V unless otherwise noted See Figure 17 Parameter Symbol Conditions Min Typ Max Units FEEDBACK VOLTAGE ADP1148 Only Vio Vin 29V 121 125 1 29 V FEEDBACK CURRENT ADP1148 Only 110 0 2 1 0 uA REGULATED OUTPUT VOLTAGE Vout Vin 29V ADP1148 3 3 1 700 mA 3 23 3 33 3 43 V ADP1148 5 1 700 mA 49 505 52 V OUTPUT VOLTAGE LINE 25 C Vin 27V to 12 V REGULATION dVour lLoap 50 mA 40 40 mV OUTPUT VOLTAGE LOAD REGULATION dV our ADP1148 3 3 5 mA lioap lt 2A 40 65 mV ADP1148 5 5 mA lioap lt 2A 60 100 mV SLEEP MODE OUTPUT RIPPLE dV out lioap OA 50 mV p p INPUT DC SUPPLY CURRENT lo 25 C Normal M ode Vn 4V lt Vn lt 18V 1 6 2 3 mA Sleep M ode ADP1148 3 3 Vn 4V lt Vn lt 18V 160 250 yA Sleep M ode ADP1148 5 Vin 24V Vu 18V 160 250 uA Shutdown V SHUTDOWN 2 1 V 10 20 4V Vi 15V CURRENT SENSE THRESHOLD Ve V7 Vo Vourt 4 25 mV Forced VOLTAGE V7 5 V Ta 25 25 mV ADP1148 Only Vo Vour 4 mV 25 mV Forced V 5V 130 150 170 mV ADP1148 3 3 V7 Vour 100 mV Forced 25 mV V 100 mV Forced 130 150 170 mV ADP1148 5 V7 Vour 100 mV Forced 25 mV V7 Vour 100 mV Forced 130 150 170 mV SHUTDOWN PIN THRESHOLD ADP1148 3 3 ADP1148 5 Vio Ta 25 C 06 08 2 0 V SHUTDOWN PIN INPUT CURRENT lio 0 V Vsuurpowu 8 V Vy 18V 1 2 5 yA Cr P
6. capacitor provides the ac current to the P channel MOSFET 5 Is the input decoupling capacitor 1 uF connected closely between Vin Pin 3 and POWER GND Pin 12 This capacitor carries the M OSFET driver peak currents 6 ISINT Vcc Pin 5 decoupled with a 10 nF capacitor to signal ground 7 Isthe SHUTDOWN Pin 10 actively pulled to ground during normal operation T he Shutdown pin is high imped ance and must not be allowed to float T o prevent noise spikes from erroneously tripping the current comparator a 1000 pF capacitor is needed across Sense and Sense D1 R1 R2 OUTPUT DIVIDER REQUIRED FOR ADJUSTABLE VERSION ONLY Figure 18 ADP1148 Layout Diagram See Board Layout REV A 11 ADP1148 ADP1148 3 3 ADP1148 5 Vin 4V TO 18V NC NC ADP1148 3 3 POWER GND Cr SIGNAL GND SOOpE 1 INT SHUTDOWN 7 8 3300pF SENSE SENSE Re 1000pF 10 Vour 3 3VAA NC NO CONNECT COILTRONICS CTX50 2 MP KRL SP 1 2 A1 0R100J Figure 19 ADP1148 Low Dropout 3 3 V 1 A High Efficiency Regulator Vin 4V TO 9V ADP1148 wc POWER GND S60pF T INT Voc SHUTDOWN tra sae x2 10V NC NO CONNECT COILTRONICS CTX50 2 MP KRL SL 1 C1 0R05J Figure 20 4 V to 9 V Input Voltage to 5 V 1 4 A Regulator 12 REV A ADP1148 ADP1148 3 3 ADP1148 5 Vin 5 2V TO 14V VN2222LL OV Vout 3 3V Psv Vout 5V SIGNAL GND 390pF T INT Voc SHUTDOWN C
7. he operating current level is user programmable via an external current sense resistor TheADP1148 incorporates automatic Power Saving Sleep M ode operation when load currents drop below the level re quired for continuous operation In sleep mode standby power is reduced to only about 2 mW at Vin 10 V In shutdown both M OSFET sare turned off TYPICAL APPLICATIONS Vin 5 2V TO 18V Cw 1004F T INT Vcc P CH i PONE IRF7204 0V NORMAL ADP1148 L gt 1 5V SHUTDOWN Rsense SHUTDOWN tH SENSE SENSE N DRIVE S GND P GND C1 10BQ040 COILTRONICS CTX 68 4 KRL SL 1 C1 0RO50L Figure 1 High Efficiency Step Down Converter REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for ts use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices 100 95 90 85 EFFICIENCY 80 75 FIGURE 70 0 02 0 2 2 LOAD CURRENT A Figure 2 ADP1148 5 Typical Efficiency One Technology Way P O 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 O Analog Devices Inc 1997 ADP1148 ADP1148 3 3 ADP1148 5
8. the lowest ESR for its size at a somewhat higher price Once the ESR requirement for Cour has been met the RM S current rating generally far ex ceeds the laippi c p p requirement In surface mount applications multiple capacitors may have to be paralleled to meet the capacitance ESR or RM S current handling requirements of the application Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations In the case of tantalum it is critical that the capacitors are surge tested for use in switching power supplies Consult the manufacturer for other specific recommendations T he Co output filter capacitor has to be sized correctly to avoid excessive ripple voltages at low frequencies See Figure 5 for output capacitor selection Transient Response T heregulator loop response can be checked by looking at the load transient response Switching regulators take several cycles to respond to a step in dc resistive load current When a load step occurs shifts by an amount equal to D 1 x ESR where ESR is the effective series resistance of Cour D 1i oap also begins to charge or discharge Cou until the regulator loop adapts to the current change and returns Voy to its steady state value D uring this recovery time Voyy can be monitored for overshoot or ringing which would indicate a stability prob lem T he external components on the Ir pin shown in the Figure 1 circuit will prove adequ
9. 2538ADP1148 3 3 4 hv ES ANALOG High Efficiency Synchronous DEVICES Step Down Switching Regulators ADP 1148 ADP1148 3 3 ADP 1148 5 FEATURES Operation From 3 5 V to 18 V Input Voltage Ultrahigh Efficiency gt 95 Low Shutdown Current Current Mode Operation for Excellent Line and Load Transient Response High Efficiency Maintained Over Wide Current Range Logic Controlled Micropower Shutdown Short Circuit Protection Very Low Dropout Operation Synchronous FET Switching for High Efficiency Adaptive Nonoverlap Gate Drives APPLICATIONS Notebook and Palmtop Computers Portable Instruments Battery Operated Digital Devices Industrial Power Distribution Avionics Systems Telecom Power Supplies GPS Systems Cellular Telephones GENERAL DESCRIPTION The ADP1148 is part of a family of synchronous step down Switching regulator controllers featuring automatic sleep mode to maintain high efficiencies at low output currents T hese devices drive external complementary power M OSFET s at Switching frequencies up to 250 kH z using a constant off time current mode architecture FUNCTIONAL BLOCK DIAGRAM ADJUSTABLE PWR SIGNAL VERSION Vin P DRIVE N DRIVE GND GND SENSE Vrg SENSE Cr Hu SHUTDOWN INT Vcc The constant off time architecture maintains constant ripple current in the inductor easing the design of wide input range converters C urrent mode operation provides excellent line and load transient response T
10. 4 T he maximum output current Imax determines the Rpsiow requirement for the two power M OSFET s When the ADP 1148 is operating in continuous mode the simplifying assumption can be made that one of the two M OSFET sis always conducting the average load current T he duty cycles for the M OSFET and diode are given by P Channe Duty Cycle V out iN N Channel Duty Cycle Vin Voyr N in From the duty cycle the required Ros on for each MOSFET can be derived P Ch roston Vin X Pp IV our X luax x 1 dp N Ch roston Vin X PNEC in Vout x Imax x 1 dy where P and Py are the allowable power dissipations and d and dy are the temperature dependency of Rosion Pp and Py will be determined by efficiency and or thermal requirements see Efficiency 1 d is generally given for a M OSFET in the form of a normalized vs temperature curve but d 0 007 C can be used as an approximation for low voltage M OSFET s T he Schottky diode D 1 shown in Figure 1 conducts only during the deadtime between the conduction of the two power M 5 D 1 s purpose is to prevent the body diode of the N channel M OSFET from turning on and storing charge during the dead time which could cost as much as 196 in efficiency D1 should be selected for forward voltage of less than 0 5 V when conducting Imax Cin and Cour Selection In continuous mode the source current of the P channel MOSFET is a square wave of duty cycle
11. 5 mV Substituting for from above gives the minimum required inductor value of Luin 5 1 x 10 x Roense X VREG Asthe inductor value increases above the minimum value the ESR requirements for the output capacitor are relaxed at the expense of efficiency If too small an inductor is used the induc tor current will decrease past zero and change polarity A result of this occurrence will be that the ADP1148 may not be in power saving mode operation and efficiency will be significantly reduced at low currents Inductor Core Oncethe minimum value for L is known the selection of the inductor must be made High efficiency converters generally cannot accommodate the core loss found in low cost powdered iron cores forcing the use of more expensive ferrite molypermalloy M PP or Kool Mu cores Actual core loss is independent of core size for a fixed inductor value but it is very dependent on inductance selected As inductance increases core losses de crease U nfortunately increased inductance requires more turns of wire and therefore copper losses will increase Ferrite designs have very low core loss so design goals can focus on copper loss and preventing saturation F errite core material saturates hard which causes the inductance to collapse abruptly when the peak design current is exceeded T his results in a sharp increase in inductor ripple current and subsequently output voltage ripple which ca
12. IN DISCHARGE CURRENT la 25 C Vour in Regulation V7 Vour 50 65 90 uA Vour 0V 2 10 uA OFF TIME torr 390 pF 1 700 mA 4 5 6 us DRIVER OUTPUT TRANSITION tr tF C 3000 pF Pins 1 14 TIMES Vin 26V 25 100 200 ns NOTES TAI limits at temperature extremes are guaranteed via correlation using standard Quality Control methods Specifications subject to change without notice 2 is calculated from the ambient temperature T and power dissipation Pp according to the following formulas ADP1148AR ADP1148AR 3 3 ADP1148AR 5 T T Pp x 110 C W ADP1148AN ADP1148AN 3 3 ADP1148AN 5 Tj 2 T4 Po x 70 C W 3D ynamic supply current is higher due to the gate charge being delivered at the switching frequency T he allowable operating frequency may be limited by power dissipation at high input voltages T heADP1148 version is tested with external feedback resistors setting the nominal output voltage to 3 3 V Specifications subject to change without notice _2 REV ADP1148 ADP1148 3 3 ADP1148 5 ELECTRI CAL CHARACTER STI CS 40 lt 85 C Vin 10 V 0 V unless otherwise noted See Figure 17 Parameter Symbol Conditions Min Typ Max Units FEEDBACK VOLTAGE ADP1148 Only Vio Vn 9V 120 1 225 1 30 V REGULATED OUTPUT VOLTAGE Vout Vin 29V ADP1148 3 3 ILoap 700 mA 317 333 34 V ADP1148 5 700 mA 4 85 5 05 5 2 V
13. INPUT DC SUPPLY CURRENT lo Normal M ode Vin 24V lt V n 18V 1 6 2 6 mA Sleep M ode ADP1148 3 Vin 24V Vy 18V 160 280 uA Sleep M ode AD P1148 5 Vin 26V Vu 18V 160 280 uA Shutdown UTDOWN 2 1 V 10 24 4V lt 12V CURRENT SENSE THRESHOLD VOLTAGE Vg V5 ADP1148 Only Vo 4 25 mV Forced 0 mV V 5V Vo 2 Voyr 4 25 mV Forced 115 150 175 mV V 5V ADP1148 3 3 100 mV Forced 0 mV V Voy 100 mV Forced 115 150 175 mV ADP1148 5 0 V7 Vour 100 mV Forced 0 mV Vz Vour 100 mV Forced 115 150 175 mV SHUTDOWN PIN THRESHOLD Vio ADP1148 3 3 ADP1148 5 0 55 0 8 2 V OFF TIME E Cy 390 pF 1 700 mA 4 5 6 2 NOTES TAIl limits at temperature extremes are guaranteed via correlation using standard Quality Control method T is calculated from the ambient temperature T and power dissipation P y according to the following formulas ADP1148AR ADP1148AR 3 ADP1148AR 5 T 2T Pp x 110 C W ADP1148AN ADP1148AN 3 ADP1148AN 5 T 2T Po x 70 C W 3D ynamic supply current is higher due to the gate charge being delivered at the switching frequency T he allowable operating frequency may be limited by power dissipation at high input voltages TheADP1148 version is tested with external feedback resistors setting the nominal output voltage to 3 3 V Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Input Supply Voltage Pin 3 Continuou
14. Vout n prevent large voltage transients a low ESR input capacitor sized for the maximum rms current must be used T he maximum rms ca pacitor current is given by Cin required Vour Vin 0 x luax Vin T his formula has a maximum at Vin 2 Vout wherelams lour 2 T his simple worst case condition is commonly used for design because even significant deviations do not offer much relief N ote that capacitor manufacturer s ripple current ratings are often based on only 2000 hours of life T his makes it advis able to further derate the capacitor or to choose a capacitor rated at a higher temperature than required Several capacitors may also be paralleled to meet size or height requirements in the design Always consult the manufacturer if there is any question RM S REV A ADP1148 ADP1148 3 3 ADP1148 5 An additional 0 1 uF 1 pF ceramic bypass capacitor is advised on Pin 3 parallel with T he selection of Cour is driven by the required effective series resistance ESR T he ESR of Cour must be less than twice the value of Rsense for proper operation of the ADP 1148 Cour required ESR lt 2Rsense Optimum efficiency is obtained by making the ESR equal to Rsense AS ESR is increased up to 2 Rense the efficiency degrades by less than 1 M anufacturers such as Sprague and United Chemmicon should be considered for high performance capacitors The OS CON semiconductor dielectric capacitor has
15. also the input for the current comparator 8 Sense The Input for the Current Comparator A built in offset between Pins 7 and 8 in conjunction with Rsense sets the current trip threshold 9 Ves For the ADP1148 adjustable version Pin 9 serves as the feedback pin from an external resistive divider used to set the output voltage AD P1148 3 3 and ADP1148 5 versions this pin is not used 10 Shutdown Taking Pin 10 of the ADP1148 ADP1148 3 3 or AD P1148 5 high holds both MOSFETs off Must be at ground potential for normal operation 11 Signal GND Small Signal Ground M ust be routed separately from other grounds to the terminal of Cour 12 Power GND Driver Power Ground Connects to source of N channel MOSFET and the terminal of 13 NC No Connection 14 N Channel Drive High Current Drive for bottom N channel MOSFET T he voltage swing at Pin 13 is from ground to Vin PIN CONFIGURATIONS 14 Lead Plastic DIP 14 Lead Plastic SO P DRIVE 1 e 14 N DRIVE 2 113 nc Vin 112 POWER GND 4 top view 11 SIGNAL GND INT Vec 5 110 SHUTDOWN 8 9 Vre SENSE 8 SENSE NC NO CONNECT FIXED OUTPUT VERSIONS SD1 CAUTION accumulate on the human body and test equipment and can discharge without detection Although ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING theADP1148 ADP1148 3 3 ADP1148 5 feature proprietary ESD protection circ
16. ate compensation for most applications A second more severe transient is caused by switching in loads with large 21 mF supply bypass capacitors T he discharged bypass capacitors are effectively put in parallel with Cout caus ing a rapid drop in N o regulator can deliver enough cur rent to prevent this problem if the load switch resistance is low and it is driven quickly T he only solution is to limit the inrush current to these capacitors below the current limit of the circuit Efficiency T he percent efficiency of a switching regulator is equal to the output power divided by the input power times 100 It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most im provement Percent efficiency can be expressed as Efficiency 100 L1 L2 L3 where L 1 L2 etc arethe individual losses as a percentage of input power For high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power REV A Although all dissipative elements in the circuit produce losses three main sources usually account for most of the losses in ADP1148 circuits 1 ADP1148 dc bias current 2 M OSFET gate charge currents 3 I x R losses 1 T he dc supply current is the current which flows into Viy Pin 3 less the gate charge current For V y 10 V the ADP1148 dc supply current is 160 uA for no load and i
17. eset to approximately 3 3 V During the off time Cr is discharged by a current which is proportional to Vour T he voltage on is analogous to the current in inductor L which likewise decays at a rate proportional to Therefore the inductor value must track the timing capacitor value The value of C is calculated from the preferred continuous mode operating frequency 12 6 x 10 x f Assumes Vin 2 Vour Figure 1 circuit A graph for selecting Cr versus frequency including the effects of input voltage is given in Figure 5 ADP1148 ADP1148 3 3 ADP1148 5 As the operating frequency is increased the gate charge losses will cause reduced efficiency see Efficiency section T he full formula for operating frequency is given by f 1 VourNin torr where 1 3 x 10 x Cr x VRresN our Vnec is the desired output voltage i e 5 V or 3 3 V Vout is the measured output voltage T hus Vreg our 1 in regulation N ote that as Viy reduces the frequency also decreases When the input to output voltage differential drops below 1 5 V the ADP1148 reduces torr by increasing the discharge current in Cr T his prevents audible operation before the device goes into dropout Once the frequency has been set by Cr the inductor L must be chosen to provide no more than 25 mV Rsense Of peak to peak inductor ripple current T his is set by the equation 25 mV Rsense _Vour Xtorr L MIN or Vout Xtorr XRsense 2
18. hold sets the peak of the inductor cur rent yielding a maximum output current Im Ax equal to the peak value less half the peak to peak ripple current The ADP 1148 operates effectively with values of Rsense from 20 ma to 200 ma A graph for selecting Rsense versus maximum output current is given in Figure 3 Solving for Rsense and allowing a margin for variations in the ADP 1148 and external component values yields Rsense 100 mV Imax T he peak short circuit current Isc px tracks Imax Once Rsense has been chosen Iscipx can be predicted from the fol lowing equation Iscirx 150 mV Rense Theload current below which power saving mode commences Ipower savi ng Is determined by the offset in comparator B and the value of the inductor chosen C omparator B is designed to have approximately 5 mV offset T his offset and the inductor can now be used to predict the power saving mode current as follows Ipower savinc 75 MV Rsense Vo X torf 2L TheADP1148 automatically extends torr during a short circuit to provide adequate time for the inductor current to decay be tween switch cycles T he resulting ripple current causes the average short circuit current Isc ava to be lowered to approxi mately Imax L and C Selection for Operating Frequency T he ADP1148 uses a constant off time architecture with tore determined by an external timing capacitor Cr Each time the P channel MOSFET switch turns on the voltage on is r
19. me as shown in Figure 17b If the Cr pin is observed falling to ground at high output currents it indicates poor decoupling or improper grounding Refer to the Board L ayout list ov A CONTINOUS MODE OPERATION B POWER SAVING MODE Figure 17 C Waveforms REV A ADP1148 ADP1148 3 3 ADP1148 5 Board Layout When laying out the printed circuit board the following check list should be used to ensure proper operation of the ADP1148 T hese items are also illustrated graphically in the layout diagram of Figure 18 C heck the following in your layout 1 Are the signal and power grounds segregated T he ADP 1148 SIGNAL GND Pin 11 must return to the plate of Coyr T he power ground returns to the source of the N channel M OSFET anode of the Schottky diode and plate of C n which should have as short lead lengths as possible 2 Does the ADP1148 SEN SE Pin 7 connect to a point close to Rsense and the plate Of Cout In adjustable versions the resistive divider R1 R2 must be connected be tween the plate of Cour and signal ground 3 Are the SENSE and SEN SE leads routed together with minimum PC trace spacing T he 1000 pF capacitor between Pins 7 and 8 should be as close as possible to the ADP1148 ADP1148 POWER GND NC NO CONNECT N DRIVE NC NC i 14 ON N CHANNEL 4 Does the plate of C y connect to the source of the P channel MOSFET as closely as possible T his
20. n cause the power saving mode operation to be falsely triggered in the ADP 1148 T o prevent this action from occurring do not allow the core to saturate M olypermalloy from M agnetics Inc is a very good low loss core material for toroids but it is more expensive than ferrite A reasonable compromise from the same manufacturer is K ool Mu T oroids are very space efficient especially when you can use several layers of wire Because they generally lack a bobbin mounting is more difficult M any new designs for surface mount All trademarks are the property of their respective holders components are also available from Coiltronics which do not increase the component height significantly Power MOSFET T wo external power M OSFET s must be selected for use with the ADP 1148 a P channel M OSFET for the main switch and an N channel M OSFET for the synchronous switch T he main selection parameters for the power M OSFET s arethe threshold voltage Vestn and on resistance Rps on T he minimum input voltage dictates whether standard threshold or logic level threshold M OSF ET s must be used For Vin gt 8 V standard threshold MOSFETs lt 4 V may be used If Vin Is expected to drop below 8 V logic level threshold MOSFETs Vesan 2 5 V are strongly recommended When logic level M OSFET s are used the ADP 1148 supply voltage must be less than the absolute maximum Ves rating for the M OSFET s e g gt 8 V of IRF730
21. ncreases pro portionally with load up to a constant 1 6 mA after the ADP1148 has entered continuous mode Because the dc bias current is drawn from Vy the resulting loss increases with input voltage For V y 10 V the dc bias losses are generally less than 196 for load currents over 30 mA H owever at very low load currents the dc bias current accounts for nearly all of the loss 2 M OSFET gate charge currents result from switching the gate capacitance of the power M OSFET s Each time a M OSFET gate is switched from low to high to low again a packet of charge dQ moves from to ground T he resulting dQ dt is a current out of Viy which is typically much larger than the dc supply current In continuous mode Icarecuc f Qe Qu The typical gate charge for a 100 N channel power M OSFET is 25 nC and for the P channel about twice that value T his results 7 5 mA in 100 kHz continu ous operation for a 296 to 3 typical midcurrent loss with Vin 10V N ote that the gate charge loss increases directly with both input voltage and operating frequency Thisisthe principal reason why the highest efficiency circuits operate at moderate frequencies Furthermore it argues against using a larger M OSFET than necessary to control 1 x R losses 3 I x losses are easily predicted from the dc resistances of the MOSFET inductor and current shunt In continuous mode the average output current flows through L a
22. nd Rsense but is chopped between the P channel and N channel M OSFET s If thetwo M OSFET s have about the same Rpsioy the resistance of one MOSFET can be simply summed with the resistances of L and Rsense to obtain I x R losses For example if each Rpsou 100 150 and Rsense 50 ma then the total resistance is 300 T his results in losses ranging from 396 to 1096 as the output current increases from 0 5 A to 2 A I x R losses cause the efficiency to roll off at high output currents Figure 6 shows how the efficiency losses in a typical ADP1148 regulator T he gate charge loss is responsible for the majority of the efficiency lost in the midcurrent region If power saving mode operation was not employed at low currents the gate charge loss alone would cause the efficiency to drop to unac ceptable levels With power saving mode operation the dc supply current represents the lone and unavoidable loss component which continues to become a higher percentage as output cur rent is reduced As expected the 1 x R losses dominate at high load currents Other losses including and Cour ESR dissi pative losses M OSFET switching losses Schottky conduction losses during deadtime and inductor core losses generally account for less than 296 total additional loss ADP1148 ADP1148 3 3 ADP1148 5 Design Example As a design example assume Viy 12 V nominal Vout 5 V Imax 2 A and f 200 kHz Rseuse
23. omparator S trips causing the internal sleep bar to go low T he circuit is now in sleep mode and the N channel Power M OSFET remains turned off While the circuit remains in this mode a significant amount of the circuit of the IC is turned off dropping the ground current from approximately 1 6 mA to a level of 160 uA In this state the load current is supplied by the output capacitor T he sleep mode is also terminated by the reset of Flip Flop 2 Component voltage current etc values are in SI units international standard unless otherwise indicated REV A T o prevent both the external MOSFETs from ever being turned on simultaneously feedback is incorporated to sense the state of the driver output pins Before the N drive output can go high the P drive output must also be high Likewise the P drive output is unable to go low while the N drive output is high By utilizing a constant off time structure the device operation is a function of the input voltage T o limit the effect of frequency variation as the device approaches dropout the controller begins to increase the discharge current as drops below Vour 1 5 V While the device is in drop out the P channel M OSFET is on constantly Rsense Selection For Output Current T he choice of Rsense is based the required output current TheADP1148 current comparator has a threshold range which extends from 0 mV to a maximum of 150 mV Rsense T he current comparator thres
24. our VFB 2204F a B 3300pF SENSE SENSE Re 1000pF 10 Vour 3 3V 2A OR 5V 2A NC NO CONNECT COILTRONICS CTX50 2 MP KRL SL 1 C1 0R050J Figure 21 Logic Selectable 5 V 1 A or 3 3 V 2 A High Efficiency Regulator REV A 13 ADP1148 ADP1148 3 3 ADP1148 5 OUTLINE D IMENSIONS Dimensions shown in inches and mm 14 Lead P lastic DIP N 14 0 795 20 19 0725 18 42 0 280 7 11 0 240 6 10 0 325 8 25 8 25 0 300 7 62 0 195 4 95 0 060 1 52 0 115 2 93 0 015 0 38 a 0 210 5 33 MX YH 0 130 0 160 4 06 A 3 30 0115 293 Ze le NS MIN 0 015 0 381 0 022 0 558 0 100 0 070 1 77 SEATING 0 008 0 204 2 54 LANE 0 014 0 356 0 045 1 15 BSC 14 Lead Plastic SO SO 14 0 3444 8 75 0 3367 8 55 A 14 8 0 1574 4 00 0 2440 6 20 0 1497 3 80 71 7 0 2284 5 80 PIN 1 0 0688 1 75 0 0196 0 50 0 0098 0 25 0 0532 1 35 gt lt 0 0099 0 25 9 0 0040 0 10 A y gt e gt 8 0 0500 0 0192 0 49 olle SEATING 157 0 0099 0 25 9 0 0500 1 27 0 0138 0 35 PLANE gsc 0 35 9 0075 0 19 0 016001 14 REV A 15 L6IZT Z B6LZZI YSN NI GALNIdd 16
25. output voltage to go above a maximum allowable value can be detected by external circuity T urning on the N channel M OSFET when this fault is detected will cause large currents to flow and blow the system fuse T he N channel MOSFET needs to be sized so it will safely handle this over current condition T he typical delay from pull ingtheC pin high and the N drive Pin 14 going high is 250 ns Note under shutdown conditions the N channel M OSFET is held OFF and pulling the pin high will not cause the N channel M OSFET to crowbar the output A simple N channel FET can be used as an interface between the overvoltage detect circuitry and the AD P1148 as shown in Figure 16 FROM CROWBAR DETECT CIRCUIT VN2222LL ACTIVE WHEN Vgarg VIN OFF WHEN Vgare GROUND Figure 16 Output Crowbar Interface Troubleshooting Since efficiency is critical to AD P1148 applications it is very important to verify that the circuit is functioning correctly in both continuous and power saving mode operation T he wave form to monitor is the voltage on the timing capacitor C1 pin In continuous mode li oap gt Ipower savinc the voltage on the pin should be a sawtooth with a 0 9 V p p swing T his voltage should never dip below 2 V as shown in Figure 17a When load currents are low l lt POWER SAVING MODE power saving mode operation occurs T he voltage on the pin now falls to ground for periods of ti
26. rnal complementary N and P channel M OSFET s T he operating frequency of the device is deter mined by the value of the external capacitor connected to the Cy pin T he output voltage is sensed by an internal voltage divider which is connected to the Sense pin ADP1148 3 3 and AD1148 5 or an external voltage divider returned to Veg AD P1148 A voltage comparator V and a gain block G compare the values of the divided output voltage with a reference voltage of 1 25 V To maximize the efficiency the ADP1148 automatically switches between two operational modes power saving and continuous T he Flip Flop 1 is the main control element when the device is in its power saving mode while the gain block is the main con trol when the output voltage moves to continuous mode D uring the continuous mode of the PM OS switch on cycle the current comparator C monitors the voltage between Sense and Sense When the voltage level reaches the threshold level the P drive output is switched to Viy which turns off the P channel MOSFET The timing capacitor Cy is now able to discharge at a rate determined by the off time controller T he discharge current is made to be proportional to the value of the output voltage measured at the Sense pin to model the inductor current which decays at a rate which is proportional to the out put voltage While the timing capacitor is discharging the N drive output goes to Viu turning on the N channel MOSFET
27. s Output Currents Pins 1 14 Sense Voltages Pins 7 8 Operating T emperature R ange Extended Commercial T emperature Range Junction T emperature Storage T emperature R ange L ead T emperature Soldering 10 sec REV A ORDERING GUIDE 0 3 V to 20 V feti 50 mA Output Package Package 0 3 V to Vcc Model Voltage Description Option o 0 C to 70 C ADP1148AN ADJ Plastic DIP N 14 40 C to 85 C ADP1148AR AD Small Outline Package SO 14 este 150 C ADP1148AN 3 3 3 3 V Plastic DIP N 14 65 C to 150 C ADP1148AR 3 3 3 3V Small Outline Package SO 14 emesis 300 C ADP1148AN 5 5V Plastic DIP N 14 ADP1148AR 5 5V Small Outline Package SO 14 ADP1148 ADP1148 3 3 ADP1148 5 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1 P Channel Drive High Current Gate Drive for T op P Channel MOSFET T he voltage swing at Pin 4 is from Viy to ground 2 NC No Connection 3 Vin Input Voltage 4 Cr External Capacitor from Pin 4 to Ground Sets the Operating Frequency T he frequency is also dependent on the ratio Voyt Vin 5 Int Vcc Internal Supply Voltage N ominally 3 3 V M ust be decoupled to signal ground Do not externally load this pin 6 Error Amplifier Decoupling Point The current comparator threshold increases with the Pin 7 voltage 7 Sense Connects to internal resistive divider that sets the output voltage in ADP1148 3 3 and ADP1148 5 versions Pin 7 is
28. uitry permanent damage may occur on devices subjected to high energy electrostatic discharges T herefore proper ff SD GENER DEVIGE ESD precautions are recommended to avoid performance degradation or loss of functionality _4 REV A Typical Performance Characteristics ADP1148 ADP1148 3 3 ADP1148 5 200 150 Rsense MQ 50 0 1 2 3 4 5 MAXIMUM OUTPUT CURRENT A Figure 3 Selecting Rsense vs Maxi mum Output Current 100 GATE CHARGE a o EFFICIENCY LOSS a 80 0 01 0 03 0 1 0 3 1 0 3 0 OUTPUT CURRENT A Figure 6 Typical Efficiency Losses FIGURE 1 CIRCUIT AVout mV 0 0 5 1 0 15 2 0 2 5 LOAD CURRENT A Figure 9 Load Regulation REV A 1000 Vsense Vour 5V 800 600 w 2 400 Q Vin 12V amp 5 Vin 7V 200 Vin 10V 0 0 100 200 300 FREQUENCY kHz Figure 4 Operating Frequency vs Timing Capacitor Value 100mA EFFICIENCY FIGURE 1 CIRCUIT 0 4 8 12 16 20 INPUT VOLTAGE V Figure 7 Efficiency vs Input Voltage ACTIVE MODE SUPPLY CURRENT mA o SLEEP MODE 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE V Figure 10 DC Supply Current
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