ANALOG DEVICES Integrated Synthesizer VCO ADF4360-0 Manual
Contents
1. C1 0 THIS BIT IS NOT USED BY THE DEVICE AND IS A DON T CARE BIT A COUNTER DIVIDE RATIO 0 1 2 3 B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED NOT ALLOWED F4 FUNCTION LATCH FASTLOCK ENABLE CP GAIN OPERATION 0 0 CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED 0 1 CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED N BP A P IS PRESCALER VALUE SET IN THE CONTROL LATCH B MUST BE GREATER THAN OR EQUAL TO A FOR CONTINUOUSLY ADJACENT VALUES OF AT THE OUTPUT IS 2 04414 0 018 DIV2 DIVIDE BY 2 0 FUNDAMENTAL OUTPUT 1 DIVIDE BY 2 DIVSEL DIVIDE BY 2 SELECT PRESCALER INPUT 0 FUNDAMENTAL OUTPUT SELECTED 1 DIVIDE BY 2 SELECTED Rev 0 Page 14 of 20 Table 9 R Counter Latch a a gt gt tc tc o o tc tc ANTI BACKLASH 14 BIT REFERENCE COUNTER ADF4360 0 CONTROL BITS DB23 DB22 DB21 0816 0815 DB11 10 THESE BITS ARE USED BY THE DEVICE AND ARE DON T CARE BITS RSV RSV BSC2 TEST MODE BIT SHOULD BE SET TOO FOR NORMAL OPERATION R10 R9 DIVIDE RATIO ANTIBACKLASH PULSE WIDTH LOCK DETECT PRECISION 3 0ns 1 3ns 6 0ns 3 0ns THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET FIVE CONSECUTIVE CYCLES OF PHASE DE2. poe poen DES 6 N Counter Latch 17 TRE 7 Counter Lath sse 17 auus 8 Applications LO 9 Fixed Frequency LO ener ied 9 Powet Up ciii iei eieneieteu 18 9 LO ass 9 PCB Design Guidelines for Chip Scale 19 9 Output Matching eee tette LO nude 9 Outline Dimensions iiti 20 nens 10 Ordering Guide e lirei eiiiai eiras aasi A 10 Rev 0 Page 2 of 20 SPECIFICATIONS 3 3 V 10 DGND 0 V Ta ADF 4360 0 Tmn to Tmax unless otherwise noted Table 1 Parameter B Version Unit Conditions Comments REFin CHARACTERISTICS REFin Input Frequency 10 250 MHz min max For f lt 10 MHz use dc coupled CMOS compatible square wave slew rate gt 21 V us REFin Input Sensitivity 0 7 V min max AC coupled to AVop V max CMOS compatible REF Input Capacitance 5 0 pF max REFin Input Current 100 max PHASE DETECTOR Phase Detector Frequency 8 MHz max CHARGE PUMP Sink Source With 4 7 High Value 2 5 mA typ Low Value 0 312 mA typ Rser Range 24 10 kQ Ice Three State Leakage Current 0 2 nA typ Sink and Source Current Matching 2 typ 1 25 V lt lt 2 5 V vs 1 5 96 typ 1 25 V lt Vo lt 2 5 V vs Temperature 2 96 typ 2 0 V LOGIC INPUTS
3. 4 60 0 n Integrated Synthesizer and ADF4360 0 FEATURES GENERAL DESCRIPTION Output frequency range 2400 MHz to 2725 MHz The ADF4360 0 is a fully integrated integer N synthesizer and Divide by 2 output voltage controlled oscillator VCO The ADF4360 0 is designed 3 0 V to 3 6 V power supply for a center frequency of 2600 MHz In addition a divide by 2 1 8 V logic compatibility option is available whereby the user gets an RF output of be Integer N synthesizer tween 1200 MHz and 1360 MHz Programmable dual modulus prescaler 16 17 32 33 Programmable output power level Control of all the on chip registers is through a simple 3 wire 3 wire serial interface interface The device operates with a power supply ranging from Analog and digital lock detect 3 0 V to 3 6 V and can be powered down when not in use Hardware and software power down mode APPLICATIONS Wireless handsets DECT GSM PCS DCS WCDMA Test equipment Wireless LANs CATV equipment AVpp DVpp Rset ADF4360 0 MULTIPLEXER MUXOUT 14 BIT COUNTER LOCK DETECT MUTE 24 BIT 24 BIT FUNCTION DATA REGISTER LATCH CHARGE PUMP cP PHASE COMPARATOR VTUNE Q y INTEGER REGISTER RFourA OUTPUT 13 BIT B STAGE COUNTER PRESCALER 1 5 BIT A COUNTER DIVSEL 1 gt lt
4. 2 125 gt 70 130 135 80 140 8 5 145 i 90 3 150 5 100 1000 10 100 1M 10M 0 25MHz 0 1MHz 2600MHz 0 1MHz 0 25 2 FREQUENCY OFFSET Hz Figure 8 Reference Spurs at 2600 MHz Figure 5 VCO Phase Noise 2600 MHz 200 kHz PFD 10 kHz Loop Bandwidth 9 200 kHz Channel Spacing 10 kHz Loop Bandwidth 75 3V 80 2 5mA PFD FREQUENCY 1MHz 85 LOOP BANDWIDTH 25kHz 90 RES BANDWIDTH 10kHz 95 VIDEO BANDWIDTH 10kHz 5 2109 a SWEEP 1 9 SECONDS ro AVERAGES 10 105 110 amp 2115 E 2 2 2 120 5 125 8 86dBc Hz 130 135 140 8 5 145 i i 150 bs 8 100 1000 10 100k 1M 10M 1MHz 0 5MHz 2250MHz 0 5MHz 1MHz FREQUENCY OFFSET Hz Figure 9 Reference Spurs at 2600 MHz Figure 6 VCO Phase Noise 1300 MHz 1 MHz Channel Spacing 25 kHz Loop Bandwidth Divide by 2 Enabled 200 kHz PFD 10 kHz Loop Bandwidth Rev 0 Page 8 of 20 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 10 SW1 and SW2 are normally closed switches SW3 is normally open When power down is initiated SW3 is closed and SW1 and SW2 are opened This ensures that there is no loading of the REF pin on power down POWER DOWN CONTROL TO R COUNTER z 04414 0 010 Figure 10 Reference Input Stage PRESCALER P P 1 The dual modulus prescaler P P 1 along with the A and B c
5. and CPenp sets the maximum charge pump output current for the synthesizer The nominal voltage potential at the pin is 0 6 V The relationship between Ic and Reser is zn Where Rser 4 7 2 5 mA 14 Internal Compensation Node This pin must be decoupled with a 10 uF capacitor 15 DGND Digital Ground 16 REFin Reference Input This is a CMOS input with a nominal threshold of Vpp 2 and a dc equivalent input resistance of 100 See Figure 10 This input can be driven from a TTL or CMOS crystal oscillator or it can be ac coupled 17 CLK Serial Clock Input This serial clock is used to clock in the serial data to the registers The data is latched into the 24 bit shift register on the CLK rising edge This input is a high impedance CMOS input 18 DATA Serial Data Input The serial data is loaded MSB first with the two LSBs being the control bits This input is a high impedance CMOS input 19 LE Load Enable CMOS Input When LE goes high the data stored in the shift registers is loaded into one of the four latches and the relevant latch is selected using the control bits 20 MUXOUT This multiplexer output allows either the lock detect the scaled RF or the scaled reference frequency to be accessed externally 21 DVop Digital Power Supply This ranges from 3 0 V to 3 6 V Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin
6. 2600 Loop B W 25 kHz 13 The spurious signals are measured with the EVAL ADF4360 xEB1 Evaluation Board and the HP8562E Spectrum Analyzer The spectrum analyzer provides the for the synthesizer frerour 10 MHz 0 dBm Rev 0 Page 4 of 20 ADF4360 0 TIMING CHARACTERISTICS DVpp 3 3 V 10 DGND 0 V 1 8 V and 3 V logic levels used Ta Tuis to Tmax unless otherwise noted Table 2 Parameter Limit at Tmn to Tmax B Version Unit Test Conditions Comments t 20 ns min LE Setup Time t 10 ns min DATA to CLOCK Setup Time ts 10 ns min DATA to CLOCK Hold Time ta 25 ns min CLOCK High Duration ts 25 ns min CLOCK Low Duration 16 10 ns min CLOCK to LE Setup Time t 20 ns min LE Pulse Width ty ts CLOCK DB1 080 158 0823 MSB 082 CONTROL BIT C2 CONTROL BIT C1 DATA 1 1 1 LE 1 1 LE 04414 0 002 Figure 2 Timing Diagram Rev 0 Page 5 of 20 ADF4360 0 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 3 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress rat AVop to GND 03Vto 3 9 V ing only functional operation of device at these or any to DVoo 0 3 V to 0 3 V other conditions above those listed in the operational sections Wco to GND 0 3 V to 3 9 V of this specification is not implie
7. Input High Voltage 1 5 V min Vint Input Low Voltage 0 6 V max Input Current 1 Input Capacitance 3 0 pF max LOGIC OUTPUTS Output High Voltage DVpp 0 4 Vmin CMOS output chosen lou Output High Current 500 pA max Output Low Voltage 0 4 V max lo 500 uA POWER SUPPLIES AVop 3 0 3 6 V min V max DVpp AVop Alpp 10 mA typ 2 5 mA typ lvco 19 0 mA typ Icone 10 mA 3 5 10 11 0 typ RF output stage is programmable Low Power Sleep 7 pA typ RF OUTPUT CHARACTERISTICS VCO Output Frequency 2400 2725 MHz min max Icone 15 mA VCO Sensitivity 56 MHz V typ Lock Time 250 us typ To within 10 Hz of final frequency Frequency Pushing Open Loop 1 MHzN typ Frequency Pulling Open Loop 15 kHz typ Into 2 00 VSWR load Harmonic Content Second 30 dBc typ Harmonic Content Third 39 dBc typ Output Power 13 6 5 dBm typ Programmable in 3 dB steps See Table 7 Output Power Variation 3 dB typ For tuned loads see Output Matching section VCO Tuning Range 1 25 2 50 V min max VCO Tuning Port Leakage Current 0 2 nA typ Rev 0 Page 3 of 20 ADF4360 0 Parameter B Version Unit Conditions Comments NOISE CHARACTERISTICS VCO Phase Noise Performance 111 dBc Hz typ 100 kHz offset from carrier 133 dBc Hz typ 1 MHz offset from carrier 140 dBc Hz typ 3 MHz offset from carrier 145 dBc Hz typ 1
8. 1 IDENTIFIER AVpp 2 ADF4360 0 TOP VIEW RFourA 4 Not to Scale RFourB 5 Vvco 5 ul z 2 Q z eo gt 4 04644 0 002 Figure 3 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Function 1 CPGND Charge Pump Ground This is the ground return path for the charge pump 2 AVop Analog Power Supply This ranges from 3 0 V to 3 6 V Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin AVop must have the same value as DVpp 3 81011 22 AGND Analog Ground This is the ground return path of the prescaler and VCO 4 RFoutA VCO Output The output level is programmable from 6 5 dBm to 13 dBm See the Output Matching section for a description of the various output stages 5 RFourB VCO Complementary Output The output level is programmable from 6 5 dBm to 13 dBm See the Output Matching section for a description of the various output stages 6 Vvco Power Supply for the VCO This ranges from 3 0 V to 3 6 V Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin must have the same value as AVpp 7 VruwE Control Input to the VCO This voltage determines the output frequency and is derived from filtering the CP output voltage 12 Cc Internal Compensation Node This pin must be decoupled to ground with a 10 nF capacitor 13 Rser Connecting a resistor between this
9. I a 5 2 z DIVSEL 2 O O AGND DGND CPGND Figure 1 Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A or otherwise under any patent or patent rights of Analog Devices Trademarks and Tel 781 329 4700 www analog com registered trademarks are the property of their respective owners Fax 781 326 8703 2004 Analog Devices Inc All rights reserved ADF4360 0 TABLE CONTENTS SPCC CATIONS fv Se eS LUE Timing Characteristics see Absolute Maximum Transistor ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Circuit Description Reference Input Section sse Prescaler P P A J Aand B eet tet RH R Counter eei eH teres PED and Charge Pump MUXOUT and Lock Detect sss InputShift Register ite tede ttti REVISION HISTORY 7 04 Revision 0 Initial Version ied 3 Moscr M 5 6 T 6 Control
10. as measured by the digital lock detect circuitry This is enabled by the Mute Till Lock Detect MTLD bit in the control latch RFoytA RFoytB 04414 0 015 Figure 15 Output Stage ADF4360 0 Rev 0 Page 11 of 20 ADF4360 0 LATCH STRUCTURE Table 6 shows the three on chip latches for the ADF4360 family The two LSBs decide which latch is programmed Table 6 Latch Structure CONTROL LATCH PRESCALER CURRENT CURRENT OUTPUT VALUE SETTING 2 SETTING 1 POWER LEVEL MUXOUT CONTROL CONTROL BITS MUTE TILL PHASE DETECTOR POLARITY COUNTER RESET DB23 DB22 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB6 DB5 DBO P2 P1 CPI5 CPI3 CPI2 PL1 M2 M1 C1 0 N COUNTER LATCH 13 BIT B COUNTER 5 BIT A COUNTER CONIEQU DIVIDE BY 2 SELECT DB23 DB22 DB21 DB20 DB19 DB11 0810 088 087 086 DB5 DBO B4 B3 C1 0 R COUNTER LATCH ANTI BACKLASH CONTROL PULSE 14 BIT REFERENCE COUNTER BITS WIDTH 5 a DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DBO RSV RSV 2 BSC1 TMB LDP ABP2 C1 1 Rev 0 Page 12 of 20 04414 0 026 Table 7 Control Latch PRESCALER VALUE CURRENT SETTING 2 CURRENT SETTING 1 OUTPUT POWER LEVEL MUXOUT CONTROL PHASE DETECTOR POLARITY COUNTER RESET A
11. 0 MHz offset from carrier Synthesizer Phase Noise Floor 172 dBc Hz typ 25 kHz PFD frequency 163 dBc Hz typ 200 kHz PFD frequency 147 dBc Hz typ 8 MHz PFD frequency In Band Phase 5 80 dBc Hz typ 1 kHz offset from carrier RMS Integrated Phase Error 1 4 Degrees typ 100 Hz to 100 kHz Spurious Signals due to PFD Frequency 13 75 dBc typ Level of Unlocked Signal with MTLD Enabled 45 dBm typ 1 Operating temperature range is 40 C to 85 Guaranteed by design Sample tested to ensure compliance 3 is internally modified to maintain constant loop gain over the frequency range 25 AVpp Wo 3 3 V P 32 5 These characteristics are guaranteed for VCO core power 10 mA Jumping from 2 4 GHz to 2 725 GHz PFD frequency 200 kHz loop bandwidth 10 kHz 7 Using 50 resistors to into 50 load For tuned loads see Output Matching The noise of the VCO is measured in open loop conditions The synthesizer phase noise floor is estimated by measuring the in band phase noise at the output of the VCO and subtracting 20 log N where N is the N divider value 10 The phase noise is measured with the EVAL ADF4360 xEB1 Evaluation Board and the HP8562E Spectrum Analyzer The spectrum analyzer provides the for the synthesizer offset frequency 1 kHz frein 10 MHz fero 200 kHz 2600 Loop B W 10 kHz 12 10 MHz fero 1 MHz
12. ADF4360 1 Output Stage better solution is to use a shunt inductor acting as an RF choke to Vvco This gives a better match than a resistor and therefore more output power Additionally a series inductor is added after the dc bypass capacitor to provide a resonant LC circuit This tunes the oscillator output and provides approxi mately 10 dB additional rejection of the second harmonic The shunt inductor needs to be a relatively low value 10 nH ADF4360 0 Experiments have shown that the circuit shown in Figure 20 provides an excellent match to 50 over the operating range of the ADF4360 0 This gives approximately 4 dBm output power across the frequency range of the ADF4360 0 Both single ended architectures can be examined using the EVAL ADF4360 0EBI evaluation board Vvco 47nH 1 5pF 3 9nH RFour mE 500 Figure 20 Differential ADF4360 0 Output Stage 04414 0 021 If the user does not need the differential outputs available on the ADF4360 0 the user may either terminate the unused out put or combine both outputs using a balun The circuit in Figure 21 shows how best to combine the outputs Vvco 47nH 10pF a 3 6nH 1 5 04414 0 022 Figure 21 Balun for Combining ADF4360 0 RF Outputs The circuit in Figure 21 is a lumped lattice type LC balun It is designed for a center frequency of 2 6 GHz and outputs 1 dBm at this frequency The series 1 nH inductor is used t
13. DF4360 0 CONTROL BITS DB23 DB22 DB21 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB6 DB5 gt DBO CPI5 CPI2 CE PIN PD2 44440000 PL1 M2 M1 PHASE DETECTOR POLARITY NEGATIVE POSITIVE CHARGE PUMP OUTPUT NORMAL 1 THREE STATE CPG CP GAIN 0 CURRENT SETTING 1 1 CURRENT SETTING 2 MTLD MUTE TILL LOCK DETECT 0 DISABLED 1 ENABLED OUTPUT POWER LEVEL PC1 2 0 C1 0 CORE POWER LEVEL 5mA 10mA 15mA 20mA COUNTER OPERATION NORMAL R A B COUNTERS HELD IN RESET OUTPUT CURRENT POWER INTO 500 USING 500 TO Vycc 3 5mA 5 0mA 7 5mA 11 0mA MODE 13dBm 11dBm 8 5dBm 6 5dBm 0 1 1 1 PRESCALER VALUE 8 9 16 17 32 33 32 33 ASYNCHRONOUS POWER DOWN NORMAL OPERATION ASYNCHRONOUS POWER DOWN SYNCHRONOUS POWER DOWN 04436 0 013 Rev 0 Page 13 of 20 THREE STATE OUTPUT DIGITAL LOCK DETECT ACTIVE HIGH N DIVIDER OUTPUT DVpp R DIVIDER OUTPUT N CHANNEL OPEN DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND ADF4360 0 Table 8 N Counter Latch a ao 13 BIT B COUNTER hr 5 A COUNTER CONTROL 50 E BITS z an 0823 DB22 DB21 DB20 DB19 0811 DB10 DB8 087 086 DBS DBO DIVSE DIV2 CPG B13 B12 B4 B3
14. DVpp must have the same value as AVpp 23 CE Chip Enable A logic low on this pin powers down the device and puts the charge pump into three state mode Taking the pin high powers up the device depending on the status of the power down bits 24 CP Charge Pump Output When enabled this provides Ice to the external loop filter which in turn drives the internal VCO Rev 0 Page 7 of 20 ADF4360 0 TYPICAL PERFORMANCE CHARACTERISTICS 3 3 3 3V _ REFERENCE lp a25m LEVEL 3 5dBm FREQUENCY 200kHz Il LOOP BANDWIDTH 10kHz RES BANDWIDTH 30Hz PR VIDEO BANDWIDTH 30Hz SWEEP 1 9 SECONDS 5 E AVERAGES 20 E a 5 2 80 4dBc Hz 2 E 2 5 o o i 3 i 2kHz ikHz 2600MHz 1kHz 2kHz 1k 10k 100k 1M 10M FREQUENCY OFFSET Hz Figure 7 Close In Phase Noise at 2600 MHz 200 kHz Channel Spacing Figure 4 Open Loop VCO Phase Noise 70 0 75 3 3V 3 3V s 10 REFERENCE laz 25mA 0 LEVEL 6dBm PFD FREQUENCY 200kHz 85 20 LOOP BANDWIDTH 10kHz 90 RES BANDWIDTH 1kHz 95 30 VIDEO BANDWIDTH 1kHz 5 AVERAGES 20 100 kJ 40 105 8 110 5 50 amp 2115 2 120 gt 60 a
15. F4360 0 SPI COMPATIBLE SERIAL BUS 5 e 5 04644 0 003 Figure 16 Fixed Frequency LO POWER UP After power up the part needs three writes for normal opera tion The correct sequence is to the R counter latch followed by the control latch and N counter latch INTERFACING The ADF4360 family has a simple SPI compatible serial inter face for writing to the device CLK DATA and LE control the data transfer When LE goes high the 24 bits that have been clocked into the appropriate register on each rising edge of CLK are transferred to the appropriate latch See Figure 2 for the timing diagram and Table 5 for the latch truth table The maximum allowable serial clock rate is 20 MHz This means that the maximum update rate possible is 833 kHz or one update every 1 2 us This is more than adequate for systems that have typical lock times in hundreds of microseconds ADuC812 Interface Figure 17 shows the interface between the ADF4360 family and the ADuC812 MicroConverter Since ADuC812 is based on an 8051 core this interface can be used with any 8051 based microcontroller The MicroConverter is set up for SPI master mode with CPHA 0 To initiate the operation the I O port driving LE is brought low Each latch of the ADF4360 family needs a 24 bit word which is accomplished by writing three 8 bit bytes from the MicroConverter to the device When the third byte has been written the LE input should be brought high t
16. LAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET BAND SELECT CLOCK DIVIDER 1 2 4 8 04414 0 017 Rev 0 Page 15 of 20 1 2 3 4 16380 16381 16382 16383 ADF4360 0 CONTROL LATCH With C2 C1 0 0 the control latch is programmed Table 7 shows the input data format for programming the control latch Prescaler Value In the ADF4360 family P2 and P1 in the control latch set the prescaler values Power Down DB21 PD2 and DB20 PD1 provide programmable power down modes In the programmed asynchronous power down the device powers down immediately after latching a 1 into Bit 1 with the condition that PD2 has been loaded with a 0 In the pro grammed synchronous power down the device power down is gated by the charge pump to prevent unwanted frequency jumps Once the power down is enabled by writing a 1 into Bit PD1 on the condition that a 1 has also been loaded to PD2 the device goes into power down on the second rising edge of the R counter output after LE goes high When the CE pin is low the device is immediately disabled regardless of the state of PD1 or PD2 When a power down is activated either synchronous or asynchronous mode the following events occur Allactive dc current paths are removed e The and timeout counters are forced to their load state conditions The charge pump is forced into three state mode The digital lock detect circuitry i
17. PLL action resumes The nominal value of is 56 MHz V or 28 MHZ V if divide by 2 operation has been selected by programming DIV2 DB22 high in the N counter latch The ADF4360 family contains linearization cir cuitry to minimize any variation of the product of Ic and Rev 0 Page 10 of 20 The operating current in VCO core is programmable in four steps 5 mA 10 mA 15 mA and 20 mA This is controlled by Bits PC1 and PC2 in the control latch OUTPUT STAGE The RFourA and pins of the ADF4360 family are con nected to the collectors of an NPN differential pair driven by buffered outputs of the VCO as shown in Figure 15 To allow the user to optimize the power dissipation versus the output power requirements the tail current of the differential pair is programmable via Bits PL1 and PL2 in the control latch Four current levels may be set 43 5 mA 5 mA 47 5 mA and 11 mA These levels give output power levels of 13 dBm 11 dBm 8 5 dBm and 6 5 dBm respectively using a 50 Q resistor to and ac coupling into a 50 load Alternatively both outputs can be combined in a 1 1 1 transformer or a 180 microstrip coupler see the Output Matching section ADF4360 0 If the outputs are used individually the optimum output stage consists of a shunt inductor to Vp Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock
18. d Exposure to absolute maxi Vvco to 0 3 V to 0 3 V mum rating conditions for extended periods may affect device Digital I O Voltage to GND 0 3 V to Vpp 0 3 V reliability Analog I O Voltage to GND 0 3 V to Vpp 0 3 V to GND 0 3 V to Voo 0 3 V This device is a high performance RF integrated circuit with an Operating Temperature Range 40 to 85 ESD rating of 1 kV and it is ESD sensitive Proper precautions Storage Temperature Range 65 to 150 should be taken for handling and assembly Maximum Junction Temperature 150 CSP Thermal Impedance Paddle Soldered 50 C W TRANSISTOR COUNT Paddle Not Soldered 88 C W 12543 CMOS and 700 Bipolar Lead Temperature Soldering Vapor Phase 60 sec 215 C Infrared 15 sec 220 C 1 GND AGND DGND OV ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING lt proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit 4 electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance ESD SENSITIVE DEVICE degradation or loss of functionality Rev 0 Page 6 of 20 ADF4360 0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 9 awe 55 p CPGND
19. d analog Digital lock detect is active high When LDP in the R counter latch is set to 0 digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns With LDP set to 1 five consecutive cycles of less than 15 ns phase error are required to set the lock detect It stays set high until a phase error of greater than 25 ns is detected on any sub sequent PD cycle The N channel open drain analog lock detect should be oper ated with an external pull up resistor of 10 nominal When a lock has been detected this output is high with narrow low going pulses DVpp ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT CONTROL MUXOUT N COUNTER OUTPUT SDOUT i DGND i Figure 13 MUXOUT Circuit INPUT SHIFT REGISTER The ADF4360 family s digital section includes a 24 bit input shift register a 14 bit R counter and an 18 bit N counter comprised of a 5 bit A counter and a 13 bit B counter Data is clocked into the 24 bit shift register on each rising edge of CLK The data is clocked in MSB first Data is transferred from the shift register to one of four latches on the rising edge of LE The destination latch is determined by the state of the two control bits C2 C1 in the shift register These are the two LSBs DB1 and DBO as shown in Figure 2 The truth table for these bits is shown in Table 5 Table 6 shows a summary of how the latches are programmed Note that the test mo
20. des latch is used for factory testing and should not be programmed by the user Table 5 C2 and C1 Truth Table Control Bits C2 C1 0 0 Control Latch 0 1 R Counter 1 0 N Counter A and B 1 1 Test Modes Latch VCO The core in the ADF4360 family uses eight overlapping bands as shown in Figure 14 to allow a wide frequency range to be covered without a large VCO sensitivity Kv and resultant poor phase noise and spurious performance The correct band is chosen automatically by the band select logic at power up or whenever the N counter latch is updated It is important that the correct write sequence be followed at power up This sequence is 1 Rcounter latch 2 Control latch 3 Ncounter latch During band select which takes five PFD cycles the VCO Vrune is disconnected from the output of the loop filter and connected to an internal reference voltage VOLTAGE V 04644 0 004 0 5 2200 2400 2600 2800 3000 FREQUENCY MHz Figure 14 Frequency vs Vrune ADF4360 0 The R counter output is used as the clock for the band select logic and should not exceed 1 MHz A programmable divider is provided at the R counter input to allow division by 1 2 4 or 8 and is con trolled by Bits BSC1 and BSC2 in the R counter latch Where the required PFD frequency exceeds 1 MHz the divide ratio should be set to allow enough time for correct band selection After band select normal
21. ency oscillator ADF4360 0 13 BIT B COUNTER TO PFD FROM VCO MODULUS CONTROL 4414 0 011 5 Figure 11 A and Counters R COUNTER The 14 bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector PFD Division ratios from 1 to 16 383 are allowed PFD AND CHARGE PUMP The PFD takes inputs from counter and counter N BP A and produces an output proportional to the phase and frequency difference between them Figure 12 is a simplified schematic The PFD includes a programmable delay element that controls the width of the antibacklash pulse This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs Two bits in the counter latch ABP2 and ABP1 control the width of the pulse see Table 9 M CHARGE PUMP R DIVIDER N DIVIDER CP OUTPUT Figure 12 Simplified Schematic and Timing In Lock 04414 0 012 Rev 0 Page 9 of 20 ADF4360 0 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip The state of MUXOUT is controlled by M3 M2 and M1 in the function latch The full truth table is shown in Table 7 Figure 13 shows the MUXOUT section in block diagram form Lock Detect MUXOUT can be programmed for two types of lock detect digital an
22. ic clock input The output of the R counter is by default the value used to clock the band select logic but if this value is too high gt 1 MHz divider can be switched on to divide the R counter output to a smaller value see Table 9 Reserved Bits DB23 to DB22 are spare bits that have been designated as Reserved They should be programmed to 0 Rev 0 Page 17 of 20 ADF4360 0 APPLICATIONS FIXED FREQUENCY LO Figure 16 shows the ADF4360 0 used as a fixed frequency LO at 2 6 GHz The low pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open loop bandwidth of 40 kHz The maximum PFD frequency of the ADF4360 0 is 8 MHz Since using a larger PFD frequency allows users to use a smaller N the in band phase noise is reduced to as low as possible 100 dBc Hz The 40 kHz bandwidth is chosen to be just greater than the point at which the open loop phase noise of the VCO is 100 dBc Hz thus giving the best possible integrated noise The typical rms phase noise 100 Hz to 100 KHz of the LO in this configuration is 0 35 The reference frequency is from a 16 MHz TCXO from Fox thus an R value of 2 is programmed Taking into account the high PFD frequency and its effect on the band select logic the band select clock divider is enabled In this case a value of 8 is chosen A very simple pull up resistor and dc blocking capacitor complete the RF output stage LOCK Vvpp DETECT AD
23. o complete the transfer SCLOCK SCLK MOSI SDATA ADuC812 PORTS LOCK DETECT 04437 0 014 Figure 17 ADuC812 to ADF4360 x Interface I O port lines on the ADuC812 are also used to control power down CE input and detect lock MUXOUT configured as lock detect and polled by the port input When operating in the described mode the maximum SCLOCK rate of the ADuC812 is 4 MHz This means that the maximum rate at which the out put frequency can be changed is 166 kHz ADSP 2181 Interface Figure 18 shows the interface between the ADF4360 family and the ADSP 21xx digital signal processor The ADF4360 family needs a 24 bit serial word for each latch write The easiest way to accomplish this using the ADSP 21xx family is to use the autobuffered transmit mode of operation with alternate fram ing This provides a means for transmitting an entire block of serial data before an interrupt is generated ADSP 21xx PORTS LOCK DETECT 04437 0 015 Figure 18 ADSP 21xx to ADF4360 x Interface Set up the word length for 8 bits and use three memory loca tions for each 24 bit word To program each 24 bit latch store the 8 bit bytes enable the autobuffered mode and write to the transmit register of the DSP This last operation initiates the autobuffer transfer Rev 0 Page 18 of 20 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The leads on the chip scale package CP 24 are rectangular The printed circuit board
24. o 0 normal operation occurs Divide by 2 Select DB23 is the divide by 2 select bit When programmed to 1 the divide by 2 output is selected as the prescaler input When set to 0 the fundamental is used as the prescaler input For exam ple using the output divide by 2 feature and a PFD frequency of 200 kHz the user needs a value of N 13 000 to generate 1 500 MHz With the divide by 2 select bit high the user may keep N 6 500 ADF4360 0 R COUNTER LATCH With C2 C1 0 1 the counter latch is programmed Table 9 shows the input data format for programming the R counter latch R Counter to R14 set the counter divide ratio The divide range is 1 00 001 to 16383 111 111 Antibacklash Pulse Width DB16 and DBI7 set the antibacklash pulse width Lock Detect Precision 0818 is the lock detect precision bit This bit sets the number of reference cycles with less than 15 ns phase error for entering the locked state With LDP at 1 five cycles are taken with LDP at 0 three cycles are taken Test Mode Bit DB19 is the test mode bit TMB and should be set to 0 With TMB 0 the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch R counter latch and N counter latch Note that test modes are for factory testing only and should not be pro grammed by the user Band Select Clock These bits set a divider for the band select log
25. o tune out any parasitic capacitance due to the board layout from each input and the remainder of the circuit is used to shift the output of one RF input by 90 and the second by 90 thus combining the two The action of the 3 6 nH inductor and the 1 5 pF capacitor accomplishes this The 12 nH is used to provide an RF choke to feed the supply voltage and the 10 pF capacitor provides the necessary dc block To ensure good RF perform ance the circuits in Figure 19 and Figure 21 are implemented with Coilcraft 0402 0603 inductors and AVX 0402 thin film capacitors Alternatively instead of the LC balun shown in Figure 21 both outputs may be combined using a 180 rat race coupler Rev 0 Page 19 of 20 ADF4360 0 OUTLINE DIMENSIONS 0 60 MAX 0 60 MAX 4 PIN 1 INDICATOR PIN 1 INDICATOR 0 80 MAX l 2 50 REF 1 00 12 Q 65TYP 0 85 0 05 MAX T COPLANARITY 0 08 0 23 1 0 20 SEATING 0 18 PLANE 0 18 COMPLIANT TO JEDECSTANDARDS MO 220 VGGD 2 Figure 22 24 Lead Lead Frame Chip Scale Package LFCSP CP 24 1 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Frequency Range Package Option ADF4360 0BCP 40 to 85 2400 MHz to 2725 MHz CP 24 1 ADF4360 0BCPRL 40 to 85 2400 MHz to 2725 MHz CP 24 1 ADF4360 0BCPRL7 40 to 85 2400 MHz to 2725 MHz CP 24 1 EVAL ADF4360 0EB1 Evaluation Board Purchase of licen
26. ounters enables the large division ratio N to be realized N BP A The dual modulus prescaler operating at CML levels takes the clock from the VCO and divides it down to a manage able frequency for the CMOS A and B counters The prescaler is programmable It can be set in software to 8 9 16 17 or 32 33 and is based on a synchronous 4 5 core There is a minimum divide ratio possible for fully contiguous output frequencies this minimum is determined by the prescaler value and is given by P A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide range division ratio in the PLL feed back counter The counters are specified to work when the pre scaler output is 300 MHz or less Thus with a VCO frequency of 2 5 GHz a prescaler value of 16 17 is valid but a value of 8 9 is not valid Pulse Swallow Function The A and B counters in conjunction with the dual modulus prescaler make it possible to generate output frequencies that are spaced only by the reference frequency divided by R The VCO frequency equation is A x where fvcois the output frequency of the VCO is the preset modulus of the dual modulus prescaler 8 9 16 17 and so on Bis the preset divide ratio of the binary 13 bit counter 3 to 8191 Ais the preset divide ratio of the binary 5 bit swallow counter 0 to 31 is the external reference frequ
27. pad for these should be 0 1 mm longer than the package lead length and 0 05 mm wider than the package lead width The lead should be centered on the pad to ensure that the solder joint size is maximized The bottom of the chip scale package has a central thermal pad The thermal pad on the printed circuit board should be at least as large as this exposed pad On the printed circuit board there should be a clearance of at least 0 25 mm between the thermal pad and the inner edges of the pad pattern to ensure that short ing is avoided Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package If vias are used they should be incorporated in the thermal pad at 1 2 mm pitch grid The via diameter should be between 0 3 mm and 0 33 mm and the via barrel should be plated with 1 ounce of copper to plug the via The user should connect the printed circuit thermal pad to AGND This is internally connected to AGND OUTPUT MATCHING There are a number of ways to match the output of the ADF4360 0 for optimum operation the most basic is to use a 50 resistor to Vvco A dc bypass capacitor of 100 pF is con nected in series as shown in Figure 19 Because the resistor is not frequency dependent this provides a good broadband match The output power in the circuit below typically gives 6 5 dBm output power into a 50 Q load Vvco 510 100pF RFour 500 04414 0 020 Figure 19 Simple
28. s reset The RF outputs are debiased to a high impedance state The reference input buffer circuitry is disabled The input register remains active and capable of loading and latching data Charge Pump Currents CPI3 CPD and in the 4360 family determine Current Setting 1 CPI6 CPI5 and CPI4 determine Current Setting 2 See the truth table in Table 7 Output Power Level Bits PL1 and PL2 set the output power level of the VCO See the truth table in Table 7 Mute Till Lock Detect DB11 of the control latch in the ADF4360 family is the Mute Till Lock Detect bit This function when enabled ensures that the RF outputs are not switched on until the PLL is locked CP Gain DB10 of the control latch in the ADF4360 family is the Charge Pump Gain bit When it is programmed to a 1 Current Setting 2 is used When it is programmed to a 0 Current Setting 1 is used Charge Pump Three State This bit puts the charge pump into three state mode when programmed to a 1 It should be set to 0 for normal operation Phase Detector Polarity The PDP bit in the ADF4360 family sets the phase detector polarity The positive setting enabled by programming a 1 is used when using the on chip VCO with a passive loop filter or with an active non inverting filter It can also be set to 0 This is required if an active inverting loop filter is used MUXOUT Control The on chip multiplexer is controlled by M2 and 1 See the
29. sed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components in an system provided that the system conforms to the Standard Specification as defined by Philips 2004 Analog Devices Inc All rights reserved Trademarks and 5 ANALOG tered trademarks are the property of their respective owners WWW ana 0 0 com iren DEVICES Rev 0 Page 20 of 20
30. truth table in Table 7 Counter Reset DB4 is the counter reset bit for the ADF4360 family When this is 1 the R counter and the A B counters are reset For normal operation this bit should be 0 Core Power Level 1 and PC2 set the power level in the VCO core The recom mended setting is 10 mA See the truth table in Table 7 Rev 0 Page 16 of 20 With C2 C1 1 0 the N counter latch is programmed Table 8 shows the input data format for programming the N counter latch A Counter Latch A5 to A1 program the 5 bit A counter The divide range is 0 00000 to 31 11111 Reserved Bits DB7 is a spare bit and has been designated as Reserved It should be programmed to 0 B Counter Latch B13 to B1 program the B counter The divide range is 3 00 0011 to 8191 11 111 Overall Divide Range The overall divide range is defined by P x B A where P is the prescaler value CP Gain DB21 of the counter latch in the ADF4360 family is the charge pump gain bit When this is programmed to 1 Current Setting 2 is used When programmed to 0 Current Setting 1 is used This bit can also be programmed through DB10 of the control latch The bit always reflects the latest value written to it whether this is through the control latch or the N counter latch Divide by 2 DB22 is the divide by 2 bit When set to 1 the output divide by 2 function is chosen When it is set t
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ANALOG DEVICES Integrated Synthesizer VCO ADF4360 0 Manual