TEXAS INSTRUMENTS TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY handbook
Contents
1. 7Cib W 2 ZC1a A ZC3a 19 20 SOURCE1 e e SOURCE3 DRAIN 11 12 e 13 14 DRAIN4 A GATE2 D4 GATE4 SOURCE2 e t e SOURCE4 4 9 16 21 GND NOTE A For correct operation no terminal may be taken below GND PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments l standard warranty Production processing does not necessarily include testing of all parameters EXAS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 Copyright O 1995 Texas Instruments Incorporated TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 absolute maximum ratings over operating case temperature range unless otherwise noted t Drain to source voltage Vps Source to GND voltage Drain to GND voltage Gate to source voltage range Vas Continuous drain current each output 25 C Continuous source to drain diode current 25 C Pulsed drain current each output Imax 25 C see Note 1 and Figure 15 Continuous gate to source zener diode current 25 C Pulsed gate to source zener diode current 25 C Single pulse avalanche energy Eas 25 C see Figures 4 15 and 16 Continuous total power dissipation 25 C see Figure 15 Operating virtual junction temperature range Ty Operating case temperature range Storage temperature ran2. 0 50 100 t IRM maximum recovery current t The above waveform is representative of D1 D2 D3 and D4 in shape only Figure 1 Reverse Recovery Current Waveform of Source to Drain Diode 25 t gt e 4 tt R y 40 DS Ves Pulse Generator 0v Vas aa r t DUT ta on gt 4 ME Rgen 50 30 pF V see Note A DD T 1 50 0 Moe VDpS on s Gass J VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A includes probe and jig capacitance Figure 2 Resistive Switching Test Circuit and Voltage Waveforms 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION Current Regulator EN 12 V 0 2 uF aS 50 e as DUT 10V Battery e 0 3 uF e e e VDD T VGS A Gate Voltage ns Ig 100 uA ig A xx Time VOLTAGE WAVEFORM IL Current 1 Current Sampling Resistor Sampling Resistor TEST CIRCUIT Figure 3 Gate Charge Test Circuit and Voltage Waveform Vpp 25 4 tay 159 uH M N VGS Pulse Generator Ip VDS 0v see Note
3. C W 100 DC Conditions dz0 5 d 0 2 10 d 0 1 0 05 0 02 1 0 01 Single Pulse tw mers Ip 0 0 1 0 0001 0 001 0 01 0 1 1 10 100 tw Pulse Duration s 1 Device mounted 24in2 4 layer FR4 printed circuit board with no heatsink NOTE A ZoJp t r t ReJB tw pulse duration cycle time d duty cycle ty tc Figure 17 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of
4. resistive load switching characteristics 25 C PARAMETER TEST CONDITIONS MIN TYP UNIT Turn on delay time td off Turn off delay time Vpp 25 V RL 209 10 ns fis tro Rise time t4 10 ns See Figure 2 tto Fall time Qg Total gate charge Vps 48 V Ip 1 125A Vas 10V Qgs th Threshold gate to source charge See Figure 3 nC Qgd Gate to drain charge Lp Internal drain inductance n Ls Internal source inductance 5 thermal resistance PARAMETER TEST CONDITIONS MIN UNIT ReJA Junction to ambient thermal resistance See Notes 4 and 7 ReJB Junction to board thermal resistance See Notes 5 and 7 Rggp Junction to pin thermal resistance See Notes 6 and 7 NOTES 4 Package mounted on an FR4 printed circuit board with no heatsink 5 Package mounted on a 24 inch2 4 layer FR4 printed circuit board 6 Package mounted in intimate contact with infinite heatsink 7 All outputs with equal power 35 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION 0 75 i l Reverse 1 00 Alus i 1 3 0r 8 TOTS pese oes 9 15 S 8 2225 e sees e 5 o EA pc L 13765 aid 150 200 250 300 350 400 450 500
5. A v 4 Ves eo 5 B soo DUT see Note B ov Rgen z 60 V Min 500 Vp BR DSX 5225 ov S 4 VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES The pulse generator has the following characteristics lt 10 ns tt 10 ns Zo 50 B Input pulse duration ty is increased until peak current IAs 11 25 A las X tav 2 17 2 mJ Energy test level is defined as EAS Figure 4 Single Pulse Avalanche Energy Test Circuit and Waveforms 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 DALLAS TEXAS 75265 VGS th Gate to Source Threshold Voltage V DS on Static Drain to Source On State Resistance Q TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS GATE TO SOURCE THRESHOLD VOLTAGE STATIC DRAIN TO SOURCE ON STATE RESISTANCE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 2 5 0 6 0 4 1 5 0 2 DS on 7 Static Drain to Source On State Resistance 0 5 0 0 40 20 0 20 40 60 80 100 120 140 160 40 20 0 20 40 60 80 100 120 140 160 TJ Junction T
6. all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
7. ON MAXIMUM DRAIN CURRENT VS DRAIN TO SOURCE VOLTAGE 100 Tc 25 C 5 1ust 5 10 o E 10 ms a 5 1 mst 5 E 500 ust x 1 ReJAS Rejpt DC Conditions 0 1 0 1 1 10 100 Vps Drain to Source Voltage V T Less than 2 duty cycle t Device mounted in intimate contact with infinite heatsink Device mounted on FR4 printed circuit board with no heatsink Figure 15 MAXIMUM PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 100 lt See Figure 4 2 5 lt lt 2 10 2 25 he B Tc 125 C s 1 0 01 0 1 1 0 10 100 tay Time Duration of Avalanche ms Figure 16 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 THERMAL INFORMATION DW PACKAGEt JUNCTION TO BOARD THERMAL RESISTANCE VS PULSE DURATION RoJB Junction to Board Thermal Resistance
8. TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 Low rps on 0 23 DW PACKAGE High Voltage Output 60 V TOP VIEW Extended ESD Capability 4000 V DRAIN1 24 DRAIN3 Pulsed 11 25 A Per Channel DRAIN1 231 DRAIN3 Fast Commutation Speed GATE1 22 GATES GND 14 211 GND description SOURCE1 5 20 SOURCE3 SOURCE 6 19 SOURCE3 SOURCE2 7 8 SOURCE4 SOURCE2 8 17 SOURCE4 GND 9 16 GND GATE2 10 15 GATE4 DRAIN2 11 14 DRAIN4 DRAIN 12 1 DRAIN4 The TPIC5403 is a monolithic gate protected power DMOS array that consists of four independent electrically isolated N channel enhancement mode DMOS transistors Each transistor features integrated high current zener diodes Zcxa and Zcxp to prevent gate damage in the event that an overstress condition occurs These zener diodes also provide up to 4000 V of ESD protection when tested using the human body model of a 100 pF capacitor in series with a 1 5 kQ resistor The TPIC5403 is offered in a 24 pin wide body surface mount DW package and is characterized for operation over the case temperature range of 40 C to 125 C schematic 1 2 23 24 DRAIN1 e e DRAIN3 971 Kt Di La 22 GATE1 3
9. emperature C TJ Junction Temperature C Figure 5 Figure 6 STATIC DRAIN TO SOURCE ON STATE RESISTANCE DRAIN CURRENT vs vs DRAIN CURRENT DRAIN TO SOURCE VOLTAGE AVgs 0 4 V lt TJ 25 C 1 unless otherwise t noted 2 5 o E 5 a 0 0 1 1 10 100 0 1 2 3 4 5 6 7 8 9 10 Ip Drain Current A Vps Drain to Source Voltage V Figure 7 Figure 8 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 7 PRODUCT PREVIEW TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLISO38A SEPTEMBER 1994 REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS DRAIN CURRENT DISTRIBUTION OF vs FORWARD TRANSCONDUCTANCE GATE TO SOURCE VOLTAGE 10 Total Number of Units 688 Ty 40 C 4 Vps 15V 9 TJ 125 C Ip 1 125 A Ty 25 C Ty 25 C 8 Ty 75 Ty 150 C 1 7 2 t o 6 5 8 4 Oo 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 VGs Gate to Source Voltage V gfs Forward Transconductance S Figure 9 Figure 10 CAPACITANCE SOURCE TO DRAIN DIODE CURRENT VS VS DRAIN TO SOURCE VOLTAGE SOURCE TO DRAIN VOLTAGE 400 V d 10 GS 2 360 f 1MH
10. ge Tstg Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 2 25 40 C to 150 C 40 C to 125 C 65 C to 150 C 260 C t Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE 1 Pulse duration 10 ms duty cycle 2 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS TEXAS 75265 TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 electrical characteristics 25 C unless otherwise noted PARAMETER TEST CONDITIONS TYP UNIT V BR DSx Drain to source breakdown voltage Ip 250 uA Vas 0 6 VGS th Gate to source threshold voltage ve Vps Vas 15 175 22 ViBR GS X Gate to source breakdown voltage IGS 250 uA L9 Lj V BR SG X Source to gate breakdown voltage 250 uA y Reverse drain to GND breakdown voltage across V BR D1 D2 D3 and D4 Drain to GND current 250 uA f Ip 2 25 A VDS on Drain to source on state voltage See Notes 2 and 3 Ig 2 25 A Forward on state voltage source to drain Vas 0 Z1 Z2 Z3 Z4 See Notes 2 and 3 a
11. nd Figure 12 Ip 2 25 A D1 D2 D3 D4 Forward on state voltage GND to drain Soo Notes 2 Zero gate voltage drain current 1 Vas 0 125 C 0 5 10 IGSSF Forward gate current drain short circuited to source VGs 15 V Vps 0 Ls RE Reverse gate current drain short circuited to IGSSR source VsG 5 V Vps 0 10 100 Look ot eakage current drain to 2 DONE Tc 125 C 05 10 T D DS on Static drain to source on state resistance See Notes 2 and 3 and Figures 6 7 c 0 3 5 Vps 15 V Ip 1 125 A gfs Forward transconductance See Notes 2 and 3 and Figure 9 1 6 2 1 S 200 250 Ciss Short circuit input capacitance common source Coss Short circuit output capacitance common source VGs 0 100 175 175 Short circuit reverse transfer capacitance See Figure 11 common source NOTES 2 Technique should limit Ty to 10 C maximum 3 These parameters are measured with voltage sensing contacts separate from the current carrying contacts source to drain and GND to drain diode characteristics 25 C PARAMETER TEST CONDITIONS UNIT Reverse recovery time Total diode charge See Figures 1 and 14 D1 D2 D3 and D4 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 3 TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995
12. z 68 0 Ty 25 320 Ciss 0 V 301 pF Coss 0 V 384 pF 280 Crss 10 V 144 pF Ty 40 240 3 Ciss a Ty 125 C 200 E 1 TJ 25 C S S 160 Ty 150 C C oss 75 120 5 Crss 8 80 o 40 0 0 1 0 4 8 12 16 20 24 28 32 36 40 0 1 1 10 Vps Drain to Source Voltage V Vsp Source to Drain Voltage V Figure 11 Figure 12 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 DALLAS TEXAS 75265 Vps 7 Drain to Source Voltage V tr Reverse Recovery Time ns 60 40 30 20 TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS DRAIN TO SOURCE VOLTAGE AND GATE TO SOURCE VOLTAGE VS GATE CHARGE Ip 1 125 A Ty 25 C See Figure 3 20 V Vpp 30 V Vpp 48 20 V 1 2 3 4 5 6 7 Gate Charge nC Figure 13 REVERSE RECOVERY TIME VS REVERSE di dt See Figure 1 D1 D2 D3 and D4 Reverse di dt A us Figure 14 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 12 10 0 100 200 300 400 500 600 Ves Gate to Source Voltage V TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY SLIS038A SEPTEMBER 1994 REVISED SEPTEMBER 1995 10 THERMAL INFORMATI
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TEXAS INSTRUMENTS TPIC5403 4 CHANNEL INDEPENDENT GATE PROTECTED POWER DMOS ARRAY handbook