DMC 60C51/31
Contents
1. Va Input high h voltage to 1 XTAL1 RST Vou Output low voltage to ports 1 29 a M Mou Output low voltage to port 0 ALE PSEN i t e an EYE Output high voltage to ports 1 2 3 ALE PSEN lo m 80A 24 E i v ls 25A 075vos HE S Lt Leona 0 9Vec uM Vo Von Output high voltage GA NEUES D Panes buaa los 3004A 0 75Voe decocta 09Voc ho Vn 0 45V i 50 In Logical 1 to 0 transition curent to ports 1 233 e50 UA AA MNS CONIC DONAR A A A A ED REPEL SU rs re ee ly Wnputleekegecurent topot0 EA OM5 WKMe 740 A Ide mode 12MHz ie 7 WE 5 Power down mode B mM BN NM Res Interna reset pul down resistor 150 kom Active mode 12 RE des J Loam te am ee ee OP TIE RP Se Note 1 See figure 8 through 11 for loc test conditions Minimum Voc for Power Down is 2V m DMC 60C51 21 O ELECTRICAL CHARACT ERISTICS AC T 0 C or 40 C 85 C Voc 5V 20 Ms 0V KH VARIABLE CLOCK SYMBOL FIGURE PARAMETER UNIT l ts Oscillator frequency Speed Ver 12 ae sions 60C31 51 T EA NM tou WU UU NNNM eo ALE pulse width w i ns l ten T Aa TI WE AN e X2. 9 M PUE E 2 3 Data hold after WR 33 i taa 50 nso Baao i EM M PES T ta 2 3 RD low to address float 0 0 ns Gree ae eee PEAL ATIE ENY AEE E tw 2 9 4 RD or WR WR high to ALE high 43 13 tag 40 taat4 External Clock tox 4 High time 2 20 ns o eui ud ee eee ee ee tam 4 Rise time 20 90 ns nam ai e a RR A 9 9 M M CRI TID PM MO EMI MEME re ton 4 Faltime 20 20 ms 390 ques DMC 60C 51 31 mmm TIMING DIAGRAM Thee ALE ipLPH TAVLL tup PSEN No teraz text texix PORTO 4 A0 A7 D tavy PORT2 4 AO A1IB AB A15 Figure 1 External Program Memory Read Cycle FROM PCL INSTRIN P2 0 P2 7 OR A8 A15 FROM DPH A0 A15 FROM PCH Figure 2 External Data Memory Read Cycle 39 nme DMC 60C51 311 me TIMING DIAGRAM Continued tan tovwx Pat NL twuox i N 1 FROM OR ME DATA OUT lt gt A0 A7 FROM PCL INSTR IN tavwL P20 P23 ORAS AISFROMDPH A0 A15 FROM PCH Figure 3 External Data Memory Write Cycle TIMING REFERENCE POINTS NOTE AC inputs during testing are driven at 0 5 for a logic T For timing purposes a port is no longer floating when a and 0 45V for a logic
3. 0 Timing measurements are made at 100m V change from load voltage occurs and begings to float when a 100mV change from the loaded Vou Vo level occurs lon la gt 3 2001 Figure 5 AC Testing Input Output Figure 6 Float Waveform Vm min for a logic 1 and Vi for a logic 0 392 m DMC 60C51 31 mamm LJ TIMING DIAGRAM Continued MAX ACTIVE MODE 12MHz 16MHz FREQ AT XTAL1 Figure 7 kc vs FREQ Valid only within frequency specifications Of the device under test Figure 9 Test Condition Idle Mode AR other pins are disconnected Figure 8 kc Test Condition Active Mode All other pins are disconnected ne DMC 60C 51 31 ae TIMING DIAGRAM Continued Figure 10 Clock Signal Waveform for lx Tests in Active and Idle Modes tan tona 5ns Figure 11 kc Test Condition Power down Mode All other pins are disconnected Voc 2V to 5 5V 394
4. by any enabled interrupt at which time the process is picked up at the interrupt service routine and continued or by a hardware reset which starts the processor the same as a power on reset POWER DOWN MODE In the Power Down mode the oscilator is stopped and the instruction that invokes Power Down is the last in struction executed The on chip RAM and Special Function Registers retain their values until the Power Down mode is terminated The only exit from Power Down is a hardware reset Reset redefines the SFRs but does not change the on chip RAM The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize 388 DMC 6OCS1 31 mem 7 POWER DOWN MODE Continued Te eon ans recen pootced Powe Severn Register PCON Table Status of the sina pins during Idie and Power Down modes ALE PSEN RORTO PORTI PORT2 PORTS meu 31 3 Bu Dms Da Dua li NM a Address Data Power Down internal Intenal 0 0 Power Down Extemal 0 0 Float Ss Data Data Data O ELECTRICAL CHARACTERISTICS DO T 0C 70 C or 40 C ac Voo 8V 20 Vss 0V a FO a mana aa ET low voltage except a a mea ram A e M M e e aaa aaa aa a M m a Na mut low voltage to EA Inout high voltage except XTALIRST
5. pulled low will source current because of the pullups Port 3 also serves the function of various special feature of the MCS 51 Family as listed below PotPN PNNO AltemateFuncton ee RR RUIN E DUIS UEM AERE SICH RE S P 3 0 10 RxD Serial input port P 3 1 11 TxD Serial output port P 32 12 INTO external interrupt 0 P33 13 INTi external interrupt 1 P34 14 TO Timer 0 extemal input P 35 15 T1 Timer 1 external input P 3 6 16 WR external data memory write strobe P 3 7 7 RD external data memory read ee i el RST PIN9 40DIP PIN10 44PLCC Reset input A high on this pin for two machine cycles while the oscillator is running resets the device An internal diffused resistor to Vss permits Power On reset using only an external capacitor to 246 DMC 60C5 1 31 Um 7 PIN DESCRIPTION Continued ALE PIN30 40DIP PIN33 44PLCC Address Latch Enable output pulse for latching the low byte of the address during accesses to extemal In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With th
6. NNI we Address hold after ALE low 48 taa 35 aa tay BELT III 234 taa 100 e a a 1 PSEN pulse width 205 ns tan 1 PSEN low valid instruction in MS 3t4 105 ns M dL tex 1 Input instruction hold after PSEN 0 0 i ns ioc 1 Input instruction float after PSEN 59 i ta ns tae 1 Address to valid instruction in 312 Staa 105 ns I A PRER NE 1 PSEN low to address float 10 10 ns m j I Data Memory tww 23 WR pulse width 400 Btag 100 50 ons tao RD low to valid data in E rei Stag 165 ns tmx 23 Datahodafte RD 0 0 ons rL OCC E CR CEU MESES UE MD E EM E OE jp tmz 2 3 Data float after RD 09 2ta 70 ns tuw 23 ALE low valid data in 517 150 ns H tp S C ER 4 teo 2 3 Address to vald data in B5 Itaa 165 ns tum 23 ALElow to RDor WR iow 200 300 3taa 50 3taa 50 ns d a et tam 2 3 Address vaid to WR low or RD low 203 Ata 130 ns ak A tow 23 Data valid to WR transition 23 i tag 90 ns
7. e bit set ALE is active only during a MOVX instruction Otherwise the pin is weakly pulled high PSEN PIN29 40DIP PIN32 44PLCC Program Store Enable is the read strobe to external Program Memory When the 60C51 is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data Memory PSEN is not activated during fetches from internal program memory EA PIN31 40DIP PIN35 44PLCC External Access enable EA must be strapped to Ves in order to enable the device to fetch code from ex temal Program Memory locations starting at 0000H up to FFFFH FEA is strapped to Voc the device exe cutes from intemal Program Memory OFFFH XTAL1 PIN19 40DIP PIN21 44PLCC NC Input to the inverting oscillator amplifier and input to the intemal clock generator circuits PIN1 12 23 34 44PLCC Non connection pins 387 ques DMC 60C 51 31 ae C PIN DESCRIPTION Continued XTAL2 PIN18 40DIP PIN20 44PLCC Output from the inverting oscillator amplifier Crystal Osailator IDLE MODE bi deron o deo vite al hw an EE vokes the Ide mode is the last instruction executed in the normal operating mode before Ide mode is activated The coritent of the on chip RAM and all the Special Function Registers remain intact during this mode The idle mode can be terminated either
8. mee MIC 60C 51 31 ae CMOS SINGLE COMPONENT 8 BIT MICROCOMPUTER FEATURES O 8 bit CPU optimized for control applications O Power control modes I Pin to pin compatible with intas 80C51 80C31 60C51 Low power mask programmable ROM 60C31 Low power CPU only O 64K Program Memory Space Data Memory sce 32 programmable O Lines O Two 16 Bit Timer counters High performance CMOS process 5 interrupt sources 2 Leva Programmable serial port 3 5 to 12MHz 5V 20 z MAXIMUM RATINGS O Ambient temperature under Bias 70C 0 630 16 002 1 H 906 O Storage temperature 65 C 150 ud O Voltage on any pin to Vss 0 5V Voc4 0 5V Maximum la per 1 0 pin 15mA Power dissipation 1Watt 383 mmu DMC 60C51 31 sue BLOCK DIAGRAM External interrupts interrupt 128 Timer 1 Counter R E ontrol Timer 0 inputs n gt l f DD RD Po P2 Pi P3 Ani z de i X i y Address Data Figure 60C51 Block Diagram Z DESCRIPTION The DAEWOO 60C31 60C51 is a high performance micro controler fabricated with DAEWOO high density CMOS technology The DAEWOO CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS The 60C51 contains a 4K x 8 ROM a 128x 8 RAM 32 I O lines two 16 bit counter timers a five source two priority level nested interrupt structure a
9. ram and Data memory In this cplication it uses strong internal pullups emitting 15 60C 51 31 DESCRIPTION Continued Port 1 PIN 1 8 40DIP PIN2 9 44PLCC Port 1 is an 8 bit bidirectional port with internal pullups Port 1 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are extemally being pulled low wil source current because of the internal pulups Port 2 PIN 21 28 40DIP PIN24 31 44PLCC Port 2 is an 8 ie Rr wa have pulled high by the intemal pullups and in that state can be used as input As inputs Port 2 pins that are externally being pulled low will source current because of the internal pullups Port 2 emits the high order address byte during fetches from extemal Program Memory and during ac cesses to external Data Memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pullups when emitting T s During accesses to external Data Memory that use 8 bit addresses MOVX Ri Port2 emits the contents of the P2 Special Function Register Port 3 PIN 10 17 40DIP PIN 13 19 44PLCC Port 3 is an 8 bit bidirectional 1 O port with internal pullups Port 3 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally being
10. serial VO port for either multi processor communication I O ex pansion or full duplex UART and on chip oscillator and clock circuits In addition the device has tow software selectable modes of power reduction ide mode and powerdown mode The idle mode freezes the CPU while allowing the RAM timers serial port and interrupt system to con 384 DMC 60C51 31 M PIN CONFIGURATION 0 1 ono 38 P0 1 AD x 5 lt lt d 36 P0 3 AD3 Q 3 A gt a of P0 4 AD4 NE BSc S ae L3 sj eos nos a P0 6 AD6 33 53 P0 7 AD7 383 8 Ze s 91 EA Vep if 3 50 ALE PROG 323 L3 33 t3 28 PSEN 13 Loz NR ii 3 28 P2 7 A15 ed y i Lr P2 6 A14 T UY E 26 P2 5 A13 1 28 25 P2 4 A12 a 24 P2 3 A11 23 P2 2 A10 i 22 P2 1 A9 P2 0 A8 PRENNENT EUREN RR tae ata ERR e E e E e NS i e EE O PIN DESCRIPTION 40 A0DIP PINA4 44PLCC Supply voltage during normal Ide and Power down operations Vss PIN20 40DIP PIN22 44PCC Circuit ground Port 0 PIN32 39 400 PIN36 43 44PLCC Port 0 is an 8 bit open drain bi directional I O port Port 0 pins that have 1 s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to extemal Prog
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DMC 60C51/31