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Allegro 8906 BIDIRECTIONAL 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING Data Sheet

1. B MicroSystems Inc output crossing through centertap True back EMF zero crossings used by the adaptive commutation delay circuit to advance the state sequencer commutate at the proper time to synchronously run the motor Back EMF zero crossings are indicated by FCOM an internal signal that toggles at every zero crossing FCOM is available at the DATA OUT terminal via the programmable data out multiplexer om Ny Ny NV cm y NV NM SOURCE ON BACK EMF VOLTAGE SINK ON FCOM TOGGLES AT BACK EMF ZERO CROSSING FCOM Dwg WP 016 1 Direction Control Serial port bit D2 controls the direction of rotation see sequencer state table The motor should be at a com plete stop before beginning a startup sequence that reverses the direction of rotation Startup Oscillator If the motor does not move at the initial startup state then it is in a null torque position In this case the outputs are commutated automatically by the startup oscillator after a period set by the external capacitor at lt where teo __4 Vesti X Csr S ee ST charge ST discharge In the next state the motor will move back EMF will be detected and the motor will accelerate synchronously Once normal synchro nous back EMF commutation occurs the startup oscillator is defeated by pulses of pulldown current at Cst at each commutation which prevents Csr from reaching its upper threshold
2. initiating the BLANK signal BLANK is an internal signal that inhibits the back EMF comparators during the commutation transients preventing errors due to inductive recovery and voltage settling transients The watchdog timing function allows time to detect correct motor position by checking the back EMF polarity after each commutation If the correct polarity is not observed between ta 4 and twp then the watchdog timer commutates the outputs to the next state to synchro nize the motor This function is useful in preventing excessive reverse rotation and helps in resynchronizing or starting with a moving spindle BLANK BLANK Dwg WP 022 NORMAL COMMUTATION Dwg WP 021 WATCHDOG TRIGGERED COMMUTATION Current Control The A8906CLB provides linear current control via the FILTER terminal an analog voltage input Maximum current limit is also provided and is controlled in four steps via the serial port Output current is sensed via an internal sense resistor Rs The voltage across the sense resistor is compared to one tenth the voltage at the FILTER terminal less the filter threshold voltage or to the maxi mum current limit reference whichever is lower This transcon ductance function is lout VriLTER Vri TERTH 10Rs where Hs IS nominally 0 2 Q and Vei_terty IS approximately 1 85 V YANK EN LOGIC ERROR FAST 4 FROM FLL V SPEED CONTROL DD INITIALIZATION ERROR SLOW _ FROM F
3. Transition 5 0 20 37 SERIAL PORT TIMING CONDITIONS CHIP SELECT CLOCK lec M A Dwg WP 019 A Minimum CHIP SELECT setup time before CLOCK rising edge 100 ns B Minimum CHIP SELECT hold time after CLOCK rising edge 150 ns C Minimum DATA setup time before CLOCK rising edge 150 ns D Minimum DATA hold time after CLOCK rising 150 ns E Minimum CLOCK low time before CHIP 50 ns F Maximum CLOCK frequency 3 3 MHz 115 Northeast Cutoff Box 15036 Worcester Massachusetts 01615 0036 508 853 5000 amm mp B MicroSystems Inc Bal l La TERMINAL FUNCTIONS Term Terminal Name LOAD SUPPLY Cpe One of two capacitors used to generate the ideal commutation points from the back EMF zero crossing points Vgg the 5 V or 12 V motor supply Timing capacitor used by the watchdog circuit to disable the back EMF compara tors during commutation transients and to detect incorrect motor position Csr Startup oscillator timing capacitor OUTA GROUND OUTs OUTc CENTERTAP BRAKE Power amplifier A output to motor 93 NJ Power and logic ground and thermal heat sink Power amplifier B output to motor Power amplifier C output to motor Motor centertap connection for back EMF detection circuitry Ac
4. 2318 89060 hv BIDIRECTIONAL 3 PHASE BRUSHLESS DC MOTOR CONTROLLER DRIVER WITH BACK EMF SENSING 1 y COMMUTATION 24 PO Le SERIAL PORT Dwg PP 040B ABSOLUTE MAXIMUM RATINGS at TA 25 C Load Supply Voltage Output Current lout 1 25 A Logic Supply Voltage Vpp Logic Input Voltage Range 0 3 V to Vpp 0 3 V Package Power Dissipation Pp See Graph Operating Temperature Range 0 to 70 C Junction Temperature Ty Storage Temperature Range 55 C to 150 C T Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry These conditions can be tolerated but should be avoided Output current rating may be restricted to a value determined by system concerns and factors These include system duty cycle and timing ambient temperature and use of any heatsinking and or forced cooling For reliable operation the specified maximum junction temperature should not be exceeded The A8906CLB is a bidirectional three phase brushless dc motor controller driver The three half bridge outputs are low on resistance n channel DMOS devices capable of driving up to 1 A The A8906CLB provides complete reliable self contained back EMF sensing motor startup and running algorithms A programmable digital frequency locked loop speed control circuit together with the linear current control circuitry provides precise motor speed regulation A s
5. Centertap The A8906CLB internally simulates the centertap voltage of the motor To obtain reliable start up performance from motor to motor the motor centertap should be connected to this terminal tBRK External Component Selection Appli cations information regarding the selection of external component values is available from the factory for external component selection frequency locked loop speed control and commutation delay capacitor selection TYPICAL APPLICATION Q VBB BYPASS VRET B MicroSystems Inc 4 23 115 Northeast Cutoff Box 15036 Worcester Massachusetts 01615 0036 508 853 5000 Cpt O DATA IN O CLOCK O CHIP SELECT O RESET BYPASS O DATA OUT O OSC REF O 45V Rey ert O SECTOR DATA CF2 Dwg EP 036C 9906 BIDIRECTIONAL 3 PHASE BRUSHLESS DC MOTOR CONTROLLER DRIVER Dimensions in Inches for reference only 24 13 0 0125 0 0091 0 2992 0 491 0 2914 0 394 0 050 0 016 0 020 112 3 0 050 0 6141 1 0 TO 8 0 013 0 5985 BSC eal NOTE 1 NOTE 3 0 0926 0 1043 0 0040 Dwg 008 25 Dimensions in Millimeters controlling dimensions 24 13 0 32 I 0 23 7 60 10 65 7 40 10 00 1 27 0 40 0 51 2 3 1 27 0 33 Es 100 ah BSC 0 TO 15 20 1 2 6 2 35 0 1 0 MIN Dwg MA 008 25A mm NOTES 1 Webbed lead frame Leads 6 7 18 and 19 are internally one piece 2 Le
6. D4 Current Limit D5 thru D18 This 14 bit word active low programs the REF time to set desired motor speed Bit Number Count Number 131 072 D19 Speed control mode switch LOW internal once around speed signal HIGH external sector data D20 and D21 These bits program the number of motor poles for the once around counter 0 is 1 12 D22 and D23 Controls the multiplexer for DATA OUT TACH once around or sector Thermal Shutdown SYNC FCOM Reset The RESET terminal when pulled low clears all serial port bits including the DO latch which puts the A8906CLB in the sleep mode VFAULT LU BRK BRAKE ACTIVATED VBRK Dwg OP 004 Braking A dynamic braking feature of the A8906CLB shorts the three motor windings to ground This is accomplished by turning the three source drivers OFF and the three sink drivers ON Activation of the brake can be implemented through the BRAKE input The supply voltage for the brake circuitry is the Cres voltage allowing the brake function to remain active after power failure Power down braking with delay can be implemented by using an external RC and other compo nents to control the brake terminal as shown Brake delay can be set using the equation below Once the brake is activated due to the inherent capacitive input the three sink drivers will remain active until the device is VBRK reset In vds
7. LL 1 1 FILTER LINEAR E CURRENT CONTROL SERIAL PORT REGISTER AND D4 ERROR FAST FROM FLL MAX CURRENT LIMIT 1 Dwg 046 Speed Control A8906CLB includes a frequency locked loop speed control system This system monitors motor speed via internal or external digital tachometer signals generates a precision speed reference determines the digital speed error and corrects the motor current via an internal charge pump and external filtering components on the FILTER terminal A once per revolution TACH signal can be generated by counting cycles of FCOM the number of motor poles must be selected via the serial port TACH is then a jitter free signal that toggles once per motor revolution The rising edge of TACH triggers REF a precision speed reference derived by a programmable counter The duration of REF is set by programming the counter to count the desired number of OSC cycles I SERIALPORT REGISTER per 8 4 BIT 14 BIT OSC FIXED PROGRAMMABLE COUNTER COUNTER Dwg EP 045 B MicroSystems Inc desired 60 x fosc total count desired motor speed rpm where the total count number of oscillator cycles is equal to the sum of the selected programmed low count numbers corre sponding to bits D5 through D18 The speed error is detected as the difference in falling edges of TACH and REF The speed error signals control the error correcting ch
8. ROUND 3 FILTER Dwg FP 034 ALLOWABLE PACKAGE POWER DISSIPATION in WATTS TEMPERATURE in Dwg GP 019B 115 Northeast Cutoff Box 15036 Worcester Massachusetts 01615 0036 508 853 5000 Copyright 1999 Allegro MicroSystems Inc umm ED B MicroSystems Inc ELECTRICAL CHARACTERISTICS at T4 25 C Vpp 5 0 V Characteristic Test Conditions Min Operating Thermal Shutdown NH Thermal Shutdown Hysteresis Output Drivers Output Leakage Current Veses 14 V Vout 14 V Ves 14 V Vout 0 V Total Output ON Resistance Source Sink Rs Output Sustaining Voltage Vas 14 V lout L mH Clamp Diode Forward Voltage Vr 1 0A Control Logic Logic Input Voltage SECTOR DATA RESET CLK 0 CHIP SELECT OSC me e pem esi E 3 Current lost Charging Discharging M Csr Threshold 25 2 75 Filter Current TER Charging Discharging Leakage 2 5 V Filter Threshold 157 185 213 2 2 Cp or Cp Continued next page ELECTRICAL CHARACTERISTICS continued Limits Characteristic Test Conditions Mi M n Typ ax EUER 2 0 1 2 1 4 Max FLL Oscillator Frequency 5 0 V TA 25 1 i 1 D4 0 D3 1 04 1 250 Back EMF Hysteresis VBEMF VCTAP at 5 0 20 37 FCOM
9. ad spacing tolerance is non cumulative 3 Exact body and lead configuration at vendor s option within limits shown 9906 BIDIRECTIONAL 3 PHASE BRUSHLESS DC MOTOR CONTROLLER DRIVER Allegro MicroSystems Inc reserves the right to make from time to time such departures from the detail specifications as may be required to permit improvements in the design of its products The information included herein is believed to be accurate and reliable However Allegro MicroSystems Inc assumes no responsibil ity for its use nor for any infringements of patents or other rights of third parties which may result from its use 115 Northeast Cutoff Box 15036 Worcester Massachusetts 01615 0036 508 853 5000 icroSystems Inc
10. and thus completing a cycle and commutating 115 Northeast Cutoff Box 15036 Worcester Massachusetts 01615 0036 508 853 5000 Adaptive Commutation Delay The adaptive commutation delay circuit uses the back EMF zero crossing indicator signal FCOM to determine an optimal commuta tion time for efficient synchronous operation This circuit commutates the outputs delayed from the last zero crossing using two external timing capacitors Cp and tFCOM ka FCOM VCWD tcD1 1 tcD2 Vcpe Dwg WP 016 2 to measure the time between crossings ICD charge where tcp tFcoM X ICD discharge Cp charges up with a fixed current from its 2 5 V reference while FCOM is high When FCOM goes low at the next zero crossing Cp is discharged at approximately twice the charging current When CD reaches the CD threshold a commutation occurs Cpo operates similarly except on the opposite phase of FCOM Thus the com mutations occur approximately halfway between zero crossings The actual delay is slightly less than halfway to compensate for electrical delays in the motor which im proves efficiency Blanking and Watchdog Timing Functions The blanking and watchdog timing functions are derived from one timing capacitor Cwp X Cwo where lBLANK Vin The CWD capacitor begins charging at each commutation
11. arge pump on the FILTER terminal which drive the external loop com pensation components to correct the motor current Sector Mode An external tachometer signal such as sector or index pulses may be used to create the TACH signal rather than the internally derived once around To use this mode the signal is input to the SECTOR terminal and the sector mode must be enabled via the serial port When Switch ing from the once around mode to sector mode it is important to monitor the SYNC signal on DATA OUT and switch modes only when SYNC is low This ensures making the transition without disturbing the speed control loop The speed reference counter should be reprogrammed at the same time Speed Loop Initialization YANK improve the acquire time of the speed control loop there is an automatic feature controlled by an internal YANK signal The motor is started at the maximized programmed current by bypassing the FILTER terminal The FILTER terminal is clamped to an internal reference the filter threshold voltage initializing it near the closed loop operating point YANK is enabled at startup and stays high until the desired speed is reached Once the first error fast occurs indicating the motor crossed through the desired speed YANK goes low This releases the clamp on the FILTER terminal and current control is returned to FILTER This feature optimizes speed acquire and minimizes settling The Current Control Block Diag
12. erial port allows the user to program various features and modes of operation such as the speed control parameters rotational direction startup current limit sleep mode diagnostic modes and others The A8906CLB is fabricated in Allegro s BCD Bipolar CMOS DMOS process an advanced mixed signal technology that combines bipolar analog and digital CMOS and DMOS power devices The A8906CLB is provided in a 24 lead wide body SOIC batwing package It provides for the smallest possible construction in surface mount applications FEATURES DMOS Outputs LOW Startup Commutation Circuitry Back EMF Commutation Circuitry Direction Control Serial Port Interface Frequency Locked Loop Speed Control Sector Data Tachometer Signal Input Programmable Start Up Current Diagnostics Mode Sleep Mode Linear Current Control Internal Current Sensing Dynamic Braking Through Serial Port Power Down Dynamic Braking System Diagnostics Data Out Data Out Ported in Real Time Internal Thermal Shutdown Circuitry Always order by complete part number e g A8906CLB E MicroSystems Inc V 1092 jeeus geq FUNCTIONAL BLOCK DIAGRAM LOGIC SUPPLY CsT BRAKE C RES Ww D Q 12 VDD FCO Z lt z 2 2 5 0 O CENTERTAP WATCHDOG wo TIMER SECTOR DATA 9 FREQUENCY CHARGE CURRENT OSC 19 T LOOP PUMP CONTROL Rg GROUND DATA IN 23 SERIAL PORT G
13. ram illustrates the YANK signal and its effects 115 Northeast Cutoff Box 15036 Worcester Massachusetts 01615 0036 508 853 5000 Serial Port The serial port functions to write various operational and diagnostic modes to the A8906CLB serial port DATA IN is enabled disabled by the CHIP SELECT terminal When CHIP SE LECT is high the serial port is disabled and the chip is not affected by changes in data at the DATA IN or CLOCK terminals To write data to the serial port the CLOCK terminal should be low prior to the CHIP SELECT terminal going low Once CHIP SELECT goes low information on the DATA IN terminal is read into the shift register on the positive going transition of the CLOCK There are 24 bits in the serial input port Data written into the serial port is latched and becomes active upon the low to high transition of the CHIP SELECT terminal at the end of the write cycle DO will be the last bit written to the serial port SERIAL PORT BIT DEFINITIONS DO Sleep Run Mode LOW Sleep HIGH Run This bit allows the device to be powered down when not in use D1 Step Mode LOW Normal Operation HIGH Step Only When in the step only mode the back EMF commutation circuitry is disabled and the power outputs are commutated by the start up oscillator This mode is intended for device and system testing D2 Direction LOW Forward HIGH Reverse and D4 These two bits set the output current limit D3
14. rs with a total source plus sink of typically 1 Internal charge pump boost circuitry provides voltage above supply for driving the high side DMOS gates Intrinsic ground clamp and flyback diodes provide protection when switching inductive loads and may be used to rectify motor back EMF in power down conditions An external Schottky power diode or pass FET is required in series with the load supply to allow motor back EMF rectification in power down conditions Back EMF Sensing Motor Startup and Running Algorithm The A8906CLB pro vides a complete self contained back EMF sensing startup and running commutation scheme The three half bridge outputs are controlled by a state machine There are six possible combinations In each state one output is high sourcing current one low sinking current and one is OFF high impedance Z Motor back EMF is sensed at the OFF output The truth table for the output drivers sequencing is Direction Control OUTA OUTg OUTc 25 lI NN At startup the outputs are enabled of the sequencer states shown The back EMF is examined at the OFF output by comparing the output voltage to the motor centertap voltage at CENTERTAP The motor will then either step forward step backward or remain stationary if in a null torque position If the motor moves the back EMF detection circuit waits for the correct polarity back EMF zero crossing
15. tive low turns ON all three sink drivers shorting the motor windings to ground External capacitor and resistor at provide brake delay External reservoir capacitor used to hold charge to drive the source drivers gates Also provides power for brake circuit Cres 16 FILTER Analog voltage input to control motor current Also compensation node for internal speed control loop SECTOR DATA External tachometer input Can use sector or index pulses from disk to provide precise motor speed feedback to internal frequency locked loop LOGIC SUPPLY OSCILLATOR DATA OUT Vpp the 5 V logic supply Clock input for the speed reference counter Typical max frequency is 10 MHz Thermal shutdown indicator FCOM TACH or SYNC signals available in real time controlled by 2 bit multiplexer in serial port When pulled low forces the chip into sleep mode clears all serial port bits CHIP SELECT Strobe input active low for data word CLOCK GROUND RESET 18 19 Power and logic ground and thermal heat sink Clock input for serial port DATA IN Sequential data input for the serial port POT noil NO da A PO o o gt X NO AR g One of two capacitors used to generate the ideal commutation points from the back EMF zero crossing points FUNCTIONAL DESCRIPTION Power Outputs The power outputs of the A8906CLB are n channel DMOS transis to

Allegro 8906 BIDIRECTIONAL 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING Data Sheet

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