LINEAR LTC2446/LTC2447 handbook
Contents
1. gt gt gt gt gt gt 9 Hr mr CD CD CD D D wo CD 24467fa LI VIE TO LTC2446 LTC2447 APPLICATIONS INFORMATION Speed Multiplier Mode In addition to selecting the speed resolution a speed multiplier mode is used to double the output rate while maintaining the selected resolution The last bit of the 5 bit speed resolution control word TWOX see Table 4 deter mines if the output rate is 1x no speed increase or 2x double the selected speed While operating in the 1x mode the device combines two internal conversions for each conversion result in order to remove the ADC offset Every conversion cycle the offset and offset drift are transparently calibrated greatly simpli fying the user interface The conversion result has no latency The first conversion following a newly selected speed resolution and or input reference is valid This is identical to the operation of the 1702440 1702444 1702445 LTC2448 LTC2449 LTC2414 and LTC2418 While operating in the 2x mode the device performs a running average of the last two conversion results This automatically removes the offset and drift of the device while increasing the ou2. CONVERSION CONVERSION gt OUTPUT lt SLEEP gt lt CONVERSION gt 24467 08 Figure 8 Internal Serial Clock Reduced Data Output Length 24467fa 19 LTC2446 LTC2447 APPLICATIONS INFORMATION Internal Serial Clock 3 Wire 1 0 Continuous Conversion This timing mode uses a 3 wire all output SCK and SDO interface The conversion resultis shifted out of the device by an internally generated serial clock SCK signal see Figure 9 CS may be permanently tied to ground simplify ing the user interface or isolation barrier The internal serial clock mode is selected by tying EXT HIGH During the conversion the SCK and the serial data output pin SDO are HIGH EOC 1 and BUSY 1 Once the conversion is complete SCK BUSY and SDO go LOW EOC 0 indicating the conversion has finished and the 4 5V TO 5 5V device has entered the low power sleep state The part remains in the sleep state a minimum amount of time 500ns then immediately begins outputting data The data output cycle begins onthe first rising edge of SCK and ends after the 32nd rising edge Datais shifted outthe SDO pin on each falling edge of SCK The internally generated serial clock is output to the SCK pin This signal may be used to shift the conversion result into external circuitry EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can
3. 24467fa 17 LTC2446 LTC2447 APPLICATIONS INFORMATION Internal Serial Clock Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle see Figure 7 In order to select the internal serial clock timing mode the EXT pin must be tied HIGH The serial data output SDO is Hi Z as long as CS is HIGH At any time during the conversion cycle CS may be pulled LOW in order to monitor the state of the converter Once CS is pulled LOW SCK goes LOW and EOC is output to the SDO EOC 1 while a conversion is in progress and EOC 0 if the device is in the sleep state Alternatively BUSY Pin 2 may be used to monitor the status of the conversion in progress BUSY is HIGH during the conver 4 5V TO 5 5V 1102446 USER SELECTABLE REFERENCES lt 0 1V TO ANALOG INPUTS lt lt CS TEST EOC TEST EOC 1 2 3 4 5 6 DON T CARE ew sot GLBL OSR3 OSR2 OSR1 OSRO TWOX DON T CARE BIT31 BIT29 BIT28 BIT27 BIT26 BIT25 24 BIT23 BIT22 BIT21 BIT20 BIT 19 BIT 0 sion and goes LOW atthe conclusion It remains LOW until the result is read from the device When testing EOC if the conversion is complete EOC 0 the device will exitthe sleep state and enter the data output state if CS remains LOW In order t
4. A DOS ENVELOPE NORMAL MODE REJECTION dB 120 140 0 60 120 180 240 DIFFERENTIAL INPUT SIGNAL FREQUENCY Hz 24467 F10 Figure 10 LTC2446 LTC2447 Normal Mode Rejection Internal Oscillator 100 NORMAL MODE REJECTION dB 140 47 49 51 53 55 57 59 61 63 DIFFERENTIAL INPUT SIGNAL FREQUENCY Hz 24467 F11 Figure 11 LTC2446 LTC2447 Normal Mode Rejection Internal Oscillator Table 6 OSR vs Notch Frequency fy with Internal Oscillator Running at 9MHz OSR NOTCH fy 64 28 16kHz 128 14 08kHz 256 7 04kHz 512 3 52kHz 1024 176kHz 2048 880Hz 4096 440Hz 8192 220Hz 16384 110Hz 32768 55Hz Simultaneous 50 60Hz rejection If Fo is grounded fs is set by the on chip oscillator at 1 8MHz 5 over supply and temperature variations At an OSR of 32 768 the first NULL is at fy 55Hz and the no latency output rate is 6 9Hz At the maximum OSR the noise performance of the device is 280nVaus LTC2446 and 200nVpms LTC2447 with better than 80dB rejection of 50Hz 2 and 60 2 2 Since the OSR is large 32 768 the wide band rejection is extremely large and the antialiasing requirements are simple The first multiple of fs occurs at 55Hz 32 768 1 8MHz see Figure 12 The first NULL becomes fy 7 04kHz with an OSR of 256 an output rate of 880Hz and Fo grounded While the NULL
5. The second difference is the 11762447 includes MUXOUT ADCIN pins These pins enable an external buffer or gain block to be inserted between the selected input channel of the multiplexer and the input to the ADC Since the buffer is driven by the output of the multiplexer only one circuit is required for all 8 input channels Additionally the transparent calibration feature of the LTC244X family automatically removes the offset errors of the external buffer In order to achieve optimum performance the MUXOUT and ADCIN pins should not be shorted together In appli cations where the MUXOUT and ADCIN need to be shorted together the LTC2446 should be used because the MUXOUT and ADCIN are internally connected for opti mum performance Output Data Format TheLTC2446 LTC2447 serial output data stream is 32 bits long The first 3 bits represent status information indicat ing the sign and conversion state The next 24 bits are the conversion result MSB first The remaining 5 bits are sub LSBs beyond the 24 bit level that may be included in averaging or discarded without loss of resolution In the case of ultrahigh resolution modes more than 24 effective bits of performance are possible see Table 4 Under these conditions sub LSBs are included in the conversion result and represent useful information beyond the 24 bit level The third and fourth bit together are also used to indicate an underrange condition the differential input voltag
6. LTC2446 No Connect These pins can either be tied to ground or left floating MUXOUTP Pin 24 LTC2447 Positive Input Channel Multiplexer Output Used to drive the input to an external buffer amplifierforthe selected positive input signal IN ADCINP Pin 25 LTC2447 Positive ADC Input Tie to output of buffer amplifier driven by MUXOUTP ADCINN Pin 26 LTC2447 Negative ADC Input Tie to output of buffer amplifier driven by MUXOUTN MUXOUTN Pin 27 LTC2447 Negative Input Channel Multiplexer Output Used to drive the input to an external buffer amplifier for the selected negative input signal IN Vec Pin 28 Positive Supply Voltage Bypass to GND with a 10uF tantalum capacitor in parallel with a 0 1uF ceramic capacitor as close to the part as possible Vperg Pin 29 Vaerg Pin 30 Global Reference Input This differential reference input can be used for any input channel selected through a single bit in the digital input word SDI Pin 34 Serial Data Input This pin is used to select the speed 1x or 2x mode resolution input channel and reference input for the next conversion cycle At initial power up the default mode of operation is CHO CH1 Vnrro1 OSR of 256 and 1x mode The serial data input contains an enable bit which determines if a new channel speed is selected If this bit is low the following conversion remains at the same speed and selected channel The serial data input is applied to the device un
7. 10 170000 4096 720nV 510nV 227 234 54 9 10 163840 439 5 10 2050 492 fo 18300 265 0 340000 8192 530nV 375nV 232 24 275 10 327680 2197 14100 246 10 36600 132 fo 679000 16384 350nV 250nV 238 244 137 10 655360 109 9 10 8190 124 fy73100 66 10 1358000 32768 280nV 200nV 241 246 69 0 1310720 549 fo 16380 62 0 146300 33 10 2717000 ADC noise increases by approximately VZ when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256 The ADC noise at OSR 128 and OSR 64 include effects from internal modulator quantization noise Maximum Conversion Rate The maximum conversion rate is the fastest possible rate at which conversions can be performed First Notch Frequency This is the first notch in the SINC portion of the digital filter and depends on the fo clock frequency and the oversample ratio Rejection at this frequency and its multiples up to modulator sample rate of 1 8MHz exceeds 12088 This is 8 times the maximum conversion rate Effective Noise Bandwidth The LTC2446 LTC2447 has extremely good input noise rejection from the first notch frequency all the way out to the modulator sample rate typically 1 8MHz Effective noise bandwidth is a measure of how the ADC will reject wideband input noise up to the modulator sample rate The example on the following page shows how the noise rejection of the LTC2446 LTC2447 reduc
8. applications as flow gas chromatography multiple RTDs or bridges or universal data acquisition Average Input Current The LTC2446 switches the input and reference to a 2pF capacitor at afrequency of 1 8MHz Asimplified equivalent circuit is shown in Figure 16 The sample capacitor for the LTC2447 is 4pF and its average input current is externally buffered from the input source The average input and reference currents can be ex pressed in terms of the equivalent input resistance of the sample capacitor where Req 1 fsy 24467fa 22 APPLICATIONS INFORMATION RATIOMETRIC 4 ABSOLUTE vs VREFG LIC2446 LTC2447 LTC2446 VARIABLE SPEED lt SDI RESOLUTION 24 BIT AX ADC 24467 F15 Figure 15 Versatile 4 Way Multiplexer Measures Multiple Ratiometric Absolute Sensors IREF S dL Rew 5000 5pF TYP 2pF SAMPLE PARASITICS Rsw 5000 2 6 SWITCHING FREQUENCY fgyy 1 8MHz INTERNAL OSCILLATOR few frosc 5 EXTERNAL OSCILLATOR 24467 F16 Figure 16 LTC2446 Input Structure When using the internal oscillator fsy is 1 8MHz and the equivalent resistance is approximately 110 Input Bandwidth and Frequency Rejection The combined effect of the internal SINC digital filter and the digital and analog autocalibration circuits determines the LTC2446 LTC2447 input bandwidth and rejection char
9. be latched on the 32nd rising edge of SCK After the 32nd rising edge SDO goes HIGH EOC 1 indicating a new conversion is in progress SCK remains HIGH during the conversion EXTERNAL OSCILLATOR 500 ining USER SELECTABLE REFERENCES 4 TO Vee ANALOG J INPUTS Fo INTERNAL OSCILLATOR LTC2446 REFG REFO1 REFO1 REF67 801 REF67 SCK 3 WIRE SPI INTERFACE 065 31 7 CONVERSION gt DATA OUTPUT gt a SLEEP Figure 9 Internal Serial Clock Continuous Operation y lt CONVERSION 24467 F09 24467fa 20 LTC2446 LTC2447 APPLICATIONS INFORMATION Normal Mode Rejection and Antialiasing One of the advantages delta sigma ADCs offer over con ventional ADCs is on chip digital filtering Combined with a large oversampling ratio the LTC2446 LTC2447 signifi cantly simplify antialiasing filter requirements LTC2446 LTC2447 s speed resolution is determined by the over sample ratio OSR of the on chip digital filter The OSR ranges from 64 for 3 5kHz output rate to 32 768 for 6 9Hz in 1x mode output rate The value of OSR and the sample rate fs determine the filter characteristics ofthe device The first NULL of the digital filter is at fy and multiples of fy where fy fg OSR see Figure 10 and Table 6 The rejection at the frequency fy 14 is better than 80dB see Figure 11 0 20
10. otherwise specifications are at 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Voc Supply Voltage 4 5 5 5 V lec Supply Current Conversion Mode CS OV Note 7 e 8 11 mA Sleep Mode CS Voc Note 7 e 8 30 TIMING CHARACTERISTICS The denotes specifications which apply over the full operating temperature range otherwise specifications at TA 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS feosc External Oscillator Frequency Range 0 1 20 MHz tuo External Oscillator High Period e 25 10000 ns ti go External Oscillator Low Period 9 25 10000 ns tconv Conversion Time OSR 256 e 0 99 1 13 1 33 ms OSR 32768 e 126 145 170 ms External Oscillator Notes 10 13 e DET ms fisck Internal SCK Frequency Internal Oscillator Note 9 e 0 8 0 9 1 MHz External Oscillator Notes 9 10 fegsc 10 Hz 24467fa 4 AL WN LIC2446 LTC2447 TIMING CHARACTERISTICS The denotes specifications which apply over the full operating temperature range otherwise specifications are at TA 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Disck Internal SCK Duty Cycle Note 9 45 55 fescK External SCK Frequency Range Note 8 e 20 MHz ti EscK External SCK Low Period Note 8 25 ns tHESCK External SCK High Period Note 8 25 ns DOUT_ISCK Internal SCK 32 Bit Data Outp
11. reference from 0 1V to on each set of reference input pins The converter output noise is determined by the thermal noise of the front end circuits and as such its value in micro volts is nearly constant with reference voltage A decrease in reference voltage will not significantly improve the converter s effective resolution On the other hand a reduced reference voltage will improve the converter s overall INL performance Input Voltage Range The analog input is truly differential with an absolute common mode range for the CHO CH7 and COM input pins extending from GND 0 3V to 0 3V Outside these limits the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly Within these limits the LTC2446 LTC2447 24467fa 8 LIC2446 LTC2447 APPLICATIONS INFORMATION convert the bipolar differential input signal Viy IN where IN and IN are the selected input channels from FS 0 5 to FS 0 5 where REF REF REF and REF arethe selected references Outside this range the converter indicates the overrange orthe underrange condition using distinct output codes MUXOUT ADCIN There are two differences between the LTC2446 and the LTC2447 The first is the RMS noise performance For a given OSR the LTC2447 noise level is approximately V2 times lower 0 5 effective bits than that of the LTC2446
12. states The converter Operating cycle begins with the conversion followed by the low power sleep state and ends with the data output input See Figure 2 The 4 wire interface consists of serial data input 501 serial data output 500 serial clock SCK and chip select CS The interface timing opera tion cycle and data out format is compatible with Linear s entire family of AX converters Initially the LTC2446 LTC2447 perform a conversion Once the conversion is complete the device enters the POWER UP IN CHO CH1 REF VREFO1 REF VREF01 OSR 256 1X MODE CONVERT CHANNEL SELECT REFERENCE SELECT SPEED SELECT DATA OUTPUT 24467 F02 Figure 2 LTC2446 LTC2447 State Transition Diagram 24467fa LI WER 7 LTC2446 LTC2447 APPLICATIONS INFORMATION Sleep state While in this sleep state power consumption is reduced below 10 The part remains in the sleep state as long as CS is HIGH The conversion result is held indefinitely in a static shift register while the converter is in the sleep state Once CS is pulled LOW the device begins outputting the conversion result There is no latency in the conversion result while operating in the 1x mode The data output cor responds to the conversion just performed This result is shifted out on the serial data out pin SDO under the con trol of the serial clock SCK Data is updated on the falling edge of SCK allowing the user to
13. 00385 RTD has a resistance of 247 090 at 400 C The LTC2446 multiplexes rail to rail inputs directly to the ADC modulator and is suitable for low impedance resistive sources such as 1000 RTDs and 3500 strain gauges that are located close to the ADC In applications where the source resistance is high or the source is located more than 5cm to 10cm from the ADC the 1702447 with an LT1368 buffer is appropriate The 1762447 automatically removes offset drift and 1 f noise of the LT 1368 One consideration for single supply applications is that both ADC inputs should always be at least 100mV from the LT1368 s supply rails All of the applications shown in Figure 18 are designed to keep both analog inputs far enough away from ground and Vcc so that the LT1368 can operate on the same 5V supply as the LTC2447 Although the LT1368 has rail to rail inputs and outputs these amplifiers still need some degree of headroom to work at the resolution level of the LTC2447 For input signals running rail to rail the supply voltage of the LT1368 can be increased in order to provide the extra headroom The LTC2446 LTC2447 reference have no such limitations they are truly rail to rail and will even operate up to 300mV outside the supply rails Reference terminals may be connected directly to the ground plane orto a reference voltage that is decoupled to the ground plane with a 1uF or larger capacitor without any degradation of performance provided the co
14. 4 5 External SCK 3 Wire 1 0 External SCK SCK Figure 6 Internal SCK Single Cycle Conversion Internal 054 05 Figures 7 8 Internal SCK 3 Wire 1 0 Continuous Conversion Internal Continuous Internal Figure 9 24467 14 LIC2446 LTC2447 APPLICATIONS INFORMATION External Serial Clock Single Cycle Operation SPI MICROWIRE Compatible This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle see Figure 4 The serial clock mode is selected by the EXT pin To select the external serial clock mode EXT must be tied low The serial data output pin SDO is Hi Z as long as 65 is HIGH At any time during the conversion cycle CS may be pulled LOW in order to monitor the state of the converter While CS is pulled LOW EOC is output to the SDO pin 1 BUSY 1 while a conversion is in progress and EOC 0 BUSY 0 if the device is in the sleep state Independent of CS the device automatically enters the low power sleep state once the conversion is complete 4 5V TO 5 5V 1 1102446 USER SELECTABLE REFERENCES lt 0 1V TO ANALOG J INPUTS TEST EOC 1 2 3 4 5 6 When the device is in the sleep state EOC 0 its conversion result is held in an internal static shift regis ter The device remains in the sleep state until the first rising edge of SCK is seen Data is sh
15. 47 ABSOLUTE MAXIMUM RATINGS notes 1 2 Supply Voltage to 0 3 to 6V Digital Output Voltage to GND 0 3V to Vec 0 3V Analog Input Pins Voltage Operating Temperature Range to OND ere 0 3V to Vcc 0 3V 17624466 117024476 222 0 C to 70 C Reference Input Pins Voltage LTC2446I LTC2447 40 to 85 C 0 3V to Vcc 0 3V Storage Temperature Range 65 C to 125 C Digital Input Voltage to GND 0 3V to Veg 0 3V PACKAGE ORDER INFORMATION GND REFG Voc MUXOUTN ADCINN ADCINP MUXOUTP VREF67 31 GND 30 REFG 1g REFG 8 Vcc 7 NC 6 NC 5 NC i NC 23 Vngrez Th Weis BLO VREF67 CH7 CH6 VREF67 CH7 20 UHF PACKAGE UHF PACKAGE 38 LEAD 5mm x 7mm PLASTIC QFN 38 LEAD 5mm x 7mm PLASTIC QFN Tymax 125 C 34 C W Tumax 125 C Oja 34 C W EXPOSED PAD PIN 39 IS GND EXPOSED PAD PIN 39 IS GND MUST BE SOLDERED TO PCB MUST BE SOLDERED TO PCB ORDER PART QFN PART ORDER PART QFN PART NUMBER MARKING NUMBER MARKING LTC2446CUHF LTC2447CUHF LTC24461UHF 2446 LTC24471UHF 2441 Order Options Tape and Reel Add ZTR Lead Free Add PBF Lead Free Tape and Reel Add ZTRPBF Lead Free Part Marking http www linear com leadfree The
16. AD LAYOUT 5 00 0 10 0 75 0 05 3 15 0 10 2 SIDES gt lt 0 00 0 05 CODES Bi ous PIN 1 MARK C 1 SEE NOTE 6 I 1 ne C42 I I 1 I 7 00 0 10 1 5 15 0 10 2 SIDES 2 SIDES I I I I I Y 0 40 0 10 Y e 0 200 REF 0 25 0 05 lt 0 115 UH QFN 1203 0 200 REF 0 75 0 05 0 00 0 05 BOTTOM VIEW EXPOSED PAD Y J vy NOTE 1 DRAWING CONFORMS PACKAGE 4 DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE OUTLINE 0 220 VARIATION WHKD MOLD FLASH MOLD FLASH IF PRESENT SHALL NOT EXCEED 0 20mm ON ANY SIDE 2 DRAWING NOT TO SCALE 5 EXPOSED PAD SHALL BE SOLDER PLATED 3 ALL DIMENSIONS ARE IN MILLIMETERS 6 SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 24467fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable CAR However no responsibility is assumed for its use Linear Technology Corporation makes no represen J A ECHNOLOGY tation that the interconnection of its circuits as described herein will not infringe on existing patent rights LTC2446 LTC2447 APPLICATIONS INFORMATION 3500 LOAD CELL CHO FULL SCALE OUTPUT 10mV CH1 VnEFOT 18a Full Bridge Voltage Sense OMEGA 44018 LINEAR THERMISTOR COMPOSITE GND 18 Half Bridge Voltage Sense VREF45 FUJIKURA FPM 120PG 4k
17. CK mode of operation such that the SCK pin is used as a digital input The frequency of the clock signal driving SCK during the data output is fescx and is expressed in Hz Note 9 The converter is in internal SCK mode of operation such that the SCK pin is used as a digital output In this mode of operation the SCK pin has total equivalent load capacitance of Cj oap 20pF Note 10 The external oscillator is connected to the Fo pin The external oscillator frequency fegsc is expressed in Hz Note 11 The converter uses the internal oscillator Fg OV Note 12 Guaranteed by design and test correlation Note 13 There is an internal reset that adds an additional 1us typ to the conversion time PIN FUNCTIONS GND Pins 1 4 5 6 31 32 33 Ground Multiple ground pins internally connected for optimum ground current flow and Voc decoupling Connect each one of these pins to a common ground plane through a low impedance connection All seven pins must be connected to ground for proper operation BUSY Pin 2 Conversion in Progress Indicator This pin is HIGH while the conversion is in progress and goes LOW indicating the conversion is complete and data is ready It remains LOW during the sleep and data output states At the conclusion of the data output state it goes HIGH indicating a new conversion has begun EXT Pin 3 Internal External SCK Selection Pin This pin is used to select internal or external SCK for outputtin
18. EOC 1 SCK stays HIGH and a new conversion starts Typically CS remains LOW during the data output state However the data output state may be aborted by pulling CS HIGH anytime between the first and 32nd rising edge 4 5V TO 5 5V Vec LTC2446 USER SELECTABLE REFERENCES 4 0 1V TO Vec ANALOG J INPUTS tEOC TEST f 50 DON T 500 ere MOM BIT31 BIT30 BIT29 DON T CARE Y Y of SCK see Figure 8 On the rising edge of CS the device aborts the data output state and immediately initiates a new conversion This is useful for systems not requiring all 32 bits of output data aborting an invalid conversion cycle or synchronizing the start of a conversion Thirteen serial input data bits are required in order to properly program the speed resolution and input channel If the data output sequence is aborted prior to the 13th rising edge of SCK the new input data is ignored and the previously selected speed resolution and channelare used for the next conversion cycle If a new channel is being programmed the rising edge of CS must come after the 14th falling edge of SCK in order to store the data input sequence inn EXTERNAL OSCILLATOR INTERNAL OSCILLATOR 35 Fo 4 WIRE SPI INTERFACE lt leoc test TEST EOC DON T CARE E HAI T28 BIT27 BIT26 BIT25 Hi Z SLEEP DATA OUTPUT
19. TO 6k IMPEDANCE 5 cus FULL SCALE OUTPUT TO 140mV VnEF23 SELECT FOR V gt 2 140mV AT MAXIMUM BRIDGE RESISTANCE VREF23 GND 18b Full Bridge Current Sense 5V CH7 SENSOR 1000 AT 0 C 247 090 AT 400 C 100Q RTD CH6 VREF67 VREF67 24467 F18 GND 18d Half Bridge Current Sense Figure 18 Muxed Inputs References Enable Multiple Ratiometric Measurements with the Same Device RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1236A 5 Precision Bandgap Reference 5V 0 05 5ppm C Drift LT1461 Micropower Series Reference 2 5V 0 04 Max 3ppm C Max Drift LTC1799 Resistor Set SOT 23 Oscillator Single Resistor Frequency Set LTC2053 Rail to Rail Instrumentation Amplifier 10uV Offset with 50nV C Drift 2 5uVp p Noise 0 01Hz to 10Hz LTC2412 2 Channel Differential Input 24 Bit No Latency Ax ADC 0 16ppm Noise 2ppm INL 200 LTC2415 1 Channel Differential Input 24 Bit No Latency AX ADC 0 23ppm Noise 2ppm INL 2x Speedup LTC2414 LTC2418 4 8 Channel Differential Input 24 Bit No Latency A ADC 0 2ppm Noise 2ppm INL 200 LTC2430 LTC2431 1 Channel Differential Input 20 Bit No Latency AX ADC 0 56ppm Noise 3ppm INL 200 LTC2436 1 2 Channel Differential Input 16 Bit No Latency Ax ADC 800nVams Noise 0 12LBS INL 0 006LBS Offset 200uA LTC2440 1 Channel Differential Input High Speed Low Noise 2uVams No
20. acteristics The digital filter s response can be ad justed by setting the oversample ratio OSR through the SPI interface or by supplying an external conversion clock to the f pin Table 7 lists the properties of the LTC2446 LTC2447 with various combinations of oversample ratio and clock fre quency Understanding these properties is the key to fine tuning the characteristics of the LTC2446 LTC2447 to the application 24467fa 23 LTC2446 LTC2447 APPLICATIONS INFORMATION Table 7 Performance vs Over Sample Ratio MAXIMUM FIRST NOTCH EFFECTIVE 3dB OVER CONVERSION RATE FREQUENCY NOISE BW POINT Hz SAMPLE RMS RMS ENOB INTERNAL INTERNAL INTERNAL INTERNAL RATIO NOISE NOISE _ Vper 5V 9MHz EXTERNAL 9MHz EXTERNAL 9MHz EXTERNAL 9MHz EXTERNAL OSR LTC2446 LTC2447 LTC2446 LTC2447 CLOCK fo CLOCK fo CLOCK fo CLOCK 1 64 23 23V 17 17 35156 10 2560 28125 10 320 3148 fo 5710 1696 10 5310 128 4 5uV 35V 201 20 17578 fo 5120 14062 5 0 640 1574 10 2860 848 fo 10600 256 28v 2v 208 213 8789 fy10240 7031 3 1 1280 787 1 1140 424 f9 21200 512 tawv 213 218 4395 fy20480 35156 fy2560 394 1 2280 212 f9 42500 1024 t4uV tv 218 224 2197 10 40960 1757 8 10 5120 197 4570 106 10 84900 2048 11pv 750nV 221 229 109 9 fo 81920 8789 10 1020 984 fo 9140 53
21. ce input can be selected for any input channel not requiring ratiometric measurements ther mocouples voltages current sense etc The flexible input multiplexer allows single ended or differential in puts coupled with a slaved reference input or a universal reference input A proprietary delta sigma architecture results in absolute accuracy offset full scale linearity of 15ppm noise as low as 200nVpys and speeds as high as 8kHz Through a simple 4 wire interface ten speed resolution combina tions can be selected The first conversion following a speed resolution channel change or reference change is valid since there is no settling time between conversions enabling scan rates of up to 4kHz Additionally a 2x mode can be selected for any speed enabling output rates up to 8kHz with one cycle of latency 4J LTC and LT are registered trademarks of Linear Technology Corporation Protected by U S Patents including 6140950 6169506 6208279 6411242 6639526 TVPICRL APPLICATION Multiple Ratiometric Measurement System VARIABLE SPEED RESOLUTION 24 BIT _ AZADO LTC2446 Speed vs RMS Noise 100 Voc 5V VREF 5V Vin V 0 2x SPEED MODE e 24 NO LATENCY MODE 2 8uV AT 880Hz SS oe 280nV AT 6 9Hz 4 50 60Hz REJECTION e e RMS NOISE uV e 10 100 1000 10000 CONVERSION RATE Hz 24467fa 1 LTC2446 LTC24
22. der control of the serial clock SCK during the data output cycle The first conversion following a new channel speed is valid Fo Pin 35 Frequency Control Pin Digital input that controls the internal conversion clock When Fo is con nected to Vcc or GND the converter uses its internal oscillator running at 9MHz The conversion rate is deter mined by the selected OSR such that teony ms 40 OSR 170 fosc kHz The first digital filter null is located at 8 teony 7kHzat OSR 256 and 55Hz Simultaneous 50 60Hz at OSR 32768 This pin may be driven with a maximum external clock of 10 24MHz resulting in a maxi mum 8kHz output rate OSR 64 2x Mode CS Pin 36 Active Low Chip Select A LOW on this pin enables the SDO digital output and wakes up the ADC Following each conversion the ADC automatically enters the sleep mode and remains in this low power state as long as CS is HIGH ALOW to HIGH transition on CS during the Data Output aborts the data transfer and starts a new conversion 500 Pin 37 Three State Digital Output During the data output period this pin is used as serial data output When the chip select CS is HIGH CS the SDO pin is in a high impedance state During the conversion and sleep periods this pin is used as the conversion status output The conversion status can be observed by pulling CS LOW This signal is HIGH while the conversion is in progress and goes LOW once the conversion is comple
23. dge of the 14th SCK once the complete data input word is programmed The remaining data output se quence time can be used to allow the external buffer amplifier to settle BUSY The BUSY output Pin 2 is used to monitor the state of conversion data output and sleep cycle While the part is converting the BUSY pin is HIGH Once the conversion is complete BUSY goes LOW indicating the conversion is complete and data out is ready The part now enters the LOW power sleep state BUSY remains LOW while data is shifted out of the device and SDI is shifted into the device It goes HIGH at the conclusion of the data input output cycle indicating a new conversion has begun This rising edge may be used to flag the completion of the data read cycle SERIAL INTERFACE TIMING MODES The LTC2446 LTC2447 s 3 or 4 wire interface is SPI and MICROWIRE compatible This interface offers several flex ible modes of operation These include internal external serial clock 3 or 4 wire 1 0 single cycle conversion and autostart The following sections describe each of these serial interface timing modes in detail In all these cases the converter can use the internal oscillator Fg LOW or an external oscillator connected to the Fg pin Refer to Table 5 for a summary CONVERSION DATA CONNECTION SCK CYCLE OUTPUT AND CONFIGURATION SOURCE CONTROL CONTROL WAVEFORMS External SCK Single Cycle Conversion External CS and SCK CS and SCK Figures
24. e LTC2446 LTC2447 will abort any Serial data transfer in progress and start anew conversion cycle anytime a LOW to HIGH transition is detected at the CS pin after the converter has entered the data output state Serial Data Input SDI The serial data input SDI Pin 34 is used to select the speed resolution input channel and reference of the LTC2446 LTC2447 SDI is programmed by a serial input data stream under the control of SCK during the data output cycle see Figure 3 Initially after powering up the device performs a conver sion with CHO INT CH1 Vggrg1 REF Vnrro1 OSR 256 output rate nominally 880Hz and 1x speed mode no Latency Once this first conversion is complete the device enters the sleep state and is ready to outputthe conversion result and receive the serial data input stream programming the speed resolution input channel and reference for the next conversion At the conclusion of each conversion cycle the device enters this state In order to change the speed resolution reference or input channel the first 3 bits shifted into the device are 101 This is compatible with the programming sequence of the LTC2414 LTC2418 LTC2444 LTC2445 LTC2448 LTC2449 If the sequence is set to 000 or 100 the follow ing input data is ignored don t care and the previously selected speed resolution channel and reference remain valid forthe next conversion Combinations otherthan 101 100 and 000
25. e is below FS or an overrange condition the differential input voltage is above FS Bit 31 first output bit is the end of conversion EOC indicator This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW This bit is HIGH during the conversion and goes LOW when the conversion is complete Bit 30 second output bit is a dummy bit DMY and is always LOW Bit 29 third output bit is the conversion result sign indi cator SIG If Vix is gt 0 this bit is HIGH If Viy is lt 0 this bit is LOW Bit 28 fourth output bit is the most significant bit MSB of the result This bit in conjunction with Bit 29 also provides the underrange or overrange indication If both Bit 29 and Bit 28 are HIGH the differential input voltage is above FS If both Bit 29 and Bit 28 are LOW the differential input voltage is below FS The function of these bits is summarized in Table 1 Table 1 LTC2446 LTC2447 Status Bits BIT31 BIT30 BIT29 BIT28 INPUT RANGE EOC DMY SIG MSB Vin 2 0 5 VREF 0 0 1 1 OV lt Viy lt 0 5 VREF 0 0 1 0 0 5 Veer lt Vin lt OV 0 0 0 1 Vin lt 70 5 VREF 0 0 0 0 Bits 28 5 are the 24 bit conversion result MSB first Bit 5 is the least significant bit LSB Bits 4 0 are sub LSBs below the 24 bit level Bits 4 0 may be included in averaging or discarded without loss of resolution Data is shifted out of the SDO pi
26. ed to synchronize the data transfer Each bit of data is shifted out the SDO pin on the falling edge of the serial clock In the Internal SCK mode of operation the SCK pin is an output and the LTC2446 LTC2447 create their own serial clock In the External SCK mode of operation the SCK pin is used as input The internal or external SCK mode is selected by tying EXT Pin 3 LOW for external SCK and HIGH for internal SCK Serial Data Output SDO The serial data output pin SDO Pin 37 provides the result of the last conversion as a serial bit stream MSB first during the data output state In addition the SDO pin is used as an end of conversion indicator during the conversion and sleep states When CS Pin 36 is HIGH the SDO driver is switched to a high impedance state This allows sharing the serial interface with other devices If CS is LOW during the convert or sleep state SDO will output EOC If CS is LOW during the conversion phase the EOC bit appears HIGH on the SDO pin Once the conversion is complete EOC goes LOW The device remains in the sleep state until the first rising edge of SCK occurs while CS LOW Chip Select Input CS The active LOW chip select CS Pin 36 is used to test the conversion status and to enable the data output transfer as described in the previous sections In addition the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed Th
27. eference selection The remaining bits ODD A1 A0 determine which channel is selected 24467fa LI MVR 11 LTC2446 LTC2447 APPLICATIONS INFORMATION Table 3 Channel Selection for the LTC2446 LTC2447 MUX ADDRESS CHANNEL INPUT REFERENCE INPUT ODD SGL SIGN GLBL A1 0 0 1 2 3 4 5 6 7 01 01 23 237 45 45 67 67 GF 67 0 0 0 0 0 REF REF 0 0 0 0 1 REF 0 0 0 1 0 REF 0 0 01 1 REF 0 1 0 0 0 REF REF 0 1 0 0 1 REF 0 1 0 1 0 REF 0 1 0 1 1 REF 1 0 0 0 0 REF REF 1 0 0 0 1 REF 1 0 0 1 0 REF 1 0 0 1 1 REF 1 1 0 0 0 REF REF 1 1 0 0 1 REF 1 1 0 1 0 REF 1 1 01 1 REF 0 0 1 0 0 REF REF 0 0 1 0 1 REF 0 0 1 10 REF REF 0 0 1 1 1 IN INT REF REF 0 1 1 0 0 IN IN REF REF 0 1 1 0 1 IN IN REF REF 0 1 1 1 0 INT IN REF 0 1 1 1 1 INT IN REF REF 1 0 1 00 IN REF 1 0 1 0 1 IN REF REF 1 0 1 1 0 IN REF 1 0 1 1 1 IN REF REF 1 1 1 0 0 IN REF 1 1 1 0 1 IN 1 1 1 1 0 IN REF 1 1 1 1 1 IN REF Defau
28. es the effective noise of an amplifier driving its input Example If an amplifier e g LT1219 driving the input of an LTC2446 LTC2447 has wideband noise of 33nV VHz band limited to 1 8MHz the total noise entering the ADC input is 33nV VHz V1 8MHz 44 3uV When the ADC digitizes the input its digital filter rejects the wideband noise from the input signal The noise reduction depends on the oversample ratio which defines the effec tive bandwidth of the digital filter At an oversample of 256 the noise bandwidth of the ADC is 787Hz which reduces the total amplifier noise to 33nV VHz N787Hz 0 931 The total noise is the RMS sum of this noise with the 2uV noise of the ADC at OSR 256 V 0 93uV 2 2uV 2 2 2yV Increasing the oversample ratio to 32768 reduces the noise bandwidth of the ADC to 6 2Hz which reduces the total amplifier noise to 33nV VHz N6 2Hz 82nV The total noise is the RMS sum of this noise with the 200nV noise of the ADC at OSR 32768 N 82nV 200nV 216nV In this way the digital filter with its variable oversampling ratio can greatly reduce the effects of external noise sources 24467fa 24 LTC2446 LTC2447 APPLICATIONS INFORMATION Automatic Offset Calibration of External Buffers Amplifiers LTC2447 enables an external amplifier to be inserted between the multiplexer output and the ADC input This enables one external buffer amplifier circ
29. g inputting data If EXT is tied low the device is in the external SCK mode and data is shifted out of the device under the control of a user applied serial clock If EXT is tied high the internal serial clock mode is selected The device generates its own SCK signal and outputs this on the SCK pin A framing signal BUSY Pin 2 goes low indicating data is being output COM Pin 7 The common negative input for all single ended multiplexer configurations The voltage on CH0 CH7 and COM pins can have any value between GND 24467fa LTC2446 LTC2447 PIN FUNCTIONS 0 3V to 0 3V Within these limits the two selected inputs and provide a bipolar input range Viy IN IN from 0 5 Vere to 0 5 Var Outside this input range the converter produces unique over range and under range output codes CHO to CH7 Pins 8 9 12 13 16 17 20 21 Analog Inputs May be programmed for Single ended or Differen tial mode Vnero1 Pin 11 Pin 10 Pin 15 Vneros Pin 14 Vreras Pin 19 Pin 18 Vrere7 Pin 23 VREF67_ Pin 22 Differential Reference Inputs The voltage on these pins can be anywhere between OV and Vcc as long as the positive reference input Vero1 Vngr23 Vrer45 Vngre7 is greater than the corresponding negative reference input VREF017 Vngr23 Vreras gt by at least 100mV NC Pins 24 25 26 27
30. g the user interface or isolation barrier The external serial clock mode is selected by tying EXT LOW Since CS is tied LOW the end of conversion EOC can be continuously monitored at the SDO pin during the convert and sleep states Conversely BUSY Pin 2 may be used to monitor the status of the conversion cycle EOC or BUSY may be used as an interrupt to an external controller 4 5V TO 5 5V 1 Voc Fo LTC2446 USER SELECTABLE REFERENCES 4 0 1V TO Vee ANALOG INPUTS indicating the conversion result is ready EOC 1 BUSY 1 while the conversion is in progress and EOC 0 BUSY 0 once the conversion enters the low power sleep state On the falling edge of EOC BUSY the conversion result is loaded into an internal static shift register The device remains in the sleep state until the first rising edge of SCK Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK EOC can be latched on the first rising edge of SCK On the 32nd falling edge of SCK SDO and BUSY go HIGH EOC 1 indicating a new conversion has begun nnn EXTERNAL OSCILLATOR INTERNAL OSCILLATOR SCK EXTERNAL DON T 1 en om GLBL 0583 0582 0581 OSRO TWOX DON T CARE BUSY CONVERSION DATA OUTPUT CONVERSION 24467 F06 Figure 6 External Serial Clock CS 0 Operation 3 Wire
31. has shifted the sample rate remains constant As a result of constant modulator sampling rate the linearity 1 8MHz NORMAL MODE REJECTION dB REJECTION gt 1204 LL IN 1000000 DIFFERENTIAL INPUT SIGNAL FREQUENCY Hz 24467 F12 2000000 Figure 12 LTC2446 LTC2447 Normal Mode Rejection Internal Oscillator 24467fa LI MVR 21 LTC2446 LTC2447 APPLICATIONS INFORMATION offset and full scale performance remain unchanged as does the first multiple of fs The sample rate fs and NULL fy may also be adjusted by driving the Fo pin with an external oscillator The sample rate is fs feosc 5 where feosc is the frequency of the clock applied to Fo Combining a large OSR with a reduced sample rate leads to notch frequencies fy near DC while maintaining simple antialiasing requirements A 100kHz clock applied to Fo results in a NULL at 0 6Hz plus all harmonics up to 20kHz see Figure 13 This is useful in applications requiring digitalization of the DC component of a noisy input signal and eliminates the need of placing a 0 6Hz filter in front of the ADC NORMAL MODE REJECTION dB 2 80 100 120 140 2 4 6 8 10 DIFFERENTIAL INPUT SIGNAL FREQUENCY Hz 24467 Figure 13 LTC2446 LTC2447 Normal Mode Rejection External Oscillator at 90kHz An external oscillator operating from 100kHz to 20MHz can be i
32. ifted out the SDO pin oneach falling edge of SCK This enables external circuitry to latch the output on the rising edge of SCK EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK On the 32nd falling edge of SCK the device begins a new conversion SDO goes HIGH EOC 1 and BUSY goes HIGH indicating a conversion is in progress At the conclusion of the data cycle CS may remain LOW and EOC monitored as an end of conversion interrupt Alternatively CS may be driven HIGH setting SDO to Hi Z and BUSY monitored for the completion of a conversion unn EXTERNAL OSCILLATOR INTERNAL OSCILLATOR 4 WIRE SPI INTERFACE SCK EXTERNAL PLETE LPL LE LALA LE LG LEELA LEE TI CONVERSION SLEEP lt DATA OUTPUT CONVERSION 24467 F04 Figure 4 External Serial Clock Single Cycle Operation 24467fa 15 LTC2446 LTC2447 APPLICATIONS INFORMATION As described above CS may be pulled LOW at any time in order to monitor the conversion status on the SDO pin Typically CS remains LOW during the data output state However the data output state may be aborted by pulling CS HIGH anytime between the fifth falling edge and the 32nd falling edge of SCK see Figure 5 On the rising edge of CS the device aborts the data output state and imme diately initiates a new conversion Thirteen serial input data bi
33. ise at 880Hz 200nVnys Noise at 6 9Hz 24 Bit No Latency AX ADC 0 000596 INL Up to 3 5kHz Output Rate LTC2444 LTC2445 8 16 Channel Differential Input High Speed Low Noise 2uVprms Noise at 1 76 2 200nVams Noise at 13 8Hz LTC2448 LTC2449 24 Bit No Latency AX ADC 0 000596 INL Up to 8kHz Output Rate Linear Technology Corporation 1630 McCarthy Blvd Milpitas CA 95035 7417 408 432 1900 FAX 408 434 0507 e www linear com 24467fa LT LT 0905 REV A PRINTED IN USA TECHNOLOGY LINEAR TECHNOLOGY CORPORATION 2004
34. ive Full Scale Error Drift 2 5V lt lt Voc REF GND 0 2 ppm of 2 IN 0 25 IN 0 75 REF Total Unadjusted Error 5V lt lt 5 5V 2 5V GND Vino 1 25V 15 ppm of VREF 5V lt Vec lt 5 5V 5V REF GND 2 5V 15 ppm of VREF 2 5V GND Viney 1 25V Note 6 15 ppm of VREF Input Common Mode Rejection 2 5V lt REF lt Voc REF GND 120 dB GND lt 1 lt A NALOG INPUT AND REFERENCE The denotes specifications which apply over the full operating temperature range otherwise specifications are at T 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN Absolute Common Mode IN Voltage e GND O0 3V Voc 0 3V V Absolute Common Mode Voltage e GND 0 3V Voc 0 3V V VIN Input Differential Voltage Range Vnrp 2 VREF 2 V IN REF Absolute Common Mode REF Voltage e 0 1 Vec V REF Absolute Common Mode REF Voltage GND Vcc 0 1V V VREF Reference Differential Voltage Range 0 1 Voc V REF REF CS IN Sampling Capacitance 2 pF stiN IN Sampling Capacitance 2 pF Cs REF REF Sampling Capacitance 2 pF Cs REF Sampling Capacitance 2 pF Ipc LEAK IN IN Leakage Current Inputs and Reference CS Vec IN GND IN GND e 15 1 15 nA REF REF REF 5V REF GND ISAMPLE IN IN Average Input Reference Curren
35. lt at power up 24467fa 12 AT NEAR LIC2446 LTC2447 APPLICATIONS INFORMATION Table 4 LTC2446 LTC2447 Speed Resolution Selection CONVERSION RATE INTERNAL EXTERNAL RMS RMS 9MHz 10 24MHz NOISE NOISE ENOB ENOB OSR3 0582 OSR1 OSRO TWOX CLOCK CLOCK 1702446 LTC2447 LTC2446 LTC2447 OSR LATENCY Keep Previous Speed Resolution 3 52kHz 4kHz 23uV 23uV 17 17 64 None 1 76kHz 2kHz 4 4uV 3 5uV 20 1 20 1 128 None 880Hz 1kHz 2 8uV 2uV 20 8 21 3 256 None 440Hz 500Hz 2uV 1 4uV 21 3 21 8 512 None 220Hz 250Hz 1 4uV 1uV 21 8 22 4 1024 None 110Hz 125Hz 11uV 750nV 22 1 22 9 2048 None 55Hz 62 5Hz 720nV 510nV 22 7 23 4 4096 None 27 5Hz 31 25Hz 530nV 375nV 23 2 24 8192 None 13 75Hz 15 625Hz 350nV 250nV 23 8 244 16384 None 6 875Hz 7 8125Hz 280nV 200nV 241 24 6 32768 none Keep Previous Speed Resolution 7 04kHz 8kHz 23uV 23uV 17 17 64 1 Cyc 3 52kHz AkHz 4 4uV 3 5uV 20 1 20 1 128 1 Cyc 1 76kHz 2kHz 2 8uV 2uV 20 8 21 3 256 1 Cyc 880Hz 1kHz 2uV 1 4uV 21 3 21 8 512 1 Cyc 440Hz 500Hz 1 4uV 1uV 21 8 22 4 1024 1 Cyc 220Hz 250Hz 11uV 750nV 22 1 22 9 2048 1 Cyc 110Hz 125Hz 720nV 510nV 22 7 23 4 4096 1 Cyc 55Hz 62 5Hz 530nV 375nV 23 2 24 8192 1 Cyc 27 5Hz 31 25Hz 350nV 250nV 23 8 244 16384 1 Cyc 13 75Hz 15 625Hz 280nV 200nV 24 1 24 6 32768 10yc gt gt gt gt gt
36. ltiple reference inputs of the LTC2447 greatly simplify sensor interfacing Each of the four references is fully differential and has a differential range of 100mV to 5V This opens up many possibilities for sensing voltages and currents eliminating much of the analog signal conditioning cir cuitry required for interfacing to conventional ADCs 1 DIFFERENTIAL 1 REFERENCE 10 INPUTS 7 gt l CHO CH6 9 1 C OFFSETS AND 1 f NOISE OF EXTERNAL SIGNAL CONDITIONING CIRCUITS ARE AUTOMATICALLY CANCELLED LTC2447 LT1368 REQUIRES 0 1uF OUTPUT COMPENSATION CAPACITOR 24467 17 Figure 17 External Buffers Provide High Impedance Inputs and Amplifier Offsets are Cancelled 24467fa 25 LTC2446 LTC2447 APPLICATIONS INFORMATION Figure 18ais astandard 3500 voltage excited strain gauge with sense wires for the excitation voltage REFO1 and REF01 sense the excitation voltage atthe gauge compen sating for voltage drop along the high current excitation supply wires This can be a significant error as the exci tation current is 14mA when excited with 5V Reference loading capacitors atthe ADC are necessary to average the reference current during sampling Both ADC inputs are always close to mid reference and hence close to mid supply when using 5V excitation Figure 18b is anovel way to interface the LTC2447 to abridge thatis specified for constant c
37. mplemented using the LTC1799 resistor set SOT 23 oscillator see Figure 14 By floating pin 4 DIV of the LTC1799 the output oscillator frequency is 10k 10MHz Ds The normal mode rejection characteristic shown in Figure 13 is achieved by applying the output of the LTC1799 with 100k to the Fo pin on the LTC2446 LTC2447 with SDI tied HIGH OSR 32768 Multiple Ratiometric and Absolute Measurements The LTC2446 LTC2447 combine a high precision high speed delta sigma converter with a versatile front end 4 5V TO 5 5V USER SELECTABLE REFERENCES 4 0 1V TO Vec ANALOG INPUTS 24467 F14 Figure 14 Simple External Clock Source multiplexer The unique no latency architecture allows Seamless changes in both input channel and reference while the absolute accuracy ensures excellent matching between both analog input channels and reference chan nels Any set of inputs differential or single ended can perform a conversion with one of two references For Bridges RTDs and other ratiometric devices each set of channels can perform a conversion with respect to a unique reference voltage For Thermocouples voltage sense current sense and other absolute sensors each set of channels can perform a conversion with respect to a single global reference voltage see Figure 15 This allows usersto measure both multiple absolute and multiple ratio metric sensors with the same device in such
38. n under control of the serial clock SCK see Figure 3 Whenever CS is HIGH SDO remains high impedance and SCK is ignored In order to shift the conversion result out of the device CS must first be driven LOW EOC is seen at the SDO pin of the device once CS is pulled LOW changes real time from HIGH to LOW at the completion of a conversion This signal may be used as an interrupt for an external microcontroller Bit 31 EOC can be captured on the first 24467fa 9 LTC2446 LTC2447 APPLICATIONS INFORMATION BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 BIT25 BIT24 BIT23 BIT22 BIT21 BIT20 BIT 19 BIT 0 BUSY ____ 24467 F03 Figure 3 SDI Speed Resolution Channel Selection and Data Output Timing rising edge of SCK Bit 30 is shifted out of the device on the first falling edge of SCK The final data bit Bit 0 is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse On the falling edge of the 32nd SCK pulse SDO goes HIGH indicating the initiation of anew conversion cycle This bit serves as EOC Bit 31 for the next conversion cycle Table 2 summarizes the output data format As longas the voltage on the IN and IN pins is maintained within the 0 3V to Vcc 0 3V absolute maximum Operating range a conversion result is generated for any differential input voltage Viy from FS 0 5 to FS 0 5 For differential input vol
39. nnection is less than bcm from the LTC2446 LTC2447 If the reference terminals are sensing a point more than 5cm to 10cm away from the ADC the reference pins should be decoupled to the ground plane with 1uF capacitors The reference terminals can also sense a resistive source with a resistance up to 500Q located close to the LTC2446 LTC2447 however parasitic capacitance must be kept to a minimum If the sense point is more than 5cm from the ADC then it should be buffered The LT1368 is also an outstanding reference buffer While offsets are not cancelled as in the ADC input circuit the 200mV offset and 2mV C driftwill not degradethe performance of most sensors The LT1369 is a quad version of the LT1368 and can serve as the input buffer for an LTC2447 and two reference buffers 24467fa 26 LIC2446 LTC2447 PACKAGE DESCRIPTION UHF Package 38 Lead Plastic QFN 5mm x 7mm Reference LTC DWG 05 08 1701 0 70 0 05 A 1 A 5 50 0 05 E S DES 4 10 0 05 2 SIDES Lr co 3 15 0 05 SIDES p ci L Y PACKAGE Y OUTLINE 0 25 0 05 lt 0 50BSC lt x 5 20 0 05 2 SIDES I 6 10 0 05 2 SIDES I M 1 50 0 05 2 SIDES gt RECOMMENDED SOLDER P
40. nternal reset state when the power supply voltage Vcc drops below approximately 2 2V This feature guarantees the integrity of the conversion result and of the serial inter face mode selection When the Vcc voltage rises above this critical threshold the converter creates an internal power on reset POR signal with a duration of approximately 0 5ms The POR signal clears all internal registers The conversion imme diately following a POR is performed on the input channel IN CH1 REF Vpefo1 at an OSR 256 in the 1x mode Following the POR signal the LTC2446 LTC2447 start a normal conversion cycle and follow the succession of states described above The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range 4 5V to 5 5V before the end of the POR time interval Reference Voltage Range These converters accept truly differential external refer ence voltages Each set of five reference inputs may be independently driven to any common mode voltage over the entire supply range of the device GND to Vcc For correct converter operation each positive reference pin REF Vngro1 VREF23 VnEr45 VnEre7 VRErg must be more positive than its corresponding negative refer ence pin REF Vngroi VEr23 VnEF45 VREF67 Vrerg by at least 100mV The LTC2446 LTC2447 can accept a differential
41. o prevent the device from exiting the low power sleep state CS must be pulled HIGH before the first rising edge of SCK In the internal SCK timing mode SCK goes HIGH and the device begins outputting data at time teoctest after the falling edge of CS if EOC 0 or teoctest after goes LOW if CS is LOW during the falling edge of EOC The value of teoctest is 500ns If CS is pulled HIGH before time tegctest the device remains in the sleep state The conversion result is held in the internal static shift register nnn EXTERNAL OSCILLATOR INTERNAL OSCILLATOR 4 WIRE SPI INTERFACE BUSY CONVERSION SLEEP gt lt DATA OUTPUT gt CONVERSION 244676 F07 Figure 7 Internal Serial Clock Single Cycle Operation 24467fa 18 LTC2446 LTC2447 APPLICATIONS INFORMATION If CS remains LOW longer than tegctest the first rising edge of SCK will occur and the conversion resultis serially shifted out of the SDO pin The data output cycle begins on this first rising edge of SCK and concludes after the 32nd rising edge Data is shifted out the SDO pin on each falling edge of SCK The internally generated serial clock is output to the SCK pin This signal may be used to shift the conversion result into external circuitry EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK After the 32nd rising edge SDO goes HIGH
42. of the 3 control bits should be avoided If the first 3 bits shifted into the device are 101 then the following 5 bits select the input channel reference for the following conversion see Table 3 The next 5 bits select the speed resolution and mode 1x no Latency 2x double output rate with one conversion latency see Table 4 If these 5 bits are set to all 0 s the previous speed remains selected for the next conversion This is useful in applica tions requiring a fixed output rate resolution but need to change the input channel or reference In this case the timing and input sequence is compatible with the LTC2414 LTC2418 When an update operation is initiated the first 3 bits are 101 the next 5 bits are the channel reference address The first bit SGL determines if the input selection is differen tial SGL 0 or single ended SGL 1 For SGL 0 two adjacent channels can be selected to form a differential input For SGL 1 one of 8 channels is selected as the positive input The negative input is COM for all single ended operations The global bit GLBL is used to determine which reference is selected GLBL 0 selects the individual reference slaved to a given channel Each set of channels has a corresponding differential input refer ence If GLBL 1 a global reference 15 selected The global reference input may be used for any input channel selected Table 3 shows a summary of input r
43. reliably latch data on the rising edge of SCK see Figure 3 The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH The device automatically initiates a new conversion and the cycle repeats Through timing control of the CS SCK and EXT pins the LTC2446 LTC2447 offer several flexible modes of opera tion internal or external SCK These various modes do not require programming configuration registers more over they do not disturb the cyclic operation described above These modes of operation are described in detail in the Serial Interface Timing Modes section Ease of Use The LTC2446 LTC2447 data output has no latency filter settling delay or redundant data associated with the conversion cycle while operating in the 1x mode There is a one to one correspondence between the conversion and the output data Therefore multiplexing multiple analog voltages and references is easy Speed resolution adjustments may be made seamlessly between two conversions without settling errors The LTC2446 LTC2447 perform offset and full scale cali brations every conversion cycle This calibration is trans parent to the user and has no effect on the cyclic operation described above The advantage of continuous calibration is extreme stability of offset and full scale readings with re specttotime supply voltage change and temperature drift Power Up Sequence The LTC2446 LTC2447 automatically enter an i
44. t Varies See Applications Section nA REF REF During Sampling MUX Break Before Make 50 ns QIRR MUX Off Isolation Vin 2Vp p DC to 1 8MHz 120 dB 24467fa 3 LTC2446 LTC2447 DIGITAL INPUTS AND DIGITAL OUTPUTS The denotes specifications which apply over the operating temperature range otherwise specifications are at 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Vin High Level Input Voltage 4 5V Vec lt 5 5V e 2 5 V CS Fo Low Level Input Voltage 4 5V lt Voc lt 5 5V e 0 8 V CS Fo Vin High Level Input Voltage 4 5V lt Voc lt 5 5V Note 8 e 2 5 V SCK Low Level Input Voltage 4 5V lt Voc lt 5 5V Note 8 0 8 V lin Digital Input Current OV lt Vin lt 10 10 CS Fo EXT SOI lin Digital Input Current OV lt Vin lt Vcc Note 8 e 10 10 SCK Cin Digital Input Capacitance 10 pF CS Fo Cin Digital Input Capacitance Note 8 10 pF SCK VoH High Level Output Voltage 800uA Voc 0 5V V 5 0 BUSY VoL Low Level Output Voltage 1 6mA 0 4V V SDO BUSY Vou High Level Output Voltage lp 800uA Note 9 Vcc 0 5V V SCK VoL Low Level Output Voltage lp 1 6mA Note 9 0 4V V loz e 10 10 Hi Z Output Leakage SDO POWER REQUIREMENTS The denotes specifications which apply over the full operating temperature range
45. tages greater than Table 2 LTC2446 LTC2447 Output Data Format FS the conversion result is clamped to the value corre sponding to the FS 1L SB For differential input voltages below FS the conversion result is clamped to the value corresponding to FS 1LSB SERIAL INTERFACE PINS The LTC2446 LTC2447 transmit the conversion results and receive the start of conversion command through a synchronous 3 or 4 wire interface During the conver sion and sleep states this interface can be used to assess the converter status and during the data output state it is used to read the conversion result and program the speed resolution and input channel Differential Input Voltage Bit 31 Bit30 Bit29 Bit28 Bit27 Bit 26 Bit 25 sus Bit 0 Vin EOC DMY SIG MSB 2 0 5 0 0 1 1 0 0 0 0 0 5 Vper 1LSB 0 0 1 0 1 1 1 1 0 25 Vage 0 0 1 0 1 0 0 0 0 25 1LSB 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 s 0 1LSB 0 0 0 1 1 1 1 1 0 25 0 0 0 1 1 0 0 0 0 25 Vper 1158 0 0 0 1 0 1 1 1 0 5 Vnge 0 0 0 1 0 0 0 0 lt 0 5 0 0 0 0 1 1 1 1 differential input voltage Viy IN IN The differential reference voltage REF REF 10 LIC2446 LTC2447 APPLICATIONS INFORMATION Serial Clock Input Output SCK The serial clock signal present on SCK Pin 38 is us
46. te SCK Pin 38 Bidirectional Digital Clock Pin In internal serial clock operation mode SCK is used asa digital output for the internal serial interface clock during the data output period In the external serial clock operation mode SCK is used as the digital input for the external serial interface clock during the data output period The serial clock Operation mode is determined by the logic level applied to the EXT pin Exposed Pad Pin 39 Ground The exposed pad on the bottom of the package must soldered to the PCB ground For Prototyping purposes this pin may remain floating 24467fa 6 LIC2446 LTC2447 FUNCTIONAL BLOCK DIAGRAM Voc INTERNAL Veer OSCILLATOR VnEF67 5 lt 19 VREF67 INT EXT e Vntrc REFG_ e VREFG m CHO CH1 amp DIFFERENTIAL 4 50 3RD ORDER SERIAL 9 SCK CH7 AX MODULATOR INTERFACE spo COM 4 5 GND L 24467 01 Figure 1 Functional Block Diagram TEST CIRCUITS Veo 1 69k SDO SDO 1 69k I CLoap 20pF Ci oap 20pF Hi Z TO Hi Z TO VoL VoL TO TO VoL TO Hi Z 24467 1003 VoL TO Hi Z APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle LTC2446 LTC2447 are multichannel multireference high speed delta sigma analog to digital converters with an easy to use 3 or 4 wire serial interface see Figure 1 Their operation is made up of three
47. temperature grade is identified by a label on the shipping container Consult LTC Marketing for parts specified with wider operating temperature ranges 24467fa LTC2446 LTC2447 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range otherwise specifications are at 25 C Notes 3 4 PARAMETER CONDITIONS MIN MAX UNITS Resolution No Missing Codes 0 1V lt Vggr lt Vcc 0 5 Vngr lt 0 5 Note 5 e 24 Bits Integral Nonlinearity Voc 5V SV REF GND Viycy 2 5V Note 6 5 15 ppm of VREF 2 5V GND Vincm 1 25V Note 6 3 ppm of VREF Offset Error 2 5V lt REFt lt Voc REF GND e 2 5 5 uV GND lt IN IN lt Vec Note 12 Offset Error Drift 2 5V lt REF lt Voc REF GND 20 nV C GND lt IN IN lt Positive Full Scale Error REF 5V REF GND IN 3 75V IN 1 25V e 10 50 ppm of VREF REF 2 5V GND IN 1 875V 0 625V e 10 50 ppm of VREF Positive Full Scale Error Drift 2 5V lt REFt lt Voc REF GND 0 2 ppm of IN 0 75REF INT 0 25 Negative Full Scale Error 5V REF GND IN 1 25V IN 3 75V e 10 50 ppm of VREF REF 2 5V GND IN 0 625V IN 1 875V e 10 50 ppm of VREF Negat
48. tput rate by 2x The resolution noise remains the same as the 1x mode If a new channel reference is selected the conversion result is valid for all conversions after the first conversion one cycle latency If a new speed resolution is selected the first conversion result is valid but the resolution noise is a function of the running average All subsequent conver sion results are valid If the mode is changed from either 1 to 2x or 2x to 1x without changing the resolution or channel the first conversion result is valid If an external buffer amplifier circuit is used for the LTC2447 the 2x mode can be used to increase the settling time ofthe amplifier between readings While operating in the 2x mode the multiplexer output input to the external buffer amplifier is switched at the end of each conversion cycle Prior to concluding the data out in cycle the analog multiplexer output is switched This occurs at the end of Table 5 LTC2446 LTC2447 Interface Timing Modes the conversion cycle just prior to the data output cycle for auto calibration The time required to read the conver sion enables more settling time for the external buffer amplifier The offset offset drift of the external amplifiers are automatically removed by the converter s auto calibra tion sequence for both the 1x and 2x speed modes While operating in the 1x mode if a new input channel reference is selected the multiplexer is switched on the falling e
49. ts are required in order to properly program the speed resolution and input reference channel If the data 4 5V 0 5 5V Im Vcc Fo LTC2446 USER SELECTABLE REFERENCES 4 0 1V TO Vec SCK EXTERNAL 50 DON T CARE 1 as CONVERSION SLEEP DATA OUTPUT gt CONVERSION lt output sequence is aborted priorto the 13th rising edge of SCK the new input data is ignored and the previously selected speed resolution and channel are used for the next conversion cycle This is useful for systems not requiring all 32 bits of output data aborting an invalid conversion cycle or synchronizing the start of a conver sion If a new channel is being programmed the rising edge of CS must come after the 14th falling edge of SCK in order to store the data input sequence EXTERNAL OSCILLATOR INTERNAL OSCILLATOR TEST EOC DON T CARE DON T CARE BIT31 30 BIT29 BIT28 BIT27 BIT26 25 DATA OUTPUT gt lt CONVERSION 7 SLEEP 24467 FOS Figure 5 External Serial Clock Reduced Output Data Length 24467fa 16 LIC2446 LTC2447 APPLICATIONS INFORMATION External Serial Clock 3 Wire 1 0 This timing mode utilizes a 3 wire serial 1 0 interface The conversion result is shifted out of the device by an exter nally generated serial clock SCK signal see Figure 6 CS may be permanently tied to ground simplifyin
50. uit to be shared between all nine analog inputs eight single ended or four differential The 1702447 performs an internal offset calibration every conversion cycle in order to remove the offset and drift of the ADC This calibration is performed through a combination of front end switching and digital processing Sincethe external amplifier is placed between the multiplexer and the ADC it is inside the correction loop This results in automatic offset correction and offset drift removal of the external amplifier The LT1368 is an excellent amplifier for this function It has rail to rail inputs and outputs and it operates on a single 5V supply Its open loop gain is 1M and its input bias current is 10nA It also requires at least a 0 1uF load capacitor for compensation It is this feature that sets it apart from other amplifiers the load capacitor attenuates sampling glitches from the LTC2447 ADCIN terminal allowing it to achieve full performance of the ADC with high impedance at the multiplexer inputs Another benefit of the LT1368 is that it can be powered from supplies equal to or greater than that of the ADC This can allow the inputs to span the entire absolute maximum of GND 0 3V to 0 3V Using a positive supply of 7 5V to 10V and a negative supply of 2 5 to 5V gives the amplifier plenty of headroom over the LTC2447 input range Interfacing Sensors to the LTC2447 Figure 18 shows a few of the ways that the mu
51. urrent excitation The Fujikura FPM 120PG is a 120psig pressure sensor that is not trimmed for absolute accuracy but is temperature compen sated for low drift when excited constant currentsource The LTC2447 s fully differential reference allows sensing the excitation current with a resistor in series with the bridge excitation Changes in ambient temperature and supply voltage will cause the current to vary but the LTC2447 compensates by using the current sense voltage as its reference The input common mode will be slightly higher than mid reference but still far enough away from the positive supply to eliminate concerns about the buffer amplifiers headroom Figure 18c isan Omega 44018 linear outputthermistor Two fixed resistors linearize the output from the thermistors The recommended 57000 series resistor is broken up into two 2850Q resistors to give a differential output centered around mid reference This ensures that the buffer ampli fiers have enough headroom at the negative supply Note that the excitation is 3V the maximum recommended by the manufacturer to prevent self heating errors The LTC2447 senses this reference voltage Figure 18d shows a standard 100Q platinum RTD This circuit shows how to use the 1702447 to make a direct resistance measurement where the output code is the RTD resistance divided by the reference resistance A 500Q sense resistor allows measurement of resistance up to 2500 A standard 0
52. ut Time Internal Oscillator Notes 9 11 41 6 35 3 30 9 ys External Oscillator Notes 9 10 e 320 fgosc S DOUT_ESCK External SCK 32 Bit Data Output Time Note 8 32 fEscK 5 t CS 4 to SDO Low Z Note 12 e 0 25 ns to CS T to SDO High Z Note 12 0 25 ns t3 CS J to SCK 4 Note 9 5 us CS J to SCK Notes 8 12 25 ns tkamax SCK J to SDO Valid 25 5 SDO Hold After SCK 4 Note 5 15 5 ts SCK Setup Before CS J e 50 ns 6 SCK Hold After CS 4 e 50 ns t SDI Setup Before SCK T Note 5 10 ns tg SDI Hold After SCK T Note 5 10 ns Note 1 Absolute Maximum Ratings are those values beyond which the life of the device may be impaired Note 2 All voltage values are with respect to GND Note 3 Vcc 4 5V to 5 5V unless otherwise specified Veer REF Vperom 2 is the positive reference input is the negative reference input Viy IN ViNcM 1 IN7 2 Note 4 Fo pin tied to GND or to external conversion clock source with feosc 10MHz unless otherwise specified Note 5 Guaranteed by design not subject to test Note 6 Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve The deviation is measured from the center of the quantization band Note 7 The converter uses the internal oscillator Note 8 The converter is in external S
53. z amp 38 L TC2445I UH FEAR Nt D LIC2446 LTC2447 TECHNOLOGY 24 Bit High Speed 8 Channel AX ADCs with selectable Multiple Reference Inputs FEATURES Five Selectable Differential Reference Inputs Four Differential Eight Single Ended Inputs 4 Way MUX for Multiple Ratiometric Measurements Up to 8kHz Output Rate Up to 4kHz Multiplexing Rate Selectable Speed Resolution 2uVems Noise at 1 76kHz Output Rate 200nVpms Noise at 13 8Hz Output Rate with Simultaneous 50 60Hz Rejection Guaranteed Modulator Stability and Lock Up Immunity for any Input and Reference Conditions 0 0005 INL No Missing Codes Autosleep Enables 20uA Operation at 6 9Hz lt 5uV Offset 4 5V lt lt 5 5V 40 C to 85 C Differential Input and Differential Reference with GND to Vc Common Mode Range No Latency Mode Each Conversion is Accurate Even After a New Channel is Selected nternal Oscillator No External Components 162447 Includes MUXOUT ADCIN for External Buffering or Gain Tiny QFN 5mm x 7mm Package APPLICATIONS Flow Weight Scales Pressure Direct Temperature Measurement Gas Chromatography DESCRIPTION LTC 2446 LTC2447 4 terminal switching enables multiplexed ratiometric measurements Four sets of se lectable differential inputs coupled with four sets of differ ential reference inputs allow multiple RTDs bridges and other sensors to be digitized by a single converter A fifth differential referen
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LINEAR LTC2446/LTC2447 handbook