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IDT IDT70T633/1S Data Sheet

1. DATAout DATAIN 5670 drw 10 Timing Waveform of Write Cycle No 2 CE Controlled Timing gt I twc gt pes KK i taw SI CE or SEM UB LB RW DATAIN 5670 drw 11 NOTES RW or CE or UB or LB Vix during all address transitions A write occurs during the overlap tew or twp of a CE Vii and a R W Vi for memory array writing cycle twR is measured from the earlier of CE or R W or SEM or R W going HIGH to the end of write cycle During this period the I O pins are in the output state and input signals must not be applied If the CE or SEM Vi transition occurs simultaneously with or after the RI Vit transition the outputs remain in the High impedance state Timing depends on which enable signal is asserted last CE or RW This parameter is guaranteed by device characterization but is not production tested Transition is measured OmV from steady state with the Output Test Load Figure 1 8 If OE Vu during RW controlled write cycle the write pulse width must be the larger of twp or twz tow to allow the I O drivers to turn off and data to be placed on the bus for the required tow If OE Vin during an RAW controlled write cycle this requirement does not apply and the write pulse can be as short as the specified twp 9 To access RAM CE Vit and SEM Vin To access semaphore CE Vu and SEM VIL tew must be met for either condition CE Vi when CEo Vu and CE1 Vin CE Vin when CEo Vin and or CE
2. NOTES 5670 tbl 15 Port to port delay through RAM cells from writing port to reading port refer to Timing Waveform of Write with Port to Port Read and BUSY M S Vin To ensure that the earlier of the two ports wins teod is a calculated parameter and is the greater of the Max spec twop twp actual or opp tow actual To ensure that the write cycle is inhibited on port B during contention on port A To ensure that a write cycle is completed on port B after contention on port A 8ns Commercial and 10ns Industrial speed grades are available in BF 208 and BC 256 packages only a D n D D SEA AC Electrical Characteristics Over the Operating Temperature and Supply Volta 707633 1S8 70T633 1S10 70T6331S12 70T633 1S15 Com Only Com Com l Com Only amp Ind amp Ind Symbol Parameter SLEEP MODE TIMING ZZx V IH c baesnge Je Jo ee TTT m sewe f e ee EELER a e o ee EECHER RR t f o NOTES 5670 tbl 15a 1 Timing is the same for both ports 2 The sleep mode pin shuts off all dynamic inputs except JTAG inputs when asserted OPTx INTx M S and the sleep mode pins themselves ZZx are not affected during sleep mode It is recommended that boundary scan not be operated during sleep mode 3 These values are valid regardless of the power supply level selected for I O and control signals 3 3V 2 5V See page 6 for details 4 8ns Commercial
3. Plank Commercial 0 C to 70 C Industrial 40 C to 85 C BC 256 ball BGA BC 256 DD 144 pin TQFP DD 144 BF 208 P E BF 208 Commercial Only 0 Commercial amp Industrial f 2 Commercial amp Industrial Speed in nanoseconds 5 Commercial Only S Standard Power 70T633 9Mbit 512K x 18 2 5V Asynchronous Dual Port RAM 70T631 4Mbit 256K x 18 2 5V Asynchronous Dual Port RAM 5670 drw 24 NOTE 1 8ns Commercial and 10ns Industrial speed grades are available in BF 208 and BC 256 packages only Preliminary Datasheet Definition PRELIMINARY datasheets contain descriptions for products that are in early release Datasheet Document History 04 25 03 Initial Datasheet 10 01 03 Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table Page 9 Updated DC power numbers for 10 12 amp 15ns speeds in the DC Electrical Characteristics Table Page 9 11 15 17 amp 25 Added footnote that indicates that 8ns speed is available in BF 208 and BC 256 packages only Page 10 Added Capacitance Derating Drawing Page 11 15 amp 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables Page 11 Added tsoe and tLzos to the AC Read Cycle Electrical Characteristics Table Page 12 Added t zos to the Waveform of Read Cycles Drawing Page 14 Added tsoeto Timing Waveform of Semaphore Read after Write Timing Either Side Drawing Page 1 amp 25 Added 8ns speed grade and 10ns
4. gt e E fe o E gt N lt q x x o ve N Ka N am N gt 9 N ge o o Q G lt Ir IDT70T633 1S IDT70T633 1S High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Sleep Mode The IDT701633 1 is equipped with an optional sleep or low power mode on both ports The sleep mode pin on both ports is active high During normal operation the ZZ pin is pulled low When ZZ is pulled high the port will enter sleep mode where it will have the lowest possible power consumption The sleep mode timing diagram demonstrates the modes of operation Normal Operation No Read Write Allowed and Sleep Mode Foraperiodoftime priorto sleep mode and after recovering from sleep JTAG Timing Specifications tucyc UE TCK Device Inputs TDI TMS tus Device Outputs 2 Te tURSR TRST tURST NOTES 1 Device inputs All device inputs except TDI TMS and TRST 2 Device outputs All device outputs except TDO JTAG AC Electrical Characteristics 23 5 Parameter S enn 1 Symbol ns n Fe n 3 30 RST JTAG Reset tURSR JTAG Reset Recovery ns 5 n n n ef n pa 5670 tbl 20 mode tzzs and tzzr new reads orwrites are notallowed Ifa write orread Operation occurs during these periods the memory array may be corrupted Validity of data out from the RAM canno
5. or token from one port to the other to indicate that a shared resource is in use The semaphores provide a hardware assist for a use assignment method called Token Passing Allocation In this method the state of a semaphore latch is used as a token indicating that a shared resource is in use If the left processor wants to use this resource itrequests the token by setting the latch This processor then IDT70T633 1S High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Preliminary Industrial and Commercial Temperature Ranges verifies its success in setting the latch by reading it Ifitwas successful it proceeds to assume control over the shared resource If it was not successful in setting the latch itdetermines that the right side processor has set the latch first has the token and is using the shared resource The left processor can then either repeatedly request that semaphore s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence Once the right side has relinquished the token the left side should succeed in gaining control The semaphore flags are active LOW A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one tothatlatch The eight semaphore flags reside within the IDT70T633 1 in a separate memory space from the Dual Port RAM array This address
6. spaceis accessed by placing a lowinput on the SEM pin which acts as a chip select for the semaphore flags and using the other control pins Address CEo CE1 RW and LB UB as they would be usedin accessing astandard Static RAM Each of the flags has aunique address which can be accessed by either side through address pins Ao A2 When accessing the semaphores none of the other address pins has any effect When writing toa semaphore only data pin Dois used Ifa low level is written into an unused semaphore location that flag will be set to a zero on that side and a one on the other side see Truth Table V That semaphore can now only be modified by the side showing the zero When a one is written into the same location from the same side the flag will be set to a one for both sides unless a semaphore request from the other side is pending and then can be written to by both sides The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications A thor ough discussion on the use of this feature follows shortly A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the firstside When asemaphore flagis read its value is spread intoall data bits so thata flag thatis a one reads as a one in all data bits anda flag containin
7. and 10ns Industrial speed grades are available in BF 208 and BC 256 packages only 5 This parameter is guaranteed by device characterization but is not production tested IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port to Port Read and BUSY M S Vin 2 5 in twc gi ADDR a MATCH ps twP gt R W a DATAN A VALID ADDR s BUSY B DATAOUT B gt lt VALID NOTES 5670 drw 14 1 To ensure that the earlier of the two ports wins taps is ignored for M S Vit SLAVE 2 CEo CEor Vil CE CEIR Vin 3 OE Vi for the reading port A If M S Vii slave BUSY is an input Then for this example BUSY a Vin and BUSY s input is shown above 5 All timing is the same for left and right ports Port A may be either the left or right port Port B is the port opposite from port A Timing Waveform of Write with BUSY M S vu lt twP gt RW twp BUSY B a lt WH RAW B 2 NOTES 5670 drw 15 1 twH must be met for both BUSY input SLAVE and output MASTER 2 BUSY is asserted on port B blocking R W B until BUSY B goes HIGH 3 tw only applies to the slave mode IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Waveform of BUSY A
8. important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4 Two sema phore request latches feed intoa semaphore flag Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the opposite side HIGH This condition will continue until a one is written to the same semaphore request latch If the opposite side semaphore request latch has been written to zero in the meantime the semaphore flag will flip over to the other side as soon as a one is written into the first request latch The L PORT R PORT SEMAPHORE SEMAPHORE REQUEST FLIP FLOP REQUEST FLIP FLOP a Li WRITE g Es g WRITE SEMAPHORE READ SEMAPHORE READ Figure 4 IDT70T633 1 Semaphore Logic 5670 drw 21 opposite side flag will now stay LOW until its semaphore request latch is written to a one From this it is easy to understand that if a semaphore is requested and the processor which requested it no longer needs the resource the entire system can hang up until a one iswritteninto thatsemaphore requestlatch The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time The semaphore logic is specially designed to resolve this problem If
9. master is based on the chip enable and Industrial and Commercial Temperature Ranges address signals only It ignores whether an access is a read or write In a master slave array both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R W signal Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave Semaphores The IDT70T633 1 is an extremely fast Dual Port 512 256K x 18 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags These flags allow either processor on the leftor right side ofthe Dual Port RAM to claim aprivilege over the other processor forfunctions defined by the system designer s software As anexample the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual PortRAM or any other shared resource The Dual Port RAM features a fast access time with both ports being completely independent of each other This means that the activity on the left portin no way slows the access time of the right port Both ports are identical in function to standard CMOS Static RAM and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of or a simultaneous READ WRITE of a non semaphore location Semaphores are pro tected against such ambiguous
10. simultaneous requests are made the logic guarantees that only one side receives the token If one side is earlier than the other in making the request the first side to make the request will receive the token If both requests arrive atthe same time the assignment will be arbitrarily made to one port or the other One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure As with any powerful programming technique if semaphores are misused or misinterpreted a software error can easily happen Initialization of the semaphores is not automatic and must be handled via the initialization program at power up Since any sema phore request flag which contains a zero must be reset to a one all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed spod yyBiy pue Ve 10 ewes si Buju y Z HA 1J9 SALON Preliminary Industrial and Commercial Temperature Ranges ZZ MIP OZ9S MAZZA lt Z X aal ddZZ OOOO POOQOOOODODODODODOOK_SSHIGNETIN OH SEMEN ag HZZL Ti tT UO BON lt pemoyle SelM JO spee1 ON gt paN Oe gt Pamo e SOU 10 SEO M U ON ra uogeJodo woy gt z PON deals jo w1oz aeM Buw L lt q D oO 5 ho ES Ka e D Ei bi gt D E
11. situations and may be used by the system program to avoid any conflicts in the non semaphore portion of the Dual Port RAM These devices have an automatic power down feature controlled by CEoand CE1 the Dual PortRAM chip enables and SEM the semaphore enable The CEo CE1 and SEM pins control on chip power down circuitry thatpermits the respective port to gointo standby mode when not selected Systems which can best use the IDT70T633 1 contain multiple processors or controllers and are typically very high speed systems which are software controlled or software intensive These systems can benefit from a performance increase offered by the hardware semaphores of the IDT70T633 1 which provide a lockout mechanism without requiring complex programming Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations The IDT70T633 1 does not use its semaphore flags to control any resources through hardware thus allowing the system designer total flexibility in system architecture An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor This can prove to be a major advantage in very high speed systems How the Semaphore Flags Work The semaphore logic is a set of eight latches which are indepen dent of the Dual Port RAM These latches can be used to pass a flag
12. to input at CMOS level standby 3 Vp 2 5V Ta 25 C for Typ values and are not production tested Jop pc f 0 100mA Typ 4 CEx Vit means CEox Vit and CE1x Vi CEx ViH means CEox Viv or CE1x Vu CEx lt 0 2V means CEox lt 0 2V and CE1x gt Vopax 0 2V CEx gt Vppax 0 2V means CEox gt Vopax 0 2V or CE1x 0 2V X represents L for left port or R for right port 5 Jee Jee and pa will all reach full standby levels Is83 on the appropriate port s if ZZL and Jor ZZR Vum 6 8ns Commercial and 10ns Industrial speed grades are available in BF 208 and BC 256 packages only IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions Vopa 3 3V 2 5V Input Pulse Levels GND to 3 0V GND to 2 5V Input Rise Fall Times 2ns Max Input Timing Reference Levels 1 5V 1 25V Output Reference Levels 1 5V 1 25V Output Load Figure 1 5670 tbl 11 900 509 DATAout 1 5V 1 25 I restr 5670 drw 03 Figure 1 AC Output Test load A tAA tACE Typical ns 0 t T T T T T 0 20 40 60 80 100 120 140 160 A Capacitance pF from AC Test Load 5670 drw 04 Figure 3 Typical Output Derating Lumped Capacitive Load IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics O
13. 0mv VoD 100mV 5670 tbl 05 ail ala s 3 To select operation at 2 5V levels on the I Os and controls of a given port the OPT pin for that port must be set to Vss OV and Vopax for that port must be supplied as indicated above Recommended DC Operating Conditions with Vppa at 3 3V art e Ee ne e Te us coe Sippy vowse 24 es 26 fv r esmase e faf ae f Vss Input High Voltage VIH Address Control amp Data I O Inputs Input High Voltage Vu JTAG Vop 100mV Input High Voltage Vu ZZ OPT M a Vop 0 2V Vop 100mvV eon ee Low Voltage 1 5670 tbl 06 NOTES 1 Vit min 1 0V for pulse width less than trc 2 or 5ns whichever is less 2 Vin max Vopa 1 0V for pulse width less than trc 2 or 5ns whichever is less 3 To select operation at 3 3V levels on the I Os and controls of a given port the OPT pin for that port must be set to Voo 2 5V and Vppax for that port must be supplied as indicated above IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Vpp 2 5V 100mV Input Leakage Current Vopo Max VN OV to VDDQ Output Low Voltage 4mA Voa Min Output High Voltage OH 4mA Vopa Min Output Low Voltage 2mA Vopo Min Output High Voltage H 2
14. 1 Vi OS won IDT70T633 1S High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Preliminary Industrial and Commercial Temperature Ranges RapidWrite Mode Write Cycle Unlike other vendors Asynchronous Random Access Memories the IDT70T651 9 is capable of performing multiple back to back write operations without having to pulse the R W CE or BEn signals high during address transitions This RapidWrite Mode functionality allows the system designer to achieve optimum back to back write cycle performance without the difficult task of generating narrow reset pulses every cycle simplifying system design and reducing time to market During this new RapidWrite Mode the end of the write cycle is now defined by the ending address transition instead of the RW or CE orBEn transition to the inactive state R W CE and BEn can be held active throughout the address transition between write cycles Care mustbetaken to still meetthe Write Cycle time twc the time in which the Address inputs must be stable Inputdata setup and hold times tow and tox will now be referenced to the ending address transition In this RapidWrite Mode the I O willremainin the Input mode for the duration of the operations due to R W being held low All standard Write Cycle specifications must be adhered to However tas and twr are only applicable when switching between read and write operations Also there are two additional conditions on the Addr
15. A2 B MATCH x SIDE B R W e EE E 3 SEM s E mee 5670 drw 13 NOTES 1 Dor Dot Vit CEoL CEor Vin CE CE1R VIL Refer also to Truth Table Il for appropriate UB LB controls 2 All timing is the same for left and right ports Port A may be either left or right port B is the opposite from port A 3 This parameter is measured from R W a or SEM a going HIGH to R W s or SEM s going HIGH 4 If tsPs is not satisfied the semaphore will fall positively to one side or the other but there is no guarantee which side will be granted the semaphore flag cr IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 707633 188 707633 1S10 70T633 1S12 70T633 1S15 Com l Only Com Com Com l Only amp Ind amp Ind Win wox win wex wn wax win tox BUSY TIMING eal on Biinontmnnnnnan Oeo eo e n ET oae me nres omaa e O a o EREECHEN BAC BUSY Access Time from Chip Enable Low f es o 2 6 os xe RSTn rmtoncipentones e loo e o taps Arbitration Priority Setup Time 25 26 25 25 ow EECHER ERR EESSECRGES EREECHEN w ew e BUSY TIMING M S V1L w e E mw wa E E e PORT TO PORT DELAY TIMING wo eroa o e e e e le e weomwcnmaommn 2
16. Control DATAout DATAout Read Data in Semaphore Flag DATAN Write Oo into Semaphore Flag L 5670 tbl 03 NOTES 1 There are eight semaphore flags written to Oo and read from all the I Os I Oo I O17 These eight semaphore flags are addressed by Ao A2 2 CE L occurs when CEo Vit and CE1 ViH CE H when CEo Vin and or CE1 Vi 3 Each byte is controlled by the respective UB and LB To read data UB and or LB VIL IDT70T633 1S High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage Ambient Temperature Industrial 40 C to 85 C 2 5V 100mV 5670 tbl 04 NOTE 1 This is the parameter TA This is the instant on case temperature Absolute Maximum Ratings Symbol Commercial amp Industrial VTERM Von Terminal Voltage 0 5 to 3 6 V VDD with Respect to GND VTERM Vona Terminal Voltage 0 3 to Vona 0 3 V Vona with Respect to GND Vora Input and UO Terminal 0 3 to Vopa 0 3 V Voltage with Respect to GND INPUTS and 1 0 s TBias Temperature 55 to 125 C Under Bias TsTG Storage 65 to 150 C Temperature TIN Junction Temperature lour For Vona 3 3V DC Output Current lour For Vona 2 5V DC Output Current 5670 tbl 07 NOTES 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the de
17. FFFF are notused as mailboxes but as part of the random access memory Refer to Truth Table III for the interrupt operation IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Busy Logic Busy Logic provides a hardware indication that both ports ofthe RAM have accessed the same location atthe same time Italso allows one of the twoaccesses to proceed and signals the other side thatthe RAM is Busy The BUSY pin can then be used to stall the access until the operation on the other side is completed If awrite operation has been attempted from the side thatreceives a BUSY indication the write signal is gated internally to prevent the write from proceeding The use of BUSY logicis not required or desirable for all applications Insome cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of anillegal or illogical operation Ifthe write inhibit function of BUSY logicis not desirable the BUSY logic can be disabled by placing the partin slave mode with the M S pin Once in slave mode the BUSY pin operates solely as awrite inhibitinputpin Normal operation can be programmed by tying the BUSY pins HIGH If desired unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW The BUSY outputs on the IDT70T633 1 RAM in master mode are push pull type outputs and do not require pull up resist
18. I O s I Oo I O017 These eight semaphores are addressed by Ao A2 3 CEo ViH CE1 SEM Vu to access the semaphores Refer to the Semaphore Read Write Control Truth Table Functional Description The IDT70T633 1 provides two ports with separate control address and I O pins that permit independent access for reads or writes to any location in memory The IDT70T633 1 has an automatic power down feature controlled by CE The CEo and CE1 control the on chip power down circuitry that permits the respective port to go into a standby mode when not selected CE HIGH When a portis enabled access to the entire memory array is permitted flag INTL is asserted when the right port writes to memory location 7FFFE HEX where a write is defined as CER R Wr VIL per the Truth Table The left port clears the interrupt through access of address location 7FFFE when CEL OEL Vu R Wisa don t care Likewise the right port interrupt flag INTR is asserted when the left port writes to memory location 7FFFF HEX and to clear the interrupt flag INTR the right port must read the memory location 7FFFF The message 18 bits at 7FFFE or 7FFFF 3FFFF or 3FFFE for IDT 707631 is user defined since itis an addressable SRAM location Ifthe interrupt Interrupts If the user chooses the interrupt function a memory location mail box or message center is assigned to each port The left portinterrupt function is notused address locations 7FFFE and 7
19. NOTES 1 All VoD pins must SeeesteGFeSSSSSSoSSRBSESSSSESSSSSSESRER UU UU IO UU 209 FES TE CES EET E SCE OER EC RM EET EES E RY SEET EE EE lt D la be connected to 2 5V power supply OPTL VDDQR Vss 1 O8L 1 O8R 1 O7L 1 O7R O6L 1 O6R Vss VDDQL O5L 1 O5R Vss VDDQR VDD VDD Vss Vss ZZL VDDQL 1 04R 1 04L 1 O3R 1 O3L Vss VDDQR 1 O2R 1 02L 1 O1R OAL 1 OoR I OoL Vss VDDaL OPTR 5670 drw 02a 2 All Vopa pins must be connected to appropriate power supply 3 3V if OPT pin for that port is set to Voo 2 5V and 2 5V if OPT pin for that port is set to Vss OV This text does not SOOO SO ee All Vss pins must be connected to ground Aug is a NC for IDT70T631 Package body is approximately 20mm x 20mm x 1 4mm This package code is used to reference the package diagram 8ns Commercial and 10ns Industrial speed grades are not available in the DD 144 package indicate orientation of the actual part marking Due to the restricted number of pins JTAG is not supported in the DD 144 package IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Pin Configurations 2 con t 03 12 03 12 13 14 15 ASS 9 CSCS SSIS SCS 8 i eet fl e foe fe f D Fe ve Oio NC Aust Atte Act BL OEL Aa Vopat On W zn D E VO11L Vopop 1 O10R Ost E e EES 70T633 1BF i ee EEN EFFE SE J 208 Ball BGA L SS
20. OER INTR AsR Ax Aon NC NC NOTES 5670 drw 02c 1 All VDD pins must be connected to 2 5V power supply 2 All Vopa pins must be connected to appropriate power supply 3 3V if OPT pin for that port is set to Voo 2 5V and 2 5V if OPT pin for that port is set to Vss OV All Vss pins must be connected to ground supply Aug is a NC for IDT70T631 Package body is approximately 17mm x 17mm x 1 4mm with 1 0mm ball pitch This package code is used to reference the package diagram ot Sa IDT70T633 1S High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Configurations 23 5 con t i jl ae es a i 03 13 03 Soo FEFFE sz egy emg EE gt ZZ4 lt 4 lt 4 lt lt lt sl sl sl lt 1 lt D Oo Gs Ge OO EIS st ai sl sl at al sl IO OTTO T T TON rT OO Oo t oO OD TOA cO Oo ONON st Oo Oo ec OO oO F oO D st o Or OO OH d d d st sg o oO o oO oo oo oO OO GO Oo OO oO ee e ON VSS EECH EENEG EE Vppar H 2 Vss H 3 O9L H 4 O9R H 5 On H 6 O10R H7 O11L H 8 Op 49 VpopoL H 10 Vss H 11 O12L 4 12 O12R H 13 Cy Wee be 707633 1DD VDD 16 DD 144 5 6 7 VDD H 17 Vss 18 Kee Top View Vss H 013R H 1 013L H 23 014R 24 1 014L H 25 VDDQR H 26 Vss 27 015R H 28 O15L 29 O016R H 30 One H 31 017R 32 1 017L H 33 Vss H 34 VppaL H 35 NC H 36
21. S TDO Test Data Output If OPTx is set to Von 2 5V then that port s I Os and controls will operate at 3 3V levels and Vopox must be supplied at 3 3V If OPTx is set to Vss OV then that TCK Test Logic Clock 10MHz Input port s I Os and controls will operate at 2 5V levels and Vopax must be supplied t 2 5V The OPT pins are independent of one another both ports can operate TMS Test Mode Select Input est Mode Seleting at 3 3V levels both can operate at 2 5V levels or either can operate at 3 3V TRST Reset Initialize TAP Controller Input with the other at 2 5V 4 The sleep mode pin shuts off all dynamic inputs except JTAG inputs when asserted OPTx INTx M S and the sleep mode pins themselves ZZx are not affected during sleep mode It is recommended that boundry scan not be operated during sleep mode 5 BUSY is an input as a Slave M S ViL and an output when it is a Master M S ViH 5670 tbl 01 IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I Read Write and Enable Control eee 1 09 17 1 00 8 fal Ei x a Bg A Cona on wie orere i C on roz fwe ower Con on weones ES TTT le bapag E Pape ef ft J rime beste iS PTT te Yn en ase 5670 tbl 02 g E ERD JL JL xjr 2 lz NOTE 1 H Vin L Vi X Don t Care Truth Table Il Semaphore Read Write
22. SEI DT 707 631S hy HIGH SPEED IDT STATIC RAM 512 256K x 18 ASYNCHRONOUS DUAL PORT 2 5V PRELIMINARY IDT70T633 1S WITH 3 3V OR 2 5V INTERFACE Features True Dual Port memory cells which allow simultaneous access of the same memory location High speed access Commercial 8 10 12 15ns max e Industrial 10 12ns max RapidWrite Mode simplifies high speed consecutive write cycles Dual chip enables allow for depth expansion without external logic IDT70T633 1 easily expands data bus width to 36 bits or more using the Master Slave select when cascading more than one device MIS Vum for BUSY output flag on Master M S Vi for BUSY input on Slave e Busy and Interrupt Flags Full hardware support of semaphore signaling between ports on chip On chip port arbitration logic Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Supports JTAG features compliant to IEEE 1149 1 in BGA 208 and BGA 256 packages Single 2 5V 100mV power supply for core LVTTL compatible selectable 3 3V 150mV 2 5V 100mV power supply for I Os and control signals on each port Available in a 256 ball Ball Grid Array 144 pin Thin Quad Flatpack and 208 ball fine pitch Ball Grid Array Industrial temperature range 40 C to 85 C is available for selected speeds Functional Block Di
23. Y outputs on the IDT70T633 1 are push pull not open drain outputs On slaves the BUSY input internally inhibits writes 2 L if the inputs to the opposite port were stable prior to the address and enable inputs of this port H if the inputs to the opposite port became stable after the address and enable inputs of this port If taps is not met either BUSYL or BUSYR LOW will result BUSYL and BUSYr outputs can not be LOW simultaneously 3 Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin 4 A18 is a NC for IDT70T631 Address comparison will be for Ao A17 5 CEx L means CEox Vu and CE1x Vin CEx H means CEox Vin and or CE1x Vi Truth Table V Example of Semaphore Procurement Sequence 2 3 em tort oom sated COo Se pen ew Serpe __1 0 lesen trot rows aaas moramo Right Port Writes 1 to Semaphore Right Port Writes 0 to Semaphore ee a ssieseeste LetPotvies Fwsenpioe 0 1 lato antowan Left Port Writes 1 to Semaphore Right Port Writes 0 to Semaphore Left Port Writes 1 to Semaphore NOTES 5670 tbl 19 1 This table denotes a sequence of events for only one of the eight semaphores on the IDT70T633 1 2 There are eight semaphore flags written to via UO and read from all
24. agram Dout0 8_L Dout9 17_L 512 256K x 18 I OoL UO Address Decoder ARBITRATION INTERRUPT SEMAPHORE BUSYL25 SEML INTL NOTES 1 Address A18x is a NC for IDT70T631 RON 2003 Integrated Device Technology Inc Dout0 8_R Dout9 17_F me Pin CEoR CEIR c pa E sc IOO0R 1 017R Address Decoder OE R BUSYR23 SEMR INTRO 4 ZZ 4 ZZ CONTROL a 22h LOGIC BUSY is an input as a Slave M S ViL and an output when it is a Master M S Vix BUSY and INT are non tri state totem pole outputs push pull The sleep mode pin shuts off all dynamic inputs except JTAG inputs when assert sleep mode pins themselves ZZx are not affected during sleep mode 5670 drw 01 ed OPTx INTx M S and the NOVEMBER 2003 DSC 5670 3 IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Description The IDT70T633 1 is a high speed 512 256K x 18 Asynchronous Dual Port Static RAM The IDT70T633 1 is designed to be used as a stand alone 9216 4608K bit Dual Port RAM or as a combination MAS TER SLAVE Dual Port RAM for 36 bit or more word system Using the IDT MASTER SLAVE Dual Port RAM approach in 36 bit or wider memory system applications results in full speed error free operation withoutthe need forad
25. and Commercial Temperature Ranges Waveform of Interrupt Timing twe ADDR a INTERRUPT SET ADDRESS 4 5 CEA RAW n His 5670 drw 18 ADDR s INTERRUPT CLEAR ADDRESS 4 INT B 5670 drw 19 NOTES All timing is the same for left and right ports Port A may be either the left or right port Port B is the port opposite from port A Refer to Interrupt Truth Table CEx Vit means CEox Vu and CE1x Vin CEx Vin means CEox Vin and or CE1x Vi Timing depends on which enable signal CE or R W is asserted last Timing depends on which enable signal CE or RAW is de asserted first Se ON Truth Table III Interrupt Flag Left Port Right Port L ec RETE IENENE SET T EE TTT aages NOTES 5670 tbl 17 1 Assumes BUSYL BUSYR Vin CEx L means CEox Vit and CE1x Vin 2 If BUSYL Vu then no change 3 If BUSYR Vit then no change A INTL and INTR must be initialized at power up 5 Aug is a NC for IDT70T631 Therefore Interrupt Addresses are 3FFFF and 3FFFE 20 Preliminary Industrial and Commercial Temperature Ranges IDT70T633 1S High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Truth Table IV Address BUSY HS el EE eee me An Aua Hl ea oe a ae 5670 tbl 18 NOTES 1 Pins BUSY and BUSYR are both outputs when the part is configured as a master Both are inputs when configured as a slave BUS
26. ditional discrete logic This device provides two independent ports with separate control address and O pins that permitindependent asynchronous access for reads or writes to any location in memory An automatic power down Industrial and Commercial Temperature Ranges feature controlled by the chip enables either CEo or CE1 permit the on chip circuitry of each port to enter a very low standby power mode The IDT70T651 9 has aRapidWrite Mode which allows the designer to perform back to back write operations without pulsing the R W input each cycle This is especially significantatthe 8 and 10ns cycle times of the IDT70T651 9 easing design considerations at these high perfor mancelevels The 70T633 1 can supportan operating voltage of either 3 3V or2 5V on one or both ports controlled by the OPT pins The power supply for the core of the device VDD remains at 2 5V IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Pin Configuration 2 707633 1BC BC 25665 256 Pin BGA 03 13 03 Top View A A2 A3 A4 A5 A6 A7 A8 A9 Aio Jan A12 A13 A14 jais faie NC TDI NC A17 Ai Ati As NC CEiL OEL INTL Ae A2 Ao NC NC Bi B2 B3 B4 BS B6 B7 B8 B9 ag B11 B12 B13 Tou Jon B16 NC NC TDO AisL Aist Aiz Ast UBL CEoL RAWL NC As AL NC NC NC C1 c2 c3 CA C5 C6 C7 c8 c9 cio Jeun c12 Jena Jeu Jos Ce NC Viel V
27. ess Inputs that must also be metto ensure correctaddress controlled writes These specifications the Allowable Address Skew taas andthe Address Rise Fall time tar mustbe met to use the RapidWrite Mode If these conditions are not met thereisthe potential forinadvertentwrite operations atrandomintermediate locations as the device transitions between the desired write addresses Timing Waveform of Write Cycle No 3 RapidWrite Mode Write Cycle twe gt ADDRESS CE or SEM DATAOUT DATAIN NOTES 5670 drw 08 1 OE Vu for this timing waveform as shown OE may equal Vu with same write functionality WO would then always be in High Z state 2 A write occurs during the overlap tew or twe of a CE Vit BEn Vit and a RW Vit for memory array writing cycle The last transition LOW of CE BEn and RM initiates the write sequence The first transition HIGH of CE BEn and RW terminates the write sequence 3 If the CE or SEM Vi transition occurs simultaneously with or after the R W Vu transition the outputs remain in the High impedance state 4 The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes 5 This parameter is guaranteed by device characterization but is not production tested Transition is measured OmV from steady state with the Output Test Load Figure 1 6 To access RAM CE Vit and SEM Vin To access semap
28. g a zero reads as all zeros fora semaphore read the SEM BEn and OE signals need to be active Please refer to Truth Table Il Furthermore the read value is latched into one side e output register when that side s semaphore select SEM BEn and outputenable OE signals goactive This serves to disallow the semaphore from changing state in the middle ofa read cycle due to a write cycle from the other side A sequence WRITE READ must be used by the semaphore in order to guarantee that no system level contention will occur A processor requests access to shared resources by attempting to write a zero into a semaphore location If the semaphore is already in use the semaphore request latch will contain a zero yet the semaphore flag will appear as one a fact which the processor will verify by the subsequent read see Table V As an example assume a processor writes a zero to the left port at a free semaphore location On a subsequent read the processor will verify that it has written success fully to that location and will assume control over the resource in question Meanwhile if a processor on the right side attempts to write a zero to the same semaphore flag it will fail as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read Had a sequence of READ WRITE been used instead system contention problems could have occurred during the gap between the read and write cycles It is
29. hore CE vn and SEM Vu tew must be met for either condition CE Vi when CEo Vu and CE1 Vin CE Vik when CEo Vik and or CE1 VIL IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics over the Operating Temperature Range and Supply Voltage Range for RapidWrite Mode Write Cycle Parameter Allowable Address Skew for RapidWrite Mode Address Rise Fall Time for RapidWrite Mode NOTE 5670 tbl 14 Ai Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle NOTE 1 A17 for IDT70T631 5670 drw 09 IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing Either Side none X OXX XX DATAOUT COREE a ote E RW Write Cycle Read Cycle 5670 drw 12 NOTES 1 CEo VH and CE1 Vit are required for the duration of both the write cycle and the read cycle waveforms shown above Refer to Truth Table II for details and for appropriate UB LB controls 2 DATAout VALID represents all I O s I Oo 1 017 equal to the semaphore value Timing Waveform of Semaphore Write Contention Ao a A2 A MATCH X SIDE A lt RW Be SEM a E ISPS Ao B
30. k M Sg M N qa Ois Vun Vooa NC vou N BRE TRST Auen Auen Aen Su NTR na ve le vee no P DEES i eck 5670 drw 02b NOTES 1 All VoD pins must be connected to 2 5V power supply 2 All Voba pins must be connected to appropriate power supply 3 3V if OPT pin for that port is set to Voo 2 5V and 2 5V if OPT pin for that port is set to Vss OV All Vss pins must be connected to ground Aug is a NC for IDT70T631 Package body is approximately 15mm x 15mm x 1 4mm with 0 8mm ball pitch This package code is used to reference the package diagram This text does not indicate orientation of the actual part marking Soro Eea IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Pin Names CEoL CEIL Chip Enables Input RWL Read Write Enable Input ERREECHEN mh UBL UBR Upper Byte Select Input LBL LBR Lower Byte Select Input VoDaL Vobar Power I O Bus 3 3V or 2 5V Input OPTR Option for selecting Vonax Input ZZ ZZR Sleep Mode Pin Input be U a d r D Master or Slave Select Input VoD Power 2 5V Input NOTES 1 Address Aug is a NC for IDT70T631 2 VoD OPTx and Vopax must be set to appropriate operating levels prior to applying inputs on 1 0x 3 OPTx selects the operating voltage levels for the I Os and controls on that port Vss Ground OV Input Test Data Input
31. mA Voa Min NOTES 5670 tbl 09 1 pba is selectable 3 3V 2 5V via OPT pins Refer to page 6 for details 2 Applicable only for TMS TDI and TRST inputs 3 Outputs tested in tri state mode DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Vpp 2 5V 100mv 70T633 1S8 70T633 1S10 70T633 1S12 70T633 1S15 Com Only Com Only Symbol IDD Dynamic Operating CEL and CEr VIL Current Both Outputs Disabled Ports Active f fmax Q O C n Z o wn Ce a So 2 S Zi a a IsB1 Standby Current CEL CER VIH Both Ports TTL f fmax Level Inputs wn oa IsB2 Standby Current Ca Vit and CEB VIH One Port TTL Active Port Outputs Disabled Level Inputs f fmax D I gt IO SO 8 8 8 z2 P z ES E E CO ISB3 Current Both Ports CEL and CMOS CER gt VDD 0 2V VIN gt VDD 0 2V or VIN lt 0 2V f 02 n N N ESS CH 315 lsB4 Full Standby Current CE a lt 0 2V and CE s gt Vop 0 2V ou s 240 One Port CMOS VIN gt VDD 0 2V or VIN lt 0 2V Active Level Inputs Port Outputs Disabled f fmax Izz Current ZZL ZZR VIH TIL f fmax NOTES 5670 tbl 10 1 At f fmax address and control lines except Output Enable are cycling at the maximum frequency read cycle of 1 tRc using AC TEST CONDITIONS 2 f 0 means no address or control lines change Applies only
32. n CEo Vin and or CE1 Vi 4 These values are valid regardless of the power supply level selected for I O and control signals 3 3V 2 5V See page 6 for details 5 8ns Commercial and 10ns Industrial speed grades are available in BF 208 and BC 256 packages only IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Read Cycles R W lt Hatz DATAouT BUSY ouT WAAAY gt gt teop 5670 drw 06 NOTES 1 Timing depends on which signal is asserted last OE CE LB or UB 2 Timing depends on which signal is de asserted first CE OE LB or UB 3 tepo delay is required only in cases where the opposite port is completing a write operation to the same address location For simultaneous read operations BUSY has no relation to valid output data 4 Start of valid data depends on which timing becomes effective last tAOE tACE tAA tABE or tBDD 5 SEM Vin 6 CE L occurs when CEo Vit and CE1 Vin CE H when CEo Vin and or CE1 Vi Timing of Power Up Power Down CE tPU PD 50 50 ISB 5670 drw 07 IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No 1 R W Controlled Timing lt twc w wres A
33. ors to operate If these RAMs are being expanded in depth then the BUSY indication for the resulting array requires the use of an external AND gate A19 CEo SLAVE CEo Dual Port RAM MASTER Dual Port RAM BUSYL BUSYR BUSYL BUSYR MASTER CE1 CE1 Dual Port RAM SLAVE Dual Port RAM BUSYL BUSYR BUSYL BUSYR Se 5670 drw 20 Figure 3 Busy and chip enable routing for both width and depth expansion with IDT70T633 1 Dual Port RAMs Width Expansion with Busy Logic Master Slave Arrays When expanding an IDT70T633 1 RAM array in width while using BUSY logic one master partis used to decide which side of the RAMs array will receive a BUSY indication and to output that indication Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal Thus on the IDT70T633 1 RAM the BUSY pin is an output if the part is used as a master M S pin Vik and the BUSY pin is an input if the part used as a slave M S pin VIL as shown in Figure 3 If two or more master parts were used when expanding in width a split decision could resultwith one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word The BUSY arbitration on a
34. rbitration Controlled by CE Timing M S Vin KE ADDRESSES MATCH CE var SCH BUSY B 5670 drw 16 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing M S Vin ADDR a ADDRESS N ADDR s MATCHING ADDRESS N BUSY B 5670 drw 17 NOTES 1 All timing is the same for left and right ports Port A may be either the left or right port Port B is the port opposite from port A 2 If taps is not satisfied the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted 3 CEx Vi when CEox Vu and CE1x Vin CEx Vin when CEox Vin and or CE1x Vit 4 CEox OEx LBx UBx Vit CE1x Vin AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 707633 1S8 70T633 1S10 70T633 1 12 70T633 1S15 Com Only Com Com Com Only amp Ind amp Ind smo ame ime Yo me w i we me me INTERRUPT TIMING ws _ unoome Joe feee ERR RRE ER Pp ff lll bag Re beta ETS 5670 tbl 16 NOTES 1 Timing is the same for both ports 2 These values are valid regardless of the power supply level selected for UO and control signals 3 3V 2 5V See page 6 for details 3 8ns Commercial and 10ns Industrial speed grades are available in BF 208 and BC 256 packages only 19 IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial
35. ss Ate AisL Ato As NC LBL SEMLIBUSYL Ae Aa OPTL NC 1 OsL D3 D5 D6 D8 Dio Wou D12 D13 pu ps D16 Guer We NC ae Vopo VDDaL SE VDDQRI SCH DDQL VDDaR VppaR Voo NC NC lien E9 E10 Jeu E12 E13 E14 es E16 ioe orn NG S A CH Got K Vss Vss Vpp Voo VpparR NC 1 07 1 O7R F1 En Jeu F12 F13 EA Ins Jee VOWIL Ge WEIS VpopoL ie ES Gen E Gees Vss Vss Voo Vppar I OeR NC I OeL G6 G10 E 12 eg G14 G Ve Gei ES esch DDQR K Vss im is Ge Vss Vss VppaL I O5L H2 H5 pn In ma Ins Hh H5 Hie Ne 1 012R re Vopnopl Vss Gg Gs ee e Vss Vss Vss VppaL NC NC U en J1 J7 J8 J10 J11 J12 J13 J14 Vis J16 1 013L ioe ion SEN a p Vss Vss ae Vss Vss ZZL Vopar 1 04R VO3R 1 04L Kin ki K12 ui Ion og Gs ce aah DDQL ae GH E an Ge Vss Vss Vss Ivopon NC NC I OsL L10 L11 L12 L14 L15 L16 fom Ges Totaly DDAR GE SCH ECH G SCH Vss Vss Voo Vppa_ 1 O2 NC I O2R e M4 vun Iw wus Mi4 wus IM E E KS Vppar Gs KC VSS Ge Ge Vss VoD VoD Mee 1 O1R 1 0O1L N2 N3 N8 Nio Mun wa wa wu Ms Nie Ces O17R NC ae a onal ee VDDaL vebal DDAR VpDpDaL VDDaL Voo NC WV Oor NC pn le p12 es P15 P16 Ee M E PA pm M Ges K e SEMR BUSYR Aen Aop Ces NC Un R1 R2 R3 R4 R5 R6 R7 R8 R9 Rio Inn Ins Jos ou ps D NC NC TRST AisR AisR A12R A9R UBR CEoR R Wr M S Asr Air JOPTR NC NC T1 T2 T3 T4 T5 T6 T7 T8 T9 tmo mi mz ma mu mis Ire NC TCK NC Ai7R Ai4R Aupl Asr NC CEiR
36. t be guaranteed immediately after ZZ is asserted prior to being in sleep During sleep mode the RAM automatically deselects itself and discon nectsits internal buffer All outputs will remain in high Z state while in sleep mode Allinputs are allowed to toggle butthe RAM willnotbe selected and will not perform any reads or writes a tUDC e Me tJCD 5670 drw 23 NOTES 1 Guaranteed by design 2 30pF loading on external output signals 3 Refer to AC Electrical Test Conditions stated earlier in this document 4 JTAG operations occur at one speed 10MHz The base device may run at any speed specified in this datasheet 5 JTAG cannot be tested in sleep mode IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Revision Number 31 28 Reserved for version number IDT Device ID 27 12 0x33B Defines IDT part number 707633 IDT JEDEC ID 11 1 Allows unique identification of device vendor as IDT ID Register Indicator Bit Bit 0 Indicates the presence of an ID register NOTE 5670 tbl 21 1 Device ID for IDT70T631 is 0x33C Scan Register Sizes Register Name Instruction IR Bypass BYR Identification IDR Boundary Scan BSR 5670 tbl 22 System Interface Parameters EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs Places the bo
37. temp to features and to ordering information Page 1 148 15 Added RapidWrite Mode Write Cycle text and waveforms 10 20 03 Page 15 Corrected tarr to 1 5V ns Min CORPORATE HEADQUARTERS for SALES for Tech Support l DT 2975 Stender Way 800 345 7015 or 408 727 6116 831 754 4613 Santa Clara CA 95054 fax 408 492 8674 DualPortHelp idt com www idt com The IDT logo is a registered trademark of Integrated Device Technology Inc
38. undary scan register BSR between TDI and TDO BYPASS 1111 Places the bypass register BYR between TDI and TDO IDCODE 0010 Loads the ID register IDR with the vendor ID code and places the register between TDI and TDO HIGHZ 0100 Places the bypass register BYR between TDI and TDO Forces all device output drivers to a High Z state CLAMP 0011 Uses BYR Forces contents of the boundary scan cells onto the device outputs Places the bypass register BYR between TDI and TDO SAMPLE PRELOAD 0001 Places the boundary scan register BSR between TDI and TDO SAMPLE allows data from device inputs and outputs to be captured in the boundary scan cells and shifted serially through TDO PRELOAD allows data to be input serially into the boundary scan cells via the TDI RESERVED All other codes Several combinations are reserved Do not use codes other than those identified above 5670 tbl 23 NOTES 1 Device outputs All device outputs except TDO 2 Device inputs All device inputs except TDI TMS and TRST 3 The Boundary Scan Descriptive Language BSDL file for this device is available on the IDT website www idt com or by contacting your local IDT sales representative 26 IDT70T633 1S Preliminary High Speed 2 5V 512 256K x 18 Asynchronous Dual Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX A 999 A A Device Power Speed Package Process Type Temperature Range
39. ver the Operating Temperature and Supply Voltage Range 70T633 1S8 70T633 1S10 70T633 1S12 70T633 1S15 Com Only Com Com l Com Only amp Ind amp Ind oe i we a we nT READ CYCLE e famm fJ e e DEIER S a ovemmeravt e e e e le m foes E E E E fe o Sowas O E E E a a oware o sf gt e DEER EEREESEEREEREEREESSEREES ER ER owane owne O o o o o o a E a R NEES GER RRE e e e ER w Sowno E ER EECHER e e o enro a waere es OOO O e E e E e E EE fefe e o le ele s wx seno owes O e E 5670 tbl 12 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage 707633 1S8 70T633 1S10 707633 1S12 707633 1S 15 Com Only Com Com l Com l Only amp Ind amp Ind sn em i nic n nix oi nae i WRITE CYCLE esoe w peee ESEH EES EHEESECH ES e feo Pf 7 EESECR ESCH EES m fansa EES E a ESCH EES e pss E Pf EES fol CAES CEES CE w pew ESECREESES ES ESEH DREES ECH e E a o fomaem o fs E a EES EES ono ssirag Wenner RER EREREERECR ERC ESEH EE EA NOTES 5670 tbl 13 1 Transition is measured Dm from Low or High impedance voltage with Output Test Load Figure 1 2 This parameter is guaranteed by device characterization but is not production tested 3 To access RAM CE Vit and SEM Vin To access semaphore CE Vun and SEM Vi Either condition must be valid for the entire tew time CE Vi when CEo Vit and CE1 Vin CE Vin whe
40. vice This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 This is a steady state DC parameter that applies after the power supply has reached its nominal operating value Power sequencing is not necessary however the voltage on any Input or I O pin cannot exceed Vopa during power supply ramp up 3 Ambient Temperature under DC Bias No AC Conditions Chip Deselected Capacitance Ta 25 C F 1 0MHz TQFP ONLY Syma Parameter conditons wax Unt ZA Input Capacitance VIN 3dV ole pF Output Capacitance Vout 3dV 10 5 5670 tb 08 NOTES 1 These parameters are determined by device characterization but are not production tested 2 3dV references the interpolated capacitance when the input and output switch from OV to 3V or from 3V to OV 3 Cour also references Cio Recommended DC Operating Conditions with Vppa at 2 5V Vss Input High Volltage VIH Address Control amp Data UO Inputs Input High Voltage VH me Input High Voltage VIL Input Low Voltage Input Low Voltage 30 NOTES 1 Vit min 1 0V for pulse width less than tRc 2 or 5ns whichever is less 2 Vin max Vopa 1 0V for pulse width less than trc 2 or 5ns whichever is less EE SS Voo 10

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