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MICROCHIP PIC17C4X handbook

1. 1 00 0 0390 Ref g H n H S 11 13 4x Pint Pin 1 e 2 O 2 0 LII B I Lj Et ELS i BN A I 11 13 4x I Lj I i Im i on Detail 3 00 0 1180 Ref R 1 0 08 Min Option 1 side Option 2 side R 0 08 0 20 d C i Base Metal Lead Finish 00 T TAA S E gt 0 20 4 L Detail Detail A 1 00 Ref 1 00 Ref b1 Package Group Plastic TQFP Millimeters Inches Symbol Min Max Notes Min Max Notes A 1 00 1 20 0 039 0 047 A1 0 05 0 15 0 002 0 006 A2 0 95 1 05 0 037 0 041 D 11 75 12 25 0 463 0 482 D1 9 90 10 10 0 390 0 398 E 11 75 12 25 0 463 0 482 E1 9 90 10 10 0
2. _ 0 05 mm mm 0 20 min 0 13 R Ind Index H i PARTING LINE i 013030 R LLE AGI i oo Ao i 1 60 Ref LIT OT Y TYP 4x _ H 20 0 0 N EN 21 10 05 mm mm D d E Base Seating 4 Plane Package Group Plastic MQFP Millimeters Inches Symbol Min Max Notes Min Max Notes 09 79 09 7 A 2 000 2 350 0 078 0 093 A1 0 050 0 250 0 002 0 010 A2 1 950 2 100 0 768 0 083 b 0 300 0 450 Typical 0 011 0 018 Typical C 0 150 0 180 0 006 0 007 D 12 950 13 450 0 510 0 530 D1 9 900 10 100 0 390 0 398 D3 8 000 8 000 Reference 0 315 0 315 Reference E 12 950 13 450 0 510 0 530 E1 9 900 10 100 0 390 0 398 ES 8 000 8 000 Reference 0 315 0 315 Reference e 0 800 0 800 0 031 0 032 L 0 730 1 030 0 028 0 041 N 44 44 44 44 CP 0 102 0 004 0830412 208 1996 Microchip Technology Inc PIC17C4X 21 5 44 Lead Plastic Surface Mount TQFP 10x10 mm 1 0 0 10 mm Lead Form D gt
3. TABLE 13 2 REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note 13h BankO RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00u 151 BankO TXSTA CSRC TX9 TXEN SYNC TRMT TX9D 0000 1x 0000 1u 17h SPBRG Baud rate generator register XXXX XXXX uuuu uuuu Legend x unknown u unchanged unimplemented read as a 0 shaded cells are not used by the Baud Rate Generator Note 1 Other non power up resets include external reset through MCLR and Watchdog Timer Reset DS30412C page 86 1996 Microchip Technology Inc PIC17CAX TABLE 13 3 BAUD RATES FOR SYNCHRONOUS MODE BAUD FOSC 33 MHz SPBRG FOSC 25 MHz SPBRG FOSC 20 MHz SPBRG FOSC 16 MHz SPBRG RATE value value value value K KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 0 3 NA NA NA NA 1 2 NA NA NA NA 24 NA NA NA NA 9 6 NA NA NA NA 19 2 NA NA 19 53 1 73 255 19 23 0 16 207 76 8 77 10 0 39 106 77 16 0 47 80 76 92 0 16 64 76 92 0 16 51 96 95 93 0 07 85 96 15 0 16 64 96 15 0 16 51 95 24 0 79 41 300 294 64 1 79 27 297 62 0 79 20 294 1 1 96 16 307 69 2 56 12
4. GOTO Unconditional Branch Syntax abel GOTO k Operands 0 lt lt 8191 Operation k lt 12 0 gt k lt 12 8 gt PCLATH lt 4 0 gt PC lt 15 13 gt PCLATH lt 7 5 gt Status Affected None Encoding 110k kkkk kkkk kkkk Description GOTO allows an unconditional branch anywhere within an 8K page boundary The thirteen bit immediate value is loaded into PC bits lt 12 0 gt Then the upper eight bits of PC are loaded into PCLATH GoTo is always a two cycle instruction Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Execute NOP lt 7 0 gt Forced Execute NOP Example GOTO THERE After Instruction PC Address THERE DS30412C page 122 1996 Microchip Technology Inc PIC17C4X INCF Increment f Syntax label INCF Operands 0 lt lt 255 d 0 1 Operation f 1 dest Status Affected Z Encoding 0001 010d ffff Description The contents of register f are incre mented lf d is 0 the result is placed in WREG If d is 1 the result is placed back in register f Words 1 Cycles 1 Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example INCF CNT 1 Before Instruction CNT OxFF 2 0 2 After Instruction CNT 0 00 2 1 1 INCFSZ Increment f skip if 0 Syntax la
5. Parameter No Sym Characteristic Min Units Conditions Fosc External CLKIN Freguency DC T 16 MHz EC osc mode PIC17C42 16 Note 1 DC 25 MHz PIC17C42 25 Oscillator Frequency DC 4 MHz RC osc mode Note 1 1 16 MHz XT osc mode 17 42 16 1 25 MHz PIC17C42 25 DC 2 MHz osc mode 1 Tosc External CLKIN Period 62 5 ns osc mode 17 42 16 Note 1 40 ns PIC17C42 25 Oscillator Period 250 ns mode Note 1 62 5 1 000 ns XT osc mode 17 42 16 40 1 000 ns PIC17C42 25 500 ns LF osc mode 2 Tcv Instruction Cycle Time Note 1 160 4 Fosc DC ns 9 TosL Clock in OSC1 High Low Time 10 ns ECoscillator TosH 4 TosR Clock in OSC1 Rise or Fall Time 5t ns ECoscillator TosF T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested t These parameters are for design guidance only and are not tested nor characterized Note 1 Instruction cycle period Tcv equals four times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in unstable oscillator operation and or higher than expected current consump
6. 1 1 1 RAS TX CK 1 1 Write to 5 i TXREG Write word 1 Write word 2 TXIF i d Interrupt flag TRMT Note Sync master mode BRG 0 Continuous transmission of two 8 bit words FIGURE 13 10 SYNCHRONOUS TRANSMISSION THROUGH TXEN DT X bio X X bi 1 X Y RA4 RX DT pin CK pin xl Write to TXREG bit 6 bit DS30412C page 94 1996 Technology Inc PIC17C4X 13 3 2 USART SYNCHRONOUS MASTER RECEPTION Once synchronous mode is selected reception is enabled by setting either the SREN RCSTA lt 5 gt bit or the CREN RCSTA lt 4 gt bit Data is sampled on the RA4 RX DT pin on the falling edge of the clock If SREN is set then only a single word is received If CREN is set the reception is continuous until CREN is reset If both bits are set then CREN takes prece dence After clocking the last bit the received data in the Receive Shift Register RSR is transferred to RCREG if it is empty If the transfer is complete the interrupt bit RCIF PIR 0 is set The actual interrupt can be enabled disabled by setting clearing the RCIE lt 0 gt bit RCIF is a read only bit which is RESET by the hardware In this case it is reset when RCREG has been read and is empt
7. 31 F Family of Devices ener rrt rentre 6 PIC14000 213 PIC16C5X 6 215 PIC16C6X PIC16C7X PIC16C8X PIC16G9XX terne tere diete teer 219 PIC17CXX FERR ccce tet ne CHR oco MI ME ME DS30412C page 226 FSR1 G General Format for Instructions 108 General Purpose RAM General Purpose RAM Bank 42 General Purpose Register GPR 32 GLINTD GOTO GPR General Purpose Register 32 Graphs vs VDD 170 200 vs VDD 5V 171 201 IOL vs VOL VDD 171 201 lot vs VOL VDD 5V nine 172 202 Maximum IDD vs Frequency External Clock 125 C to 40 C 167 197 Maximum IPD vs VDD Watchdog Disabled 168 198 Maximum IPD vs VDD Watchdog Enabled 169 199 RC Oscillator Frequency vs VDD Cext 100 pF 164 194 RC Oscillator Frequency vs VDD Cext 22 pF 164 194 RC Oscillator Frequency vs VDD Cext 300 pF 165 195 Transconductance of LF Oscillator vs VDD 166 196 Transconductance of XT Oscillator vs VDD 166 196 Typical IDD vs Frequency External Clock 25 C
8. 71 cR 72 Timer3 Select oit ttes 71 On bit DS30412C page 229 PIC17C4X Timing Diagrams Asynchronous Master Transmission Asynchronous Reception Back to Back Asynchronous Master Transmission 90 Interrupt INT TMRO Pins 26 PIC17C42 Capture 159 PIC17C42 CLKOUT and WO 156 PIC17C42 Memory Interface Read 162 PIC17C42 Memory Interface Write 161 PIC17C42 PWM Timing 159 PIC17C42 RESET Watchdog Timer Oscillator Start up Timer and Power up Timer 157 PIC17C42 0 Clock 158 17 42 2 and Clock 158 PIC17C42 USART Module Synchronous 160 PIC17C42 USART Module Synchronous Transmission 160 17 43 44 Capture Timing 188 PIC17C43 44 CLKOUT and 185 PIC17C43 44 External Clock PIC17C43 44 Memory Interface Read 191 PIC17C43 44 Memory Interfac
9. 1996 Microchip Technology Inc DS30412C page 85 PIC17C4X 13 1 USART Baud Rate Generator BRG The BRG supports both the Asynchronous and Syn chronous modes of the USART It is a dedicated 8 bit baud rate generator The SPBRG register controls the period of a free running 8 bit timer Table 18 1 shows the formula for computation of the baud rate for differ ent USART modes These only apply when the USART is in synchronous master mode internal clock and asynchronous mode Given the desired baud rate and Fosc the nearest inte ger value between 0 and 255 can be calculated using the formula below The error in baud rate can then be determined TABLE 13 1 BAUD RATE FORMULA SYNC Mode Baud Rate 0 Asynchronous Fosc 64 X 1 1 Synchronous Fosc 4 X 1 X value in SPBRG 0 to 255 Example 13 1 shows the calculation of the baud rate error for the following conditions Fosc 16 MHz Desired Baud Rate 9600 SYNC 0 EXAMPLE 13 1 CALCULATING BAUD RATE ERROR Desired Baud rate Fosc 64 X 1 9600 16000000 64 1 X E 25 042 25 Calculated Baud Rate 16000000 64 25 1 9615 Calculated Baud Rate Desired Baud Rate Desired Baud Rate 9615 9600 9600 0 16 Error Writing a new value to the SPBRG causes the BRG timer to be reset or cleared this ensures that the BRG does not for a timer overflow before outputting the new baud rate
10. 30 H3 LSVINOId PUE H3 LSVINO Id pue Sepniour KBojouuoe diyoouoip 1021 0 401420 ff 200200 120042 900900MS S00900MS 200 00 5 27911214 c00S00AQ 200200 12049 LWA LOOSOOAG 900900MS S00900MS 200 00 5 62609 04 2017914 9 200200 660 9 LOOSOOAG 900900MS S00900MS 200 00 5 7839214 20179114 0 9 200200 90229 4N 6c0 9LWN3 100600 900900MS S00900MS 200 00 5 8091014 Z0129LIN3 9 200200 62029 LOOSOOAG 900900MS S00900MS 200 00 5 839L Old 0 9 200200 162029 900900MS S00900MS 200 00 5 2299014 200S00AGd 9 200200 112029 LOOSOOAG 900900MS GO0900MS 200 00 5 11270172904 SOLZOLINA 9 200200 SO Z9LINA 112029 LOOSOOAG 900900MS S00900MS 200 00 5 1499124 S0L 9LIN3 00 9 200200 9 0 9 LWA S00900MS 200 00 5 299 27
11. D1 gt Package Group Ceramic CERDIP Dual In Line CDP Millimeters Inches Min Max Notes Min Max Notes 0 10 0 10 A 4 318 5 715 0 170 0 225 Typical Typical Typical Typical Reference Reference Reference Reference Typical Typical eB 15 240 18 034 0 600 0 710 L 3 175 3 810 0 125 0 150 N 40 40 40 40 S 1 016 2 286 0 040 0 090 51 0 381 1 778 0 015 0 070 1996 Microchip Technology Inc DS30412C page 205 PIC17C4X 21 2 40 Lead Plastic Dual In line 600 mil Pin No 1 Indicator I Area Le D gt N Plane we nU LH AAA ARE Bilis banana D1 gt Package Group Plastic Dual In Line PLA Millimeters Inches Typical Typical Typical Typical Reference Reference Typical Typical Reference Reference DS30412C page 206 1996 Microchip Technology Inc 21 3 D 0 177 007 9 8 DE A 1 27 050 2Sides 44 Lead Plastic Leaded Chip Carrier Square PIC17C4X 0 812 0 661
12. DT ei 15 99 6 NER 9 36 OvVetfloW QW 51 dod ERR UU TERRE REN 9 P Package Marking Information Packaging Information Parameter Measurement Information PG Program Courter e eU metu HE Peripheral Banks 42 Peripheral Interrupt Enable ass Peripheral Interrupt Request 24 PICDEM 1 Low Cost PIC16 17 Demo Board 143 144 PICDEM 2 Low Cost PIC16CXX Demo Board 143 144 PICDEM 3 Low Cost PIC16C9XXX Demo Board 144 PICMASTER RT In Circuit Emulator 143 Low Cost Development System 143 gi 19 34 92 96 98 Pin Compatible Devices DS30412C page 228 4 nhe ett ahah 19 34 60 PORTE 19 34 62 Power down Mode sese 105 Power on Reset POR 15 99 Power up Timer PWRT 15 99 PRar t dni 20 35 2 20 35 PR3 CA1L 35 PR3L CA L 35 Prescaler Assignments 69 PRO MATE Universal Programmer 143 enr eit pereo ee 20 PRODL ig Program Counter PC 41 Program Memory External Access Waveforms 31 Extern
13. ZHN be44 ZHI 0914 ZHI be44 ZHI 0914 ZHIN b944 peigesip LAM peigesip LAM peigesip LAM peigesip LAM peigesip LAM xeu yng gt NGS vn gt gt Xew yng dd 18 xeu 09 2 2616 ge ZzHy 12 dA aa zHx 12 9 ge 2 2616 xeu ynog aal A0 9 OL A0 9 OL ASY A09 OL ASY A0 9 1 ZHN 4 ZHIN ZHN GZ 4 XEN ZHIN 91 0914 ZHN 8 0914 pelgesip LAM LOM peigesip LAM pelgesip LAM LAM xeu AGG xeu ddl AGG xeu AGG ye xeu ddl xeu yng xew yw xew xew yw OLAS Y A0 9 OLAS Y A0 9 OL A0 9 OF ZHIN b914 Xew ZHIN beJ4 ZHI Sa 244 ZHI 91 ZHI 8 0914 peigesip LAM pelgesip LAM peigesip LAM pelgesip LAM peigesip LAM ASSI yng NGO S e xeu yng dd xeu aqg xeu yng
14. 167 197 Typical IPD vs VDD Watchdog Disabled 25 C 168 198 Typical IPD vs VDD Watchdog Enabled 25 C 169 199 Typical RC Oscillator vs Temperature 163 193 VTH Input Threshold Voltage of I O Pins vs ME 172 202 VTH Input Threshold Voltage of OSC1 Input In XT HS and LP Modes vs VDD 173 203 VTH of MCLR TOCKI and OSC1 In RC Mode vs VDD 173 203 WDT Timer Time Out Period vs VDD 170 200 H Hardware Multiplier essen 49 ned lien 64 VO PORS 53 Programming Considerations 64 Read Modify Write Instructions 64 Successive Operations 64 INGE 123 INCFSNZ 124 INGESZ irent tror e tte eee ten 123 INDFO 94 40 INDE ira eds 34 40 1996 Microchip Technology Inc PIC17C4X Indirect Addressing Indirect Addressing Operation Registers Initialization Conditions For Special Function Registers 19 Initializing PORTB eene 57 Initializing PORTO Lett cere 58 Initializing PORTD esee 60 Initializing PORTE Aine 62 Instruction Flow Pipelining 14 Instruction Set SUBWE 2
15. Max 40 C to 85 C Min 40 C to 85 C 4 5 VDD Volts DS30412C page 202 1996 Microchip Technology Inc PIC17CAX Applicable Devices 42 842 42A 43 R43 44 FIGURE 20 19 VTH of I O PINS SCHMITT TRIGGER vs VDD VIH max 40 C to 85 C a VIH typ 25 C min 40 C to 85 C VIL max 40 C to 85 C 7 VIL typ 25 C in 40 C to 85 C VDD Volts FIGURE 20 20 INPUT THRESHOLD VOLTAGE OSC1 INPUT IN XT AND LF MODES vs Max 40 C to D Min 40 C to 85 C 4 0 4 5 Volts 1996 Microchip Technology Inc DS30412C page 203 PIC17C4X NOTES DS30412C page 204 1996 Microchip Technology Inc PIC17C4X 21 0 PACKAGING INFORMATION 21 1 N 11617 40 Lead Ceramic CERDIP Dual In line and CERDIP Dual In line with Window 600 mil m Pin No 1 Indicator LS I I Area lt eB 3 CA Se 1 2 ei
16. 101 External Clock Input Operation EC OSC Configuration 101 External Parallel Resonant Crystal Oscillator Circuit 22 0 102 External Series Resonant Crystal Oscillator Circuit 102 RC Oscillator Mode 102 Watchdog Timer Block Diagram 104 Wake up From Sleep Through Interrupt 105 General Format for Instructions 108 Q Cycle 109 Parameter Measurement Information 154 External Clock Timing 155 CLKOUT and I O Timing 156 Reset Watchdog Timer Oscillator Start Up Timer and Power Up Timer Timing 157 TimerO Clock 158 Timer1 Timer2 And Timer3 Clock TIMINGS css tee regeret ee ina 158 Capture Timings 159 PWM 159 USART Module Synchronous Transmission Master Slave Timing 160 USART Module Synchronous Receive Master Slave Timing 160 Memory Interface Write Timing 161 Memory Interface Read Timing 162 Typical RC Oscillator Frequency vs Temperature 163 Typical RC Oscillator Frequency VS ERA eod
17. 2 TMR1ON 0000 0000 0000 0000 12h Bank 2 TMR3L register low byte XXXX uuuu uuuu 13h Bank 2 TMR3H register high byte XXXX uuuu uuuu 06h Unbanked CPUSTA STKAV GLINTD TO PD 11 11 11 qq 14 2 PR1 period register XXXX uuuu uuuu 15h Bank 2 PR2 Timer2 period register XXXX XXXX uuuu uuuu 16h Bank 2 PR3L CA1L Timer3 period capture1 register low byte XXXX XXXX uuuu uuuu 17h Bank 2 PR3H CA1H Timer3 period capture1 register high byte XXXX xxxx uuuu uuuu 10h Bank 3 PW1DCL DC1 DCO XMS uu 11h Bank 3 PW2DCL DC1 TM2PW2 xx0 uu0 12h Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 XXXX XXXX uuuu uuuu 13h Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu 14h Bank 3 CA2L Capture2 low byte XXXX XXXX uuuu uuuu 15h Bank 3 CA2H Capture2 high byte XXXX uuuu uuuu Legend x unknown u unchanged unimplemented read as 0 a value depends on condition shaded cells are not used by TMR1 TMR2 or TMR3 Note 1 1996 Microchip Technology Inc Other non power up resets include external reset through MCLR and WDT Timer Reset DS30412C page 81 PIC17C4X NOTES MM DS30412C page 82 1996 Technology Inc PIC17C4X 13 0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECE
18. Read TMR TMRxIF Instruction TMRx W executed Read TMRx TMRx W Read TMRx Note 1 TCLK12 is sampled in Q2 and Q4 2 4 indicates a sampling point 3 The latency from TCLK12 J to timer increment is between 2Tosc and 6Tosc DS30412C page 80 1996 Microchip Technology Inc PIC17C4X FIGURE 12 10 TMR1 TMR2 AND TMR3 OPERATION IN MODE atadasas aladadas 01030304 01030304 ailadaslad 04 aladadas 01040304 aladaaos EN 0 ame X AD15 ADO ALE 2 0 Start TMR1 L 1 1 1 MOVWF MOVF MOVF BSF 2 0 Stop TMR1 Instruction MOVLB 3 NOP fetched NOP 1 TMR1 W TMR1 W Write TMR1 Read TMR1 Read TMR1 X om X osh X on X 06h PR1 TMR1ON WR TMR1 WR TCON2 TMR1IF RD TMR1 TMR TMR1 reads 03h reads 04h TABLE 12 6 SUMMARY OF TMR1 TMR2 AND TMR3 REGISTERS Value on Value on all Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 0 Power on other resets Reset Note1 16h Bank 3 CA2ED1 CA2EDO CA1ED1 CA1EDO T16 TMR3CS TMR2CS 1 5 0000 0000 0000 0000 17h Bank 3 PWM2ON PWM1ON CA1 PR3
19. 80 TMR1 TMR2 and TMR3 Operation Timer 81 TXSTA Register Address 15h Bank 0 83 RCSTA Register Address 13h Bank 0 84 USART Transmit USART m Asynchronous Master Transmission 90 Asynchronous Master Transmission Back to Back 90 RX Pin Sampling Scheme 91 Asynchronous Reception 92 Synchronous Transmission 94 Synchronous Transmission Through 94 Synchronous Reception Master Mode SREN Configuration Word Crystal or Ceramic Resonator Operation XT or LF OSC Configuration 100 Figure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 14 7 Figure 14 8 Figure 14 9 Figure 15 1 Figure 15 2 Figure 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 Figure 17 8 Figure 17 9 Figure 17 10 Figure 17 11 Figure 17 12 Figure 18 1 Figure 18 2 Figure 18 3 Figure 18 4 Figure 18 5 Figure 18 6 Figure 18 7 Figure 18 8 Figure 18 9 Figure 18 10 Figure 18 11 Figure 18 12 Figure 18 13 Figure 18 14 Figure 18 15 Figure 18 16 Figure 18 17 Figure 18 18 Figure 18 19 Figure 18 20 Figure 19 1 Crystal Operation Overtone Crystals XT OSC Configuration
20. 17 Figure 4 3 Time Out Sequence on Power Up MCLR NOT Tied to Figure 4 4 Slow Rise Time MCLR Tied to VDD Figure 4 5 Oscillator Start Up Time Figure 4 6 Using On Chip Figure 4 7 Brown out Protection Circuit 1 Figure 4 8 PIC17C42 External Power On Reset Circuit For Slow VDD Power Up 18 Figure 4 9 Brown out Protection Circuit 2 Figure 5 1 Interrupt Logic 5 2 INTSTA Register Address 07h Uribanked enne 22 Figure 5 3 PIE Register Address 17h Bank 1 23 Figure 5 4 Register Address 16h Bank 1 24 Figure 5 5 INT Pin TOCKI Pin Interrupt Timing 26 Figure 6 1 Program Memory Map and Stack 29 Figure 6 2 Memory Map in Different Modes 30 Figure 6 3 External Program Memory Access Waveforms essen 31 Figure 6 4 Typical External Program Memory Connection 31 Figure 6 5 PIC17C42 Register File 33 Figure 6 6 PIC17CR42 42A 43 R43 44 Register File tiere nennen nnne 33 Figure 6 7 ALUSTA Register Address 04h Unbanked ss 36 Figure 6 8 CPUSTA Register Address 06h Unbanked nne 37 Figure 6
21. LNI OVY IMOOL L VH S Ivu3Hdld3d JINON wL 1HOd lVIH3S MO X L sVH lQ Xu vvH VH INI 0VH 284 984 lt 8 gt sna viva lt 0 2 gt 14 9 X10 L 68H L r8H eINMd c8H 4 4 lt 91 gt HOLV1 NO lt 91 gt 1 1 3aooaa 0854 8 8114110 10HLNO9 NOILONYLSNI lt 91 gt 1 lt 8 gt viva 4933318 3Ovds VIVO NI Q3ddviw 5 151944 HOS 31lHWOvad 0 2 SN lt 8 gt lt 94 gt Sna ul lt 91 gt 1996 Microchip Technology Inc DS30412C page 10 PIC17C4X PIC17CR42 42A 43 R43 44 BLOCK DIAGRAM 2 FIGURE 3 1924135 AGOW 1531 YAWIL dNLYVLS 250 13599 NO H3MOd YOLVYHANAS 39019 SIVNOIS JOHINOO 31HOd 30 HM
22. TABLE 13 9 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 16h Bank 1 PIR RBIF TMRAIF 2 TMR1IF CA2IF CA1IF 0000 0010 0000 0010 13h RCSTA SPEN RX9 SREN CREN FERR RX9D 0000 00x 0000 00u 16h BankO TXREG TX7 TX6 TX5 TX3 TX2 TX1 TX0 XXXX uuuu uuuu 17h Bank 1 PIE RBIE 2 CA2IE TXIE RCIE 0000 0000 0000 0000 15h BankO TXSTA CSRC TX9 TXEN SYNC TRMT TX9D 0000 1x 0000 1u 17h SPBRG Baud rate generator register XXXX XXXX uuuu uuuu Legend unknown u unchanged unimplemented read as a 0 shaded cells are not used for synchronous slave transmission Note 1 Other non power up resets include external reset through MCLR and Watchdog Timer Reset TABLE 13 10 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note 16h Bank1 PIR RBIF TMRSIF TMR2IF TMR1IF CA2IF TXIF RCIF 0000 0010 0000 0010 13h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00u 14h RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 uuuu uuuu 17h Bank1 PIE RBIE 2 CA2IE TXIE RCIE 0000
23. lt 8 gt VIVO NI 693151099 401 3dooaa 31IHWQV3H lt 0 2 gt SN4 ul lt gt 8 x 8 __ lt 94 gt SNG ul lt 94 gt DS30412C page 11 1996 Microchip Technology Inc PIC17C4X TABLE 3 1 PINOUT DESCRIPTIONS Name NO oe pid Nos Description OSC1 CLKIN 19 21 37 ST Oscillator input crystal resonator or RC oscillator mode External clock input in external clock mode OSC2 CLKOUT 20 22 38 O Oscillator output Connects to crystal or resonator in crystal oscillator mode In RC oscillator or external clock modes OSC2 pin outputs CLKOUT which has one fourth the fre quency of OSC1 and denotes the instruction cycle rate MCLR VPP 32 35 7 ST Master clear reset input Programming Voltage VPP input This is the active low reset input to the chip PORTA is a bi directional I O Port except for RAO and RA1 which are input only RAO INT 26 28 44 ST RAO INT can also be selected as an external interrupt input Interrupt can be configured to be on positive or negative edge 1 25 27 43 ST 1 can also be selected as an external interrupt input and the interrupt can be configured to be on posi tive or negative edge RA1 TOCKI can also be selected to be the clock
24. 1996 Microchip Technology Inc DS30412C page 101 PIC17C4X 14 24 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built Prepack aged oscillators provide a wide operating range and better stability A well designed crystal oscillator will provide good performance with TTL gates Two types of crystal oscillator circuits can be used one with series resonance or one with parallel resonance Figure 14 5 shows implementation of a parallel reso nant oscillator circuit The circuit is designed to use the fundamental frequency of the crystal The 74AS04 inverter performs the 180 degree phase shift that a par allel oscillator requires The 4 7 resistor provides the negative feedback for stability The 10 potentiometer biases the 74AS04 in the linear region This could be used for external oscillator designs FIGURE 14 5 EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other Devices 4 7 74 804 PIC17CXX 74AS04 OSC1 Figure 14 6 shows a series resonant oscillator circuit This circuit is also designed to use the fundamental fre quency of the crystal The inverter performs a 180 degree phase shift in a series resonant oscillator circuit The 330 kO resistors provide the negative feed back to bias the inverters in their linear region FIGURE 14 6 EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR
25. TOSE 4 TOSTA lt 6 gt 05 lt 5 gt TOSTA lt 4 1 gt Prescaler output PSOUT Sampled Prescaler FIGURE 11 3 TMRO TIMING WITH EXTERNAL CLOCK INCREMENT ON FALLING EDGE ge ae en a output Increment TMRO TMRO Note 1 The delay from the TOCKI edge to the TMRO increment is 3Tosc to 7Tosc 2 1 PSOUT is sampled here 3 The PSOUT high time is too short and is missed by the sampling circuit DS30412C page 68 1996 Microchip Technology Inc PIC17CAX 11 3 Read Write Consideration for TMRO Although TMRO is a 16 bit timer counter only 8 bits at a time can be read or written during a single instruction cycle Care must be taken during any read or write 11 31 READING 16 BIT VALUE The problem in reading the entire 16 bit value is that after reading the low or high byte its value may change from FFh to Example 11 1 shows a 16 bit read To ensure a proper read interrupts must be disabled during this routine EXAMPLE 11 1 16 BIT READ MOVPF TMROL TMPLO MOVPF TMROH TMPHI MOVFP TMPLO WREG tmplo gt wreg CPFSLT TMROL tmrOl lt wreg RETURN then return MOVPF TMROL TMPLO read low tmr0 MOVPF TMROH TMPHI read high tmr0 RETURN return read low read high tmr0 11 3 2 WRITING A 16 BIT VALUE TO TMRO Since writing to either TMROL or TMROH will eff
26. Frequency 2 2 Rs of 3300 is required for a capacitor com LF 455 kHz 15 68 pF bination of 15 15 pF 2 0 MHz 10 33 pF 3 Only the capacitance of the board was present XT 4 0 MHz 22 68 pF Crystals Used 8 0 MHz 33 100 pF 5 16 0 MHz 33 100 pF 32 768 kHz Epson C 001R32 768K A 20 PPM E 1 0 MHz ECS 10 13 1 50 PPM Higher capacitance increases the stability of the oscillator but also increases the start up time These 2 0 MHz ECS 20 20 1 50 PPM values are for design guidance only Since each reso 4 0 MHz 5 40 20 1 50 PPM nator has its own characteristics the user should 8 0 MHz ECS ECS 80 S 4 50 PPM consult the resonator manufacturer for appropriate ECS 80 18 1 values of external components 16 0 MHz ECS 160 20 1 TBD Resonators Used 25 MHz CTS CTS25M 50 PPM 455 kHz Panasonic EFO A455K04B 0 396 32 MHz CRYSTEK HF 2 50 PPM 2 0 MHz Murata Erie CSA2 00MG t 0 5 1423 EXTERNAL CLOCK OSCILLATOR 4 0MHz Murata Erie CSA4 00MG t 0 596 8 0 MHz Murata Erie CSA8 00MT 0 5 In the EC oscillator mode the OSC1 input can be driven by CMOS drivers In this mode the 16 0 MHz 16 00 t 0 5 a 2 saa i ilti it OSC1 CLKIN pin is hi impedance and the OSC2 CLK esonators used did not have built in capacitors OUT pin is the CLKOUT output 4 Tosc FIGURE 14 4 EXTERNAL CLOCK INPUT OPERATION EC OSC CONFIGURATION Clock from OSC1 ext system PIC17CXX CLKOUT OSC2 Fosc 4
27. io port t123 TCLK12 mc MCLR wdt Watchdog Timer oe OE wr WR os OSC1 Uppercase symbols and their meanings Driven Low Edge Period Fall Rise High Valid Invalid Hi impedance Hi impedance 1996 Microchip Technology Inc DS30412C page 153 PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 17 1 PARAMETER MEASUREMENT INFORMATION All timings are measure between high and low measurement points as indicated in the figures below INPUT LEVEL CONDITIONS PORTO D and E pins 2 4V X X i Data in valid a All other input pins Data in invalid VIH 0 9VDD 0 1VDD a Data in valid ist Data in invalid OUTPUT LEVEL CONDITIONS VOH 0 7VDD VDD 2 VoL 0 3VDD Data out valid i testi en Data out invalid Output hi impedance 0 1VDD X X EUM e Fall Time LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD 2 RL 464 lt 50 DS30412C page 154 1996 Technology Inc PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 174 Timing Diagrams and Specifications FIGURE 17 2 EXTERNAL CLOCK TIMING OSC2 T T In EC and RC modes only TABLE 17 2 EXTERNAL CLOCK TIMING REQUIREMENTS
28. pue 19e104d epoo aiqejoajas aw BopuoreM L 9 Old 9 89 d3OL 5 9 9 0 OHNLL 26 910 9 9 3401 5 9 9 0 626991019 sounyeo4 0830412 219 1996 Microchip Technology Inc PIC17C4X PIC17CXX Family of Devices 8 upiqedeo 1ueuno pue 1284019 epoo Jaw L 9LOId IIV 4301 997d 9 did uid or HIAL ZHIALL vr9 191d dAON 4301 9 did told dAON 4301 9 did EvOLLOld dAON 4301 9 did 1 2 dAON 4301 9 did VevoZLlold d40N 99714 did HHIAL OHIALL SoJnjeeJ 91 1996 Microchip Technology Inc DS30412C page 220 PIC17C4X PIN COMPATIBILITY Devices that have the
29. 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this data sheet easy to follow If not why 4 What additions to the data sheet do you think would enhance the structure and subject 5 What deletions from the data sheet could be made without affecting the overall usefulness 6 Isthere any incorrect or misleading information what and where 7 How would you improve this document 8 How would you improve our software systems and silicon products DS30412C page 236 1996 Microchip Technology Inc PIC17C4X Product Identification System PIC17CAX To order or to obtain information e g on pricing or delivery please use the listed part numbers and refer to the factory or the listed sales offices PART NO XX X XX XXX Examples Pattern QTP SQTP ROM Code factory specified or 17 42 16 P Special Requirements Blank for OTP and Commercial Temp Windowed devices PDIP package Package P PDIP 16 MHZ JW Windowed CERDIP normal VDD limits P lt PDIP 600 mil PQ b PIC17LC44 08 PT Commercial L PLCC Temperature 0 C to 70 C 8MHz Range I 40 C to 85 C extended VDD limits Frequency 08 8 2 PIC17C43 25 16 16 MHz i Industrial Tem 25 25 Mhz 33 33 2
30. VIH 0 9VDD X 0 1VDD a c Data in valid ist Data in invalid OUTPUT LEVEL CONDITIONS 0 7VDD VDD 2 VoL 0 3VDD AM Data out valid GPU TS i i riven Data out invalid Output hi impedance 0 1 X PME gt e Rise Time lt Fall Time LOAD CONDITIONS Load Condition 1 50 lt CL 1996 Microchip Technology Inc DS30412C page 183 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 19 5 Timing Diagrams and Specifications FIGURE 19 2 EXTERNAL CLOCK TIMING OSC2 T T In EC and RC modes only TABLE 19 2 EXTERNAL CLOCK TIMING REQUIREMENTS Param No Sym Characteristic Min Max Units Conditions Fosc External CLKIN Frequency DC 8 MHz osc mode 08 devices 8 MHz devices Note 1 DC 16 MHz 16 devices 16 MHz devices DC 25 MHz 25 devices 25 MHz devices DC 33 MHz 83 devices 33 MHz devices Oscillator Frequency DC 4 MHz RC osc mode Note 1 1 8 MHz XT osc mode 08 devices 8 MHz devices 1 16 MHz 16 devices 16 MHz devices 1 25 MHz 25 devices 25 MHz devices 1 33 MHz 33 devices 33 MHz devices DC 2 MHz LF osc mode 1 Tosc External Period 125 ns osc mode 08 devices 8 MHz devices Note 1 62 5
31. cese 136 SWAPF TSTFSZ 140 XORLW 141 XORWE 12222222221 141 Instruction Set Summary 107 ner e ee entes 26 22 INTEDG ttt 38 67 Interrupt on Change Feature 55 Interrupt Status Register 22 Interrupts Context Saving 27 Flag bits iiti n uere er redo ere tr odi tandis TMR2IE nico Qni Interrupts era either ncm teet S Operation Peripheral Interrupt Enable 23 Peripheral Interrupt Request 24 PWM Status Register endete 22 Table Write Interaction 45 TIMING iei oen erre rn 26 Vectors Peripheral Interrupt 26 RAO INT Interrupt TOGKI Interrupt tenes TMRO Interrupt Vectors Priorities Wake up from SLEEP 105 at ho MEE ERE 22 INTS TA enr nr nee Nr nn nr 34 INTSTA Register 22 IOREW 124 IORWE treten t ee
32. PWM2ON PWM10ON CA1 PR3 2 TMR1ON 0000 0000 0000 0000 10h Bank 2 TMR1 Timer1 register XXXX XXXX uuuu uuuu 11h Bank 2 TMR2 Timer2 register XXXX XXXX uuuu uuuu 16h Bank 1 PIR RBIF TMRSIF TMR2IF TMR1IF TXIF 0000 0010 0000 0010 17h Bank 1 PIE RBIE TMRSIE TMR2IE TMR1IE CA2IE 0000 0000 0000 0000 07h Unbanked INTSTA PEIF TOCKIF TOIF INTF PEIE TOIE INTE 0000 0000 0000 0000 06h Unbanked CPUSTA STKAV GLINTD TO PD 11 11 11 qq 14h Bank 2 PR1 Timer1 period register XXXX XXXX uuuu uuuu 15h Bank 2 PR2 Timer2 period register XXXX XXXX uuuu uuuu 10h Bank 3 PW1DCL DC1 DCO xx Peste ee 11h Bank 3 PW2DCL DC1 DCO TM2PW2 xx0 uu0 12h Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC2 XXXX uuuu uuuu 13h Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC2 XXXX XXXX uuuu uuuu Legend x unknown u unchanged unimplemented read as a 0 value depends on condition shaded cells are not used by Timer1 or Timer2 Note 1 Other non power up resets include external reset through MCLR and WDT Timer Reset DS30412C page 74 1996 Microchip Technology Inc PIC17C4X 12 1 3 USING PULSE WIDTH MODULATION FIGURE 12 5 SIMPLIFIED PWM BLOCK PWM OUTPUTS WITH TMR1 AND TMR2 DIAGRAM Two high speed pu
33. 137 GI peni I RE pe i 83 Synchronous Master Mode 93 Synchronous Master Reception 95 Synchronous Master Transmission 93 Synchronous Slave 97 T 26 TOCKIE TOCKIF TOCS Table Latch Table Pointer Table Read Example 48 Odd 43 Table Reads Section 48 TABLRD Operation sese 44 48 48 TRD Operation 44 Table Write e P Interaction Section essen nennen TABLWT Operation Terminating Long Writes 45 TIMING E TLWT Operation To External Memory 46 To Internal Memory 45 TABLRD TABLWT TBEPTBE ttes canteens 34 40 TCLK12 Terminating Long Writes 45 Time Out Sequence 16 Timer Resources Timer 16 bit ttt eo Clock Source Select bit Section Timer2 16 bit Mode oret eo etes 74 Clock Source Select
34. Example 9 3 shows the instruction sequence to initial ize PORTD The Bank Select Register BSR must be selected to Bank 1 for the port to be initialized EXAMPLE 9 3 INITIALIZING PORTD MOVLB 1 Select Bank 1 CLRF PORTD Initialize PORTD data latches before setting H the data direction register MOVLW Value used to initialize data direction MOVWF DDRD Set RD lt 3 0 gt as inputs RD lt 5 4 gt as outputs RD lt 7 6 gt as inputs FIGURE 9 7 PORTD BLOCK DIAGRAM IN 1 0 PORT MODE to D Bus IR INSTRUCTION READ Data Bus Input RD PORTD WR PORTD RD DDRD WR DDRD EX EN DATA ADDR OUT SYS BUS SYS Control Note I O pins have protection diodes to VDD and Vss DS30412C page 60 1996 Microchip Technology Inc PIC17C4X TABLE 9 7 PORTD FUNCTIONS Name Bit Buffer Type Function RDO AD8 bitO TTL Input Output or system bus address data pin RD1 AD9 bit TTL Input Output or system bus address data pin RD2 AD10 bit2 TTL Input Output or system bus address data pin RD3 AD1 1 bit3 TTL Input Output or system bus address data pin RD4 AD12 bit4 TTL Input Output or system bus address data pin RD5 AD13 bit5 TTL Input Output or system bus address data pin RD6 AD14 bit6 TTL Input Output or system bus address data pin RD7
35. PIC17CXX Instruction Set development tools from 146 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation Commercial Devices 148 External Clock Timing Requirements 155 CLKOUT and Timing Requirements 156 Reset Watchdog Timer Oscillator Start Up Timer and Power Up Timer Requirements 157 0 Clock Requirements 158 Timer1 Timer2 and Timer3 Clock Requirement Capture Requirements E PWM Requirements 1996 Microchip Technology Inc DS30412C page 233 PIC17C4X Table 17 9 Serial Port Synchronous Transmission Requirements 160 Table 17 10 Serial Port Synchronous Receive Requirements 160 Table 17 11 Memory Interface Write Requirements 161 Table 17 12 Memory Interface Read Requirements 162 Table 18 1 Pin Capacitance per Package 163 Table 18 2 Oscillator Frequencies 165 Table 19 1 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation Commercial Devices 176 Table 19 2 External Clock Timing Requirements 184 Table 19 3 CLKOUT and I O Timing Requirements 185 Table 19 4 Reset Watchdog Timer Oscillator Start Up Timer and Pow
36. RCIE 0000 0000 0000 0000 16h Bank 3 1 CA2ED1 2 0 CA1ED1 CA1EDO T16 TMR2CS TMR1CS 0000 0000 0000 0000 17h Bank 3 TCON2 PWM2ON PWM1ON CA1 PR3 TMR3ON TMR2ON 1 0000 0000 0000 0000 Legend x unknown u unchanged unimplemented read as 0 q Value depends on condition Shaded cells are not used by PORTB Note 1 Other non power up resets include external reset through MCLR and the Watchdog Timer Reset 1996 Microchip Technology Inc DS30412C page 57 PIC17CAX 9 3 PORTC and DDRC Registers PORTO is an 8 bit bi directional port The correspond ing data direction register is DDRC A 1 in DDRC con figures the corresponding port as an input A in the DDRC register configures the corresponding port pin as an output Reading PORTC reads the status of the pins whereas writing to it will write to the port latch PORTC is multiplexed with the system bus When operating as the system bus PORTO is the low order byte of the address data bus AD7 ADO The timing for the system bus is shown in the Electrical Characteris tics section Note This port is configured as the system bus when the device s configuration bits are selected to Microprocessor or Extended Microcontroller modes In the two other microcontroller modes this port is a gen eral purpose I O Example 9 2 shows the instruction sequence to initial
37. ns 16 devices 16 MHz devices 40 ns 25 devices 25 MHz devices 30 3 ns 33 devices 33 MHz devices Oscillator Period 250 ns osc mode Note 1 125 1 000 ns XT osc mode 08 devices 8 MHz devices 62 5 1 000 ns 16 devices 16 MHz devices 40 1 000 ns 25 devices 25 MHz devices 30 3 1 000 ns 33 devices 33 MHz devices 500 ns LF osc mode 2 Tcv Instruction Cycle Time 121 2 4 Fosc DC ns Note 1 3 TosL Clock in OSC1 10 ns oscillator TosH high or low time 4 TosR Clock 05 1 5t ns EC oscillator TosF rise or fall time 1 Data in column is 5V 25 unless otherwise stated These parameters are for design guidance only and are not tested These parameters are for design guidance only and are tested nor characterized Note 1 Instruction cycle period Tcv equals four times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current con sumption devices are tested to operate at min values with an external clock applied to the OSC1 CLKIN pin When an external clock input is used the cycle time limit is no clock for all devices
38. 1996 Microchip Technology Inc DS30412C page 214 PIC17C4X PIC16CXXX Family of Devices E 3 pue jenas esn 9 91 214 uano Oll uiu pue 19e1oJd 8 qE199 9S OUI L 2481295 UO J9MOdg S89IA6D lluie4 ZL 9LOld 4055 utd 0z 9105 did 9 81 79 6 229291014 dOSS uid 02 2105 did 9 1 9 6 14929214 4055 uid 02 2105 9 1 9 6 029291014 4055 utd 0z 9105 9 81 79 6 866091014 dOSS uid 02 2105 9 1 9 6 999091019 4088 9 0 0105 9 1 9 6 799991019 SeJnjee DS30412C page 215 1996 Microchip Technology Inc PIC17C4X PIC16C6X Family of Devices E 4 S891A8p S U JO 10 Sales 220 1081002 esee d SION ejep pue jenas asn Arwe X929 LOld piqedeo juano pue 32910Jd epoo 95 Aurel L 9 ddO L dJON 001d 9 did 9 0 45401 d40N 001d U d py dig 9 0 l1uvsf Ozl IdS 14 5 4 5 CHL CULL 9 0 8909101 d40N
39. 6 0 mA VDD 4 5V Note 6 RA2 12 V jPulled up to externally applied voltage OSC2 CLKOUT 2 4 V 5 mA VDD 4 5V RC and EC osc modes Capacitive Loading Specs on Output Pins OSC2 pin 25 tt pF In EC or RC osc modes when OSC2 pin is outputting CLKOUT External clock is used to drive OSC1 All pins OSC2 50 tt pF in RC mode System Interface Bus 10011 pF Microprocessor or PORTD Extended Microcontroller mode T These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested These parameters are for design guidance only and are tested nor characterized Tf Design guidance to attain the AC timing specifications These loads are not tested Note 1 In RC oscillator configuration the OSC1 pin is a Schmitt Trigger input It is not recommended that the PIC17CXX devices be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 These specifications are for the programming of the on chip program memory EPROM through the use of the table write instructions The complete p
40. Write to TXREG 5 Word 1 Word 2 2 BRG output org shift clock RAS TXICK pin SN Start Bit X S6 X Bit 787 Stop Bit Start lt 7 Bt0 I Word 1 2 TXIF bit T aI 55 Word 1 Word 2 gt Transmit Shift Reg ues TRMT bit Transmit Shift Reg Note This timing diagram shows two consecutive transmissions TABLE 13 5 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 16h Bank 1 PIR RBIF TMR2IF TMR1IF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010 13h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00u 16h TXREG Serial port transmit register XXXX XXXX uuuu uuuu 17h Bank 1 PIE RBIE TMRSIE TMR2IE TMR1IE CA2IE TXIE RCIE 0000 0000 0000 0000 15h BankO TXSTA CSRC TX9 TXEN SYNC TRMT TX9D 0000 1x 0000 1u 17h SPBRG Baud rate generator register uuuu uuuu Legend x unknown u unchanged unimplemented read as a 0 shaded cells are not used for asynchronous transmission Note 1 Other non power up resets include external reset through MCLR and Watchdog Timer Reset DS30412C page 90
41. snid LYVLSOld 917 LHVLSOId 1 01933 YALSVINOId 22 avid yONPOld 1996 Microchip Technology Inc DS30412C page 146 PIC17C4X Applicable Devices 42 R42 42A 43 43 44 17 0 PIC17C42 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings T Ambient temperature under ert erre a er e re xe 55 to 125 C Storage temperature onte rec idt das ueste dicet 65 C to 150 C Voltage on VDD with respect to VSS iii 0 to 7 5V Voltage on MCLR with respect to VSS Note 2 0 6V to 14V Voltage on RA2 and RAS with respect to VS 0 6V to 12 Voltage on all other pins with respect to 55 0 6V to VDD 0 6V Total power dissipation Note T 1 0W Maximum current out of VSS pin S Total ede oi eee 250 mA Maximum current into VDD pin s LE FE c ERE 200 mA Input clamp current VI lt or VI gt VDD eee 220 mA Output clamp current IOK VO lt 0 or VO gt 320 mA Maximum output current sunk by any I O pin except RA2 and RA3G 35 mA Maximum output current sunk by RA2 or pins sise 60 mA Maximum output current sourced by I O pin siennes 20 mA Maximum current su
42. 0 5Tcy 45 ns OE low to Data Valid These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 5 This specification ensured by design 1996 Microchip Technology Inc DS30412C page 191 PIC17C4X NOTES DS30412C page 192 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 42 42 43 R43 44 20 0 PIC17CR42 42A 43 R43 44 DC AND AC CHARACTERISTICS The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed In some graphs or tables the data presented is outside specified operating range e g outside specified range This is for information only and devices are ensured to operate properly only within the specified range The data presented in this section is a statistical summary of data collected on units from different lots over a period of time Typical represents the mean of the distribution while max or min represents mean 3o and mean 3 respectively where o is standard deviation TABLE 20 1 PIN CAPACITANCE PER PACKAGE TYPE Typical Capacitance pF 40 pin DIP 44 pin PLCC 44 pin MQFP 44 pin TQFP Pin Name All pins except MCLR 10 10 10 10 VDD and Vss MCLR pin 20 20 20 20 FIGURE 20 1 TYPICAL RC OSCILLATOR FREQUENCY vs TEMPERATURE Fosc
43. 1996 Microchip Technology Inc DS30412C page 41 PIC17C4X 6 8 Bank Select Register BSR The BSR is used to switch between banks in the data memory area Figure 6 13 In the PIC17C42 PIC17CR42 and PIC17C42A only the lower nibble is implemented While in the PIC17C43 PIC17CR43 and 17 44 devices the entire byte is implemented The lower nibble is used to select the peripheral regis ter bank The upper nibble is used to select the general purpose memory bank All the Special Function Registers SFRs are mapped into the data memory space In order to accommodate the large number of registers a banking scheme has been used A segment of the SFRs from address 10h to address 17h is banked The lower nibble of the bank select register BSR selects the currently active peripheral bank Effort has been made to group the peripheral registers of related functionality in one bank However it will still be necessary to switch from bank to bank in order to address all peripherals related to a single task To assist this MOVLB bank instruction is in the instruction set FIGURE 6 13 BSR OPERATION PIC17C43 R43 44 Address For the PIC17C43 PIC17CR43 and PIC17C44 devices the need for a large general purpose memory space dictated a general purpose RAM banking scheme The upper nibble of the BSR selects the cur rently active general purpose RAM bank To assist this a MOVLR bank instruction has
44. Parameter No Sym Characteristic Min Typt Max Units Conditions Output Low Voltage D080 VoL ports except RA2 IOL VDD 1 250 mA 0 1VDD V 4 5 lt lt 6 0 0 1Vbb V VDD 2 5V D081 with TTL buffer 0 4 V 6 mA VDD 4 5V Note 6 D082 RA2 and RA3 3 0 V 101 60 0 mA VDD 6 0V D083 OSC2 CLKOUT 0 4 V loi 1 mA VDD 4 5V 0084 and EC osc modes 0 1VDD V VDD 5 mA PIC17LC43 LC44 only Output High Voltage Note 3 D090 I O ports except RA2 VDD 2 500 mA 0 9VDD V 14 5 VDD lt 6 0 0 9 V 2 5 0091 with 2 4 6 0 mA VpD 4 5V Note 6 0092 RA2 12 V Pulled up to externally applied voltage D093 OSC2 CLKOUT 2 4 V 5 mA VDD 4 5V 0094 and EC osc modes 0 9VDD VDD 5 mA PIC17LC43 LC44 only Capacitive Loading Specs on Output Pins D100 Cosc2 OSC2 CLKOUT pin 25 pF In EC or RC osc modes when OSC2 pin is outputting CLKOUT external clock is used to drive OSC1 D101 I O pins and OSC2 50 pF in RC mode D102 System Interface Bus 50 pF Microprocessor PORTD Extended Microcontroller mode These parameters characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated T
45. eint inten sd ection eats 34 Example 8 1 8x8 Multiply Routine Example 8 2 8 x 8 Signed Multiply Routine 49 X Example 8 3 16 x 16 Multiply Routine 50 Example 8 4 16 x 16 Signed Multiply Routine ce LAE 141 Example 9 1 Initializing Br XORWF LS a 141 Example 9 2 Initializing 58 Example 9 3 Initializing PORTD Example 9 4 Initializing PORTE 62 Z Example 9 5 Read Modify Write Instructions on an Pott niter die 64 rta ueste 9 36 Example 11 1 16 Bit Read 69 9 Example 11 2 16 Bit 69 Example 12 1 Sequence to Read Capture 78 Example 12 2 Writing to TMRS Example 12 3 Reading from Example 13 1 Calculating Baud Rate Error Example F 1 PIC17C42 to Sleep LIST OF FIGURES Figure 3 1 PIC17C42 Block Diagram 10 Figure 3 2 PIC17CR42 42A 43 R43 44 Block Diagrami treten tente Figure 3 3 Clock Instruction Cycle Figure 4 1 Simplified Block Diagram of On chip Reset 15 Figure 4 2 Time Out Sequence on Power Up MCLR Tied to
46. PIC17C43T 08JW MICROCHIP 7 High Performance 8 Bit CMOS EPROM ROM Microcontroller Devices included in this data sheet Pin Diagram Pr PDIP CERDIP Windowed CERDIP e PIC17C42A RDO AD8 PICI7C43 m PIC17CR43 RC2 AD2 lt gt lt RD3 AD11 RC3 AD3 gt RD4 AD12 PIC17C44 RC4 AD4 lt RD5 AD13 RC5 AD5 4 RD6 AD14 7C42T RC6 AD6 lt 2 lt RD7 AD15 RC7 AD7 gt Q MCLR VPP Microcontroller Core Features PEU er RB1 CAP2 4 RE1 OE Only 58 single word instructions to learn RB2 PWM1 lt gt lt gt RE2 WR RB3 PWM2 lt TEST All single cycle instructions 121 ns except for RB4 TCLK12 RAO INT program branches and table reads writes which tie pan are two cycle RB7 RAS OSC1 CLKIN RA4 RX DT Operating speed OSC2 CLKOUT lt RAS TX CK DC 33 MHz clock input DC 121 ns instruction cycle e TMR2 8 bit timer counter Program Memory Tips 16 bit timer counter Device Data Memory Universal Synchronous Asynchronous Receiver EPROM ROM Transmitter USART SCI PIC17CR42 2K 232 Special Microcontroller Features PIC17C42A B 232 Power on Reset POR Power up Timer PWRT PIC17C43 4K 454 and Oscilla
47. PR3L CA1L Set Comparator x16 lt 6 gt Capture1 Enable Edge select CA2H prescaler select pe RB1 CAP2 Set CA2IF PIR lt 3 gt CA2ED1 CA2EDO TCON1 lt 7 6 gt DS30412C page 78 1996 Microchip Technology Inc PIC17C4X 12 2 2 DUAL CAPTURE REGISTER This mode is selected by setting CA1 PR3 A block dia gram is shown in Figure 12 8 In this mode TMR3 runs without a period register and increments from 0000h to FFFFh and rolls over to 0000h The TMR3 interrupt Flag TMRSIF is set on this roll over The TMRSIF bit must be cleared in software Registers and PR3L CA1L make a 16 bit capture register Capture1 It captures events on pin RBO CAP1 Capture mode is configured by the CA1ED1 and CA1EDO bits Capture1 Interrupt Flag bit is set on the capture event The corresponding interrupt mask bit is CA1IE The Capture Overflow Status bit is CA1OVF The Capture2 overflow status flag bit is double buff ered The master bit is set if one captured word is already residing in the Capture2 register and another event has occurred on the RB1 CA2 pin The new event will not transfer the TMR3 value to the capture register which protects the previous unread capture value When the user reads both the high and the low bytes in any order of the Cap
48. DS30412C page 184 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 42 42 43 843 44 FIGURE 19 3 CLKOUT AND I O TIMING Pin input Pin output old value new value T In EC and RC modes only TABLE 19 3 CLKOUT AND I O TIMING REQUIREMENTS Parameter No Sym Characteristic Min Typt Max Units Conditions 10 TosH2ckL 5 1 to CLKOUTL 154 30 ns Note 1 11 TosH2ckH OSC1 to CLKOUTT 153 30 ns Note 1 12 TckR CLKOUT rise time 54 154 ns Note 1 13 TckF CLKOUT fall time 5t 15 ns Note 1 14 TckH2ioV CLKOUT f to Port PIC17CR42 42A 43 0 5 204 ns Note 1 out valid R43 44 PIC17LCR42 42A 43 0 5Tcy 504 ns Note 1 R43 44 15 TioV2ckH Port in valid before PIC17CR42 42A 43 0 25 254 ns Note 1 CLKOUTT R43 44 PIC17LCR42 42A 43 0 25TcY 504 ns Note 1 R43 44 16 TckH2iol Port in hold after CLKOUTT 0 ns Note 1 17 TosH2ioV OSC1 Q1 cycle to Port out valid 100 ns 18 TosH2iol OSC1 Q2 cycle to Port input invalid 04 ns I O in hold time 19 TioV2osH Port input valid to OSC14 30 ns I O in setup time 20 TioR Port output rise time 10 351 5 21 TioF Port output fall time 10 351 5 22 TinHL INT pin high or low time 25 E ns 23 TrbHL RB7 RB0 change INT high or
49. Debug using source files absolute listing file Transfer data dynamically via DDE soon to be replaced by OLE Run up to four emulators on the same PC The ability to use MPLAB with Microchip s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools 16 10 Assembler MPASM The MPASM Universal Macro Assembler is a PC hosted symbolic assembler It supports all microcon troller series including the PIC12C5XX PIC14000 PIC16C5X PIC16CXXX and PIC17CXX families MPASM offers full featured Macro capabilities condi tional assembly and several source and listing formats It generates various object code formats to support Microchip s development tools as well as third party programmers DS30412C page 144 1996 Microchip Technology Inc PIC17C4X MPASM allow full symbolic debugging from Microchip Universal Emulator System PICMASTER MPASM has the following features to assist in develop ing software for specific use applications Provides translation of Assembler source code to object code for all Microchip microcontrollers Macro assembly capability Produces all the files Object Listing Symbol and special required for symbolic debug with Microchip s emulator systems Supports Hex default Decimal and Octal source and listing formats MPASM provides a
50. 0 1234 2 The contents is written to the program memory location After Instruction table write completion pointed to by TBLPTR REG 0x55 If TBLPTR points to external TBLATH 0x12 program memory location then TBLATL 0x34 the instruction takes two cycle TBLPTR 0 56 If TBLPTR points to an internal MEMORY TBLPTR 0x1234 EPROM location then the instruction is terminated when an interrupt is received Note MCLR VPP pin must be at the programming voltage for successful programming of internal memory If MCLR VPP VDD the programming sequence of internal memory will be executed but will not be successful although the internal memory location may be disturbed 3 The TBLPTR can be automati cally incremented 0 TBLPTR is not incremented l i 1 TBLPTR is incremented Words 1 Cycles 2 many if write is to on chip EPROM program memory Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register TBLATH or TBLATL EE I Cue DE RS ua B c Ic I MM DS30412C page 138 1996 Microchip Technology Inc PIC17C4X TABLWT Table Write TLRD Table Latch Read 1 TABLWT 0 1 REG Syntax abel TLRD tf Before Instruction Operands 0 lt 1 lt 255 0x53 te 0 1 S Operation Ift 0 TBLATL 0x55 TBLATL gt f TBLPTR 0 356 EL MEMORY TBLPTR Ox
51. 0 1 Operation If t 0 f B TBLATL 1 f TBLATH Status Affected None Encoding 1010 Oltx ffff ffff Description Data from file register is written into the 16 bit table latch TBLAT If t 1 high byte is written If t 0 low byte is written This instruction is used in conjunction with TABLWT to transfer data from data memory to program memory Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register TBLATH or TBLATL Example TLWT t RAM Before Instruction t 0 RAM OxB7 TBLAT 0x0000 0x00 TBLATL 0x00 After Instruction RAM OxB7 TBLAT 0x00B7 TBLATH 0x00 TBLATL 0xB7 Before Instruction t 1 RAM OxB7 TBLAT 0x0000 TBLATH 0x00 TBLATL 0x00 After Instruction RAM OxB7 TBLAT 0xB700 TBLATH 0xB7 TBLATL 0x00 TSTFSZ Test f skip if 0 Syntax label TSTFSZ f Operands lt lt 255 Operation skip if f 0 Status Affected None Encoding 0011 0011 ffff Description If f 2 0 the next instruction fetched during the current instruction execution is discarded and an NOP is executed making this a two cycle instruction Words 1 Cycles 1 2 Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register f If skip Q1 Q2 Q3 Q4 Forced Execute Example HERE TSTFSZ NZERO ZERO Before Instruction PC Address HERE Afte
52. 2 AND BLOCK FIGURE 9 3 4 AND RA5 BLOCK DIAGRAM DIAGRAM Data Bus Serial port input signal Data Bus RD PORTA RD PORTA Q2 Q2 Serial port output signals WR PORTA Y Q4 Note pins have protection diodes to Vss QE S SRPEN SYNC TXEN COHEN SREN for RAA SPEN SYNC SYNC CSRC for RA5 Note I O pins have protection diodes to VDD and Vss TABLE 9 1 PORTA FUNCTIONS Name Bit0 Buffer Function RA0 INT bit0 ST Input or external interrupt input RA1 TOCKI bit1 ST Input or clock input to the TMRO timer counter and or an external interrupt input RA2 bit2 ST Input Output Output is open drain type bit3 ST Input Output Output is open drain type RA4 RX DT bit4 ST Input or USART Asynchronous Receive or USART Synchronous Data bit5 ST Input or USART Asynchronous Transmit or USART Synchronous Clock RBPU bit7 Control bit for PORTB weak pull ups Legend ST Schmitt Trigger input TABLE 9 2 REGISTERS BITS ASSOCIATED WITH PORTA Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 10h Bank 0 PORTA RBPU RA5 4 RA2 1 0 xxxx 0 uu uuuu 05h Unbanked
53. Bank 2 1 Bank 3 1 Bank 1 1 Bank 2 Bank 3 1 10h PORTA DDRC TMR1 PW1DCL 10h PORTA DDRC TMR1 PW1DCL 11h DDRB TMR2 PW2DCL 1th DDRB PORTC TMR2 PW2DCL 12h PORTB DDRD TMR3L PW1DCH 12h PORTB DDRD TMR3L PW1DCH 13h RCSTA PORTD TMR3H PW2DCH 13h RCSTA PORTD TMR3H PW2DCH 14h RCREG DDRE PR1 CA2L 14h RCREG DDRE PR1 CA2L 15h TXSTA PORTE PR2 CA2H 15h TXSTA PORTE PR2 CA2H 16h TXREG PIR PR3L CA1L TCON1 16h TXREG PIR PR3L CA1L TCON1 17h SPBRG PIE PR3H CA1H TCON2 17h SPBRG PIE PR3H CA1H TCON2 18h 18h PRODL 19h PRODH oe General 1Ah Purpose RAM 1Fh 20h General General Purpose Purpose FFh RAM 2 Note 1 SFR file locations 10h 17h are banked other SFRs ignore the Bank Select Register FFh BSR bits Note 1 SFR file locations 10h 17h are banked other SFRs ignore the Bank Select Register BSR bits 2 General Purpose Registers GPR locations 20h FFh and 120h 1FFh are banked All other GPRs ignore the Bank Select Register BSR bits 1996 Microchip Technology Inc DS30412C page 33 PIC17C4X TABLE 6 3 SPECIAL FUNCTION REGISTERS Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other Reset resets 3 Unbanked 00h INDFO Uses contents of FSRO to addre
54. Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products Connecting to the Microchip BBS Connect worldwide to the Microchip BBS using either the Internet or the CompuServe communications net work Internet You can telnet or ftp to the Microchip BBS at the address mchipbbs microchip com CompuServe Communications Network When using the BBS via the Compuserve Network in most cases a local call is your only expense The Microchip BBS connection does not use CompuServe membership services therefore you do not need CompuServe membership to join Microchip s BBS There is no charge for connecting to the Microchip BBS The procedure to connect will vary slightly from country to country Please check with your local CompuServe agent for details if you have a problem CompuServe service allow multiple users various baud rates depending on the local point of access The following connect procedure applies in most loca tions 1 Set your modem to 8 bit No parity and One stop 8N1 This is not the normal CompuServe setting which is 7E1 Dial your local CompuServe access number 3 Depress the Enter key and a garbage string will appear because CompuServe is expecting a 7E1 setting 4 Type depress the Enter key and Host will appear 5 Type MCHIPBBS depress the Enter key and you will be connected to the Microchip BBS In the Unit
55. PIC17CAX FIGURE 9 5 BLOCK DIAGRAM OF RB3 AND RB2 PORT PINS Peripheral Data in RBPU PORTA lt 7 gt Match Sigrial from other pins Port Input Latch RD DDRB Q2 RD PORTB 02 WR DDRB Q4 WR PORTB Q4 PWM output PWM select Note pins have protection diodes to and Vss DS30412C page 56 1996 Microchip Technology Inc PIC17CAX Example 9 1 shows the instruction sequence to initial ize PORTB The Bank Select Register BSR must be selected to Bank 0 for the port to be initialized EXAMPLE 9 1 INITIALIZING PORTB MOVLB 0 Select Bank 0 CLRF PORTB Initialize PORTB by clearing output data latches MOVLW OxCF Value used to initialize data direction MOVWF DDRB Set RB 3 0 as inputs RB 5 4 as outputs RB 7 6 as inputs TABLE 9 3 PORTB FUNCTIONS Name Bit Buffer Type Function RBO CAP1 bitO ST Input Output or the RBO CAP1 input pin Software programmable weak pull up and interrupt on change features RB1 CAP2 bit1 ST Input Output or the RB1 CAP2 input pin Software programmable weak pull up and interrupt on change features RB2 PWM1 bit2 ST Input Output or the RB2 PWM1 output pin Software programmable weak pull up and interrupt on change features RB3 PWM2
56. 0327026 N Pics H D 0 177 7007 mes Di gt auger Nt lt D ee A A a ria D 0 101 Seating Toss as 7 004 Plane A A Ro E A 11 E up 0 38 n 1 VAN TL mi aye 0 177 1007 0 254 0 254 010 LAN 010 Max LAN 0 508 0 508 1524 00 Y 020 1 651 L 1 651 li ze EJ 98 1 14 0 64 R 1 14 0 64 0457 025 0457 025 FG DE Package Group Plastic Leaded Chip Carrier PLCC Millimeters Inches Symbol Min Max Notes Min Max Notes A 4 191 4 572 0 165 0 180 A1 2 413 2 921 0 095 0 115 D 17 399 17 653 0 685 0 695 D1 16 510 16 663 0 650 0 656 D2 15 494 16 002 0 610 0 630 03 12 700 12 700 Reference 0 500 0 500 Reference E 17 399 17 653 0 685 0 695 E1 16 510 16 663 0 650 0 656 E2 15 494 16 002 0 610 0 630 E3 12 700 12 700 Reference 0 500 0 500 Reference N 44 44 44 44 CP 0 102 0 004 LT 0 203 0 381 0 008 0 015 1996 Microchip Technology Inc DS30412C page 207 PIC17C4X 21 4 44 Lead Plastic Surface Mount MQFP 10x10 mm Body 1 6 0 15 mm Lead Form 0 20 ABO 0G 20 9
57. 145 PEN DET 72 irre ree tee Ree rennes 71 CATED Ayo essere tees 71 GATE 23 GRATIE i te ete be eie Ne tet den 24 GATOVE n eta cn we EE ral caste 72 CG visnpM sd 71 Oe uestis 71 CA2H 20 35 GAZIE abs ie bed e NL se abt e 23 78 GA2IE ced ores inten eo M steam 24 78 CA2L 20 35 72 Calculating Baud Rate Error 86 39 117 Selection Ceramic Resonators 101 Crystal Oscillator EET Capture Sequence to Read Example 78 Capture1 71 OVEMIOW 22 ds 72 Capture2 tire tement 71 Overflow 72 Carry Ceramic Resonators Circular Buffer be go seda Clearing the Prescaler x Clock Instruction Cycle Figure 14 Clocking Scheme Instruction Cycle Section 14 CLRF CLRWDT Code Protection Si mde Men i ce Mn seme 118 Configuration 100
58. 1996 Microchip Technology Inc PIC17C4X 13 2 2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 13 4 The data comes in the RA4 RX DT pin and drives the data recovery block The data recovery block is actually a high speed shifter operating at 16 times the baud rate whereas the main receive serial shifter operates at the bit rate or at FOSC Once asynchronous mode is selected reception is enabled by setting bit CREN RCSTA lt 4 gt The heart of the receiver is the receive serial shift reg ister RSR After sampling the stop bit the received data in the is transferred to the RCREG if it is empty If the transfer is complete the interrupt bit PIR lt O gt is set The actual interrupt can be enabled disabled setting clearing the RCIE PIE lt 0 gt bit RCIF is a read only bit which is cleared by the hardware It is cleared when RCREG has been read and is empty RCREG is a double buffered regis ter i e it is a two deep FIFO It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR On detection of the stop bit of the third byte if the RCREG is still full then the overrun error bit OERR RCSTA lt 1 gt will be set The word in the RSR will be lost RCREG can be read twice to retrieve the two bytes in the FIFO The OERR bit has to be cleared in software which is done by resetting the receive logic C
59. 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 42 42 43 R43 44 19 0 PIC17CR42 42A 43 R43 44 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings T Ambient temperature under creer ent edi rere re ee do es 55 to 125 C Storage temperature oerte roe ete ere dicet e hes reae herbe nus 65 C to 150 C Voltage on VDD with respect to VSS iii 0 to 7 5V Voltage on MCLR with respect to VSS Note 2 0 6V to 14V Voltage on RA2 and RAS with respect to VS 0 6V to 14V Voltage on all other pins with respect to 55 0 6V to VDD 0 6V Total power dissipation Note 1 1 0W Maximum c rrentout Of 55 010 5 total 2e t dette do 250 Maximum current into VDD pin S total n ED Cer ELLE E c ELE MER Ls ees 200 mA Input clamp current VI lt or VI gt VDD een 220 mA Output clamp current IOK VO lt 0 or VO gt 320 mA Maximum output current sunk by any I O pin except RA2 and RA3G 35 mA Maximum output current sunk by RA2 or pins sise 60 mA Maximum output current sourced by I O pin siennes 20 mA Maximum current sunk by PORTA and PORTB combined 150 mA Maximum current sourced by PORTA and PORTB combined ss 100 mA Maximum current sunk by PORTC PORTD and PORTE combined 150 mA Maximum current sourced by PORTC
60. 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 19 10 USART MODULE SYNCHRONOUS RECEIVE MASTER SLAVE TIMING 125 RA4 RX DT gt TABLE 19 10 SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No Sym Characteristic Min Typt Max Units Conditions 125 TdtV2ckL SYNC RCV MASTER 8 SLAVE 15 ns Data hold before DT hold time 126 TckL2dtl Data hold after DT hold time 15 ns T Data in column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1996 Microchip Technology Inc DS30412C page 189 PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19 11 MEMORY INTERFACE WRITE TIMING NOT SUPPORTED IN PIC17LC4X DEVICES ALE OE WR AD lt 15 0 gt gt 152 TABLE 19 11 MEMORY INTERFACE WRITE REQUIREMENTS NOT SUPPORTED IN PIC17LC4X DEVICES Parameter No Characteristic Min Typt Max Units Conditions TadV2alL AD lt 15 0 gt address valid to ALE 0 25Tcy 10 ns address setup time TalL2ad ALEJ to address out invalid 0 ns address hold time TadV2wrL Data out valid to 0 25Tcy 40 ns data setup time Twr
61. 43 R43 44 FIGURE 18 15 vs VDD 5V 2 5 3 0 3 5 4 0 4 5 Volts FIGURE 18 16 101 vs VOL VDD 5 0 Max 40 C Typ 25 C Min 85 C 1 5 Volts DS30412C page 171 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 18 17 101 vs VoL 5 1 5 40 C to 85 C Min 40 C to 85 C 4 0 4 5 VDD Volts DS30412C page 172 1996 Microchip Technology Inc PIC17CAX Applicable Devices 42 R42 42A 43 43 44 FIGURE 18 19 VTH of PINS SCHMITT TRIGGER vs VDD VIH max 40 C to 85 C VIH typ 25 C min 40 C to 85 C VIL max 40 C to 85 C 7 VIL typ 25 C n 40 C to 85 C 4 0 VDD Volts FIGURE 18 20 VTH INPUT THRESHOLD VOLTAGE OSC1 INPUT IN XT AND LF MODES vs Min 40 C to 85 C 4 0 4 5 Volts 1996 Microchip Technology Inc DS30412C page 173 PIC17C4X NOTES DS30412C page 174
62. CA1OVF PWM2ON PWM1ON TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000 Unbanked 18h 9 PRODL Low Byte of 16 bit Product 8 x 8 Hardware Multiply XXXX XXXX uuuu uuuu 19h 9 PRODH High Byte of 16 bit Product 8 x 8 Hardware Multiply XXXX XXXX uuuu uuuu Legend unknown unchanged unimplemented read as 0 value depends on condition Shaded cells are unimplemented read as 0 Note 1 The upper byte of the program counter is not directly accessible PCLATH is a holding register for PC 15 8 whose contents are updated from or transferred to the upper byte of the program counter 2 The TO and PD status bits in CPUSTA are not affected by a MCLR reset 3 Other non power up resets include external reset through MCLR and the Watchdog Timer Reset 4 The following values are for both TBLPTRL and TBLPTRH All PIC17C4X devices Power on Reset 0000 0000 and All other resets 0000 0000 except the PIC17C42 Power on Reset xxxx xxxx and All other resets uuuu uuuu 5 The PRODL and PRODH registers are not implemented on the PIC17C42 1996 Microchip Technology Inc DS30412C page 35 PIC17CAX 6 2 2 1 ALU STATUS REGISTER ALUSTA The ALUSTA register contains the status bits of the Arithmetic and Logic Unit and the mode control bits for the indirect addressing register As with all the other registers the ALUSTA register can be the de
63. FIGURE 19 8 PWM TIMINGS PWM1 and PWM2 PWM Mode TABLE 19 8 PWM REQUIREMENTS Parameter No Sym Characteristic Min Typt Max Units Conditions 53 TccR PWM1 and PWM output rise time 10 35 ns 54 PWM1 PWM2 output fall time 10 35 8 ns 3 These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested This specification ensured by design DS30412C page 188 1996 Microchip Technology Inc PIC17CAX Applicable Devices 42 842 424 43 R43 44 FIGURE 19 9 USART MODULE SYNCHRONOUS TRANSMISSION MASTER SLAVE TIMING RASTXCK RA4 RX DT pin TABLE 19 9 SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No Sym Characteristic Min Max Units Conditions 120 TckH2dtV SYNC XMIT MASTER amp SLAVE PIC17CR42 42A 43 R43 44 50 ns Clock high to data out valid pIC17LCR42 42A 43 R43 44 75 ns 121 TckRF Clock out rise time and fall time PIC17CR42 42A 43 R43 44 25 ns Master Mode PIC17LCR42 42A 43 R43 44 40 ns 122 TdtRF Data out rise time and fall time PIC17CR42 42A 43 R43 44 25 ns PIC17LCR42 42A 43 R43 44 40 ns T Data in Typ column is at 5V
64. Function Interrupt Vectors Priorities Mode Memory Access Table 6 2 Table 6 3 Table 7 1 Table 8 1 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 9 7 Table 9 8 Table 9 9 Table 9 10 Table 11 1 Table 12 1 Table 12 2 Table 12 3 Table 12 4 Table 12 5 Table 12 6 Table 13 1 Table 13 2 Table 13 3 Table 13 4 Table 13 5 Table 13 6 Table 13 7 Table 13 8 Table 13 9 Table 13 10 Table 14 1 Table 14 2 Table 14 3 Table 14 4 Table 15 1 Table 15 2 Table 16 1 Table 17 1 Table 17 2 Table 17 3 Table 17 4 Table 17 5 Table 17 6 Table 17 7 Table 17 8 EPROM Memory Access Time Ordering Suffix 31 Special Function Registers 34 Interrupt Table Write 1 1 45 Performance Comparison 49 PORTA Functions 54 Registers Bits Associated with PORTA 54 PORTB Functions 57 Registers Bits Associated with PORTB 57 PORTO Functions 59 Registers Bits Associated with PORTC 59 PORTD Functions 61 Registers Bits Associated with PORTD 61 PORTE FUNCHONS ann 63 Registers Bits Associated with PORTE 63 Registers
65. Ift 0 TBLATL gt f Prog Mem TBLPTR TBLAT Ifi 1 TBLPTR 1 TBLPTR None 1010 10ti ffff 1 A byte of the table latch TBLAT is moved to register file f If t 0 the high byte is moved Ift 1 the low byte is moved 2 Then the contents of the program memory location pointed to by the 16 bit Table Pointer TBLPTR is loaded into the 16 bit Table Latch TBLAT 3 Ifi 1 TBLPTR is incremented If i20 TBLPTR is not incremented 2 8 cycle if f PCL Q2 Q3 Read Execute Write register f register TBLATH or TBLATL 1996 Microchip Technology Inc DS30412C page 137 PIC17C4X TABLRD Table Read TABLWT Table Write 1 TABLRD 1 1 REG Syntax abel TABLWT tif Before Instruction Operands lt f lt 255 0x53 ie 0 1 TBLATH te 0 1 TBLATL 0x55 TBLPTR 0xA356 Operation If t 0 MEMORY TBLPTR 0x1234 f TBLATL 3 i Ift 1 table f gt TBLATH TBLATH 0x12 TBLAT Prog Mem TBLPTR TBLATL 0x84 Ifi 1 TBLPTR 0xA357 TBLPTR 1 TBLPTR MEMORY TBLPTR 0 5678 Status Affected None Example2 TABERD 050 REG Encoding 1010 11ti fff Before Instruction Description 1 Load value in into 16 bit table REG 0 53 latch TBLAT TBLATH If t 0 load into low byte erit T If 1 load into high byte X MEMORY TBLPTR
66. Move data from data memory location f Bank Select Register BSR Only the to data memory location p Location f low 4 bits of the Bank Select Register can be anywhere in the 256 word data are affected The upper half of the BSR space 00h to FFh while p can be 00h is unchanged The assembler will to 1Fh encode the fields as 0 Either p can be WREG a useful Words 1 Special situation 1 is particularly useful for transfer WOES ring a data memory location to a periph Q Cycle Activity eral register such as the transmit buffer at 02 Q3 04 oran UC porc Both sands p carbe Decode Read Execute Write literal indirectly addressed literal u k Words 1 BSR lt 3 0 gt Cycles 1 Example MOVLB 0x5 Q Cycle Activity Before Instruction Q1 Q2 Q3 Q4 BSR register 0x22 Decode Read Execute Write After Instruction register f register p BSRregister 0x25 Example MOVFP REG2 Note For the PIC17C42 only the low four bits of the BSR register are physically imple Before Instruction 5 mented The upper nibble is read as O 0x33 REG2 0x11 After Instruction REG1 0x33 REG2 0x33 OO E EI I el DS30412C page 126 1996 Microchip Technology Inc PIC17C4X Move Literal to high nibble in MOVLR BSR Syntax label MOVLR Operands lt lt 15 Operation k BSR lt 7 4 gt Status Affected
67. None Encoding 0011 0000 Compares the contents of data memory location to the contents of WREG by performing an unsigned subtraction If the contents of lt the contents of WREG then the fetched instruction is discarded and an NOP is executed instead making this a two cycle instruc Description tion Words 1 Cycles 1 Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register f If skip Q1 Q2 Q3 Q4 Forced NOP NOP Execute NOP Example HERE CPFSLT REG NLESS LESS Before Instruction PC Address HERE Ww 7 After Instruction If REG WREG PC Address LESS If REG 2 WREG PC Address NLESS DAW Decimal Adjust WREG Register Syntax DAW fs Operands 0 lt lt 255 sc 0 1 Operation If WREG 3 0 gt 9 DC 1 then WREG lt 3 0 gt 6 f lt 3 0 gt 5 lt 3 0 gt else WREG lt 3 0 gt f lt 3 0 gt 5 lt 3 0 gt If WREG lt 7 4 gt gt 9 1 then WREG lt 7 4 gt 6 gt f lt 7 4 gt s lt 7 4 gt else WREG lt 7 4 gt f lt 7 4 gt s lt 7 4 gt Status Affected Encoding 0010 111s ffff DAW adjusts the eight bit value WREG resulting from the earlier addi tion of two variables each in packed BCD format and produces a correct packed BCD result 5 0 Resultis placed in Data memory location and WREG 5 1 Result is placed in Data memory location
68. None Encoding 1011 101x kkkk uuuu Description The 4 bit literal is loaded into the most significant 4 bits of the Bank Select Register BSR Only the high 4 bits of the Bank Select Register are affected The lower half of the BSR is unchanged The assembler will encode the fields as 0 Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Execute Write k u literal k to BSR lt 7 4 gt Example MOVLR 5 Before Instruction BSR register 0x22 After Instruction BSR register 0x52 Note This instruction is not available in the PIC17C42 device MOVLW Move Literal to WREG Syntax label MOVLW Operands 0 lt k lt 255 Operation k WREG Status Affected None Encoding 1011 0000 kkkk kkkk Description The eight bit literal k is loaded into WREG Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to literal k WREG Example MOVLW 5 After Instruction WREG 0x5A 1996 Microchip Technology Inc DS30412C page 127 PIC17C4X MOVPF Movep to f Syntax MOVPF Operands 0 lt lt 255 0 lt lt 31 Operation p f Status Affected Z Encoding 010p Description Move data from data memory location p to data memory location f Location f can be anywhere in the 256 byte data space 00h to FFh while p can be 00h to 1Fh Either p or f can be
69. TQFP is not available for the PIC17C42 1996 Microchip Technology Inc DS30412C page 2 PIC17C4X Table of Contents DUELO S P NN Ra HA 5 2 0 PIG17C4X 2 eee rete tee eel e OE 7 3 0 Architectural Oyervi W E 9 4 0 RES n ERE CORR DURER ER e OBERE RR en BE OP n ERE EE REM Ee DUE HERE 15 5 0 MEU pts 21 6 0 Memory Orgariizatlon ep SEED PLC Pega HEP er o ne E HR ere eer 29 7 0 Table Reads and Table WINES incontri reete eti redi Doi edet e ides v abere duced 43 8 0 Hardware Multipllgr 9 2 Rec EUN ed C eh Ee i Ce 49 9 0 Hedge cz ae 53 100 Overview of Timer Resources iere tec ere deco ee 65 11 09 ERIPUIT 67 12 0 Timer2 Timer3 PWMs and 71 13 0 Universal Synchronous Asynchronous Receiver Transmitter USART Module 83 14 07 Special Features ofthe CPU ridotte ete plo cen ES des te est exea 99 15 09 Instruction SUS um Marys bietet bae indus 107 16 0 Development S pport eR Ege 143 17 0 PIC17CA2 Electrical
70. TXIE USART Transmit Interrupt Enable bit 1 Enable Transmit buffer empty interrupt 0 Disable Transmit buffer empty interrupt RCIE USART Receive Interrupt Enable bit 1 Enable Receive buffer full interrupt 0 Disable Receive buffer full interrupt Readable bit W Writable bit Value at POR reset 1996 Microchip Technology Inc DS30412C page 23 PIC17C4X 5 3 Peripheral Interrupt Request Register Note These bits will be set by the specified con PIR dition even if the corresponding interrupt This register contains the individual flag bits for the peripheral interrupts enable bit is cleared interrupt disabled or the GLINTD bit is set all interrupts dis abled Before enabling an interrupt the user may wish to clear the interrupt flag to ensure that the program does not immedi ately branch to the peripheral interrupt ser vice routine FIGURE 5 4 PIR REGISTER ADDRESS 16h BANK 1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 1 0 RBIF TMR2IF 2 CAMIF RCIF Readable bit bit7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W Writable bit n Value POR reset RBIF PORTB Interrupt on Change Flag bit 1 One of the PORTB inputs changed Software must end the mismatch condition 0 None of the PORTB inputs have changed TMRSIF Timer3 Interrupt Fl
71. The TLWT t f and TABLWT t i f instructions are used to write data from the data memory space to the program memory space The TLRD t f and TABLRD t i f instructions are used to write data from the pro gram memory space to the data memory space DATA MEMORY PROGRAM MEMORY TABLWT 1 1 TABLWT The program memory can be internal or external For the program memory access to be external the device needs to be operating in extended microcontroller or microprocessor mode Figure 7 1 through Figure 7 4 show the operation of these four instructions FIGURE 7 1 TLWT INSTRUCTION TBLPTRH TBLPTRL TABLE LATCH 16 bit TABLATH TABLATL 8 bit value from register loaded into the high or low byte in TABLAT 16 bit 16 bit TABLAT value written to address Program Memory TBLPTR If i 1 then TBLPTR TBLPTR 1 If i 0 then TBLPTR is unchanged TLWT 0 DATA MEMORY PROGRAM MEMORY Note 1 8 bitvalue from register f loaded into the high or low byte in TABLAT 16 bit 1996 Microchip Technology Inc DS30412C page 43 PIC17C4X FIGURE 7 3 TLRD INSTRUCTION OPERATION TABLE POINTER TBLPTRH TBLPTRL TABLE LATCH 16 bit TABLATH TABLATL TLRD 1 TLRD 0 DATA MEMORY PROGRAM MEMORY FIGURE 7 4 TABLRD INSTRUCTION OPERATION TABLE
72. Typical represents the mean of the distribution while max or min represents mean and mean 3 respectively where o is standard deviation TABLE 18 1 CAPACITANCE PER PACKAGE TYPE Typical Capacitance pF 40 pin DIP 44 pin PLCC 44 pin 44 pin TOFP Pin Name All pins except MCLR 10 10 10 10 VDD and Vss MCLR pin 20 20 20 20 FIGURE 18 1 TYPICAL RC OSCILLATOR FREQUENCY vs TEMPERATURE Fosc Frequency normalized to 25 C Fosc 25 C VDD 5 5V VDD 3 5V MN 1996 Microchip Technology Inc DS30412C page 163 oc 1 v 3 PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 18 2 TYPICAL RC OSCILLATOR FREQUENCY vs Cext 22 pF T 25 C Volts FIGURE 18 3 TYPICAL RC OSCILLATOR FREQUENCY vs Volts DS30412C page 164 1996 Technology Inc PIC17CAX Applicable Devices 42 R42 42A 43 43 44 FIGURE 18 4 TYPICAL RC OSCILLATOR FREQUENCY vs Cext 300 pF T 25 C Volts TABLE 18 2 RC OSCILLATOR FREQUENCIES Average
73. WDTPS1 FEO3h PMO FEO4h PM1 FEO6h 2 1 FEOFh 1 Note 1 This location does not exist on the PIC17C42 Note When programming the desired configura tion locations they must be programmed in ascending order Starting with address FEOOh 14 2 Oscillator Configurations 14 2 1 OSCILLATOR TYPES PIC17CXX be operated in four different oscil lator modes The user can program two configuration bits FOSC1 FOSCO to select one of these four modes LF Low Power Crystal XT Crystal Resonator EC External Clock Input RC Resistor Capacitor 14 2 2 CRYSTAL OSCILLATOR CERAMIC RESONATORS In XT or LF modes a crystal or ceramic resonator is connected to the OSC1 CLKIN and OSC2 CLKOUT pins establish oscillation Figure 14 2 The PIC17CXX Oscillator design requires the use of a par allel cut crystal Use of a series cut crystal may give a frequency out of the crystal manufacturers specifica tions For frequencies above 20 MHz it is common for the crystal to be an overtone mode crystal Use of overtone mode crystals require a tank circuit to attenuate the gain at the fundamental frequency Figure 14 3 shows an example of this FIGURE 14 2 CRYSTAL OR CERAMIC RESONATOR OPERATION XT OR LF OSC CONFIGURATION SLEEP gt internal logic PIC17CXX See Table 14 2 and Table 14 3 for recommended values of C1 and C2 Note 1 A series resistor may b
74. WDTPS1 WDTPSO as 00 Section 14 1 Under normal operation the WDT must be cleared on a regular interval This time is less the minimum WDT overflow time Not clearing the WDT in this time frame will cause the WDT to overflow and reset the device 14 31 WDT PERIOD The WDT has a nominal time out period of 12 ms with postscaler 1 The time out periods vary with temper ature VDD and process variations from part to part see DC specs If longer time out periods are desired a postscaler with a division ratio of up to 1 256 can be assigned to the WDT Thus typical time out periods up to 3 0 seconds can be realized The CLRWDT and SLEEP instructions clear the and the postscaler if assigned to the WDT and pre vent it from timing out thus generating a device RESET condition The TO bit in the CPUSTA register will be cleared upon a WDT time out 14 3 2 CLEARING THE AND POSTSCALER The WDT and postscaler are cleared when The device is in the reset state ASLEEP instruction is executed ACLRWDT instruction is executed Wake up from SLEEP by an interrupt The WDT counter postscaler will start counting on the first edge after the device exits the reset state 14 3 3 PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst case conditions Min Temperature Max max WDT postscaler it may take several seconds before a WD
75. affected 6 4 2 INDIRECT ADDRESSING OPERATION The indirect addressing capability has been enhanced over that of the PIC16CXX family There are two con trol bits associated with each FSR register These two bits configure the FSR register to Auto decrement the value address in the FSR after an indirect access Auto increment the value address in the FSR after an indirect access change to the value address in the FSR after an indirect access These control bits are located in the ALUSTA register The FSR1 register is controlled by the FS3 FS2 bits and FSRO is controlled by the FS1 FSO bits When using the auto increment or auto decrement features the effect on the FSR is not reflected in the ALUSTA register For example if the indirect address causes the FSR to equal 0 Z bit will not be set If the FSR register contains a value of Oh an indirect read will read Oh Zero bit is set while an indirect write will be equivalent to a NOP status bits are not affected Indirect addressing allows single cycle data transfers within the entire data space This is possible with the use of the and instructions where either p or f is specified as INDFO or INDF1 If the source or destination of the indirect address is in banked memory the location accessed will be deter mined by the value in the BSR A simple program to clear RAM from 20h FFh is shown in Example 6 1 EXAMPLE
76. f Description Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register f and other specified register Example DAW 0 Before Instruction WREG 5 REG1 0 0 After Instruction WREG 0x05 REG1 0x05 C 1 2 0 Example 2 Before Instruction WREG OxCE REG1 22 C 0 DC 0 After Instruction WREG 0x24 0 24 1 0 DS30412C page 120 1996 Microchip Technology Inc PIC17C4X DECF Decrement f Syntax label DECF f d Operands 0 lt 1 lt 255 0 1 f 1 dest Status Affected Z Encoding 0000 011d ffff Description Decrement register If d is 0 the result is stored in WREG If d is 1 the result is stored back in register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example DECF CNT i Before Instruction CNT 0 01 2 0 After Instruction CNT 0x00 Z 1 52 Decrement f skip Syntax label DECFSZ Operands lt lt 255 0 1 Operation 1 gt dest skip if result 0 Status Affected None Encoding 0001 0119 ffff ffff The contents of register are decre mented If d is 0 the result is placed in WREG If d is 1 the result is placed back in register f If the resul
77. low byte of the PC is mapped in the data memory PCL is readable and writable just as is any other register PCH is the high byte of the PC and is not directly addressable Since PCH is not mapped in data or pro gram memory an 8 bit register PCLATH PC high latch is used as a holding latch for the high byte of the PC PCLATH is mapped into data memory The user can read or write PCH through PCLATH The 16 bit wide PC is incremented after each instruc tion fetch during Q1 unless Modified by GOTO CALL LCALL RETURN RETLW or instruction Modified by an interrupt response Due to destination write to PCL by an instruction Skips are equivalent to a forced NOP cycle at the skipped address Figure 6 11 and Figure 6 12 show the operation of the program counter for various situations FIGURE 6 11 PROGRAM COUNTER OPERATION Internal data bus 8 PCLATH FIGURE 6 12 PROGRAM COUNTER USING THE CALL AND GOTO INSTRUCTIONS 15 13 12 87 Opcode Last write to PCLATH 3 7 54 v 0 PCLATH Using Figure 6 11 the operations of the PC and PCLATH for different instructions are as follows LCALL instructions An 8 bit destination address is provided in the instruction opcode PCLATH is unchanged PCLATH PCH Opcode lt 7 0 gt PCL b Read instructions on PCL Any instruction that reads PCL PCL data bu
78. on power up only designed to keep the part in RESET while the power supply stabi lizes With these two timers on chip most applications need no external reset circuitry The SLEEP mode is designed to offer a very low cur rent power down mode The user can wake from SLEEP through external reset Watchdog Timer Reset or through an interrupt Several oscillator options are also made available to allow the part to fit the applica tion The RC oscillator option saves system cost while the LF crystal option saves power Configuration bits are used to select various options This configuration word has the format shown in Figure 14 1 R P 1 U x U x U x U x PM bit15 7 U x 1 U x 1 1 H P PMO WDTPS1 WDTPSO FOSC1 FOSCO R Readable bit 1 bit0 1 1 bit 15 9 Unimplemented Read as a 1 bit 15 6 4 PM2 PM1 PMO Processor Mode Select bits 111 Microprocessor Mode 110 Microcontroller mode 101 Extended microcontroller mode 000 Code protected microcontroller mode bit 7 5 Unimplemented Read as a 0 bit 3 2 WDTPS1 WDTPSO WDT Postscaler Select bits 11 enabled postscaler 1 10 enabled postscaler 256 01 enabled postscaler 64 00 WDT disabled 16 bit overflow timer bit 1 0 FOSC1 FOSCO Oscillator Select bits 11 EC oscillator 10 XT oscillator 01 RC oscillator 00 LF oscillator Programmab
79. user can activate a capture by writing to the port pin This may be useful during development phase to emu late a capture interrupt The input on capture pin RB1 CAP2 is synchronized internally to internal phase clocks This imposes certain restrictions on the input waveform see the Electrical Specification section for timing The Capture2 overflow status flag bit is double buff ered The master bit is set if one captured word is already residing in the Capture2 register and another event has occurred on the RB1 CA2 pin The new event will not transfer the Timer3 value to the capture register protecting the previous unread capture value When the user reads both the high and the low bytes in any order of the Capture2 register the master overflow bit is transferred to the slave overflow bit CA2OVF and then the master bit is reset The user can then read TCON to determine the value of CA2OVF The recommended sequence to read capture registers and capture overflow flag bits is shown in Example 12 1 EXAMPLE 12 1 SEQUENCE TO READ CAPTURE REGISTERS Select Bank 3 Read Capture2 low byte store in LO BYTE Read Capture2 high byte store in HI BYTE Read TCON2 into file PSTAT VAL MOVLB 3 MOVPF CA2L LO BYTE MOVPF CA2H HI BYTE MOVPF TCON2 STAT VAL FIGURE 12 7 TIMER3 WITH ONE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM Equal Reset TMR3CS 1 lt 2 gt RB5 TCLK3 PR3H CA1H
80. xew yw gge xew gge xew yw pz xew A0 9 OLAS A0 9 OL A0 9 OL AG Y A0 9 G IX ZHI 0244 ZHIN 0914 ZHIN v ZHIN ZHI 0944 peigesip LAM pelgesip LAM peigesip LAM 5 LAM LAM NGG e xeu AGG ye xeu ydg ddl AGG xeu ydg AGG ye xeu ddl AGG xeu yng xew ywg xew vulg xew ywg xew yw 9 xew yw 9 A0 9 OLAS Y A0 9 A0 9 OLAS Y A0 9 OL ggA A0 9 OH tt92191ld 91 tt92L9Id 80 t 9712191d t49 19ld Gc t49 19ld 91 t492191d 80 r49712191d 91192 t92191d Gc t92191d 91 t92191Id 80 r912191d 250 seo Aog Ver9219ld Sc VCVOZ Old 2 80 Vct912191d ct49 191d 1 2 91 1 1 2 80 Ct4H9712 191d 1996 Microchip Technology Inc DS30412C page 176 PIC17CAX 19 1 Applicable Devices 42 842 42A 43 R43 44 DC CHARACTERISTICS PIC17CR42 42A 43 R43 44 16 Commercial Industrial PIC17CR42 42A 43 R43 44 25 Commercial Industrial PIC17CR42 42A 43 R43 44 33 Commercial Industrial DC CHARACTERISTICS Standard Operating Conditions unless otherwise sta
81. 0 a value depends on condition Shaded cells not used by Note 1 Other non power up resets include external reset through MCLR and the Watchdog Timer Reset DS30412C page 70 1996 Technology Inc PIC17C4X 12 0 1 2 TIMERS PWMS AND CAPTURES The PIC17C4X has a wealth of timers and time based functions to ease the implementation of control applica tions These time base functions include two PWM out puts and two Capture inputs and Timer2 are two 8 bit incrementing timers each with a period register PR1 and PR2 respectively and separate overflow interrupt flags Timer and Timer2 can operate either as timers increment on internal Fosc 4 clock or as counters increment on fall ing edge of external clock on pin RB4 TCLK12 They are also software configurable to operate as a single 16 bit timer These timers are also used as the time base for the PWM pulse width modulation mod ule Timer3 is a 16 bit timer counter consisting of the and TMR3L registers This timer has four other associated registers Two registers are used as a 16 bit period register or a 16 bit Capture register PRSH CA1H PR3L CA1L The other two registers are strictly the Capture registers CA2H CA2L Timer3 is the time base for the two 16 bit captures can be software configured to increment from the internal system clock or from an external signal on t
82. 0000 0000 0000 0101 Description Return from Interrupt Stack is POP ed and Top of Stack TOS is loaded in the PC Interrupts are enabled by clearing the GLINTD bit GLINTD is the global interrupt disable bit CPUSTA lt 4 gt Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register TOSTA Forced NOP NOP Execute NOP Example RETFIE After Interrupt PC TOS GLINTD 0 RETLW Return Literal toWREG Syntax abel Operands lt lt 255 Operation WREG TOS PCLATH is unchanged Status Affected Encoding 1011 0110 kkkk kkkk Description WREG is loaded with the eight bit literal K The program counter is loaded from the top of the stack the return address The high address latch PCLATH remains unchanged Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to literal k WREG Forced NOP NOP Execute NOP Example CALL TABLE WREG contains table offset value WREG now has table value TABLE ADDWF PC WREG offset RETLW Begin table RETLW k1 fis kn End of table Before Instruction WREG 0x07 After Instruction WREG value of k7 1996 Microchip Technology Inc DS30412C page 131 PIC17C4X RETURN Return from Subroutine Syntax label RETURN Operands None Operation TOS Status Affected None Encoding 0000 0000 0000 0010 Description Retur
83. 0000 0000 uuuu uuuu Unbanked PRODL 9 18h XXXX XXXX uuuu uuuu uuuu uuuu PRODH 9 19h XXXX XXXX uuuu uuuu uuuu uuuu Legend u unchanged unimplemented read as 0 value depends on condition Note 1 One or more bits in INTSTA PIR will be affected to cause wake up 2 When the wake up is due to an interrupt and the GLINTD bit is cleared the PC is loaded with the interrupt vector 3 See Table 4 3 for reset value of specific condition 4 Only applies to the PIC17C42 5 Does not apply to the PIC17C42 DS30412C page 20 1996 Technology Inc PIC17CAX 5 0 INTERRUPTS The PIC17C4X devices have 11 sources of interrupt External interrupt from the RAO INT pin Change on RB7 RBO pins TMRO Overflow TMR1 Overflow TMR2 Overflow TMR3 Overflow USART Transmit buffer empty USART Receive buffer full Capture Capture2 TOCKI edge occurred There are four registers used in the control and status of interrupts These are CPUSTA INTSTA PIE PIR The CPUSTA register contains the GLINTD bit This is the Global Interrupt Disable bit When this bit is set all interrupts are disabled This bit is part of the controller core functionality and is described in the Memory Orga nization section FIGURE 5 1 INTERRUPT LOGIC TMRilF w TMRIIE TMR2IF N TMR2IE 7 TMR3IF When an interru
84. 1001 WREG 0 00 0000 1101 1 After Instruction REG1 0x0C 0000 1011 WREG 0 00 0000 1101 C 1 result is positive 2 0 Example2 SUBWFB REG1 0 Before Instruction REGI 0x1B 0001 1011 WREG Ox1A 0001 1010 0 After Instruction REGI 0x1B 0001 1011 WREG 0x00 C 1 result is zero Z 1 Example3 SUBWFB 1 1 Before Instruction REG1 0x03 0000 0011 WREG 0xE 0000 1101 1 After Instruction REGI OxF5 1111 0100 28 comp WREG 0x0E 0000 1101 C 0 result is negative 2 0 DS30412C page 136 1996 Microchip Technology Inc PIC17CAX SWAPF Swap f Syntax label SWAPF Operands lt lt 255 d e 0 1 Operation f lt 3 0 gt dest lt 7 4 gt f lt 7 4 gt dest lt 3 0 gt Status Affected None Encoding 0001 110d ffff ffff Description The upper and lower nibbles of register f are exchanged If d is 0 the result is placed in WREG If d is 1 the result is placed in register Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example SWAPF REG 0 Before Instruction REG 0x53 After Instruction REG 0x35 TABLRD Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Q1 Table Read abel TABLRD t i f 0 lt 1 lt 255 ie 0 1 te 0 1 1 TBLATH f
85. 16h 0000 0010 0000 0010 uuuu uuuuU PIE 17h 0000 0000 0000 0000 uuuu uuuu Legend u unchanged x unknown unimplemented read as 0 Note 1 One or more bits in INTSTA PIR will be affected to cause wake up 2 When the wake up is due to an interrupt and the GLINTD bit is cleared the PC is loaded with the interrupt vector See Table 4 3 for reset value of specific condition 3 4 Only applies to the PIC17C42 5 Does not apply to the PIC17C42 lt value depends on condition 1996 Microchip Technology Inc DS30412C page 19 PIC17C4X TABLE 4 4 INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS Cont d Register Address Power on Reset pcd roi 2 1 10 uuuu uuuu uuuu uuuu TMR2 11h XXXX XXXX uuuu uuuu uuuu uuuu TMR3L 12h XXXX XXXX uuuu uuuu uuuu uuuu TMR3H 13h XXXX XXXX uuuu uuuu uuuu uuuu PR1 14h XXXX XXXX uuuu uuuu uuuu uuuu PR2 15h XXXX XXXX uuuu uuuu uuuu uuuu PR3 CA1L 16h XXXX XXXX uuuu uuuu uuuu uuuu PR3 CA1H 17h XXXX uuuu uuuu uuuu uuuu Bank 3 PW1DCL 10h Xx uu uu PW2DCL 11h Xx uu uu PW1DCH 12h XXXX XXXX uuuu uuuu uuuu uuuu PW2DCH 13h XXXX XXXX uuuu uuuu uuuu uuuu CA2L 14h XXXX XXXX uuuu uuuu uuuu uuuu CA2H 15h XXXX XXXX uuuu uuuu uuuu uuuu 1 16h 0000 0000 0000 0000 uuuu uuuu TCON2 17h 0000 0000
86. 2 TABLWT2 1 TABLWT2 cycle2 INST PC 2 execute 1 1 1 1 1 1 1 Data write cycle Data write cycle 1996 Microchip Technology Inc DS30412C page 47 PIC17CAX 7 3 Table Reads EXAMPLE 7 2 TABLE READ The table read allows the program memory to be read MOVLW HIGH TBL ADDR Load the Table This allows constant data to be stored in the program address memory space and retrieved into data memory when EL ded Example 7 2 reads 16 bit value nee TABLRD 0 0 DUMMY Dummy read gram memory address TBLPTR After the dummy byte Updates TABLATCH has been read from the TABLATH the TABLATH is TLRD 1 INDFO Read HI byte loaded with the 16 bit data from program memory of TABLATCH address TBLPTR 1 The first read loads the data into TABLRD 0 1 INDFO Read LO byte the latch and can be considered a dummy read of TABLATCH and unknown data loaded into INDFO should be con Update TABLATCH figured for either auto increment or auto decrement FIGURE 7 7 TABLRD TIMING ei Q4 ei Q4 Q4 ei 04 AD15 ADO for De buain Instruction TABLRD fetched INST PC 1 INST PC 2 executed Data read cycle Instruction INST PC 1 TABLRD cycle TABLRD cycle2 INST 1 FIGURE 7 8 TABLRD TIMING CONSECUTIVE TAB
87. 255 dc 0 1 WREG f dest Status Affected Z Encoding 0000 1114 Description Add WREG to register f If d is 0 the result is stored in WREG If d is 1 the result is stored back in register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example ADDWF REG 0 Before Instruction WREG 0x17 REG 0xC2 After Instruction WREG OxD9 REG 0xC2 DS30412C page 112 1996 Microchip Technology Inc PIC17C4X ADDWFC ADD WREG and Carry bit to f Syntax abel ADDWFC fd Operands 0 lt lt 255 d 0 1 Operation WREG f C dest Status Affected Z Encoding 0001 000d ffff ffff Description Add WREG the Carry Flag and data memory location f If d is 0 the result is placed in WREG If d is 1 the result is placed in data memory location Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example ADDWFC REG 0 Before Instruction Carry bit 1 0x02 WREG 9 0 40 After Instruction Carry bit 0 REG 0x02 WREG 0x50 ANDLW And Literal with WREG Syntax abel ANDIW k Operands 0 lt lt 255 Operation WREG AND WREG Status Affected Z Encoding 1011 0101 kkkk kkkk Description The contents of WREG are AND ed with
88. 3V 1904 pue 91HOd lt 0 91 gt 2 H91v1 77271014 91 X58 91 X Mv 0 1014 91 X MP 9b X He 2191 91 NOu WOHd3 gt 19599 Ndo OL S IVNOIS 1 gt 9 lt 9 gt 14 AHOWNWZIN 1 1 viva LNI OVY 201 1 0 9 1HOd 1 5 HO XL SVEH VH 0 LNI OVY Y S1HOd lt g gt sna viva lt 0 2 gt 3unldvo gwg 199 x 10 L eaH ero L vau 2I NMd zad LNMd ca4 Ldv9 044 x lt 94 gt lt 94 gt 1 1318 1 I 3aooaa 1454 0854 5114110 TOHLNOO NOILONYLSNI 1 1 viva PVOLLOld 8 X VSP 8 X EvOLLOld 8 X LOId 8 X ZEZ 8X cec viva 9333198
89. 500 485 29 2 94 16 480 77 3 85 12 500 0 9 500 0 7 8250 0 6250 0 5000 0 4000 0 LOW 32 22 255 24 41 255 19 53 255 15 625 255 BAUD 10 MHz SPBRG FOSC 7 159 MHz SPBRG FOSC 5 068 MHz SPBRG RATE value value value K KBAUD 9 ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 9 6 9 766 1 73 19 2 19 23 0 16 76 8 75 76 1 36 96 96 15 0 16 300 312 5 4 17 500 500 0 HIGH 2500 LOW 9 766 255 9 622 0 23 129 19 24 0 23 32 77 82 41 82 25 94 20 1 88 7 298 3 0 57 4 NA 0 1789 8 255 6 991 185 9 6 0 131 92 19 2 0 65 22 79 2 3 13 15 18 97 48 1 54 12 5 316 8 5 60 3 RE NA m A 0 1267 0 255 4 950 255 Fosc 3 579 MHz KBAUD ERROR FOSC 1 MH SPBRG decimal KBAUD ERROR F 32 768 SPBRG OSC 32 768 kHz value decimal SPBRG value decimal KBAUD ERROR 1996 Microchip Technology Inc DS30412C page 87 PIC17CAX TABLE 13 4 BAUD RATES FOR ASYNCHRONOUS MODE BAUD Fosc 33 MHz SPBRG FOSC 25 MHz SPBRG FOSC 20 MHz SPBRG 16 MHz SPBRG RATE value value value value KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 0 3 NA NA NA NA 1 2 NA NA 1 221 1 73 255 1 202 0 16 207 2 4 2 398 0 07 214 2 396 0 14 162 2 404 0 16 129 2 404 0 16 103 9 6 9 548 0 54 53 9 53
90. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 16h Bank 1 PIR RBIF TMR2IF TMR1IF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010 13h BankO RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00u 14h Bank 0 RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 uuuu uuuu 17h Bank 1 PIE RBIE 2 CA2IE TXIE RCIE 0000 0000 0000 0000 15h 0 TXSTA CSRC TX9 TXEN SYNC TRMT TX9D 0000 1x 0000 1u 17h SPBRG Baud rate generator register uuuu uuuu Legend x unknown u unchanged unimplemented read as a 0 shaded cells are not used for asynchronous reception Note 1 Other non power up resets include external reset through MCLR and Watchdog Timer Reset DS30412C page 92 1996 Microchip Technology Inc PIC17C4X 13 3 USART Synchronous Master Mode In Master Synchronous mode the data is transmitted in a half duplex manner i e transmission and reception do not occur at the same time when transmitting data the reception is inhibited and vice versa The synchro nous mode is entered by setting the SYNC TXSTA lt 4 gt bit In addition the RCSTA lt 7 gt bit is set in order to configure the RA5 and RA4 I O ports to CK clock and DT data lines respectively The Master mode indicates that the processor transmits the master clock on the CK line The Master mode is entered by settin
91. Bits Associated with Timer0 70 Turning On 16 bit Timer 74 Summary of Timer and Timer2 Registers rennes 74 PWM Frequency vs Resolution at 25 MEZ anat fee pentes 76 Registers Bits Associated with PWM 77 Registers Associated with Capture 79 Summary of TMR1 TMR2 and TMR3 Registers 81 Baud Rate Formula 86 Registers Associated with Baud Rate Generator 86 Baud Rates for Synchronous Mode 87 Baud Rates for Asynchronous Mode 88 Registers Associated with Asynchronous Transmission 90 Registers Associated with Asynchronous Reception 92 Registers Associated with Synchronous Master 94 Registers Associated with Synchronous Master Reception 96 Registers Associated with Synchronous Slave 98 Registers Associated with Synchronous Slave Reception Configuration Locations Capacitor Selection for Ceramic Resonaltors eterne 101 Capacitor Selection for Crystal OscillatoR 2 eee eee eeeeeeeeeeeeeeeeteeeeeeeeee 101 Registers Bits Associated with the Watchdog Opcode Field Descriptions
92. Figure 19 5 Figure 19 6 Figure 19 7 Figure 19 8 Figure 19 9 Figure 19 10 Figure 19 11 Figure 19 12 Figure 20 1 Figure 20 2 Figure 20 3 Figure 20 4 Figure 20 5 Figure 20 6 Figure 20 7 Figure 20 8 Figure 20 9 Figure 20 10 Figure 20 11 Figure 20 12 Figure 20 13 Figure 20 14 Figure 20 15 Figure 20 16 Figure 20 17 Figure 20 18 Figure 20 19 Figure 20 20 External Clock CLKOUT and I O Timing Reset Watchdog Timer Oscillator Start Up Timer and Power Up Timer Timing TimerO Clock Timings Timer1 Timer2 and Timer3 Clock Timings 187 Capture Timings 188 PWM 188 USART Module Synchronous Transmission Master Slave Timing 189 USART Module Synchronous Receive Master Slave Timing 189 Memory Interface Write Timing Not Supported in PIC17LC4X Devices 190 Memory Interface Read Timing Not Supported in PIC17LC4X Devices 191 Typical RC Oscillator Frequency vs Temperature 193 Typical RC Oscillator Frequency VS 2 RE 194 Typical RC Oscillator Frequency VSLMDD 194 Typical RC Oscillator Freguency VS MDD s iie 195 Transconductance gm of LF Oscillator VS VDD 196 Transconductance gm
93. Locations Oscillator Word EN 99 CPFSEQ 119 CPFSGT 119 CPFSLT seems 120 CPU STATUS Register CPUSTA 37 CPUSTA si etie eo Mn ee 34 37 105 WERDE 84 Crystal Operation Overtone Crystals 101 Crystal or Ceramic Resonator Operation 100 Crystal Oscillator CSRG haa DE ee Ee D Data Memory cj ER 29 32 Indirect Addressing 39 Organization 32 PR 29 32 Transfer to Program Memory 43 DAW 120 po 9 36 DDRB 19 34 55 DDRC 19 34 58 DDRD 19 34 60 DDRE 19 34 62 DECFSNZ T DEGFSZ eR eene er DINER 1996 Microchip Technology Inc DS30412C page 225 PIC17C4X Delay From External Clock Edge 68 Development Support Development Tools esee Device Drawings 44 Lead Plastic Surface Mount MQFP 10x10 mm 1 6 0 15 mm Lead Form 209 DIGIT BORROW Digit Carry DC Duty ere a ERR d E Electrical Characteristics PIC17C42 Absolute Maximum Ratings 147 Capture Timing CLKOUT and I O Timing DC Characteristics External Cl
94. POINTER TBLPTRH TBLPTRL TABLE LATCH 16 bit TABLATH TABLATL TABLRD i TABLRD 0 i f DATA MEMORY PROGRAM MEMORY Prog Mem TBLPTR Note 1 8 bit value from TABLAT 16 bit high or low byte loaded into register 8 bit value from 16 bit high or low byte loaded into register f 16 bit value at Program Memory TBLPTR loaded into TABLAT register 1 then TBLPTR TBLPTR 1 If i 0 then TBLPTR is unchanged DS30412C page 44 1996 Microchip Technology Inc PIC17C4X 7 1 Table Writes to Internal Memory table write operation to internal memory causes a long write operation The long write is necessary for programming the internal EPROM Instruction execu tion is halted while in a long write cycle The long write will be terminated by any enabled interrupt To ensure that the EPROM location has been well programmed a minimum programming time is required see specifi cation 0114 Having only one interrupt enabled to terminate the long write ensures that no unintentional interrupts will prematurely terminate the long write The sequence of events for programming an internal program memory location should be 1 Disable all interrupt sources except the source to terminate EPROM program write 2 Raise MCLR VPP pin to the programming volt age 3 Clear the WDT 4 Do the table write The interrupt will t
95. Parameter Typ No Characteristic t Max Units Conditions 45 Tt123H TCLK12 and high time 0 5Tcv 20 ns 46 Tt123L TCLK12 and TCLKS low time 0 5Tcv 20 ns 47 Tt123P TCLK12 and TCLK3 input period Tcv 408 ns value 1 2 4 8 48 TckE2tmrl Delay from selected External Clock Edge to 2Tosc 6 6Tosc 6 Timer increment These parameters are characterized but tested t Data in column is at 5V 25 C unless otherwise stated These parameters for design guidance only and are not tested 5 This specification ensured design 1996 Microchip Technology Inc DS30412C page 187 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 FIGURE 19 7 CAPTURE TIMINGS CAP1 and CAP2 Capture Mode TABLE 19 7 CAPTURE REQUIREMENTS Parameter No Sym Characteristic Min Typt Max Units Conditions 50 TccL and input low time 10 ns 51 TccH Capture1 and Capture input high time 10 ns 52 Capture1 and Capture2 input period 2TCY ns N prescale value N 4 or 16 These parameters characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested This specification ensured by design
96. RB2 PWM1 RB3 PWM2 RB4 TCLK12 lt RC3 AD3 RC2 AD2 lt RC1 AD1 lt RCO ADO NC VDD VDD lt RDO AD8 RD1 AD9 RD2 AD10 lt RD3 AD1 1 XVOLIDId RD4 AD12 O gt RD5 AD13 RD6 AD14 gt RD7 AD15 MCLR VPP Vss O lt Vss REO ALE O s RE1 OE O lt RE2 WR TEST 488 gt Doz VH Coz ANVOVH Og 988 gt Oe 1NOH19 79S0 Ozz HO XL SVH gt 5 RE2 WR RE1 OE REO ALE Vss Vss MCLR VPP RD7 AD15 RD6 AD14 RD5 AD13 RD4 AD12 RA1 TOCKI lt RA2 lt OSC2 CLKOUT OSC1 CLKIN RA4 RX DT RB7 lt RAS TX CK RB6 34 ELLA RB5 TCLK3 92 8 On 09 I aaa gt ON tav eou ec LIQYEQ4 CU 33 OL RB4 TCLK12 32 RB3 PWM2 31 LE lt gt RB2 PWM1 lt RB1 CAP2 RBO CAP1 Vss Vss RC7 AD7 lt RC6 AD6 RC5 AD5 lt RC4 AD4 All devices are available in all package types listed in Section 21 0 with the following exceptions ROM devices are not available in Windowed CERDIP Packages
97. Register DDR which is used to configure the port pins as inputs or outputs These five ports are made up of 33 I O pins Some of these ports pins are multiplexed with alternate functions PORTO PORTD and PORTE are multiplexed with the System bus These pins are configured as the system bus when the device s configuration bits are selected to Microprocessor or Extended Microcontroller modes In the two other microcontroller modes these pins are general purpose PORTA and PORTB are multiplexed with the peripheral features of the device These peripheral features are Timer modules Capture module PWM module USART SCI module External Interrupt pin When some of these peripheral modules are turned on the port pin will automatically configure to the alternate function The modules that do this are PWM module USART SCI module When pin is automatically configured as an output by a peripheral module the pins data direction DDR bit is unknown After disabling the peripheral module the user should re initialize the DDR bit to the desired con figuration The other peripheral modules which require an input must have their data direction bit configured appropri ately Note A pin is a peripheral input can be con figured as an output DDRx y is cleared The peripheral events will be determined by the action output on the port pin 9 1 PORTA Register PORTA is a 6 bit wide latc
98. Schmitt Trigger input It is not recommended that the PIC17CXX devices be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 These specifications are for the programming of the on chip program memory EPROM through the use of the table write instructions The complete programming specifications can be found in PIC17CXX Programming Specifications Literature number 0530139 5 The MCLR VPP pin may be kept in this range at times other than programming but is not recommended 6 For TTL buffers the better of the two specifications may be used Note When using the Table Write for internal programming the device temperature must be less than 40 C DS30412C page 152 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 R42 42A 43 43 44 17 3 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats 1 TppS2ppS 2 TppS T F Frequency T Time Lowercase symbols pp and their meanings ad Address Data ost Oscillator Start up Timer al ALE pwrt Power up Timer Capture and Capture2 rb PORTB ck CLKOUT or clock rd RD dt Data in nw RD or WR in INT pin 10
99. Table 5 1 If two enabled interrupts occur at the same time the interrupt of the highest priority will be ser viced first This means that the vector address of that interrupt will be loaded into the program counter PC Note 1 Individual interrupt flag bits are set regard less of the status of their corresponding mask bit or the GLINTD bit Note 2 Note 3 GOTO LOOP When disabling any of the INTSTA enable bits the GLINTD bit should be set disabled For the PIC17C42 only If an interrupt occurs while the Global Inter rupt Disable GLINTD bit is being set the GLINTD bit may unintentionally be re enabled by the users Interrupt Service Routine the RETFIE instruction The events that would cause this to occur are 1 An interrupt occurs simultaneously with an instruction that sets the GLINTD bit 2 The program branches to the Interrupt vector and executes the Interrupt Ser vice Routine 3 The Interrupt Service Routine com pletes with the execution of the RET FIE instruction This causes the GLINTD bit to be cleared enables interrupts and the program returns to the instruction after the one which was meant to disable interrupts The method to ensure that interrupts are globally disabled is 1 Ensure that the GLINTD bit was set by the instruction as shown in the follow ing code CPUSTA GLINTD Disable Global Interrupt Global Interrupt Disabled NO try
100. This port is configured as the system bus when the device s configuration bits are selected to Microprocessor or Extended Microcontroller modes In the two other microcontroller modes this port is a gen eral purpose Example 9 4 shows the instruction sequence to initial ize PORTE The Bank Select Register BSR must be selected to Bank 1 for the port to be initialized EXAMPLE 9 4 INITIALIZING PORTE MOVLB 1 Select Bank 1 CLRF PORTE Initialize PORTE data latches before setting 2 the direction register MOVLW 0x03 Value used to initialize data direction MOVWF DDRE Set lt 1 0 gt inputs RE lt 2 gt as outputs 3 RE 7 3 are always read as 0 FIGURE 9 8 PORTE BLOCK DIAGRAM IN 1 0 PORT MODE Data Bus TTL Input Buffer RD PORTE WR PORTE RD DDRE WR DDRE EX EN CNTL svsBUS SYS Control Note pins have protection diodes to VDD and Vss DS30412C page 62 1996 Microchip Technology Inc PIC17C4X TABLE 9 9 PORTE FUNCTIONS Name Bit Buffer Type Function REO ALE bitO TTL Input Output or system bus Address Latch Enable ALE control pin Input Output or system bus Output Enable OE control pin RE1 OE bit TTL RE2 WR bit2 TTL Input Output
101. WREG a useful special situation is particularly useful for transfer ring a peripheral register e g the timer or an I O port to a data memory loca tion Both f and p can be indirectly addressed Words 1 Cycles 1 Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register p register f Example MOVPF REG1 REG2 Before Instruction 0x11 REG2 0x33 After Instruction 0x11 REG2 0x11 MOVWF Move WREG to f Syntax label MOVWF f Operands 0 lt 1 lt 255 Operation WREG f Status Affected None Encoding 0000 0001 ffff Description Move data from WREG to register f Location can be anywhere in the 256 word data space Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register f Example MOVWE REG Before Instruction WREG Ox4F REG OxFF After Instruction WREG Ox4F REG Ox4F EE eel DS30412C page 128 1996 Microchip Technology Inc PIC17C4X MULLW Multiply Literal with WREG Syntax label MULLW Operands lt lt 255 Operation x WREG PRODH PRODL Status Affected None Encoding 1011 1100 kkkk kkkk Description An unsigned multiplication is carried out between the contents of WREG and the 8 bit literal k The 16 bit result is placed in PRODH PRODL register pair PR
102. amp bitMode emere er 738 External Clock Input ini TO Overview 65 Timer Mode 2 81 Timing in External Clock Mode 80 Two 8 bit Timer Counter Mode 73 Using with 75 71 TMRIIE 23 TMRIIF 24 nisle 72 TMR2 20 35 8 bit i eee i pine 73 External Clock Input i In Timer Mode 2 81 Timing in External Clock Mode Two 8 bit Timer Counter Mode Using with PWM 75 265 riii 71 TMROIE ero e s a 23 TMR3 Dual Capture1 Register Mode 79 Example Reading 80 Example Writing 80 External Clock Input E In Timer Mode centre eerte 81 One Capture and One Period Register Mode 78 Overview E Reading Writing sisi 80 Timing in External Clock Mode 80 TMR3CS T ire iiec e tritt is TMRGIF TMRO2L de o a TMR3ON pita an e tet Transmit Status and Control Register s inno oe ets ene OEE E TSTFSZ Turning on 16 bit Timer TXO
103. development tools The PC compatible 386 and higher machine platform and Microsoft Windows 3 x environment were chosen to best make these fea tures available to you the end user A CE compliant version of PICMASTER is available for European Union EU countries 16 3 ICEPIC Low cost PIC16CXXX In Circuit Emulator ICEPIC is a low cost in circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8 bit OTP microcontrollers ICEPIC is designed to operate on PC compatible machines ranging from 286 through Pentium based under Windows environment ICEPIC features real time non intrusive emulation 16 4 PRO Il Universal Programmer The PRO MATE Universal Programmer is a full fea tured programmer capable of operating in stand alone mode as well as PC hosted mode The PRO MATE has programmable and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability It has an LCD display for displaying error messages keys to enter commands and a modular detachable socket assembly to support various package types In stand alone mode the PRO MATE can read verify or pro PIC16C5X PIC16CXXX PIC17CXX PIC14000 devices It can also set configuration and code protect bits in this mode 16 5 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy to use low cost prototype
104. either clear the SPEN bit or the TXEN bit This will reset the transmit logic so that it will be in the proper state when transmit is re enabled 1996 Microchip Technology Inc DS30412C page 93 PIC17C4X TABLE 13 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 16h Bank 1 PIR RBIF TMRSIF TMR2IF TMR1IF CA2IF 0000 0010 0000 0010 13h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00u 16h BankO TXREG TX7 TX6 TX5 TX3 TX2 TX1 uuuu uuuu 17h Bank 1 PIE RBIE TMR2IE CA2IE TXIE RCIE 0000 0000 0000 0000 151 BankO TXSTA CSRC TX9 TXEN SYNC TRMT TX9D 0000 1x 0000 1u 17h SPBRG Baud rate generator register XXXX XXXX uuuu uuuu Legend x unknown u unchanged unimplemented read as a 0 shaded cells are not used for synchronous master transmission Note 1 Other non power up resets include external reset through MCLR and Watchdog Timer Reset FIGURE 13 9 SYNCHRONOUS TRANSMISSION lados laaalos odas 5280 15 laglasjasa odas OC OX XC Wordi DT RA4 RX DT pin
105. for RC frequency variation from part to part due to normal process variation The variation is larger for larger R since leakage current variation will affect RC frequency more for large R and for smaller C since variation of input capacitance will affect RC fre quency more See Section 18 0 for variation of oscillator frequency due to VDD for given Rext Cext values as well as fre quency variation due to operating temperature for given C and Vpp values The oscillator frequency divided by 4 is available on the OSC2 CLKOUT pin and can be used for test pur poses or to synchronize other logic see Figure 3 2 for waveform FIGURE 14 7 RC OSCILLATOR MODE Internal clock am PIC17CXX OSC2 CLKOUT Fosc 4 1996 Microchip Technology Inc PIC17C4X 14 8 Watchdog Timer WDT The Watchdog Timer s function is to recover from soft ware malfunction The WDT uses an internal free run ning on chip RC oscillator for its clock source This does not require any external components This RC oscillator is separate from the RC oscillator of the OSC1 CLKIN pin That means that the WDT will run even if the clock on the OSC1 CLKIN and OSC2 CLK OUT pins of the device has been stopped for example by execution of a SLEEP instruction During normal operation and SLEEP mode a WDT time out gener ates a device RESET The WDT can be permanently disabled by programming the configuration bits
106. from f Syntax label SUBWF 5 Operands 0 lt 1 lt 255 0 1 f W dest Status Affected OV C DC 2 Encoding 0000 0104 ffff ffff Description Subtract WREG from register 25 complement method is 0 the result is stored in WREG If d is 1 the result is stored back in register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example 1 SUBWF 1 Before Instruction REG1 3 WREG 2 2 After Instruction REG1 1 WREG 2 C 1 result is positive 2 0 2 Before Instruction REG1 2 WREG 2 After Instruction REG1 0 WREG 2 C 1 result is zero Z 1 3 Before Instruction REG1 1 WREG 2 After Instruction REG1 FF WREG 2 C 0 result is negative 2 0 SUBWFB Subtract WREG from f with Borrow Syntax label SUBWFB Operands lt lt 255 d e 0 1 Operation f W C gt dest Status Affected C DC 2 Encoding 0000 0014 ffff ffff Description Subtract WREG and the carry flag borrow from register 25 comple ment method If d is 0 the result is stored WREG If d is 1 the result is stored back in register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example 1 SUBWFB 1 Before Instruction REGI 0x19 0001
107. input to the TimerO timer counter RA2 24 26 42 ST High voltage high current open drain input output port pins RA3 23 25 41 5 High voltage high current open drain input output port pins RA4 RX DT 22 24 40 ST RA4 RX DT can also be selected as the USART SCI Asynchronous Receive or USART SCI Synchronous Data RA5 TX CK 21 23 39 ST can also be selected as the USART SCI Asynchronous Transmit or USART 5 Synchronous Clock PORTB is a bi directional I O Port with software configurable weak pull ups RBO CAP1 11 13 29 y o ST RBO CAP1 can also be the input pin RB1 CAP2 12 14 30 ST RB1 CAP2 can also be the CAP2 input pin RB2 PWM1 13 15 31 y o ST RB2 PWM1 can also be the PWM1 output pin RB3 PWM2 14 16 32 ST RB3 PWM2 can also be the PWM2 output pin RB4 TCLK12 15 17 33 ST RB4 TCLK12 can also be the external clock input to Timer1 and Timer2 RB5 TCLK3 16 18 34 ST RB5 TCLK3 can also be the external clock input to Timer3 RB6 17 19 35 ST RB7 18 20 36 ST PORTO is a bi directional I O Port RCO ADO 2 3 19 TTL This is also the lower half of the 16 bit wide system bus RC1 AD1 3 4 20 VO TTL in microprocessor mode or extended microcontroller RC2 AD2 4 5 21 O TTL mode multiplexed system bus configuration these RC3 AD3 5 6 22 vo TTL pins are address output as well as data input or output RC4 AD4 6 7 23 TTL RC5 AD5 7 8 24
108. is POPed and the GLINTD bit is cleared to re enable interrupts Wake up If in SLEEP mode or terminate long write TOIE INTF UNTE D to CPU TOCKIF TOCKIE PEIF PEIE GLINTD 1996 Microchip Technology Inc DS30412C page 21 PIC17C4X 5 1 Interrupt Status Register INTSTA Note INTF TOCKIF or PEIF will be set by the specified condition even if the corre sponding interrupt enable bit is clear inter rupt disabled or the GLINTD bit is set all interrupts disabled The Interrupt Status Control register INTSTA records the individual interrupt requests in flag bits and con tains the individual interrupt enable bits not for the peripherals i T Care should be taken when clearing any of the INTSTA The PEIF bit Sa read only bit wise OR of all the periph register enable bits when interrupts are enabled eral flag bits in the PIR register Figure 5 4 is clear If any of the INTSTA flag bits TOIF or PEIF are set in the same instruction cycle as the corresponding interrupt enable bit is cleared the device will vector to the reset address 0x00 When disabling any of the INTSTA enable bits the GLINTD bit should be set disabled FIGURE 5 2 INTSTA REGISTER ADDRESS 07h UNBANKED 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 0 PEIF TOCKIF TOIF INTF PEIE TOCKIE
109. is detected 1 Rising edge of RAO INT pin generates interrupt 0 Falling edge of RAO INT pin generates interrupt bit6 TOSE TimerO Clock Input Edge Select bit This bit selects the edge upon which TMRO will increment When TOCS 0 1 Rising edge of RA1 TOCKI pin increments TMRO and or generates a TOCKIF interrupt 0 Falling edge of RA1 TOCKI pin increments TMRO and or generates a TOCKIF interrupt When TOCS 1 Don t care bit5 TOCS TimerO Clock Source Select bit This bit selects the clock source for TMRO 1 Internal instruction clock cycle TCY 0 TOCKI pin bit 4 1 PS3 PSO TimerO Prescale Selection bits These bits select the prescale value for TMRO 53 50 Prescale Value 0000 1 1 0001 1 2 0010 1 4 0011 1 8 0100 1 16 0101 1 32 0110 1 64 0111 1 128 1 256 bit 0 Unimplemented Read as 0 1996 Microchip Technology Inc DS30412C page 67 PIC17C4X 11 1 0 Operation When the TOCS TOSTA lt 5 gt bit is set TMRO incre ments on the internal clock When TOCS is clear TMRO increments on the external clock RA1 TOCKI pin The external clock edge can be configured in software When the TOSE TOSTA 6 bit is set the timer will increment on the rising edge of the RA1 TOCKI pin When TOSE is clear the timer will increment on the fall ing edge of the RA1 TOCKI pin The prescaler can be programmed to introduce a prescale of 1 1 to 1 256 The timer increments from 0000h to FFFFh and roll
110. is set after a device reset When the stack pointer equals Fh STKAV is cleared When the stack pointer rolls over from Fh to Oh the STKAV bit will be held clear until a device reset Note 1 There is not a status bit for stack under flow The STKAV bit can be used to detect the underflow which results in the stack pointer being at the top of stack Note 2 There are no instruction mnemonics called PUSH or POP These are actions that occur from the execution of the CALI RETURN RETLW and RETFIE instruc tions or the vectoring to an interrupt vec tor Note 3 After a reset if a POP operation occurs before a PUSH operation the STKAV bit will be cleared This will appear as if the stack is full underflow has occurred If a PUSH operation occurs next before another POP the STKAV bit will be locked clear Only a device reset will cause this bit to set After the device is PUSHed sixteen times without a POP the seventeenth push overwrites the value from the first push The eighteenth push overwrites the second push and so on 6 4 Indirect Addressing Indirect addressing is a mode of addressing data memory where the data memory address in the instruction is not fixed That is the register that is to be read or written can be modified by the program This can be useful for data tables in the data memory Figure 6 10 shows the operation of indirect address ing This shows the
111. moving of the value to the data memory address specified by the value of the FSR register Example 6 1 shows the use of indirect addressing to clear RAM in a minimum number of instructions A similar concept could be used to move a defined num ber of bytes block of data to the USART transmit reg ister TXREG The starting address of the block of data to be transmitted could easily be modified by the program FIGURE 6 10 INDIRECT ADDRESSING Instruction Executed 328 7 Address File INDFx Instruction Fetched Opcode 1996 Microchip Technology Inc DS30412C page 39 PIC17C4X 6 4 1 INDIRECT ADDRESSING REGISTERS PIC17C4X has four registers for indirect address ing These registers are INDFO and FSRO INDF1 and FSR1 Registers INDFO and INDF1 are not physically imple mented Reading or writing to these registers activates indirect addressing with the value in the correspond ing FSR register being the address of the data The FSR is an 8 bit register and allows addressing any where in the 256 byte data memory address range For banked memory the bank of memory accessed is specified by the value in the BSR If file INDFO or INDF1 itself is read indirectly via an FSR 05 are read Zero bit is set Similarly if INDFO or INDF1 is written to indirectly the operation will be equivalent to a and the status bits are not
112. of the clock on the RA5 TX CK pin Data out is stable around the falling edge of the synchronous clock Figure 13 10 The transmission can also be started by first loading TXREG and then setting TXEN This is advantageous when slow baud rates are selected since BRG is kept in RESET when the TXEN CREN and SREN bits are clear Setting the TXEN bit will start the BRG creating a shift clock immediately Normally when transmission is first started the TSR is empty so a transfer to TXREG will result in an immediate transfer to the TSR resulting in an empty TXREG Back to back transfers are possible Clearing TXEN during a transmission will cause the transmission to be aborted and will reset the transmit ter The RA4 RX DT and 5 pins will revert to hi impedance If either CREN or SREN are set during a transmission the transmission is aborted and the RA4 RX DT reverts to a hi impedance state for a reception The RAS TX CK pin will remain an output if the CSRC bit is set internal clock The transmitter logic is not reset although it is disconnected from the pins In order to reset the transmitter the user has to clear the TXEN bit If the SREN bit is set to interrupt an ongoing transmission and receive a single word then after the single word is received SREN will be cleared and the serial port will revert back to transmitting since the TXEN bit is still set The DT line will immediately switch from hi impedance r
113. on an The actual write to an port happens at the end of an instruction cycle whereas for reading the data must be valid at the beginning of the instruction cycle Figure 9 9 Therefore care must be exercised if a write followed by a read operation is carried out on the same I O The sequence of instructions should be such to allow the pin voltage to stabilize load dependent before executing the instruction that reads the values on that port Otherwise the previous state of that pin may be read into the CPU rather than the new state When in doubt it is better to separate these instructions with NOP or another instruction not accessing this I O port FIGURE 9 9 SUCCESSIVE I O OPERATION Qi Q2 03 04 Q1 02 04 Q1 02 Q3 Q4 Q1 02 Q3 Q4 Note PC X PC 1 2 X PC 3 This example shows a write to PORTB Instruction followed by a read from PORTE fetched PORTB W Note that write to j data setup time 0 25 TPD PORTB where instruction cycle TPD propagation delay Therefore at higher clock frequencies a write followed by a read may be problematic NOP NOP RB7 RB0 pin sampled here MOVWF PORTB MOVF PORTB W write to PORTB executed 1 1 Instruction DS30412C page 64 1996 Microchip Technology Inc PIC17C4X 10 0 OVERV
114. or 1024Tosc time out seguence begins from the first rising edge of MCLH Table 4 3 shows the reset conditions for some special registers while Table 4 4 shows the initialization condi tions for all the registers The shaded registers in Table 4 4 are for all devices except the 17 42 In the PIC17C42 the PRODH and PRODL registers are general purpose RAM TABLE 4 2 STATUS BITS AND THEIR SIGNIFICANCE TO PD Event 1 1 Power on Reset MCLR Reset during normal operation or CLRWDT instruction executed 1 0 MCLR Reset during SLEEP or interrupt wake up from SLEEP 0 1 WDT Reset during normal operation 0 0 Reset during SLEEP In Figure 4 2 Figure 4 3 and Figure 4 4 TPWRT gt TOST as would be the case in higher frequency crys tals For lower frequency crystals i e 32 kHz TOST would be greater TABLE 4 3 RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER Event PCH PCL CPUSTA OST Active Power on Reset 0000h 11 11 Yes MCLR Reset during normal operation 0000h 11 11 No MCLR Reset during SLEEP 0000h 11 10 Yes 2 WDT Reset during normal operation 0000h 11 01 No WDT Reset during SLEEP 9 0000h 1 00 Yes 2 Interrupt wake up from SLEEP GLINTD set 1 11 10 Yes 2 GLINTD is clear PC 1 1 10 10 Yes 2 Legend u unchanged x unknown unimplemented read as
115. protected mode 2 0007 Note 2 does not exist on the PIC17C42 select code protected microcontroller mode PM1 PMO 00 In this mode instructions that are in the on chip pro gram memory space can continue to read or write the program memory An instruction that is executed out side of the internal program memory range will be inhib ited from writing to or reading from program memory Note Microchip does not recommend code tecting windowed devices If the code protection bit s have not been pro grammed the on chip program memory can be read out for verification purposes DS30412C page 106 1996 Microchip Technology Inc PIC17C4X 15 0 INSTRUCTION SET SUMMARY The PIC17CXX instruction set consists of 58 instruc tions Each instruction is a 16 bit word divided into an OPCODE and one or more operands The opcode specifies the instruction type while the operand s fur ther specify the operation of the instruction The PIC17CXX instruction set can be grouped into three types byte oriented bit oriented literal and control operations These formats are shown in Figure 15 1 Table 15 1 shows the field descriptions for the opcodes These descriptions are useful for under standing the opcodes in Table 15 2 and in each spe cific instruction descriptions byte oriented instructions represents regis ter designator and d represents a destination design
116. siete TX9d TXEN TXIE TXREG 19 34 89 93 97 98 XS TA He te ente 19 34 92 96 98 U Upward Compatibility eee 5 USART Asynchronous Master Transmission 90 Asynchronous 89 Asynchronous Receive Asynchronous Transmitter 89 Baud Rate Generator 86 Synchronous Master Mode 93 Synchronous Master Reception 95 Synchronous Master Transmission 93 Synchronous Slave Mode 97 Synchronous Slave Transmit 97 Wake up from SLEEP 105 Wake up from SLEEP Through Interrupt 105 Watchdog Timer 99 103 530412 230 1996 Technology Inc PIC17C4X acte gii oe eme eere ERES 99 103 LIST OF EXAMPLES Clearing the 103 Example 3 1 Signed 9 Normal Timer 103 Example 3 2 Instruction Pipeline Flow 14 Period 103 Example 5 1 Saving STATUS and WREG in RAM 27 Programming Considerations 103 Example 6 1 Indirect Addressing WDTPSO 99 Example 7 1 Table Write WDTPS1 sens 99 Example 7 2 Table WRBEQ
117. that If the GLINTD bit is cleared prior to the long write are not fully programmed and may lose when the long write is terminated the program will their state over time branch to the interrupt vector If the GLINTD bit is set prior to the long write when the long write is terminated the program will not vector to the interrupt address TABLE 7 1 INTERRUPT TABLE WRITE INTERACTION Interrupt Enable Flag Source SENTE Bit Bit Action RA0 INT TMRO 0 1 1 Terminate long table write to internal program TOCKI memory branch to interrupt vector branch clears flag bit 0 1 0 None 1 0 x None 1 1 1 Terminate table write do not branch to interrupt vector flag is automatically cleared Peripheral PK OF Terminate table write branch to interrupt vector None None Terminate table write do not branch to interrupt vector flag is set 1996 Microchip Technology Inc DS30412C page 45 PIC17CAX 7 2 Table Writes to External Memory 7 2 2 TABLE WRITE CODE Table writes to external memory are always two cycle The i operand of the TABLWT instruction can specify instructions The second cycle writes the data to the that the value in the 16 bit TBLPTR register is auto external memory location The sequence of events for matically for the next write an external memory write are the same for an internal Example 7 1 the TBLPTR register is not automatically
118. the internal instruction cycle clock or from an external clock source on the RB4 TCLK12 pin The timer clock source is con figured by the TMRxCS bit x 1 for Timer1 or 2 for Timer2 When TMRxCS is clear the clock source is internal and increments once every instruction cycle Fosc 4 When TMRxCS is set the clock source is the RB4 TCLK12 pin and the timer will increment on every falling edge of the RBA TCLK12 pin The timer increments from 00h until it equals the Period register PRx It then resets to 00h at the next incre ment cycle The timer interrupt flag is set when the timer is reset TMR1 and 2 have individual interrupt flag bits The 1 interrupt flag bit is latched into TMR1IF and the TMR2 interrupt flag bit is latched into TMR2IF Each timer also has a corresponding interrupt enable bit TMRxIE The timer interrupt can be enabled by set ting this bit and disabled by clearing this bit For periph eral interrupts to be enabled the Peripheral Interrupt Enable bit must be enabled PEIE is set and global interrupts must be enabled GLINTD is cleared The timers can be turned on and off under software control When the Timerx On control bit TMRxON is set the timer increments from the clock source When is cleared the timer is turned off and cannot cause the timer interrupt flag to be set 12 1 1 1 EXTERNAL CLOCK INPUT FOR TIMER1 OR TIMER2 When TMRxCS is set the clock source is the RB4
119. tion All devices are tested to operate at min values with an external clock applied to the OSC1 pin When an external clock input is used the cycle time limit is no clock for all devices 1996 Microchip Technology Inc DS30412C page 155 PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 17 3 CLKOUT AND I O TIMING Pin input euro old value new value T In EC and RC modes only TABLE 17 3 CLKOUT AND I O TIMING REQUIREMENTS Parameter No Sym Characteristic Min Typt Max Units Conditions TosH2ckL OSC1T to CLKOUT TosH2ckH OSC1T to CLKOUTT TckR CLKOUT rise time TckF CLKOUT fall time 153 TckH2ioV CLKOUTT to Port out valid 0 5TCY 204 TioV2ckH Port in valid before CLKOUTT 0 25TCY 25 TckH2iol Port in hold after CLKOUTT 0t TosH2ioV 1 Q1 cycle to Port out valid TioR Port output rise time 21 TioF Port output fall time 10 351 5 22 TinHL INT pin high or low time 25 ns 23 TrbHL RB7 RB0 change INT high or low time 25 ns These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not parameters are for design guidance only and are tested nor characterized Note 1 Measurements are taken in EC Mode where OSC2
120. to PORTB 16 7 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 is a simple demonstration board that supports the 16 62 PIC16C64 PIC16C65 PIC16C73 and PIC16C74 microcontrollers the necessary hardware and software is included to run the basic demonstration programs The user can program the sample microcontrollers provided with the PICDEM 2 board on a PRO MATE II pro grammer or PICSTART 16C and easily test firmware The PICMASTER emulator may also be used with the PICDEM 2 board to test firmware Additional prototype area has been provided to the user for adding addi tional hardware and connecting it to the microcontroller socket s Some of the features include a RS 232 inter face push button switches a potentiometer for simu lated analog input a Serial EEPROM to demonstrate usage of the bus and separate headers for connec tion to an LCD module and a keypad 16 8 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package It will also support future 44 pin PLCC microcontrollers with a LCD Module the neces sary hardware and software is included to run the basic demonstration programs The user can pro gram the sample microcontrollers provided with the PICDEM 3 board on a PRO MATE II program mer or PICSTART Plus with an adapter socket and easily test firmware The PICMASTER emulator may al
121. 0 Note 1 On wake up this instruction is executed The instruction at the appropriate interrupt vector is fetched and then executed 2 The OST is only active when the Oscillator is configured for XT or LF modes 3 The Program Counter 0 that is the device branches to the reset vector This is different from the mid range devices DS30412C page 16 1996 Microchip Technology Inc PIC17C4X FIGURE 4 2 TIME OUT SEQUENCE ON POWER UP MCLR TIED TO VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET FIGURE 4 3 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED Vpp VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET FIGURE 4 4 SLOW RISE TIME MCLR TIED TO VDD INTERNAL POR PWRT OST TIME OUT INTERNAL RESET 1996 Microchip Technology Inc DS30412C page 17 PIC17C4X FIGURE 4 5 OSCILLATORSTART UPTIME FIGURE 4 8 PIC17C42 EXTERNAL POWER ON RESET CIRCUIT FOR SLOW POWER UP MCLR PIC17C42 MUTO OST TIME OUT PWRT TIME OUT TPWRT Note 1 An external Power on Reset circuit is required only if VDD power up time is too slow The diode D helps discharge the capacitor quickly when VDD powers INTERNAL RESET This figure shows in greater detail the
122. 0 0000 0010 13h BankO RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00u 14h Bank 0 RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RXO XXXX XXXX uuuu uuuu 17h Bank 1 PIE RBIE 2 2 TXIE RCIE 0000 0000 0000 0000 15h BankO TXSTA CSRC TX9 TXEN SYNC TRMT TX9D 0000 1x 0000 1u 17h SPBRG Baud rate generator register XXXX XXXX uuuu uuuu Legend x unknown u unchanged unimplemented read as a 0 shaded cells are not used for synchronous master reception Note 1 Other non power up resets include external reset through MCLR and Watchdog Timer Reset HS REEL Iont 24 HS I IS IE MM DS30412C page 96 1996 Technology Inc PIC17C4X 134 USART Synchronous Slave Mode The synchronous slave mode differs from the master mode in the fact that the shift clock is supplied exter nally at the RA5 TX CK pin instead of being supplied internally in the master mode This allows the device to transfer or receive data in the SLEEP mode The slave mode is entered by clearing the CSRC TXSTA lt 7 gt bit 13 4 1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the sync master and slave modes are identical except in the case of the SLEEP mode If two words are written to TXREG and then the SLEEP instruction executes the following will occur The first word will immediately transfer to the TSR and will trans mit as the shif
123. 0 76 40 9 469 1 36 32 9 615 0 16 25 19 2 19 09 0 54 26 19 53 1 73 19 19 53 1 73 15 19 23 0 16 12 76 8 73 66 4 09 6 78 13 1 73 4 78 13 1 73 3 83 33 8 51 2 96 103 12 7 42 4 97 65 1 73 3 104 2 8 51 2 NA 300 257 81 14 06 1 390 63 30 21 0 312 5 4 17 0 500 515 62 3 13 0 NA NA HIGH 515 62 0 0 312 5 0 250 0 LOW 2 014 255 1 53 255 1 221 255 0 977 255 BAUD Fosc 10 MHz SPBRG FOSC 7 159 MHz SPBRG FOSC 5 068 MHz SPBRG RATE value value value K KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 0 3 NA NA 0 31 3 13 255 1 2 1 202 0 16 129 1 203 0 23 92 1 2 0 65 2 4 2 404 0 16 64 2 380 0 83 46 2 4 0 32 9 6 9 766 1 73 15 9 322 2 90 11 9 9 3 13 r 19 2 19 53 1 73 7 18 64 2 90 5 19 8 3 13 3 76 8 78 13 1 73 1 79 2 3 13 0 96 NA NA 300 NA NA 500 NA NA NA HIGH 156 3 0 111 9 0 79 2 0 LOW 0 610 255 0 437 255 0 309 255 SPBRG value decimal KBAUD ERROR FOSC 1 MHz KBAUD SPBRG value ERROR decimal FOSC 32 768 kHz KBAUD ERROR SPBRG value decimal DS30412C page 88 1996 Microchip Technology Inc PIC17C4X 13 2 USART Asynchronous Mode In this mode the USART uses standard nonre turn to zero NRZ format one start bit eight or nine da
124. 0000 0000 0000 15h BankO TXSTA CSRC TX9 TXEN SYNC TRMT TX9D 0000 1x 0000 1u 17h SPBRG Baud rate generator register XXXX XXXX uuuu uuuu Legend x unknown u unchanged unimplemented read as a 0 shaded cells are not used for synchronous slave reception Note 1 Other non power up resets include external reset through MCLR and Watchdog Timer Reset DS30412C page 98 1996 Technology Inc PIC17CAX 14 0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other proces Sors are special circuits to deal with the needs of real time applications The PIC17CXX family has a host of such features intended to maximize system reliability minimize cost through elimination of external compo nents provide power saving operating modes and offer code protection These are OSC selection Reset Power on Reset POR Power up Timer PWRT Oscillator Start up Timer OST Interrupts Watchdog Timer WDT SLEEP Code protection FIGURE 14 1 CONFIGURATION WORD The PIC17CXX has a Watchdog Timer which can be shut off only through EPROM bits It runs off its own RC oscillator for added reliability There are two timers that offer necessary delays on power up One is the Oscil lator Start up Timer OST intended to keep the chip in RESET until the crystal oscillator is stable The other is the Power up Timer PWRT which provides a fixed delay of 96 ms nominal
125. 001d utd pp dig 9 0 14 5 Oel IdS CAL 89291214 d3O L d40N 001d utd pr dig 224 95 791291214 d3O L d40N 001d dig 5 9 9 Lld d40N 001d did 24 45 v999191d 9105 uld gz 14 5 Oal ldS COWL 2999 Lld 9105 uld gz luvsn Oal IdS 6929014 4055 0105 uid gz 24 45 094291214 4055 2105 uid gz 4088 2105 uid gz 24 45 Oal IdS CULL Sso1meeJ 1996 Microchip Technology Inc DS30412C page 216 PIC17CAX PIC16C7X Family of Devices E 5 5 10 sejes 990 INOA 12591409 SION eyep pue jenas esn Alwe X 29 LOId Ayiqedeo jueno pue 19e104d epoo e qeioejes AWE L 9 514 IV 4301 d40N 9 did 0 oz 09101 d40N 99714 1uvsn did Oal IdS 02 7
126. 13 WREG 0x93 LCALL Long Call Syntax label Operands 0 lt lt 255 Operation PC 1 TOS k PCL PCLATH PCH Status Affected Encoding 1011 0111 kkkk kkkk Description LCALL allows an unconditional subrou tine call to anywhere within the 64k pro gram memory space First the return address PC 1 is pushed onto the stack A 16 bit desti nation address is then loaded into the program counter The lower 8 bits of the destination address is embedded in the instruction The upper 8 bits of PC is loaded from PC high holding latch PCLATH Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write literal k register PCL Forced NOP NOP Execute NOP Example MOVLW HIGH SUBROUTINE MOVPF LCALL WREG PCLATH LOW SUBROUTINE Before Instruction SUBROUTINE PC After Instruction PC 16 bit Address Address SUBROUTINE 1996 Microchip Technology Inc DS30412C page 125 PIC17C4X MOVFP Move f to p MOVLB Move Literal to low nibble in BSR Syntax label fp Syntax abel MOVLB Operands 0 lt lt 255 Operands lt lt 15 0 lt lt 31 Operation k BSR lt 3 0 gt Operation f gt p Status Affected None Status Affected None Encoding 1011 1000 uuuu kkkk Encoding 011 pppp ffff Description The four bit literal is loaded in the Description
127. 164 Typical RC Oscillator Frequency VS iei eget e xoc x 164 Typical RC Oscillator Frequency VS rte irae 165 Transconductance gm of LF Oscillator eerie nA 166 Transconductance gm of XT Oscillator VS VDD 166 Typical IDD vs Frequency External Clock 25 C sist 167 Maximum IDD vs Frequency External Clock 125 C to 40 167 Typical IPD vs VDD Watchdog Disabled 25 168 Maximum IPD vs Watchdog Disabled rre pee 168 Typical IPD vs Watchdog Enabled 25 C 169 Maximum IPD vs Watchdog Enabled 169 Timer Time Out Period vs VDD 170 vs VDD 170 vs VDD 5 171 IOL vs VOL VDD 171 IOL vs VOL VDD 5 172 VTH Input Threshold Voltage of Pins TTL vs VDD 172 VTH VIL of I O Pins Schmitt Trigger vs VDD Stites ib oie ean 173 VTH Input Threshold Voltage of OSC1 Input In XT and LF Modes vs VDD 173 Parameter Measurement Information 183 DS30412C page 232 1996 Microchip Technology Inc PIC17CAX Figure 19 2 Figure 19 3 Figure 19 4
128. 16h TXREG Serial port transmit register XXXX XXXX uuuu uuuu 17h SPBRG Baud rate generator register XXXX XXXX uuuu uuuu Bank 1 10h DDRC Data direction register for PORTC 1111 1111 1111 1111 ith PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO eat amas anois AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO 12h DDRD Data direction register for PORTD 1111 1111 1111 1111 13h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO det Eme amu AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 14h DDRE Data direction register for PORTE SELS STE 15h PORTE RE2 WR RE1 OE REO ALE xxx uuu 16h PIR RBIF TMRSIF TMR2IF TMR1IF CA2IF 0000 0010 0000 0010 17h PIE RBIE TMRSIE TMR2IE TMRIIE CA2IE 0000 0000 0000 0000 Legend unknown unchanged unimplemented read as 0 value depends condition Shaded cells are unimplemented read as 0 Note 1 The upper byte of the program counter is not directly accessible PCLATH is holding register lt 15 8 gt whose contents are updated from or transferred to the upper byte of the program counter 2 The TO and PD status bits in CPUSTA are not affected by a MCLR reset 3 Other non power up resets include external reset through MCLR and the Watchdog Timer Reset 4 The following values are for both TBLPTRL and TBLPTRH All PIC17C4X devices Power on Reset 0000 0000 and All other re
129. 2091 01 Juvsn 2105 dlas uld gz WEZO9LOld Juvsn 2105 dlas uid ge 79 0 67291214 4088 2105 4106 9 4 Ozl IdS 022991014 dOSS uid 0z 2105 did uid g1 9 0 114091214 2105 uid 81 9 0 29204 4055 uid 0z 0105 9 9 0 01 091014 seunyee4 DS30412C page 217 1996 Microchip Technology Inc PIC17C4X PIC16C8X Family of Devices E 6 S891A8p 10 sejes 20 1081002 esee d SION pue penas esn Ajue X829 LOld upiqedeo uano pue joejod epoo ejqejoeles 9 9195 S Y uo jewog 4108 Z L 9 LOld IY OIOS did uid 8 p 8899L Old did 8491018 2108 did 9 8 1 0789091019 9105 did uid 8 07859191 2105 9 81 78291014 1996 Microchip Technology Inc DS30412C page 218 PIC17C4X PIC16C9XX Family Of Devices E 7 aBeyoed siul 10 dIY90JOIN 290 12810002 BSed q BION eyep pue jenas asn seowep Awe xx29L2ld 1ue4no
130. 390 0 398 L 0 45 0 75 0 018 0 030 e 0 80 BSC 0 031 BSC b 0 30 0 45 0 012 0 018 b1 0 30 0 40 0 012 0 016 0 09 0 20 0 004 0 008 c1 0 09 0 16 0 004 0 006 N 44 44 44 44 0 7 0 7 Note 1 Dimensions D1 and 1 do not include mold protrusion Allowable mold protrusion is 0 25m m 0 010 side D1 and E1 dimensions including mold mismatch 2 Dimension b does not include Dambar protrusion allowable Dambar protrusion shall be 0 08m m 0 003 3 This outline conforms to JEDEC MS 026 1996 Microchip Technology Inc DS30412C page 209 PIC17C4X 21 6 Package Marking Information 40 Lead PDIP CERDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX AABBCDE MICROCHIP 40 Lead CERDIP Windowed PIC17C43 25I P L006 9441 MICROCHIP Example XXXXXXXXXXX PIC17C44 XXXXXXXXXXX XXXXXXXXXXX L184 MICROCHIP MICROCHIP AABBCDE 9444CCT 44 Lead PLCC Example MICROCHIP MICROCHIP XXXXXXXXXX PIC17C42 XXXXXXXXXX L013 AABBCDE 9445CCN 44 Lead Example XXXXXXXXXX PIC17C44 XXXXXXXXXX 25 XXXXXXXXXX L247 O AABBCDE O 9450CAT 44 Lead Example XXXXXXXXXX PIC17C44 XXXXXXXXXX 25 XXXXXXXXXX L247 O 9450CAT Legend MM M Microchip part number information XX X Customer
131. 4 Note This instruction is not available in the PIC17C42 device EE EE ee Eu S 1996 Microchip Technology Inc DS30412C page 129 PIC17C4X NEGW Negate W NOP No Operation Syntax labe NEGW 15 Syntax abel Operands lt lt 255 Operands None se 0 1 Operation No operation Operation WREG 1 gt f Status Affected None WREG 1 5 ae 0000 0000 0000 0000 Status Affected Z 9 Description No operation Encoding 0010 110s ffff ffff F Words 1 Description WREG is negated using two s comple ment If s is 0 the result is placed in Cycles 1 WREG and data memory location If Q Cycle Activity 5 is 1 the result is placed only data memory location f Q1 Q2 Q3 Q4 Words 4 Decode NOP Execute NOP Cycles 1 Example Cycle Activity at 02 04 NODE Decode Read Execute Write register f register f and other specified register Example NEGW REG 0 Before Instruction WREG 0011 1010 0x3A REG 1010 1011 OxAB After Instruction WREG 1100 0111 0xC6 REG 1100 0111 0xC6 DS30412C page 130 1996 Microchip Technology Inc PIC17C4X RETFIE Return from Interrupt Syntax abel RETFIE Operands None Operation TOS 0 GLINTD PCLATH is unchanged Status Affected GLINTD Encoding
132. 5 C unless otherwise stated These parameters are for design guidance only and are not tested T These parameters are for design guidance only and are not tested nor characterized Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC17CXX devices be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages Negative current is defined as coming out of the pin These specifications are for the programming of the on chip program memory EPROM through the use of the table write instructions The complete programming specifications can be found in PIC17CXX Programming Specifications Literature number DS30139 5 The MCLR VPP pin may be kept in this range at times other than programming but is not recommended 6 For TTL buffers the better of the two specifications may be used AO 1996 Microchip Technology Inc DS30412C page 179 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 Standard Operating Conditions unless otherwise stated Operating temperature DC CHARACTERISTICS 40 C lt lt 85 for industrial and lt lt 70 for commercial Operating voltage VDD range as described in Section 19 1
133. 5 pA max at 5 5V WDT disabled IPD max at 5 5V WDT disabled Freq 4 MHz max Freq 4 MHz max XT 4 5V to 5 5V 4 5V to 5 5V IDD 24 mA max IDD 38 mA max IPD 5 pA max at 5 5V WDT disabled IPD 5gA max at 5 5V WDT disabled Freq 16 MHz max Freq 25 MHz max EC VDD 4 5V to 5 5V VDD 4 5V to 5 5V IDD 24 max IDD 38 mA max IPD 5 pA max at 5 5V WDT disabled IPD max at 5 5V WDT disabled Freq 16 MHZ max Freq 25 MHz max LF VDD 4 5V to 5 5V Von 4 5V to 5 5V IDD 150 uA max at 32 kHz WDT enabled 150 max at 32 kHz enabled IPD 5 pA max at 5 5V WDT disabled IPD max at 5 5V WDT disabled Freq 2 MHz max Freq 2 MHz max DS30412C page 148 1996 Microchip Technology Inc PIC17CAX Applicable Devices 42 R42 42A 43 43 44 17 1 DC CHARACTERISTICS PIC17C42 16 Commercial Industrial PIC17C42 25 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature DC CHARACTERISTICS 40 C lt lt 85 for industrial and lt TA 70 commercial Parameter No Sym Characteristic Min Typf Max Units Conditions D001 VDD Supply Voltage 4 5 5 5 V D002 Data Retention 1 5 V Device in SLEEP mode Voltage Note 1 D003 VPOR start voltage to Vss V See section on Power on Reset for ensure internal det
134. 6 1 INDIRECT ADDRESSING MOVLW 0x20 MOVWF FSRO FSRO 20h BCF ALUSTA FS1 Increment FSR BSF ALUSTA 50 after access BCF ALUSTA C C 0 MOVLW END RAM 1 2 LP CLRF INDFO Addr FSR 0 CPFSEQ FSRO FSRO END 1 clear next YES All RAM is cleared 6 5 Table Pointer TBLPTRL and TBLPTRH File registers TBLPTRL and TBLPTRH form a 16 bit pointer to address the 64K program memory space The table pointer is used by instructions TABLWT and TABLRD The TABLRD and the TABLWT instructions allow trans fer of data between program and data space The table pointer serves as the 16 bit address of the data word within the program memory For a more complete description of these registers and the operation of Table Reads and Table Writes see Section 7 0 6 6 Table Latch TBLATH TBLATL The table latch TBLAT is a 16 bit register with TBLATH and TBLATL referring to the high and low bytes of the register It is not mapped into data or pro gram memory The table latch is used as a temporary holding latch during data transfer between program and data memory see descriptions of instructions TABLRD TABLWT TLRD and TLWT For a more complete description of these registers and the operation of Table Reads and Table Writes see Section 7 0 DS30412C page 40 1996 Microchip Technology Inc PIC17C4X 6 7 Program Counter Module The Program Counter PC is a 16 bit register PCL the
135. 9 TOSTA Register Address 05h Uribanked ertet 38 Figure 6 10 Indirect 39 Figure 6 11 gt Program Counter Operation 41 1996 Microchip Technology Inc DS30412C page 231 PIC17CAX Figure 6 12 Figure 6 13 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 12 6 Figure 12 7 Figure 12 8 Figure 12 9 Figure 12 10 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 13 7 Figure 13 8 Figure 13 9 Figure 13 10 Figure 13 11 Figure 14 1 Figure 14 2 Program Counter using The CALL and GOTO Instructions 41 BSR Operation 17 43 843 44 42 TLWT Instruction 43 TABLWT Instruction Operation TLRD Instruction Operation 2 44 TABLRD Instruction Operation 44 TABLWT Write Timing External eese 46 Consecutive TABLWT Write Timing External Memory 2 TABLRD TABLRD Timing Consecutive TAB
136. 9291014 Ve vl WEL EL 20029 200200 0 49 8c049 LOOSOOAG 900900MS S00900MS 200 00 5 4 69 69 69291014 60L 9LW3 9 200200 20229 2029 LWA 100600 900900MS S00900MS 200 00 5 229 129 029291014 60179114 00900 Vv9 v9 00 9 200200 20249 LWA SZOZ9 LWA LOOSOOAG 900900MS GO0900MS 200 00 5 4 29 2929124 VIN 9 200200 606 9 Le029LIN3 LOOSOOAG 900900MS S00900MS 200 00 5 99291014 LLZ9LIN3 200S800AGd 200200 0 9 LWA L00900Ag S00900MS 200 00 5 899 966 799091014 10LZ9LIN3 86 ZS 9G GG 9 200200 10229HN3 SLOZ9LINA LOOSOOAG 900900MS S00900MS 200 00 5 VS 29091014 LOLZVLWA 200200 10027 LWA S00900MS 200 00 5 0001214 10LZ9LIN3 200200 81049 INE GO0900MS c00 00MS 609 806021214 100 diy2o1oin 21607 22 4 1S09 M07 1S09 M07 1500 01 3O HALSVINOId suoneonddy sajidwog
137. AD15 bit7 TTL Input Output or system bus address data pin Legend TTL TTL input TABLE 9 8 REGISTERS BITS ASSOCIATED WITH PORTD Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO dol PORTE AD15 014 AD13 AD12 AD11 AD10 AD9 AD8 ana 12 Bank 1 DDRD Data direction register for PORTD 1111 1111 1111 1111 Legend x unknown u unchanged Note 1 Other non power up resets include external reset through MCLR and the Watchdog Timer Reset 1996 Microchip Technology Inc DS30412C page 61 PIC17C4X 9 4 1 PORTE AND DDRE REGISTER PORTE is a 3 bit bi directional port The corresponding data direction register is DDRE A 1 in DDRE config ures the corresponding port pin as an input A 0 in the DDRE register configures the corresponding port pin as an output Reading PORTE reads the status of the pins whereas writing to it will write to the port latch PORTE is multiplexed with the system bus When operating as the system bus PORTE contains the con trol signals for the address data bus AD15 ADO These control signals are Address Latch Enable ALE Output Enable OE and Write WR The control sig nals OE and WR are active low signals The timing for the system bus is shown in the Electrical Characteris tics section Note
138. C DC Z No Operation Rotate left f through Carry Rotate left f no carry Rotate right f through Carry Rotate right f no carry Set f Subtract WREG from f OV C DC Z Subtract WREG from f with Borrow OV C DC Z Swap f None TABLRD tif Table Read 2 3 1010 10ti ffff ffff None 7 Legend Refer to Table 15 1 for opcode field descriptions Note 1 2 s Complement method 2 Unsigned arithmetic 3 If s 1 only the file is affected If s 0 both the WREG register and the file are affected If only the Working register WREG is required to be affected then f WREG must be specified 4 During an LCALL the contents of PCLATH are loaded into the MSB of the PC and kkkk is loaded into the LSB of the PC PCL 5 Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM The instruc tion is terminated by an interrupt event When writing to external program memory it is a two cycle instruc tion 6 Two cycle instruction when condition is true else single cycle instruction 7 Two cycle instruction except for TABLRD to PCL program counter low byte in which case it takes 3 cycles 8 A skip means that instruction fetched during execution of current instruction is not executed instead an NOP is executed 9 These instructions are not available on the PIC17C42 DS30412C page 110 1996 Technology Inc PIC17C4X TABLE 15 2 P
139. C page 222 1996 Microchip Technology Inc PIC17C4X APPENDIX F ERRATA FOR PIC17C42 SILICON The PIC17C42 devices that you have received have the following anomalies At present there is no intention for future revisions to the present PIC17C42 silicon If these cause issues for the application it is recom mended that you select the PIC17C42A device Note New designs should use the PIC17C42A 1 When the Oscillator Start Up Timer OST is enabled in LF or XT oscillator modes any inter rupt that wakes the processor may cause aWDT reset This occurs when the WDT is greater than or equal to 50 time out period when the SLEEP instruction is executed This will not occur in either the EC or RC oscillator modes Work arounds a Always ensure that the CLRWDT instruction is executed before the WDT increments past 50 of the WDT period This will keep the false WDT reset from occurring b When using the WDT as a normal timer WDT disabled ensure that the WDT is less than or equal to 50 time out period when the SLEEP instruction is executed This can be done by monitoring the TO bit for changing state from set to clear Example 1 shows putting the PIC17C42 to sleep EXAMPLE 1 17 42 TO SLEEP 55 CPUSTA TO 0 CLRWDT 5 WDT 0 LOOP 5 CPUSTA TO WDT rollover GOTO LOOP NO Wait SLEEP XES goto Sleep 2 When the clock source of or
140. CIRCUIT To Other 330 330 Devices 4777 74AS04 74AS04 74AS04 PIC17CXX OSC1 DS30412C page 102 1425 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings RC oscillator fre quency is a function of the supply voltage the resistor Rext and capacitor Cext values and the operating temperature In addition to this oscillator frequency will vary from unit to unit due to normal process parameter variation Furthermore the difference in lead frame capacitance between package types will also affect oscillation frequency especially for low Cext values The user also needs to take into account variation due to tolerance of external R and C components used Figure 14 6 shows how the R C combination is con nected to the PIC17C XX For Rext values below 2 2 kQ the oscillator operation may become unstable or stop completely For very high Rext values e g 1 MQ the oscillator becomes sensitive to noise humidity and leakage Thus we recommend to keep Rext between 3 and 100 Although the oscillator will operate with no external capacitor Cext 0 pF we recommend using values above 20 pF for noise and stability reasons With little or no external capacitance oscillation frequency can vary dramatically due to changes in external capaci tances such as PCB trace capacitance or package lead frame capacitance See Section 18 0
141. Cext Rext Fosc 25 22 10 3 33 2 12 100 353 kHz 13 100 pF 3 3k 3 54 MHz 10 5 1k 2 43 MHz 14 10k 1 30 MHz 17 100k 129 kHz 10 300 pF 3 3k 1 54 MHz 14 5 1k 980 kHz 12 10k 564 kHz 16 160 35 2 18 1996 Microchip Technology Inc DS30412C page 165 PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 18 5 TRANSCONDUCTANCE gm OF LF OSCILLATOR vs VDD 4 0 Volts FIGURE 18 6 TRANSCONDUCTANCE gm OF XT OSCILLATOR vs 4 0 VoD Volts DS30412C page 166 1996 Microchip Technology Inc PIC17CAX Applicable Devices 42 R42 42A 43 43 44 FIGURE 18 7 TYPICAL IDD vs FREQUENCY EXTERNAL CLOCK 25 C 100000 100k 1M External Clock Frequency Hz FIGURE 18 8 MAXIMUM vs FREQUENCY EXTERNAL CLOCK 125 C TO 40 C 100000 1M External Clock Freq
142. Characteristics sis ics dials inne cete eL de Pe ee e de eec eth 147 18 0 PIC17C42 DC and AC 163 19 0 PIC17CR42 42A 43 R43 44 Electrical 175 20 0 PIC17CR42 42A 43 R43 44 DC and AC 193 21 0 Packaging riformatlort er hin po ae iv iege 205 Appendix Az ModifiCatiohs 5 e e pas IR e dt D fea eite ee p MO oae p d SER Ras 211 Appendix B Gompatlibility Le EL RR ee ts 211 Appendix Whats tp t er MEE RE ERR ERR itt 212 Appendix Di What s Changed 5 itte perte eR cera Re ce med pe goes Lace geo 212 Appendix E PIC16 17 213 Appendix Errata for PIC17C42 Silicon iii 223 qm 226 PIC17C4X Product Identification System issues 237 For register and module descriptions in this data sheet device legends show which devices apply to those sections For example the legend below shows that some features of only the PIC17C43 PIC17CR43 PIC17C44 are described in this section Applicable Devices 42 RA2 42A 43 R43 44 To Our Valued
143. Customers We constantly strive to improve the quality of all our products and documentation We have spent an excep tional amount of time to ensure that these documents are correct However we realize that we may have missed a few things If you find any information that is missing or appears in error from the previous version of the PIC17C4X Data Sheet Literature Number DS30412B please use the reader response form in the back of this data sheet to inform us We appreciate your assistance in making this a better document To assist you in the use of this document Appendix C contains a list of new information in this data sheet while Appendix D contains information that has changed 1996 Microchip Technology Inc DS30412C page 3 PIC17C4X NOTES DS30412C page 4 1996 Microchip Technology Inc PIC17C4X 1 0 OVERVIEW This data sheet covers the PIC17C4X group of the PIC17CXX family of microcontrollers The following devices are discussed in this data sheet PIC17C42 e PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 PIC17C44 The PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 and PIC17C44 devices include architec tural enhancements over the PIC17C42 These enhancements will be discussed throughout this data sheet The PIC17C4X devices are 40 44 Pin EPROM ROM based members of versatile PIC17CXX family of low cost high performance CMOS fully static 8 bit microcontrollers All PIC16 17 microcontrollers empl
144. Description CLRWDT instruction resets the watchdog timer It also resets the prescaler of the WDT Status bits TO and PD are set Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register ALUSTA Example CLRWDT Before Instruction WDT counter 27 After Instruction WDT counter 0x00 WDT Postscaler gt 0 1 PD 1 COMF Complement f Syntax label fd Operands lt lt 255 d e 0 1 Operation f dest Status Affected Z Encoding 0001 001d ffff Description The contents of register are comple mented If d is 0 the result is stored in WREG If d is 1 the result is stored back in register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register Example COMF 0 Before Instruction REG1 0x13 After Instruction REG1 0x13 WREG OxEC DS30412C page 118 1996 Microchip Technology Inc PIC17C4X nes Syntax label CPFSEQ f Operands 0 lt 1 lt 255 f WREG Status Affected skip if f WREG unsigned comparison None Encoding 0011 0001 ffff ffff Description Compares the contents of data memory location to the contents of WREG by performing an unsigned subtraction If WREG then the fetched instruc tion is discarded and an NOP is exe cuted instead making this a two cy
145. F operation takes place 2 2 cd bin bit5 and PORTB is written to the output latches If another bit of PORTB is used as a bi directional pin BCF 7 idbp pepp Lipp peep e g bit0 and it is defined as an input at this time the DDRB 6 10 pppp 10 input signal present on the pin itself would be read into the CPU and re written to the data latch of this particu lar pin overwriting the previous content As long as the pin stays in the input mode no problem occurs How ever if bit0 is switched into output mode later on the content of the data latch may now be unknown Note that the user may have expected the pin values to be 00 pppp The 2nd caused RB7 to be latched as the pin value High Se se Note A pin actively outputting a Low or High should not be driven from external devices in order to change the level on this pin i e wired or wired and The resulting high output currents may damage the device Reading a port reads the values of the port pins Writing to the port register writes the value to the port latch When using read modify write instructions BCF BSF BTG etc on a port the value of the port pins is read the desired operation is performed with this value and the value is then written to the port latch 9 5 2 SUCCESSIVE OPERATIONS ON I O PORTS Example 9 5 shows the effect of two sequential read modify write instructions
146. FFFF Ift 1 f After Instruction table write completion REG 0x53 Status Affected None TBLATH 0 53 Encoding 1010 00 ffff ffff TBLATL 0x55 TBLPTR 0xA357 Description Read data from 16 bit table latch MEMORY TBLPTR 1 0 5355 TBLAT into file register f Table Latch is unaffected Example 2 TABLWT 1 0 REG 1 high byte is read Before Instruction If t 0 low byte is read REG 0x58 This instruction is used in conjunction TREAT FORSAN with TABLRD to transfer data from TBLATL E 0x55 gram memory to data memory TBLPTR 0 56 MEMORY TBLPTR OxFFFF Words 1 After Instruction table write completion Cycles 1 Cycle Activity X TBLATL 0x53 Q1 Q2 Q3 Q4 TBLPTR OxA356 Decode Read Execute Write MEMORY TBLPTR 5 register register f TBLATH or TBLATL Program 15 Example TLRD t RAM Before Instruction zl TBLPTR t 0 15 87 0 TBLAT Ox00AF TBLATH 0x00 TBLATL OxAF 16 bits After Instruction RAM OxAF TBLAT 0 00 TBLATH 0x00 TBLATL OxAF Before Instruction t 1 TBLAT OxOOAF 0x00 TBLATL OxAF After Instruction RAM 0x00 TBLAT OxOOAF TBLATH 0x00 TBLATL OxAF 16 bits 1996 Microchip Technology Inc DS30412C page 139 PIC17C4X TLWT Table Latch Write Syntax label TLWT tff Operands 0 lt lt 255
147. FUNCTION REGISTERS Register Address Power on Reset sa 2 Unbanked INDFO 00h 0000 0000 0000 0000 0000 0000 FSRO 01h XXXX XXXX uuuu uuuu uuuu uuuu PCL 02h 0000h 0000h 10 03h 0000 0000 0000 0000 uuuu uuuu ALUSTA 04h 1111 xxxx 1111 uuuu 1111 uuuu 05 05h 0000 000 0000 000 0000 000 CPUSTA 06h 11 11 11 qq uu qq INTSTA 07h 0000 0000 0000 0000 uuuu uuuuU INDF1 08h 0000 0000 0000 0000 uuuu uuuu FSR1 09h XXXX XXXX uuuu uuuu uuuu uuuu WREG 0Ah XXXX XXXX uuuu uuuu uuuu uuuu TMROL OBh XXXX uuuu uuuu uuuu uuuu TMROH OCh XXXX XXXX uuuu uuuu uuuu uuuu TBLPTRL 4 uuuu uuuu uuuu uuuu TBLPTRH uuuu uuuu uuuu uuuu TBLPTRL 6 0000 0000 0000 0000 uuuu uuuu TBLPTRH 6 OEh 0000 0000 0000 0000 uuuu uuuu BSR OFh 0000 0000 0000 0000 uuuu uuuu Bank 0 PORTA 10h 0 O uu uuuu uuuu uuuu DDRB 11h 111171114 1111 1111 uuuu uuuu PORTB 12h XXXX XXXX uuuu uuuu uuuu uuuu RCSTA 13h 0000 00x 0000 00u uuuu uuu RCREG 14h XXXX XXXX uuuu uuuu uuuu uuuu TXSTA 15h 0000 1x 0000 1u uuuu uu TXREG 16h XXXX XXXX uuuu uuuu uuuu uuuu SPBRG 17h XXXX XXXX uuuu uuuu uuuu uuuu Bank 1 DDRC 10h LT 1111 1111 uuuu uuuu PORTC 11h XXXX XXXX uuuu uuuu uuuu uuuu DDRD 12h 1111 1111 1111 1111 uuuu uuuu PORTD 13h uuuu uuuu uuuu uuuu DDRE 14h 111 111 uuu PORTE 15h uuu uuu
148. Fax 905 405 6253 ASIA PACIFIC Hong Kong Microchip Asia Pacific Unit 2101 Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong N T Hong Kong Tel 852 2 401 1200 Fax 852 2 401 3431 Beijing Microchip Technology Beijing Unit 915 6 Chaoyangmen Bei Dajie Dong Erhuan Road Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel 86 10 85282100 Fax 86 10 85282104 India Microchip Technology Inc India Liaison Office No 6 Legacy Convent Road Bangalore 560 025 India Tel 91 80 229 0061 Fax 91 80 229 0062 Japan Microchip Technology Intl Inc Benex S 1 6F 3 18 20 Shinyokohama Kohoku Ku Yokohama shi Kanagawa 222 0033 Japan Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Microchip Technology Korea 168 1 Youngbo Bldg 3 Floor Samsung Dong Kangnam Ku Seoul Korea Tel 82 2 554 7200 Fax 82 2 558 5934 Shanghai Microchip Technology RM 406 Shanghai Golden Bridge Bldg 2077 Yan an Road West Hong Qiao District Shanghai PRC 200335 Tel 86 21 6275 5700 Fax 86 21 6275 5060 DNV MSC The Netherlands Accredited by the RvA 150 9001 05 9000 REGISTERED FIRM gt a m m e ASIA PACIFIC continued Singapore Microchip Technology Singapore Pte Ltd 200 Middle Road 07 02 Prime Centre Singapore 188980 Tel 65 334 8870 Fax 65 334 8850 Taiwan R O C Microchip Technology Taiwan 10F 1C 207 Tung Hua North Road Taipei Taiwan ROC T
149. Frequency normalized to 25 C Fosc 25 C SS VDD 5 5V VDD 3 5V _ 1996 Microchip Technology Inc DS30412C page 193 oc 1 v 3 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 FIGURE 20 2 TYPICAL RC OSCILLATOR FREQUENCY vs Cext 22 pF T 25 C Volts FIGURE 20 3 TYPICAL RC OSCILLATOR FREQUENCY vs Volts DS30412C page 194 1996 Technology Inc PIC17C4X Applicable Devices 42 42 42 43 843 44 FIGURE 20 4 TYPICAL RC OSCILLATOR FREQUENCY vs Cext 300 pF T 25 C Volts TABLE 20 2 RC OSCILLATOR FREQUENCIES Average Cext Rext Fosc 25 22 10 3 33 2 12 100 353 kHz 13 100 pF 3 3k 3 54 MHz 10 5 1k 2 43 MHz 14 10k 1 30 MHz 17 100k 129 kHz 10 300 pF 3 3k 1 54 MHz 14 5 1k 980 kHz 12 10k 564 kHz 16 160 35 2 18 1996 Microchip Technology Inc DS30412C page 195 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 FIGURE 20 5 TRANSCONDUCTANCE gm OF LF O
150. H2adl WRT to data out invalid 0 25Tcv 8 ns data hold time TwrL WR pulse width 0 25Tcv 8 ns These parameters are characterized but not tested 1 Data in column is 5 25 unless otherwise stated These parameters for design guidance only and are not tested 5 This specification ensured by design DS30412C page 190 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 42 42 43 R43 44 FIGURE 19 12 MEMORY INTERFACE READ TIMING NOT SUPPORTED IN PIC17LC4X DEVICES 162 EI 4 163 TABLE 19 12 MEMORY INTERFACE READ REQUIREMENTS NOT SUPPORTED IN PIC17LC4X DEVICES Parameter No Sym Characteristic Min Typt Max Units Conditions 150 TadV2alL AD15 ADO address valid to ALE 0 25Tcy 10 ns address setup time 151 TalL2adl ALE to address out invalid 5 ns address hold time 160 Tad72oeL AD15 ADO hi impedance to 0 ns ToeH2adD to AD15 ADO driven 0 25 15 ns TadV2oeH Data in valid before OET 35 ns data setup time ToeH2adl OETto data in invalid data hold time ns TalH ALE pulse width 0 25Tcv 6 ns ToeL OE pulse width 0 5Tcy 35 ns TalH2alH to ALET cycle time Tcy 6 ns 167 Tacc Address access time EET 0 75 30 ns 168 Toe Output enable access time
151. IC17CXX INSTRUCTION SET Cont d Mnemonic Description Cycles 16 bit Opcode Status Notes Operands MSb LSb Affected TABLWT tif Table Write 2 1010 1161 ffff 5 Table Latch Read Table Latch Write 1 1 Test f skip if 0 1 XORWF Exclusive OR WREG with f 0000 1104 ffff ffff 2 BIT ORIENTED FILE REGISTER OPERATIONS BCF fb Bit Clear f 1 1000 1bbb None Bit Set f 1 Bit test skip if clear Bit test skip if set BTG fb Bit Toggle f 1 001 bbb ffff ffff None LITERAL AND CONTROL OPERATIONS ADDLW k ADD literal to WREG 1 011 0001 kkkk kkkk OV C DC Z AND literal with WREG 1 Subroutine Call 2 Clear Watchdog Timer 1 Unconditional Branch 2 Inclusive OR literal with WREG 1 Long Call 2 Move literal to low nibble in BSR 1 Move literal to high nibble in BSR 1 Move literal to WREG 1 Multiply literal with WREG 1 None Return from interrupt and enable interrupts 2 GLINTD Return literal to WREG 2 None Return from subroutine 2 None Enter SLEEP Mode 1 TO PD Subtract WREG from literal 1 OV C DC Z XORLW k Exclusive OR literal with WREG 1 1011 0100 Z Legend Refer to Table 15 1 for opcode field descriptions Note 1 2 s Complement method 2 Unsigned arithmetic 3 Ifs 1 only the file is affected If s 0 both the WREG register and the file are affected If only the
152. IEW OF TIMER RESOURCES The 17 has four timer modules Each module can generate an interrupt to indicate that an event has occurred These timers are called TimerO 16 bit timer with programmable 8 bit prescaler Timer1 8 bit timer Timer2 8 bit timer Timer3 16 bit timer For enhanced time base functionality two input Cap tures and two Pulse Width Modulation PWM outputs are possible The PWMs use the TMR1 and TMR2 resources and the input Captures use the TMR3 resource 10 1 0 Overview The TimerO module is a simple 16 bit overflow counter The clock source can be either the internal system clock Fosc 4 or an external clock The TimerO module also has a programmable pres caler option The PS3 PS0 bits TOSTA lt 4 1 gt deter mine the prescaler value TMRO can increment at the following rates 1 1 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 When 0 clock source is an external clock the TimerO module can be selected to increment on either the rising or falling edge Synchronization of the external clock occurs after the prescaler When the prescaler is used the external clock frequency may be higher then the device s fre quency The maximum frequency is 50 MHz given the high and low time requirements of the clock 10 2 Overview The TlmerO module is an 8 bit timer counter with an 8 bit period register When the value rolls over f
153. INGS TABLE 17 5 TIMERO CLOCK REQUIREMENTS Parameter No Sym Characteristic Min Typt Units Conditions 40 TOCKI High Pulse Width No Prescaler 0 5TcY 205 ns With Prescaler 10 ns 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5 Tcv 208 ns With Prescaler 10 ns 42 Period Tcv 408 ns N prescale value 1 2 4 256 These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested This specification ensured by design FIGURE 17 6 TIMER1 TIMER2 AND TIMER3 CLOCK TIMINGS TCLK12 or TABLE 17 6 TIMER1 TIMER2 AND CLOCK REQUIREMENTS Parameter Typ No Sym Characteristic Min t Max Units Conditions 45 Tt123H TCLK12 and TCLK3 high time 0 5 Tcy 4 2061 ns 46 Tt123L 12 and TCLK3 low time 0 5 Tcy 4 205 ns 47 Tt123P TCLK12 and TCLK3 input period Tcv 408 ns prescale value N 1 2 4 8 48 TckE2tmrl Delay from selected External Clock Edge to 2TOSC 6 Timer increment These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for de
154. INTE R Readable bit bit7 bitO W Writable bit n Value at POR reset bit 7 PEIF Peripheral Interrupt Flag bit This bit is the OR of all peripheral interrupt flag bits AND ed with their corresponding enable bits 1 A peripheral interrupt is pending 0 No peripheral interrupt is pending bit6 TOCKIF External Interrupt on TOCKI Pin Flag bit This bit is cleared by hardware when the interrupt logic forces program execution to vector 18h 1 The software specified edge occurred on the RA1 TOCKI pin 0 The software specified edge did not occur on the RA1 TOCKI pin bit 5 TOIF TMRO Overflow Interrupt Flag bit This bit is cleared by hardware when the interrupt logic forces program execution to vector 10h 1 TMRO overflowed 0 2 TMRO did not overflow bit 4 INTF External Interrupt on INT Pin Flag bit This bit is cleared by hardware when the interrupt logic forces program execution to vector 08h 1 The software specified edge occurred on the RAO INT pin 0 The software specified edge did not occur on the RAO INT pin bit 3 PEIE Peripheral Interrupt Enable bit This bit enables all peripheral interrupts that have their corresponding enable bits set 1 Enable peripheral interrupts 0 Disable peripheral interrupts bit2 TOCKIE External Interrupt TOCKI Pin Enable bit 1 Enable software specified edge interrupt on the RA1 TOCKI pin 0 Disable interrupt on the RA1 TOCKI pin bit 1 T
155. IVER TRANSMITTER USART MODULE The USART module is a serial I O module The USART can be configured as a full duplex asynchronous sys tem that can communicate with peripheral devices such as CRT terminals and personal computers or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A D or D A integrated circuits Serial EEPROMs etc USART can be configured in the following modes Asynchronous full duplex Synchronous Master half duplex Synchronous Slave half duplex The SPEN RCSTA lt 7 gt bit has to be set in order to configure RA4 and RA5 as the Serial Communication Interface The USART module will control the direction of the RA4 RX DT and RA5 TX CK pins depending on the states of the USART configuration bits in the RCSTA and TXSTA registers The bits that control direction are SPEN TXEN SREN CREN CSRC The Transmit Status And Control Register is shown in Figure 13 1 while the Receive Status And Control Register is shown in Figure 13 2 FIGURE 13 1 TXSTA REGISTER ADDRESS 15h BANK 0 R W 0 R W 0 R W 0 R W 0 U 0 R 1 R W x CSRC TX9 TXEN SYNC TRMT TX9D R Readable bit bit7 bit 7 CSRC Clock Source Select bit Synchronous mode 1 Master Mode Clock generated internally from BRG 0 Slave mode Clock from external source Asynchronous mode Don t ca
156. LEEP event occurs The OST time out is invoked only for XT and LF oscilla tor modes on a Power on Reset or a Wake up from SLEEP The OST counts the oscillator pulses on OSC1 CLKIN pin The counter only starts incrementing after the amplitude of the signal reaches the oscillator input thresholds This delay allows the crystal oscillator or resonator to stabilize before the device exits reset The length of time out is a function of the crystal reso nator frequency 414 SEQUENCE On power up the time out sequence is as follows First the internal POR signal goes high when the POR trip point is reached If MCLR is high then both the OST and PWRT timers start In general the PWRT time out is longer except with low frequency crystals resona tors The total time out also varies based on oscillator configuration Table 4 1 shows the times that are asso ciated with the oscillator configuration Figure 4 2 and Figure 4 3 display these time out sequences If the device voltage is not within electrical specification at the end of a time out the pin must be held low until the voltage is within the device specifica tion The use of an external RC delay is sufficient for many of these applications TABLE 4 1 TIME OUT IN VARIOUS SITUATIONS Oscillator Power up Wake up MCLR Configuration from Reset SLEEP XT LF Greater of 1024Tosc 96 ms or 1024Tosc EC RC Greater of 96 ms
157. LRD Instr ctlons RAO and Block Diagram its RAS Block Diagram RA4 and RAS Block Diagram Block Diagram of RB lt 7 4 gt and RB lt 1 0 gt Port ner 55 Block Diagram of RB3 and RB2 Port Pins 56 Block Diagram of RC lt 7 0 gt Port Pins 58 PORTD Block Diagram in Port Mode 60 PORTE Block Diagram in Port Mode 62 Successive I O Operation 64 TOSTA Register Address 05h Unbanked 67 0 Module Block Diagram 68 TMRO Timing with External Clock Increment on Falling Edge 68 TMRO Timing Write High or Low Byte 69 TMRO Read Write in Timer Mode 70 TCON 1 Register Address 16h Bank 3 71 2 Register Address 17h Bank 3 72 Timer1 and Timer2 in Two 8 bit Timer Counter 73 TMR1 and TMR2 16 bit Timer Counter e 74 Simplified PWM Block Diagram 2 75 PWM Output 5 75 Timer3 with One Capture and One Period Register Block Diagram 78 Timer3 with Two Capture Registers Block 79 TMR1 2 and TMR3 Operation External Clock
158. LRD INSTRUCTIONS cel cel Q4 Q4 cel Q4 Q4 cel Q4 cel Q4 AD15 ADO Instruction TABLRD1 TABLRD2 INST 2 INST PC 3 fetched i i Instruction executed INST PC 1 TABLRD1 1 TABLRD1 cycle2 TABLRD2 TABLRD2 cycle2 INST PC 2 Data read cycle Data read cycle gt DS30412C page 48 1996 Microchip Technology Inc PIC17CAX 8 0 HARDWARE MULTIPLIER All PIC17C4X devices except the PIC17C42 have 8 x 8 hardware multiplier included in the ALU of the device By making the multiply a hardware operation it completes in a single instruction cycle This is an unsigned multiply that gives 16 bit result The result is stored into the 16 bit PRODuct register PRODH PRODL The multiplier does not affect any flags in the ALUSTA register Making the 8 x 8 multiplier execute in a single cycle gives the following advantages Example 8 2 shows the sequence to do an 8 x 8 signed multiply To account for the sign bits of the arguments each argument s most significant bit MSb is tested and the appropriate subtractions are done EXAMPLE 8 1 8x8 MULTIPLY ROUTINE MOVFP ARG1 WREG MULWF ARG2 ARGI ARG2 gt PRODH PRODL EXAMPLE 8 2 8x8 SIGNED MULTIPLY ROUTINE Higher computati
159. M bank is no longer 0 The disabling of global interrupts has been enhanced so there is no additional testing of the GLINTD bit after a BSF CPUSTA GLINTD instruction 1996 Microchip Technology Inc DS30412C page 211 PIC17C4X APPENDIX WHAT S NEW The structure of the document has been made consis tent with other data sheets This ensures that important topics are covered across all PIC16 17 families Here is an overview of new features Added the following devices PIC17CR42 PIC17C42A PIC17CR43 33 MHz option is now available APPENDIX D WHAT S CHANGED To make software more portable across the different PIC16 17 families the name of several registers and control bits have been changed This allows control bits that have the same function to have the same name regardless of processor family Care must still be taken since they may not be at the same special func tion register address The following shows the register and bit names that have been changed Old Name New Name TX8 9 TX9 RC8 9 RX9 RCD8 RX9D TXD8 TX9D Instruction DECFSNZ corrected to DOFSNZ Instruction INCFSNZ corrected to INFSNZ Enhanced discussion on PWM to include equation for determining bits of PWM resolution Section 13 2 2 and 13 3 2 have had the description of updating the FERR and RX9 bits enhanced The location of configuration bit PM2 was changed Figure 6 1 and Figure 14 1 Enhanced descript
160. MPLAB and fuzzyLAB are trade marks and SQTP is a service mark of Microchip in the U S A fuzzyTECH is a registered trademark of Inform Software Corporation IBM IBM PC AT are registered trademarks of International Business Machines Corp Pentium is a trade mark of Intel Corporation Windows is a trademark and MS DOS Microsoft Windows are registered trademarks of Microsoft Corporation CompuServe is a registered trademark of CompuServe Incorporated All other trademarks mentioned herein are the property of their respective companies 1996 Microchip Technology Inc 1 0830412 235 PIC17C4X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 602 786 7578 Please list the following information and use this outline to provide us with your comments about this Data Sheet To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX 2 Application optional Would you like a reply Y N Device PIC17C4X Literature Number DS30412C Questions 1 What are the best features of this document
161. MRICS is set the 16 bit TMR2 TMR1 incre ments on the falling edge of clock input TCLK12 The input on the RBA TCLK12 pin is sampled and synchro nized by the internal phase clocks twice every instruc tion cycle This causes a delay from the time a falling edge appears on RB4 TCLK12 to the time TMR2 TMR is actually incremented For the external clock input timing requirements see the Electrical timer increments once every instruction cycle Fosc 4 Specification section When TMRICS is set the timer increments on every falling edge of the RB4 TCLK12 pin For the 16 bit timer to increment both TMR1ON and TMR2ON bits must be set Table 12 1 TABLE 12 1 TURNING ON 16 TIMER 2 TMR1ON Result 16 bit timer TMR2 TMR1 ON Only TMR1 increments 16 bit timer OFF Set Interrupt TMR1IF PIR lt 4 gt MR10ON TCON2 lt 0 gt TMR2 x 8 1 8 RB4 TCLK12 __ 4 16 PR2 x 8 1 8 TABLE 12 2 SUMMARY OF TIMER1 AND TIMER2 REGISTERS TMR1CS 1 lt 0 gt Value on Value on all ddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 16h Bank 3 TCON1 CA2ED1 CA2EDO CA1ED1 CA1EDO T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 17h Bank 3 TCON2 2
162. N TCON2 5 bit controls the configura tion of the RB3 PWM2 pin FIGURE 12 6 PWM OUTPUT Write new Timer interrupt interrupt PWM value new PWM value transferred to slave Note dotted line shows PWM output if duty registers were not double buffered If the new duty cycle is written after the timer has passed that value then the PWM does not reset at all during the current cycle causing a glitch In this example PWM period 50 Old duty cycle is 30 New duty cycle value is 10 1996 Microchip Technology Inc DS30412C page 75 PIC17C4X 12 1 3 1 PERIODS The period of the PWM1 output is determined by Timer1 and its period register PR1 The period of the PWM2 output can be software configured to use either Timer1 or Timer2 as the time base When TM2PW2 bit PW2DCL 5 is clear the time base is determined by and When TM2PW2 is set the time base is determined by Timer2 and PR2 Running two different PWM outputs on two different timers allows different PWM periods Running both PWMs from Timer1 allows the best use of resources by freeing Timer2 to operate as an 8 bit timer Timer and Timer2 can not be used as a 16 bit timer if either PWM is being used The PWM periods can be calculated as follows period of PWM1 PR1 1 x 4Tosc period of PWM2 PR1 1 x 4Tosc or PR2 1 x 4Tosc The duty cycle of PWMx is determine
163. NED MULTIPLICATION MULWF ARG2H ARGIH ARG2H gt ALGORITHM PRODH PRODL MOVPF PRODH RES3 RESS RESO MOVPF PRODL RES2 ARG1H ARG1L ARG2H ARG2L 5 016 MOVFP ARG1L WREG ARG1H ARG2H 2 MULWF ARG2H ARGIL ARG2H gt ARG1H ARG2L 28 PRODH PRODL 98 PRODL WREG ARG1L ARG2H 2 d ADDWF 51 Add cross ARG1L ARG2L PRODH WREG products ADDWE C RES2 1 ARG2H 7 ARG1H ARGIL 216 4 1 ARG1H 7 ARG2H ARG2L 216 ADDWFC RES3 ARG1H WREG MULWF ARG2L ARGIH ARG2L gt PRODH PRODL MOVFP PRODL WREG ADDWF RES1 F Add cross MOVFP PRODH WREG products ADDWFC RES2 F CLRF WREG F ADDWE C RES3 55 ARG2H 7 ARG2H ARG2L neg GOTO SIGN ARG1 no check ARG1 MOVFP ARG1L WREG SUBWF RES2 MOVFP ARG1H WREG SUBWFB RES3 SIGN ARG1 55 ARG1H 7 ARGlH ARGlL neg GOTO CONT CODE no done MOVFP ARG2L WREG SUBWF RES2 MOVFP ARG2H WREG SUBWFB RES3 CONT CODE 1996 Microchip Technology Inc DS30412C page 51 PIC17C4X NOTES EE E DS30412C page 52 1996 Technology Inc PIC17C4X 9 0 1 0 PORTS The 17 4 devices have five ports PORTA through PORTE PORTB through PORTE have a corre sponding Data Direction
164. ODH contains the high byte WREG is unchanged None of the status flags are affected Note that neither overflow nor carry is possible in this operation A zero result is possible but not detected Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write literal k registers PRODH PRODL Example MULLW OxC4 Before Instruction WREG OxE2 PRODH 7 PRODL After Instruction WREG 4 PRODH OxAD PRODL 0x08 Note This instruction is not available in the PIC17C42 device MULWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Q1 Decode Example Multiply WREG with f abel MULWF f 0 lt lt 255 WREG x f gt PRODH PRODL None 0011 0100 ffff An unsigned multiplication is carried out between the contents of WREG and the register file location f The 16 bit result is stored in the PRODH PRODL register pair PRODH contains the high byte Both WREG and f are unchanged None of the status flags are affected Note that neither overflow nor carry is possible in this operation A zero result is possible but not detected 1 1 Q2 Q3 Read register f Write registers PRODH PRODL Execute MULWE REG Before Instruction WREG 4 0 5 PRODH 2 PRODL After Instruction WREG 4 0 5 PRODH 0x8A PRODL 0x9
165. OIE TMRO Overflow Interrupt Enable bit 1 Enable TMRO overflow interrupt 0 Disable TMRO overflow interrupt bit 0 INTE External Interrupt on RAO INT Pin Enable bit 1 Enable software specified edge interrupt on the RAO INT pin 0 Disable software specified edge interrupt on the RAO INT pin DS30412C page 22 1996 Microchip Technology Inc PIC17C4X 5 2 Peripheral Interrupt Enable Register PIE This register contains the individual flag bits for the Peripheral interrupts FIGURE 5 3 PIE REGISTER ADDRESS 17h BANK 1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 RW 0 RBIE TMRSIE TMR2IE TMR1IE CA2IE bit7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit0 RBIE PORTB Interrupt on Change Enable bit 1 Enable PORTB interrupt on change 0 Disable PORTB interrupt on change TMR3IE Timer3 Interrupt Enable bit 1 Enable Timera interrupt 0 Disable Timer3 interrupt TMR2IE Timer2 Interrupt Enable bit 1 Enable Timer2 interrupt 0 Disable Timer2 interrupt TMRIIE Timer1 Interrupt Enable bit 1 Enable Timer1 interrupt 0 Disable Timer1 interrupt CA2IE Capture2 Interrupt Enable bit 1 Enable Capture interrupt on RB1 CAP2 0 Disable Capture interrupt on RB1 CAP2 pin Capture1 Interrupt Enable bit 1 Enable Capture interrupt on RB2 CAP1 pin 0 Disable Capture interrupt on RB2 CAP1 pin
166. Obbb ffff ffff Description If bit b in register is 1 then the next instruction is skipped If bit b is 1 then the next instruction fetched during the current instruction exe cution is discarded and an NOP is exe cuted instead making this a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register f If skip Q1 Q2 Q3 Q4 Forced NOP NOP Execute NOP Example HERE BTFSS FLAG 1 FALSE TRUE Before Instruction PC address HERE After Instruction If FLAG lt 1 gt 0 PC address FALSE If FLAG lt 1 gt 1 PC address TRUE BTG Bit Toggle f Syntax label f b Operands 0 lt 1 lt 255 0 lt lt 7 febs f lt b gt Status Affected None Encoding 0011 1bbb ffff ffff Description Bit b in data memory location f is inverted Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register f Example BTG 4 Before Instruction PORTC 0111 0101 0x75 After Instruction PORTC 0110 0101 0x65 DS30412C page 116 1996 Microchip Technology Inc PIC17C4X CALL Subroutine Call Syntax label CALL Operands 0 lt k lt 4095 Operation PC 1 TOS k lt 12 0 gt k lt 12 8 gt PCLATH lt 4 0 gt PC lt 15 13 gt PCLATH lt 7 5 gt Status Affected None Encoding 111 kkkk
167. Oscillator Cycle PIC17C43 Frequency Time PIC17C42 PIC17C44 8 MHz 500 ns 25 25 16 MHz 250 ns 12 15 20 MHz 200 ns 90 10 25 MHz 160 ns N A 70 33 MHz 121 ns N A 1 Note 1 The access times for this requires the use of fast SRAMS Note The external memory interface is not sup ported for the LC devices FIGURE 6 4 TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM AD15 ADO AD7 ADO PIC17C4X AD15 AD8 LSB WR Note 1 Use of I O pins is only required for paged memory 2 This signal is unused for ROM and EPROM devices 1996 Microchip Technology Inc DS30412C page 31 PIC17C4X 6 2 Data Memory Organization Data memory is partitioned into two areas The first is the General Purpose Registers GPR area while the second is the Special Function Registers SFR area The SFRs control the operation of the device Portions of data memory are banked this is for both areas The GPR area is banked to allow greater than 232 bytes of general purpose RAM SFRs are for the registers that control the peripheral functions Banking requires the use of control bits for bank selection These control bits are located in the Bank Select Reg ister BSR If an access is made to a location outside this banked region the BSR bits are ignored Figure 6 5 shows the data memory map orga
168. PDIP package Device 17 44 Standard Vdd range 29 MHz ons PIC17C44T Tape and Reel normal VDD limits PIC17LC44 Extended Vdd range Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recom mended workarounds To determine if an errata sheet exists for a particular device please contact one of the following 1 Your local Microchip sales office see below 2 The Microchip Corporate Literature Center U S FAX 602 786 7277 3 The Microchip s Bulletin Board via your local CompuServe number CompuServe membership NOT required Please specify which device revision of silicon and Data Sheet include Literature you are using For latest version information and upgrade kits for Microchip Development Tools please call 1 800 755 2345 or 1 602 786 7302 1996 Microchip Technology Inc DS30412C page 237 PIC17C4X NOTES EE SE DS30412C page 238 1996 Technology Inc PIC17C4X NOTES uU EI IS SEE LEIS MM DS30412C page 239 1996 Technology Inc MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 786 7200 Fax 480 786 7277 Technical Support 480 786 7627 Web Address http
169. PORTD and PORTE combined 100 mA Note 1 Power dissipation is calculated as follows Pdis VDD x IDD X x X VoL x IOL Note 2 Voltage spikes below Vss at the MCLR pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 1000 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss T NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability AM U J 1996 Microchip Technology Inc DS30412C page 175 oc 1 4 v 3 y jeu adA ou 129195 Jesn eui JEU gt 1 3 suoneouioeds XYW NIN JO JOU 1nq 9 suonoejes 0 1 ejeoipui pepeus au PIC17C4X Applicable Devices 42 42 42A 43 R43 44 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION COMMERCIAL DEVICES TABLE 19 1
170. R W 1 HR W 1 HR W 1 HR W x HR W x HR W x 253 252 251 FSO OV Z DC C Readable bit 5 i W Writable bit QUE n Value POR reset x unknown bit 7 6 FS3 FS2 FSR1 Mode Select bits 00 Post auto decrement FSR1 value 01 Post auto increment FSR1 value 1 FSR1 value does not change 51 50 FSRO Mode Select bits 00 Post auto decrement FSRO value 01 Post auto increment FSRO value 1x FSRO value does not change OV Overflow bit bit 5 4 bit 3 This bit is used for signed arithmetic 25 complement It indicates an overflow of the 7 bit magnitude which causes the sign bit bit7 to change state 1 Overflow occurred for signed arithmetic in this arithmetic operation 0 No overflow occurred bit 2 Z Zero bit 1 The result of an arithmetic or logic operation is zero 0 The results of an arithmetic or logic operation is not zero bit 1 DC Digit carry borrow bit For ADDWF and ADDLW instructions 1 2A carry out from the 4th low order bit of the result occurred 0 No carry out from the 4th low order bit of the result Note For borrow the polarity is reversed bit 0 C carry borrow bit For ADDWF and ADDLW instructions 1 A carry out from the most significant bit of the result occurred Note that a subtraction is executed by adding the two s complement of the second operand For rotate RRCF RLCF instructions this bit is loaded with either the high or low order bit of the sour
171. RB lt 3 gt bit 0 2 is disabled The RB3 PWM2 pin uses the state of the DDRB lt 3 gt bit for data direction bit 4 PWM10ON PWM1 On bit 1 is enabled The RB2 PWM pin ignores the state of the DDRB lt 2 gt bit 0 PWM is disabled The RB2 PWM1 pin uses the state of the DDRB 2 bit for data direction bit3 CA1 PR3 CA1 PR3 Register Mode Select bit 1 Enables Capture1 PR3H CA1H PRS3L CA1L is the Capture1 register Timer3 runs without a period register 0 Enables the Period register PR3H CA1H PR3L CA1L is the Period register for Timer3 bit 2 TMR3ON Timer3 On bit 1 Starts Timer3 0 Stops Timer3 bit 1 TMR2ON Timer2 On bit This bit controls the incrementing of the Timer2 register When Timer2 Timer1 form the 16 bit timer T16 is set TMR2ON must be set This allows the MSB of the timer to increment 1 Starts Timer2 Must be enabled if the T16 bit 1 lt 3 gt is set 0 Stops Timer2 bit 0 TMR10ON Timer1 On bit When T16 is set in 16 bit Timer Mode 1 Starts 16 bit Timer2 Timer1 0 Stops 16 bit 2 When T16 is clear in 8 bit Timer Mode 1 Starts 8 bit Timer 0 Stops 8 bit Timer1 DS30412C page 72 1996 Microchip Technology Inc PIC17CAX 12 1 and Timer2 1211 TIMER1 TIMER2 IN 8 BIT MODE Both Timerl and Timer2 will operate in 8 bit mode when the T16 bit is clear These two timers can be inde pendently configured to increment from
172. RE 17 11 MEMORY INTERFACE WRITE TIMING ALE WR OE AD lt 15 0 gt gt 152 TABLE 17 11 MEMORY INTERFACE WRITE REQUIREMENTS Parameter No Sym Characteristic Min Units Conditions 150 TadV2alL AD lt 15 0 gt address valid to ALEL 0 25Tcy 30 address setup time to address out invalid address hold time TadV2wrL Data out valid to WR L 0 25Tcy 40 data setup time 153 TwrH2ad WRT to data out invalid 0 25Tcv 8 ns data hold time 154 WR pulse width 0 25Tcv 8 ns These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 8 This specification is guaranteed by design 1996 Microchip Technology Inc DS30412C page 161 PIC17C4X Applicable Devices 42 R42 42 43 R43 44 FIGURE 17 12 READ TIMING TABLE 17 12 MEMORY INTERFACE READ REQUIREMENTS Parameter Sym Characteristic Min Units Conditions No TadV2alL AD lt 15 0 gt address valid to ALEL 0 25 30 ns address setup time TalL2adl ALE to address out invalid 5 ns address hold time TadZ2oel AD lt 15 0 gt hig
173. REN is set If the OERR bit is set transfers from the RSR to RCREG are inhibited so it is essential to clear the OERR bit if it is set The framing error bit FERR RCSTA 2 is set if a stop bit is not detected FIGURE 13 7 RX PIN SAMPLING SCHEME Note The FERR and the 9th receive bit are buff ered the same way as the receive data Reading the RCREG register will allow the RX9D and FERR bits to be loaded with val ues for the next received Received data therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old FERR and RX9D information 13 23 SAMPLING The data on the RA4 RX DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RA4 RX DT pin The sam pling is done on the seventh eighth and ninth falling edges of a x16 clock Figure 11 3 The x16 clock is a free running clock and the three sample points occur at a frequency of every 16 falling edges Start bit RX RA4 RX DT pin baud CLK 7 Baud CLK for all but start bit x16 CLK Samples 12 13 14 15 1996 Microchip Technology Inc DS30412C page 91 PIC17C4X Steps to follow when setting up an Asynchronous 7 Read RCSTA to get the ninth bit if enabled and Reception FERR bit to determine if any error occurred dur 1 Initia
174. RUPT Q1 Q2 031 Q4 01 02 031 01 021 03 04 01 021 031 04 01 02 0231 04 osci JUV UV Nf NJ VU VV HS Tost CLKOUT 4 INT RAO INT pin i i Interrupt Latency 2 GLINTD bit Processor INSTRUCTION FLOW in SLEEP PC PC x I i i i i Inst PC SLEEP Inst PC 1 Inst 2 Inst 1 i SLEEP i Inst PC 1 Dummy Cycle Note 1 XT or LF oscillator mode assumed 2 Tost 1024Tosc drawing not to scale This delay will not be there for RC osc mode 3 When GLINTD 0 processor jumps to interrupt routine after wake up If GLINTD 1 execution will continue in line 4 CLKOUT is not available in these osc modes but shown here for timing reference 1996 Microchip Technology Inc DS30412C page 105 PIC17CAX 14 42 MINIMIZING CURRENT CONSUMPTION To minimize current consumption all I O pins should be either at VDD or VSS with no external circuitry drawing current from the I O pin I O pins that are hi impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs The TOCKI input should be at VDD or Vss The contributions from on chip pull ups on PORTB should also be con sidered and disabled when possible 14 5 Code Protection The code in the program memory can be protected by selecting the microcontroller in code
175. SCILLATOR vs VDD 4 0 VDD Volts FIGURE 20 6 TRANSCONDUCTANCE gm OF XT OSCILLATOR vs Min 85 C VoD Volts DS30412C page 196 1996 Microchip Technology Inc PIC17CAX Applicable Devices 42 842 42A 43 R43 44 FIGURE 20 7 TYPICAL IDD vs FREQUENCY EXTERNAL CLOCK 25 C 100000 100k 1M External Clock Frequency Hz FIGURE 20 8 MAXIMUM vs FREQUENCY EXTERNAL CLOCK 125 C TO 40 C 100000 1M External Clock Frequency Hz 1996 Microchip Technology Inc DS30412C page 197 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 FIGURE 20 9 TYPICAL IPD vs WATCHDOG DISABLED 25 C Temp 40 C 6 5 7 0 VDD Volts DS30412C page 198 1996 Microchip Technology I
176. Select bit This bit selects the edge upon which TMRO will increment When TOCS 0 1 Rising edge of RA1 TOCKI pin increments TMRO and or generates a TOCKIF interrupt 0 Falling edge of RA1 TOCKI pin increments TMRO and or generates a TOCKIF interrupt When TOCS 1 Don t care bit5 TOCS Timer0 Clock Source Select bit This bit selects the clock source for TimerO 1 Internal instruction clock cycle TCY 0 pin bit 4 1 PS3 PSO Prescale Selection bits These bits select the prescale value for 53 50 Prescale Value 0000 1 1 0001 1 2 0010 1 4 0011 1 8 0100 1 16 0101 1 32 0110 1 64 0111 1 128 1 256 bit 0 Unimplemented Read as 0 DS30412C page 38 1996 Technology Inc PIC17C4X 6 3 Stack Operation The PIC17C4X devices have a 16 x 16 bit wide hard ware stack Figure 6 1 The stack is not part of either the program or data memory space and the stack pointer is neither readable nor writable The PC is PUSHed onto the stack when CALL instruction is executed or an interrupt is acknowledged The stack is POPed in the event of a RETURN RETLW Or a instruction execution PCLATH is not affected by a PUSH or a POP operation The stack operates as a circular buffer with the stack pointer initialized to 0 after all resets There is a stack available bit STKAV to allow software to ensure that the stack has not overflowed The STKAV bit
177. T time out occurs The WDT and postscaler is the Power up Timer during the Power on Reset sequence 14 3 4 WDT AS NORMAL TIMER When the WDT is selected as a normal timer the clock source is the device clock Neither the WDT nor the postscaler are directly readable or writable The over flow time is 65536 Tosc cycles On overflow the TO bit is cleared device is not reset The CLRWDT instruction can be used to set the TO bit This allows the WDT to be a simple overflow timer When in sleep the WDT does not increment 1996 Microchip Technology Inc DS30412C page 103 PIC17C4X FIGURE 14 8 WATCHDOG BLOCK DIAGRAM On chip RC Postscaler Oscillator 1 4 to 1MUX WDTPS1 WDTPSO WDT Enable Note 1 This oscillator is separate from the external RC oscillator on the OSC1 pin WDT Overflow TABLE 14 4 REGISTERS BITS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on all Name Bit4 Bit 3 Bit 2 Power on other resets Reset Note1 Config WDTPS1 WDTPSO Note 2 Note 2 06h Unbanked CPUSTA GLINTD 11 11 11 qq Legend unimplemented read as 0 value depends on condition shaded cells not used by the WDT Note 1 Other non power up resets include external reset through MCLR and Watchdog Timer Reset 2 This value will be as the device was programmed or if unprogrammed will re
178. TCLK12 pin and the timer will increment on every falling edge on the RB4 TCLK12 pin The TCLK12 input is synchronized with internal phase clocks This causes a delay from the time a falling edge appears on TCLK12 to the time TMR1 or TMR2 is actually incremented For the external clock input timing requirements see the Electrical Specification section FIGURE 12 3 TIMER1 AND TIMER2 IN TWO 8 TIMER COUNTER MODE ON 2 lt 0 gt TMR1CS 1 lt 0 gt RB4 TCLK12 2 lt 1 gt TMR2CS 1 lt 1 gt 1996 Microchip Technology Inc Ee TMR1 Set TMR1IF T CERE PIR lt 4 gt Comparator x8 PR1 ES TMR2 Set TMR2IF PIR lt 5 gt Comparator x8 TT PR2 DS30412C page 73 PIC17C4X 12 1 2 1 amp TIMER2 16 BIT MODE To select 16 bit mode the T16 bit must be set In this mode TMR1 and TMR2 are concatenated to form a 16 bit timer TMR2 TMR1 The 16 bit timer incre ments until it matches the 16 bit period register PR2 PR1 On the following timer clock the timer value is reset to Oh and the TMRAIF bit is set When selecting the clock source for the16 bit timer the TMR1CS bit controls the entire 16 bit timer and TMR2CS is a don t care When TMR1CS is clear the 12 1 2 1 EXTERNAL CLOCK INPUT FOR TMR1 TMR2 When T
179. TE IN TIMER MODE lo las iat los jas loe las las at las Jas AD15 ADO ALE WR TRMOL WR TMROH RD TMROL 12 X FE FF 56 XA v X MOVPF TMROL W Read TMROL X MOVPF TMROL W Read TMROL 12 Xm X MOVFP MOVPF Instruction DATAL TMROL DATAH TMROH TMROLW TMROLW fetched Write TMROL Write TMROH Read TMROL Read TMROL Previously MOVFP MOVFP MOVPF MOVPF MOVPF Instruction Fetched DATAL TMROL DATAH TMROH TMROLW TMROLW TMROLW executed Instruction Write TMROL Write TMROH Read TMROL Read TMROL Read TMROL In this example old TMRO value is 12FEh new value of AB56h is written TABLE 11 1 REGISTERS BITS ASSOCIATED WITH TIMERO Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 05h Unbanked TOSTA INTEDG TOSE TOCS PS3 PS2 PS1 50 0000 000 0000 000 06h Unbanked CPUSTA STKAV GLINTD TO PD 11 11 11 qq 07h Unbanked INTSTA PEIF TOCKIF TOIF INTF PEIE TOCKIE TOIE INTE 0000 0000 0000 0000 OBh Unbanked TMROL TMRO register low byte XXXX XXXX uuuu uuuu OCh Unbanked TMROH TMRO register high byte XXXX XXXX uuuu uuuu Legend unknown u unchanged unimplemented read as a
180. TE is for the control signals External components are needed to demultiplex the address and data This can be done as shown in Figure 6 4 The waveforms of address and data are shown in Figure 6 3 For complete timings please refer to the electrical specification section FIGURE 6 3 EXTERNAL PROGRAM MEMORY ACCESS WAVEFORMS Q1 a3 ai a4 al X gt Address out Datain Address out Data out WR __ Read Write cycle The system bus requires that there is no bus conflict minimal leakage so the output value address will be capacitively held at the desired value As the speed of the processor increases external EPROM memory with faster access time must be used Table 6 2 lists external memory speed requirements for a given PIC17C4X device frequency In extended microcontroller mode when the device is executing out of internal memory the control signals will continue to be active That is they indicate the action that is occurring in the internal memory The external memory access is ignored This following selection is for use with Microchip EPROMSs For interfacing to other manufacturers mem ory please refer to the electrical specifications of the desired PIC17C4X device well as the desired mem ory device to ensure compatibility TABLE 6 2 EPROM MEMORY ACCESS TIME ORDERING SUFFIX EPROM Suffix PIC17C4X Instruction
181. TION instructions have been removed 4 new instructions for transferring data between data memory and program memory This can be used to self program the EPROM program memory Single cycle data memory to data memory trans fers possible MOVPF and instructions These instructions do not affect the Working reg ister WREG W register WREG is now directly addressable A PC high latch register PCLATH is extended to 8 bits The PCLATCH register is now both readable and writable Data memory paging is redefined slightly DDR registers replaces function of TRIS regis ters Multiple Interrupt vectors added This can decrease the latency for servicing the interrupt Stack size is increased to 16 deep BSR register for data memory paging Wake up from SLEEP operates slightly differ ently The Oscillator Start Up Timer OST and Power Up Timer PWRT operate in parallel and not in series PORTB interrupt on change feature works on all eight port pins TMRO is 16 bit plus 8 bit prescaler Second indirect addressing register added FSR1 and FSR2 Configuration bits can select the FSR registers to auto increment auto dec rement remain unchanged after an indirect address Hardware multiplier added 8 x 8 gt 16 bit PIC17C43 and PIC17C44 only Peripheral modules operate slightly differently Oscillator modes slightly redefined placed in different registers and the control bit for gl
182. TMR2ON TMR1ON 0000 0000 0000 0000 10h Bank 2 TMR1 Timer1 register uuuu uuuu 11h Bank 2 TMR2 Timer2 register XXXX uuuu uuuu 16h Bank 1 RBIF TMRSIF TMR2IF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010 17h Bank 1 PIE RBIE TMR3IE TMR2IE TMR1IE CA2IE RCIE 0000 0000 0000 0000 07h Unbanked INTSTA PEIF TOCKIF TOIF INTF PEIE TOCKIE TOIE INTE 0000 0000 0000 0000 06h Unbanked CPUSTA STKAV GLINTD TO PD 11 11 11 qq 10h Bank 3 PW1DCL DC1 DCO uu 11h Bank 3 PW2DCL DC1 DCO TM2PW2 xx0 uu0 12h Bank 3 PW1DCH DC8 DC7 DC6 DC5 DC4 DC3 DC2 XXXX UUUU 13h Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 XXXX XXXX uuuu uuuu Legend x unknown u unchanged unimplemented read as 0 value depends on conditions shaded cells are not used by PWM 1996 Microchip Technology Inc DS30412C page 77 PIC17C4X 12 2 4 ONE CAPTURE AND ONE PERIOD REGISTER MODE In this mode registers PR3H CA1H and PR3L CA1L constitute a 16 bit period register A block diagram is shown in Figure 12 7 The timer increments until it equals the period register and then resets to 0000h Interrupt Flag bit TMRSIF is set at this point This interrupt can be disabled by clearing the TMR3 Interrupt Enable bit TMRSIE TMRSIF must be cleared in software This mode is selected if control bit CA1 PR3 i
183. TOSTA INTEDG TOSE TOCS PS3 PS2 PS1 50 0000 000 0000 000 13h Bank 0 RCSTA SPEN RC9 SREN CREN FERR OERR RC9D 0000 00x 0000 00u 15h Bank 0 TXSTA CSRC TX9 TXEN SYNC TRMT TX9D 0000 1x 0000 1u Legend x unknown u unchanged unimplemented reads as 0 Shaded cells not used by PORTA Note 1 Other non power up resets include external reset through MCLR and the Watchdog Timer Reset DS30412C page 54 1996 Microchip Technology Inc PIC17C4X 9 2 PORTB and DDRB Registers PORTB is an 8 bit wide bi directional port The corre sponding data direction register is DDRB A 1 in DDRB configures the corresponding port pin as an input A 0 in the DDRB register configures the corresponding port pin as an output Reading PORTB reads the status of the pins whereas writing to it will write to the port latch Each of the PORTB pins has a weak internal pull up A single control bit can turn on all the pull ups This is done by clearing the RBPU PORTA lt 7 gt bit The weak pull up is automatically turned off when the port pin is configured as an output The pull ups are enabled on any reset PORTB also has an interrupt on change feature Only pins configured as inputs can cause this interrupt to occur i e any RB7 RBO pin configured as an output is excluded from the interrupt on change comparison The input pins of RB7 RBO are compared with the value in the PORTB data latch The m
184. TTL RC6 AD6 8 9 25 TTL RC7 AD7 9 10 26 VO TTL Legend Input only Output only I O Input Output P Power Not Used TTL TTL input ST Schmitt Trigger input DS30412C page 12 1996 Microchip Technology Inc PIC17CAX TABLE 3 1 PINOUT DESCRIPTIONS DIP PLCC I O P Buffer soe Name No No No Type Type Description PORTD is a bi directional Port RDO AD8 40 43 15 VO TTL This is also the upper byte of the 16 bit system bus in RD1 AD9 39 42 14 VO TTL microprocessor mode or extended microprocessor mode RD2 AD10 38 41 13 VO TTL or extended microcontroller mode In multiplexed system bus configuration these pins are address output as well RD3 AD11 37 40 12 VO TTL data input or output RD4 AD12 36 39 11 VO TTL RD5 AD13 35 38 10 VO TTL RD6 AD14 34 37 9 VO TTL RD7 AD15 33 36 8 TTL PORTE is a bi directional I O Port REO ALE 30 32 4 VO TTL In microprocessor mode or extended microcontroller mode it is the Address Latch Enable ALE output Address should be latched on the falling edge of ALE output RE1 OE 29 31 3 TTL In microprocessor or extended microcontroller mode it is the Output Enable OE control output active low RE2 WR 28 30 2 TTL In microprocessor or extended microcontroller mode it is the Write Enable WR control output active low TEST 27 29 1 ST mode sel
185. Timer2 is selected to external clock the overflow interrupt flag will be set twice once when the timer equals the period and again when the timer value is reset to Oh If the latency to clear TMRxIF is greater than the time to the next clock pulse no problems will be noticed If the latency is less than the time to the next timer clock pulse the interrupt will be serviced twice Work arounds a Ensurethatthe timer has rolled over to Oh before clearing the flag bit b Clear the timer in software Clearing the timer in software causes the period to be one count less than expected Design considerations The device must not be operated outside of the speci fied voltage range An external reset circuit must be used to ensure the device is in reset when a brown out occurs or the VDD rise time is too long Failure to ensure that the device is in reset when device voltage is out of specification may cause the device to lock up and ignore the MCLR pin 1996 Microchip Technology Inc DS30412C page 223 PIC17C4X NOTES EE RE DS30412C page 224 1996 Microchip Technology Inc PIC17C4X ALU 9 A USTA 34 36 108 ALUSTA Register ANDLW ANDWF Application Notes BINDS Minnie 55 seen in 144 Asynchronous Master Transmission 90 A
186. V 2 5 6 0V 2 5 6 0V 2 5 6 0V 2 5 6 0V 2 5 6 0V Program Memory x16 EPROM 2K 2K 4K 8K ROM 2K 4K Data Memory bytes 232 232 232 454 454 454 Hardware Multiplier 8 x 8 Yes Yes Yes Yes Timer0 16 bit 8 bit postscaler Yes Yes Yes Yes Yes Yes 8 bit Yes Yes Yes Yes Yes Yes Timer2 8 bit Yes Yes Yes Yes Yes Yes Timer3 16 bit Yes Yes Yes Yes Yes Yes Capture inputs 16 bit 2 2 2 2 2 2 PWM outputs up to 10 bit 2 2 2 2 2 2 USART SCI Yes Yes Yes Yes Yes Yes Power on Reset Yes Yes Yes Yes Yes Yes Watchdog Timer Yes Yes Yes Yes Yes Yes External Interrupts Yes Yes Yes Yes Yes Yes Interrupt Sources 11 11 11 11 11 11 Program Memory Code Protect Yes Yes Yes Yes Yes Yes Pins 33 33 33 33 33 33 High Current Capabil Source 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA ity Sink 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA Package Types 40 pin DIP 40 pin DIP 40 pin DIP 40 pin DIP 40 pin DIP 40 pin DIP 44 pin PLCC 44 pin PLCC 44 pin PLCC 44 pin PLCC 44 pin PLCC 44 pin PLCC 44 pin MQFP 44 pin MQFP 44 pin MQFP 44 pin MQFP 44 pin MQFP 44 pin 44 pin TQFP 44 pin TQFP 44 pin TQFP 44 pin TQFP 44 pin TQFP Note 1 Pins RA2 can sink up to 60 mA 1996 Microchip Technology Inc DS30412C page 6 PIC17CAX 2 0 DEVICE VARIETIES A variety of frequency ranges and packaging options are available Depending on application and production requirement
187. Working register WREG is required to be affected then f WREG must be specified 4 During an LCALL the contents of PCLATH are loaded into the MSB of the PC and kkkk is loaded into the LSB of the PC PCL 5 Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM The instruc tion is terminated by an interrupt event When writing to external program memory it is a two cycle instruc tion 6 Two cycle instruction when condition is true else single cycle instruction 7 Two cycle instruction except for TABLRD to PCL program counter low byte in which case it takes 3 cycles 8 A skip means that instruction fetched during execution of current instruction is not executed instead an NOP is executed 9 These instructions are not available on the PIC17C42 1996 Microchip Technology Inc DS30412C page 111 PIC17C4X ADDLW ADD Literal to WREG Syntax label ADDIW Operands 0 lt k lt 255 Operation WREG k gt WREG Status Affected OV C DC Z Encoding 1011 0001 kkkk kkkk Description The contents of WREG are added to the 8 bit literal k and the result is placed in WREG Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to literal k WREG Example ADDLW 0x15 Before Instruction WREG 0x10 After Instruction WREG 0x25 ADDWF ADD WREG to f Syntax abel ADDWF 1 Operands 0 lt 1 lt
188. a tor The file register designator specifies which file register is to be used by the instruction The destination designator specifies where the result of the operation is to be placed If d 0 the result is placed in the WREG register If d 1 the result is placed in the file register specified by the instruction bit oriented instructions 0 represents bit field des ignator which selects the number of the bit affected by the operation while f represents the number of the file in which the bit is located literal and control operations k represents an 8 or 11 bit constant or literal value The instruction set is highly orthogonal and is grouped into byte oriented operations bit oriented operations literal and control operations All instructions are executed within one single instruc tion cycle unless aconditional test is true the program counter is changed as a result of an instruction atable read or a table write instruction is exe cuted in this case the execution takes two instruction cycles with the second cycle executed as a NOP One instruction cycle consists of four oscillator periods Thus for an oscillator frequency of 25 MHz the normal instruction execution time is 160 ns If a conditional test is true or the program counter is changed as a result of an instruction the instruction execution time is 320 ns TABLE 15 1 OPCODE FIELD DESCRIPTIONS Field Descri
189. ad as all 1 s DS30412C page 104 1996 Microchip Technology Inc PIC17C4X 14 4 Power down Mode SLEEP PD bit which is set on power up is cleared when SLEEP is invoked The TO bit is cleared if WDT The Power down mode is entered by executing a time out occurred and caused wake up SLEEP instruction This clears the Watchdog Timer and postscaler if enabled The PD bit is cleared and the TO bit is set in the CPUSTA register In SLEEP mode the oscillator driver is turned off The ports maintain their status driving high low or hi impedance When the SLEEP instruction is being executed the next instruction PC 1 is pre fetched For the device to wake up through an interrupt event the corresponding interrupt enable bit must be set enabled Wake up is regardless of the state of the GLINTD bit If the GLINTD The MCLH VPP pin must be at a logic high level bit is set disabled the device continues execution at A time out RESET does not drive the the instruction after the SLEEP instruction If the MCLR VPP pin low GLINTD bit is clear enabled the device executes the instruction after the SLEEP instruction and then branches to the interrupt vector address In cases The device can wake up from SLEEP through one of where the execution of the instruction following SLEEP the following events is not desirable the user should have a NOP after the SLEEP instru
190. ag bit If Capture1 is enabled CA1 PR3 1 1 Timer3 overflowed 0 Timers did not overflow If Capture1 is disabled CA1 PR3 0 1 TimerS value has rolled over to 0000h from equalling the period register PRSH PR3L value 0 Timer3 value has not rolled over to 0000h from equalling the period register PR3H PR3L value TMR2IF Timer2 Interrupt Flag bit 1 Timer2 value has rolled over to 0000h from equalling the period register PR2 value 0 Timer2 value has not rolled over to 0000h from equalling the period register PR2 value Timer1 Interrupt Flag bit If Timer1 is 8 bit mode T16 0 1 value has rolled over to 0000h from equalling the period register PR value 0 value has not rolled over to 0000h from equalling the period register PR2 value If Timer1 is in 16 bit mode T16 1 1 TMR1 TMR2 value has rolled over to 0000h from equalling the period register PR1 PR2 value 0 TMR1 TMR2 value has not rolled over to 0000h from equalling the period register PR1 PR2 value CA2IF Capture Interrupt Flag bit 1 Capture event occurred on RB1 CAP2 pin 0 Capture event did not occur RB1 CAP2 pin Capture1 Interrupt Flag bit 1 Capture event occurred on RBO CAP 1 pin 0 Capture event did not occur on RBO CAP 1 pin TXIF USART Transmit Interrupt Flag bit 1 Transmit buffer is empty 0 Transmit buffer is full RCIF USART Receive Interrupt Flag bit 1 Rece
191. again YES continue with program low CPUSTA GLINTD TABLE 5 1 INTERRUPT VECTORS PRIORITIES Address Vector Priority 0008h External Interrupt on RAO 1 Highest INT pin INTF 0010h overflow interrupt 2 TOIF 0018h External Interrupt on TOCKI 3 TOCKIF 0020h Peripherals PEIF 4 Lowest 1996 Microchip Technology Inc DS30412C page 25 PIC17C4X 5 5 RAO INT Interrupt The external interrupt on the RAO INT pin is edge trig gered Either the rising edge if INTEDG bit 05 lt 7 gt is set or the falling edge if INTEDG bit is clear When a valid edge appears on the RAO INT pin the INTF bit INTSTA lt 4 gt is set This interrupt can be disabled by clearing the INTE control bit INTSTA lt 0 gt The INT interrupt can wake the processor from SLEEP See Section 14 4 for details on SLEEP operation 5 6 TMRO Interrupt An overflow FFFFh gt 0000h in TMRO will set the TOIF INTSTA lt 5 gt bit The interrupt can be enabled disabled by setting clearing the TOIE control bit INTSTA lt 1 gt For operation of the 0 module see Section 11 0 5 7 Interrupt The external interrupt on the RA1 TOCKI pin is edge triggered Either the rising edge if the TOSE bit 05 lt 6 gt is set or the falling edge if the TOSE bit is clear When a valid edge appears on the RA1 TOCKI pin the TOCKIF bit INTSTA lt 6 gt is set This interrupt can be disabl
192. ails Power on Reset signal D004 SvDD VDD rise rate to 0 060 mV ms section on Power on Reset for ensure internal details Power on Reset signal D010 IDD Supply Current 3 6 mA Fosc 4 MHz 4 D011 Note 2 6 12 mA 8 MHz 0012 11 24 mA 16 MHz 0013 19 38 mA Fosc 25 MHz 0014 95 150 uA Fosc 32 kHz enabled osc configuration D020 IPD Power down Current 10 40 5 5V enabled 0021 Note 3 lt 1 5 uA VDD 5 5V disabled These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters for design guidance only and are not tested This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data The supply current is mainly a function of the operating voltage and frequency Other factors such as I O pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tristated pulled to or Vss TOCKI VDD MCLR VDD enabled disabled as specified Current consumed from the oscillator and l O s driving external capacitive or resistive loads need to be con sidered For the RC oscillator t
193. al Connection Diagram 31 Map ERR 29 Modes Extended Microcontroller 29 Microcontroller Microprocessor ES Protected Microcontroller 29 Organization 22 Transfers from Data Memory 43 Protected Microcontroller 29 Lies estote ot de ebd at dene 38 67 PS eium arena nenne ae eom age 38 67 PSS 38 67 PUSH 27 39 PW1DCH 20 35 PW1DCL 20 35 PW2DCH 20 35 PW2DCL 20 35 PWM 71 75 Duty Cycle 76 External Clock Source 76 vs Resolution 76 Interrupts oreet rere mente 76 Max Resolution Frequency for External Glock at cete ete 77 Output Periods PWM1 PWM2 PWRT RBIE 1996 Microchip Technology Inc PIC17C4X Receive Status and Control Register Register File Map Status Bits and Their Significance Time Out in Various Situations Time Out Sequence Saving STATUS and WREG in RAM SFR Special Function Registers SFR As Source Destination Special Features of the CPU Special Function Registers 1996 Microchip Technology Inc SWAP P
194. am memory as well as external program memory Execution automatically switches between internal and external memory The 16 bits of address allow a program memory range of 64K words Space Configuration Memory Reserved The microprocessor mode only accesses the external program memory The on chip program memory is PM20 ignored The 16 bits of address allow a program mem ory range of 64K words Microprocessor mode is the default mode of an unprogrammed device Boot ROM Test EPROM The different modes allow different access to the con figuration bits test memory and boot ROM Table 6 1 User memory space may be internal external or lists which modes can access which areas in memory both The memory configuration depends on the Test Memory and Boot Memory are not required for processor mode normal operation of the device Care should be taken to This location is reserved on the PIC17C42 ensure that no unintended branches occur to these areas 1996 Microchip Technology Inc DS30412C page 29 PIC17C4X TABLE 6 1 MODE MEMORY ACCESS The PIC17C4X operate in modes where the gram memory is off chip They are the microprocessor Internal Configuration Bits and extended microcontroller modes The micropro Operating Program Test Memory cessor mode is the default for an unprogrammed Mode Boot ROM device Microprocessor No A
195. an interrupt will be generated if the RCIE bit was set 7 Read RCSTA to get the ninth bit if enabled and determine if any error occurred during reception 8 Read the 8 bit received data by reading RCREG 9 If any error occurred clear the error by clearing CREN Note To terminate a reception either clear the SREN and CREN bits or the SPEN bit This will reset the receive logic so that it will be in the proper state when receive is re enabled FIGURE 13 11 SYNCHRONOUS RECEPTION MASTER MODE SREN 4 1 adadad 1 4 0 4 a4 db b 5 adag RA4 RX DT pin DT X bito SC bit7 5 pin Write to the SREN bit SREN bit J CREN bit 0 RCIF bit Read RCREG Note Timing diagram demonstrates SYNC master mode with SREN 1 1996 Microchip Technology Inc DS30412C page 95 PIC17C4X TABLE 13 8 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 16h Bank 1 PIR RBIF TMRAIF TMR2IF TMR1IF CA2IF CA1IF TXIF RCIF 0000 001
196. been provided in the instruction set If the currently selected bank is not implemented such as Bank 13 any read will read all 0 s Any write is com pleted to the bit bucket and the ALU status bits will be set cleared as appropriate Note Registers in Bank 15 in the Special Func Register area are reserved for Microchip use Reading of registers in this bank may cause random values to be read Range 10h 17h Bank 0 Bank 1 Bank 3 Bank 4 Bank 1 Bank 15 Only Banks 0 through Bank 3 are implemented Selection of an unimplemented bank is not recommended Bank 15 is reserved for Microchip use reading of registers in this bank may cause random values to be read Only Banks 0 and Bank 1 are implemented Selection of an unimplemented bank is not recommended DS30412C page 42 1996 Microchip Technology Inc PIC17C4X 7 0 TABLE READS AND TABLE FIGURE 7 2 TABLWT INSTRUCTION WRITES OPERATION The 17 has four instructions that allow the pro cessor to move data from the data memory space to the program memory space and vice versa Since the TBLPTRH TBLPTRL program memory space is 16 bits wide and the data memory space is 8 bits wide two operations are required to move 16 bit values to from the data mem TABLATH TABLATL TABLE POINTER TABLE LATCH 16 bit
197. bel INCFSZ Operands 0 lt 1 lt 255 0 1 f 1 dest skip if result 0 Status Affected None Encoding 0001 1114 ffff ffff Description The contents of register are incre mented If d is 0 the result is placed WREG If d is 1 the result is placed back in register f If the result is 0 the next instruction which is already fetched is discarded and an NOP is executed instead making it a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination If skip Q1 Q2 Q3 Q4 Forced NOP NOP Execute NOP Example HERE NCFSZ CNT 1 NZERO ZERO Before Instruction PC Address HERE After Instruction If CNT PC If CNT PC Wow CNT 1 0 Address ZERO 0 Address NZERO 1996 Microchip Technology Inc DS30412C page 123 PIC17C4X INFSNZ Increment f skip if not 0 IORLW Inclusive OR Literal with WREG Syntax INFSNZ Syntax label IORLW Operands 0 lt lt 255 Operands lt lt 255 0 1 Operation WREG OR gt WREG Operation f 1 dest skip if not 0 Status Affected 7 Status Affected None Encoding 1011 0011 kkkk kkkk Encoding pee ee Ne Description The contents of WREG are OR ed with Description The contents of register are incre the eight bit literal k The
198. bit3 ST Input Output or the RB3 PWM output pin Software programmable weak pull up and interrupt on change features RB4 TCLK12 bit4 ST Input Output or the external clock input to and Timer2 Software grammable weak pull up and interrupt on change features RB5 TCLK3 bit5 ST Input Output or the external clock input to Timer3 Software programmable weak pull up and interrupt on change features RB6 bit6 ST Input Output pin Software programmable weak pull up and interrupt on change features RB7 bit7 ST Input Output pin Software programmable weak pull up and interrupt on change features Legend ST Schmitt Trigger input TABLE 9 4 REGISTERS BITS ASSOCIATED WITH PORTB Value on bhois all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on resets Note1 12h Bank 0 PORTB PORTB data latch XXXX XXXX uuuu uuuu 11h Bank 0 DDRB Data direction register for PORTB 1111 1211 10h Bank 0 PORTA 5 4 2 RA1 TOCKI RAO INT 0 0 uu uuuu 06h Unbanked CPUSTA STKAV GLINTD TO PD 11 11 11 qq 07h Unbanked INTSTA PEIF TOCKIF TOIF INTF PEIE TOCKIE TOIE INTE 0000 0000 0000 0000 16h Bank 1 PIR RBIF TMRSIF TMR2IF TMR1IF CA2IF 0000 0010 0000 0010 17h Bank 1 PIE RBIE TMRSIE TMR2IE TMR1IE CA2IE
199. buffer Vss 10 2 001 V MCLR OSC1 and RC Vss 0 2VDD V 1 mode OSC1 in XT and LF mode 0 5VDD V Input High Voltage ports with TTL buffer 2 0 VDD V with Schmitt Trigger buffer 0 8VDD VDD V MCLR 0 8VDD VDD V OSC1 XT and LF mode 0 5VDD V Hysteresis of 0 15VDD V Schmitt Trigger inputs Input Leakage Current Notes 2 3 ports except RA2 1 Vss lt VPIN lt VDD Pin at hi impedance PORTB weak pull ups dis abled MCLR 2 VPIN Vss VDD RA2 2 Vss VRA3 lt 12V OSC1 TEST 1 Vss lt VPIN lt VDD 10 VMCLR 12V when programming IPURB weak pull up current 60 200 400 uA VPIN 55 RBPU 0 7 These parameters characterized but not tested T Data Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested t These parameters are for design guidance only and are not tested nor characterized Tf Design guidance to attain the AC timing specifications These loads are not tested Note 1 In RC oscillator configuration the OSC1 pin is a Schmitt Trigger input It is not recommended that the PIC17CXX devices be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent n
200. cation ensured design 1996 Microchip Technology Inc DS30412C page 159 PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 17 9 USART MODULE SYNCHRONOUS TRANSMISSION MASTER SLAVE TIMING ___ RA4 RX DT pin TABLE 17 9 SERIAL PORT SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter No Sym Characteristic Min Typt Max Units Conditions 120 TckH2dtV SYNC XMIT MASTER amp SLAVE Clock high to data out valid 65 ns 121 TckRF Clock out rise time and fall time Master 10 35 ns Mode 122 TdtRF Data out rise time and fall time 10 35 ns t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 17 10 USART MODULE SYNCHRONOUS RECEIVE MASTER SLAVE TIMING RA5 TX CK Qoam pin RA4 RX DT pin x Parameter No Characteristic 125 TdtV2ckL SYNC MASTER amp SLAVE Data hold before ROW Feiste POR DT hold time 126 TckL2atl Data hold after DT hold time ns T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30412C page 160 1996 Technology Inc PIC17CAX Applicable Devices 42 R42 42A 43 43 44 FIGU
201. ccess NEA Regardless of the processor mode data memory is always on chip Microcontroller Access Access Access No Access Microcontroller Protects Access Access Microcontroller FIGURE 6 2 MEMORY MAP IN DIFFERENT MODES PIC17C42 PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 PIC17C44 DS30412C page 30 Microprocessor Mode Extended Microcontroller Mode Microcontroller Modes External Program Memory OFF CHIP ON CHIP 0000h External Program Memory OFF CHIP ON CHIP 0000h On chip Program Memory PROGRAM SPACE FFFFh Boot ROM OFF CHIP ON CHIP 00h FFh OFF CHIP ON CHIP External Program Memory OFF CHIP ON CHIP 00h FFh OFF CHIP ON CHIP 0000h OFFFh TFFFh External Program Memory OFF CHIP ON CHIP 00h FFh ON CHIP DATA SPACE OFF CHIP OFFFh 1FFFh 1000h 2000h PROGRAM SPACE FFFFh Boot ROM ON CHIP OFF CHIP 00h 120h 1FFh OFF CHIP ON CHIP 00h 120h 1FFh OFF CHIP ON CHIP 120h 1FFh DATA SPACE OFF CHIP ON CHIP 1996 Microchip Technology Inc PIC17CAX 6 1 2 EXTERNAL MEMORY INTERFACE When either microprocessor or extended microcontrol ler mode is selected PORTC PORTD and PORTE are configured as the system bus PORTC and PORTD are the multiplexed address data bus and POR
202. ce register 0 No carry out from the most significant bit of the result Note For borrow the polarity is reversed DS30412C page 36 1996 Microchip Technology Inc PIC17C4X 6 2 2 2 CPU STATUS REGISTER CPUSTA The CPUSTA register contains the status and control bits for the CPU This register is used to globally enable disable interrupts If only a specific interrupt is desired to be enabled disabled please refer to the INTerrupt STAtus INTSTA register and the Peripheral Interrupt Enable PIE register This register also indi cates if the stack is available and contains the Power down PD and Time out TO bits The TO PD and STKAV bits not writable These bits are set and cleared according to device logic Therefore the result of an instruction with the CPUSTA register as destina tion may be different than intended FIGURE 6 8 CPUSTA REGISTER ADDRESS 06h UNBANKED 0 0 0 0 R 1 R W 1 R 1 1 0 0 0 0 STKAV GLINTD TO PD Readable bit bit7 bit0 W Writable bit U Unimplemented bit Read as 0 Value at POR reset bit 7 6 Unimplemented Read as 0 bit 5 STKAV Stack Available bit This bit indicates that the 4 bit stack pointer value is Fh or has rolled over from Fh Oh stack overflow 1 Stack is available 0 Stack is full or a stack overflow may have occurred Once this bit has been cleared by stack overflow only a device reset will se
203. cillator provides a low cost solution the LF oscillator is for low frequency crystals and minimizes power consumption XT is a standard crystal and the EC is for external clock input The SLEEP power down mode offers additional power saving The user can wake up the chip from SLEEP through several external and internal interrupts and device resets There are four configuration options for the device oper ational modes Microprocessor Microcontroller Extended microcontroller Protected microcontroller The microprocessor and extended microcontroller modes allow up to 64K words of external program memory A highly reliable Watchdog Timer with its own on chip RC oscillator provides protection against software mal function Table 1 1 lists the features of the PIC17C4X devices A UV erasable CERDIP packaged version is ideal for code development while the cost effective One Time Programmable OTP version is suitable for production in any volume The PIC17C4X fits perfectly in applications ranging from precise motor control and industrial process con trol to automotive instrumentation and telecom appli cations Other applications that require extremely fast execution of complex software programs or the flexibil ity of programming the software code as one of the last steps of the manufacturing process would also be well suited The EPROM technology makes customization of application programs with unique security
204. cle instruction Words 1 Cycles 1 Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register f If skip Q1 Q2 Q3 Q4 Forced NOP NOP Execute NOP Example HERE CPFSEQ REG NEQUAL EQUAL Before Instruction PC Address HERE WREG REG 2 7 After Instruction If REG WREG PC Address EQUAL If REG WREG PC Address NEQUAL Dum Se Syntax label CPFSGT f Operands 0 lt 1 lt 255 f WREG skip if f gt WREG unsigned comparison Status Affected None Encoding 0011 0010 ffff Compares the contents of data memory location to the contents of the WREG by performing an unsigned subtraction If the contents of gt the contents of WREG then the fetched instruction is discarded and an NOP is executed instead making this a two cycle instruc Description tion Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register f If skip Q1 Q2 Q3 Q4 Forced NOP NOP Execute NOP Example HERE CPFSGT REG NGREATER GREATER Before Instruction PC Address HERE WREG After Instruction l REG gt WREG PC Address GREATER l REG lt WREG PC Address NGREATER 1996 Microchip Technology Inc DS30412C page 119 PIC17C4X erat o a Syntax abel CPFSLT f Operands 0 lt lt 255 Operation f WREG skip if f lt WREG unsigned comparison Status Affected
205. codes combinations model numbers parameter storage etc fast and convenient Small footprint package options make the 17 ideal for applications with space limitations that require high performance High speed execution powerful peripheral features flexible and low power consumption all at low cost make the PIC17C4X ideal for a wide range of embedded con trol applications 1 1 Family and Upward Compatibility Those users familiar with the PIC16C5X PIC16CXX families of microcontrollers will see the architectural enhancements that have been imple mented These enhancements allow the device to be more efficient in software and hardware requirements Please refer to Appendix A for a detailed list of enhancements and modifications Code written for PIC16C5X or PIC16CXX can be easily ported to PIC17CXX family of devices Appendix B 1 2 Development Support The PIC17CXX family is supported by a full featured macro assembler a software simulator an in circuit emulator a universal programmer a C compiler and fuzzy logic support tools 1996 Microchip Technology Inc DS30412C page 5 PIC17C4X TABLE 1 1 PIC17CXX FAMILY OF DEVICES Features 17 42 PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 PIC17C44 Maximum Frequency of Operation 25 MHz 33 MHZ 33 MHz 33 MHz 33 MHz 33 MHz Operating Voltage Range 4 5 5 5
206. ction A POR reset External reset input on MCLR VPP pin Note If the global interrupts are disabled WDT Reset if WDT was enabled GLINTD is set but any interrupt source has both its interrupt enable bit and Interrupt from RAO INT pin RB port change i responding interrupt flag bits set the interrupt or some Peripheral Interrupts device will immediately wake up from 14 4 1 WAKE UP FROM SLEEP The following peripheral interrupts can wake up from sleep The TO bit is set and the PD bit is SLEEP cleared e Capturel interrupt The WDT is cleared when the device wake from Capture2 interrupt SLEEP regardless of the source of wake up USART synchronous slave transmit interrupt 144 11 WAKE UP DELAY USART synchronous slave receive interrupt When the oscillator type is configured in XT or LF mode the Oscillator Start up Timer OST is activated on wake up The OST will keep the device in reset for Other peripherals can not generate interrupts since during SLEEP no on chip Q clocks are present Any reset event will cause a device reset Any interrupt 1024Tosc This needs to be taken into account when event is considered a continuation of program execu considering the interrupt response time when coming tion The TO and PD bits in the CPUSTA register can out of SLEEP be used to determine the cause of device reset The FIGURE 14 9 WAKE UP FROM SLEEP THROUGH INTER
207. d also avoid read modify write operations on the duty cycle registers such as ADDWF PW1DCH This may cause duty cycle outputs that are unpredictable TABLE 12 3 PWM FREQUENCY vs RESOLUTION AT 25 MHz PWM Frequency kHz Frequency 244 48 8 65 104 97 66 390 6 PRx Value OxFF 0 7 Ox5F 0x3F 0x0F High 10 bit 9 bit 8 5 bit 8 bit 6 bit Resolution Standard 8 bit 7 bit 6 5 bit 6 bit 4 bit Resolution 12 1 3 2 PWM INTERRUPTS PWM module makes use of TMR1 or TMR2 inter rupts A timer interrupt is generated when TMR1 or TMR2 equals its period register and is cleared to zero This interrupt also marks the beginning of a PWM cycle The user can write new duty cycle values before the timer roll over The interrupt is latched into the TMR1IF bit and the TMR2 interrupt is latched into the TMR2IF bit These flags must be cleared in soft ware 12 1 3 3 EXTERNAL CLOCK SOURCE The PWMs will operate regardless of the clock source of the timer The use of an external clock has ramifica tions that must be understood Because the external TCLK12 input is synchronized internally sampled once per instruction cycle the time TCLK12 changes to the time the timer increments will vary by as much as TCY one instruction cycle This will cause jitter in the duty cycle as well as the period of the PWM output This jitter will be unless the external clock is syn chro
208. d be subroutines that were called isters during an interrupt e g WREG ALUSTA and the Depending on the application other registers may also BSR registers This requires implementation in soft need to be saved such as PCLATH ware EXAMPLE 5 1 SAVING STATUS AND WREG IN RAM The addresses that are used to store the CPUSTA and WREG values must be in the data memory address range of 18h 1Fh Up to 8 locations can be saved and restored using the MOVFP instruction bits nor corrupts the WREG register PUSH MOVFP MOVFP MOVFP ISR POP MOVFP MOVFP MOVFP RETFIE WREG TEMP W ALUSTA TEMP STATUS BSR TEMP BSR TEMP W WREG TEMP STATUS ALUSTA TEMP BSR BSR This instruction neither affects the status Save WREG Save ALUSTA Save BSR This is the interrupt service routine Restore WREG Restore ALUSTA Restore BSR Return from Interrupts enabled 1996 Microchip Technology Inc DS30412C page 27 PIC17C4X NOTES EE RE DS30412C page 28 1996 Technology Inc PIC17C4X 6 0 MEMORY ORGANIZATION FIGURE 6 1 PROGRAM MEMORY MAP There are two memory blocks in the 17 4 pro AND STACK gram memory and data memory Each block has its lt 15 0 gt own bus 50 that access to each block can occur during CALL RETURN 16 the same oscillator cycle RETFIE RETLW data memory can further be broken dow
209. d by the 10 bit value DCx lt 9 0 gt The upper 8 bits are from register PWxDCH and the lower 2 bits are from PWxDCL lt 7 6 gt PWxDCH PWxDCL lt 7 6 gt Table 12 3 shows the maximum PWM frequency FPWM given the value in the period register The number of bits of resolution that the PWM can achieve depends on the operation frequency of the device as well as the PWM frequency FPWM Maximum PWM resolution bits for a given PWM fre quency Fosc log Eose bits log 2 The PWMx duty cycle is as follows Duty Cycle x Tosc where DCx represents the 10 bit value from PWxDCH PWxDCL If DCx 0 then the duty cycle is zero If PRx PWxDCH then the PWM output will be low for one to four Q clock depending on state of the PWxDCL lt 7 6 gt bits For a Duty Cycle to be 100 the PWxDCH value must be greater then the PRx value The duty cycle registers for both PWM outputs are dou ble buffered When the user writes to these registers they are stored in master latches When TMR2 overflows and a new PWM period begins the master latch values are transferred to the slave latches and the PWMx pin is forced high Note For PW1DCH PW1DCL PW2DCH and PW2DCL registers a write operation writes to the master latches while a read operation reads the slave latches As a result the user may not read back what was just written to the duty cycle registers The user shoul
210. ded 6 For TTL buffers the better of the two specifications may be used Note When using the Table Write for internal programming the device temperature must be less than 40 C 1996 Microchip Technology Inc DS30412C page 181 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 19 4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 3 Tcc sT 2 specifications only 2 TppS 4 Ts specifications only T F Frequency T Time Lowercase symbols pp and their meanings ad Address Data ost Oscillator Start Up Timer al ALE pwrt Power Up Timer Capture Capture2 rb PORTB ck CLKOUT or clock rd RD dt Data in nw RD or WR in INT pin 10 io port t123 TCLK12 mc MCLR wdt Watchdog Timer oe OE wr WR os OSC1 Uppercase symbols and their meanings Driven Low Edge Period Fall Rise High Valid Invalid Hi impedance Hi impedance DS30412C page 182 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 42 42 43 R43 44 FIGURE 19 1 PARAMETER MEASUREMENT INFORMATION All timings are measure between high and low measurement points as indicated in the figures below INPUT LEVEL CONDITIONS PORTO D and E pins 2 4V X mm Data in valid i st All other input pins Data in invalid
211. e Write 190 PIC17C43 44 PWM Timing 188 PIC17C43 44 RESET Watchdog Timer Oscillator Start up Timer and Power up Timer 186 PIC17C43 44 TimerO Clock 187 PIC17C43 44 Timer1 Timer2 and Timer3 Clock 187 PIC17C43 44 USART Module Synchronous R CEIVE 189 PIC17C43 44 USART Module Synchronous Transmission 0 eee eeeeeeeeeeeeeeeeeeeeeeeaeeeeeeaeeeteneeeeteaaes 189 Synchronous Reception 95 Synchronous Transmission 94 Table Read 2 48 Table memes 46 SIMRO on t nta Ee 68 69 TMRO Read Write in Timer Mode 70 TMR1 2 and TMR3 in External Clock Mode 80 TMR1 TMR2 and in Timer Mode 81 Wake Up from SLEEP 105 Timing Diagrams and Specifications 155 Timing Parameter Symbology 153 T RD ntt 44 139 TEW i Lacer tre coe ed t Ropa e o te 43 140 TMRO 16 bit Read 69 16 bit Wtite 69 Glock Tirmihg 5 1 cierto 158 Module Operation cai aii carentem ak eec Prescaler Assignments Read Write Considerations 69 Read Write in Timer 70
212. e also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tristated pulled to or Vss TOCKI VDD MCLR VDD enabled disabled as specified Current consumed from the oscillator and driving external capacitive or resistive loads needs to be sidered For the RC oscillator the current through the external pull up resistor be estimated as VDD 2 R For capacitive loads the current can be estimated for an individual I O pin as CL VDD 1 CL Total capacitive load on the I O pin f average frequency the pin switches The capacitive currents are most significant when the device is configured for external execution includes extended microcontroller mode The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VDD or Vss For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula IR VDD 2Rext mA with in kOhm DS30412C page 178 1996 Technology Inc PIC17C4X Applicable Devices 42 42 42 43 843 44 19 3 CHARACTERISTICS PIC17CR42 42A 43 R43 44 16 Commercial Industrial PIC17CR42 42A 43 R43 44 25 Commercial Indu
213. e contents of register are rotated one bit to the left If d is O the result is placed in WREG If d is 1 the result is stored back in register NIS Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example RLNCF REG 1 Before Instruction C 0 REG 1110 1011 After Instruction REG 1101 0111 RRCF Rotate Right f through Carry Syntax abel RRCF fd Operands lt lt 255 d e 0 1 Operation fen gt lt 1 gt lt 0 gt gt gt d lt 7 gt Status Affected Encoding 0001 1008 ffff ffff Description The contents of register are rotated one bit to the right through the Carry Flag If d is 0 the result is placed in WREG If is 1 the result is placed back in register f register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example 0 Before Instruction REG1 1110 0110 30 After Instruction REG1 1110 0110 WREG 0111 0011 gt 210 EE SEE eee 1996 Microchip Technology Inc DS30412C page 133 PIC17C4X RRNCF Rotate Right f no carry Syntax label RRNCF Operands lt lt 255 d e 0 1 Operation fen gt lt 1 gt lt 0 gt d lt 7 gt Status Aff
214. e required for AT strip cut crystals DS30412C page 100 1996 Microchip Technology Inc PIC17C4X FIGURE 14 3 CRYSTAL OPERATION TABLE 14 3 CAPACITOR SELECTION OVERTONE CRYSTALS XT FOR CRYSTAL OSCILLATOR OSC CONFIGURATION Osc Type Freq C1 C2 LF 32 kHz 100 150pF 100 150 pF 1 MHz 10 33 pF 10 33 pF 2 MHz 10 33 pF 10 33 pF XT 2 MHz 47 100 pF 47 100 pF 4 MHz 15 68 pF 15 68 pF 8 MHz 15 47 pF 15 47 pF 0 1 uF PIC17C42 16 MHz TBD TBD 25 2 15 47 15 47 To filter the fundamental frequency 32 MHz 3 0 3 0 3 nt mm Where f tank circuit resonant frequency This should be Higher the stability midway between the fundamental and 3rd overtone oscillator but also increases the start up time and the freguencies of the crystal oscillator current These values are for design guid ance only RS may be required in XT mode to avoid overdriving the crystals with low drive level specifica TABLE 14 2 CAPACITOR SELECTION i tion Since each crystal has its own characteristics FOR the user should consult the crystal manufacturer for RESONATO appropriate values for external components Note 1 For gt 4 5V C1 C2 30 pF is recom Oscillator Resonator Capacitor Range
215. eceive mode to transmit and start driving To avoid this TXEN should be cleared In order to select 9 bit transmission the TX9 TXSTA lt 6 gt bit should be set and the ninth bit should be written to TX9D TXSTA 0 The ninth bit must be written before writing 8 bit data to TXREG This is because a data write to TXREG can result in an immediate transfer of the data to the TSR if the TSR is empty If the was empty and TXREG was written before writing the new TX9D the present value of TX9D is loaded Steps to follow when setting up a Synchronous Master Transmission 1 Initialize the SPBRG register for the appropriate baud rate see Baud Rate Generator Section for details 2 Enable the synchronous master serial port by setting the SYNC SPEN and CSRC bits 3 Ensure that the CREN and SREN bits are clear these bits override transmission when set 4 interrupts are desired then set the bit the GLINTD bit must be clear and the PEIE bit must be set 5 f 9 bit transmission is desired then set the TX9 bit 6 Start transmission by loading data to the TXREG register 7 f 9 bit transmission is selected the ninth bit should be loaded in TX9D 8 Enable the transmission by setting TXEN Writing the transmit data to the TXREG then enabling the transmit setting TXEN allows transmission to start sooner then doing these two events in the reverse order Note To terminate a transmission
216. echnical staff with micro controller and memory experts To provide you with the most responsive service possible the Microchip systems team monitors the BBS posts the latest component data and software tool updates provides technical help and embedded systems insights and discusses how Microchip products pro vide project solutions The web site like the BBS is used by Microchip as a means to make files and information easily available to customers To view the site the user must have access to the Internet and a web browser such as Netscape or Microsoft Explorer Files are also available for FTP download from our FTP site Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to www microchip com The file transfer site is available by using an FTP ser vice to connect to ftp mchip com biz mchip The web site and file transfer site provide a variety of services Users may download files for the latest Development Tools Data Sheets Application Notes User s Guides Articles and Sample Programs A vari ety of Microchip specific business information is also available including listings of Microchip sales offices distributors and factory representatives Other data available for consideration is Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips Device Errata Job Postings
217. ected None Encoding 0010 000d ffff ffff Description The contents of register are rotated one bit to the right If is O the result is placed in WREG If d is 1 the result is placed back in register f register f Jp Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example 1 RRNCF REG 1 Before Instruction WREG REG 1101 0111 After Instruction WREG 0 REG 1110 1011 Example 2 RRNCF REG 0 Before Instruction WREG REG 1101 0111 After Instruction WREG 1110 1011 REG 1101 O111 SETF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Set f label SETF fs 0xf 255 s e 0 1 FFh 5 f FFh gt d None 0010 101s IDE If s is 0 both the data memory location and WREG are set to FFh If s is 1 only the data memory location 15 set to FFh 1 1 Q1 Q2 Q3 Q4 Decode Read Execute Write register f register f and other specified register Example1 SETF REG 0 Before Instruction REG OxDA WREG 0x05 After Instruction REG OxFF WREG OxFF Example2 1 Before Instruction REG OxDA WREG 0x05 After Instruction REG OxFF WREG 0x05 DS30412C page 134 1996 Microchip Technology Inc PIC17C4X SLEEP Enter SLEEP mode Syntax label SLEEP Operands None Operatio
218. ection control input Always tie to Vss for nor mal operation Vss 10 11 5 6 P Ground reference for logic and I O pins 31 12 27 28 33 34 VDD 1 1 44 16 17 P supply for logic and I O pins Legend Input only Output only I O Input Output P Power Not Used TTL TTL input ST Schmitt Trigger input 1996 Microchip Technology Inc DS30412C page 13 PIC17C4X 3 1 Clocking Scheme Instruction Cycle The clock input from OSC1 is internally divided by four to generate four non overlapping quadrature clocks namely Q1 Q2 Q3 and Q4 Internally the pro gram counter PC is incremented every Q1 and the instruction is fetched from the program memory and latched into the instruction register in Q4 The instruc tion is decoded and executed during the following Q1 through Q4 The clocks and instruction execution flow are shown in Figure 3 3 FIGURE 3 3 CLOCK INSTRUCTION CYCLE 02 93 04 3 2 Instruction Flow Pipelining An Instruction Cycle consists of four Q cycles Q1 Q2 Q3 and Q4 The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the program counter to change e g GOTO then two cycles are required to complete the instruction Example 3 2 A fetch c
219. ectively inhibit increment of that half of the TMRO in the next cycle following write but not inhibit increment of the other half the user must write to TMROL first and TMROH next in two consecutive instructions as shown in Example 11 2 The interrupt must be disabled Any write to either TMROL or TMROH clears the prescaler EXAMPLE 11 2 16 BIT WRITE BSF CPUSTA GLINTD Disable interrupt MOVFP RAM L TMROL TMROH CPUSTA GLINTD Done enable interrupt 11 4 Prescaler Assignments TimerO has an 8 bit prescaler The prescaler assign ment is fully under software control i e it can be changed on the fly during program execution When changing the prescaler assignment clearing the pres caler is recommended before changing assignment The value of the prescaler is unknown and assigning a value that is less then the present value makes it dif ficult to take this unknown time into account FIGURE 11 4 TMRO TIMING WRITE HIGH OR LOW BYTE AD15 ADO rok ALE TMROL TO 1 New NTO x New 0 1 x Fetch Instruction executed Write to TMROL W TMROL MOVFP TMROL W Read TMROL TMROL W MOVFP TMROL W Read TMROL Read TMROL Value NTO 1 TMROH V Value NTO Value NTO VES V X 1996 Microchip Technology Inc DS30412C page 69 PIC17CAX FIGURE 11 5 0 READ WRI
220. ed States to find the phone number closest to you set your modem to 7 1 and dial 800 848 4480 for 300 2400 baud or 800 331 7166 for 9600 14400 baud connection After the system responds with Host Name type NETWORK depress the Enter key and follow 5 directions For voice information or calling from overseas you may call 614 723 1550 for your local CompuServe number Microchip regularly uses the Microchip BBS to distribute technical information application notes source code errata sheets bug reports and interim patches for Microchip systems software products For each SIG a moderator monitors scans and approves or disap proves files submitted to the SIG No executable files are accepted from the user community in general to limit the spread of computer viruses Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides System users a listing of the latest versions of all of Microchip s development systems software products Plus this line provides information on how customers can receive any currently available upgrade kits The Hot Line Numbers are 1 800 755 2345 for U S and most of Canada and 1 602 786 7302 for the rest of the world 960513 Trademarks The Microchip name logo PIC PICSTART PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U S A and other countries FlexROM
221. ed by clearing the TOCKIE control bit INTSTA lt 2 gt The TOCKI interrupt can wake up the processor from SLEEP See Section 14 4 for details on SLEEP operation 5 8 Peripheral Interrupt The peripheral interrupt flag indicates that at least one of the peripheral interrupts occurred PEIF is set The PEIF bit is a read only bit and is a bit wise OR of all the flag bits in the PIR register AND ed with the corre sponding enable bits in the PIE register Some of the peripheral interrupts can wake the processor from SLEEP See Section 14 4 for details on SLEEP opera tion FIGURE 5 5 INT PIN INTERRUPT TIMING Q1 a2 03 04 01 a2 03 04 Q1 02 03 04 01 02 03 04 01 02 03 04 01 a2 a3 04 01 03 04 RA0 INT or RA1 TOCKI ox TA TA TOCKIF GLINTD PC PC Instruction i executed Inst PC Dummy X Dummy RETFIE Dummy DS30412C page 26 1996 Microchip Technology Inc PIC17C4X 5 9 Context Saving During Interrupts Example 5 1 shows the saving and restoring of infor mation for an interrupt service routine The PUSH and During an interrupt only the returned PC value is saved POP routines could either be in each interrupt service on the stack Typically users may wish to save key reg routine or coul
222. el 886 2 2717 7175 Fax 886 2 2545 0139 EUROPE United Kingdom Arizona Microchip Technology Ltd 505 Eskdale Road Winnersh Triangle Wokingham Berkshire England RG41 5TU Tel 44 118 921 5858 Fax 44 118 921 5835 Denmark Microchip Technology Denmark ApS Regus Business Centre Lautrup 1 3 Ballerup 2750 Denmark Tel 45 4420 9895 Fax 45 4420 9910 France Arizona Microchip Technology SARL Parc d Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A ler Etage 91300 Massy France Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav Heinemann Ring 125 D 81739 M nchen Germany Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V Le Colleoni 1 20041 Agrate Brianza Milan Italy Tel 39 039 65791 1 Fax 39 039 6899883 11 15 99 Microchip received QS 9000 quality system certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona in July 1999 The Company s quality system processes and procedures are QS 9000 compliant for its 8 bit MCUs KEELO code hopping devices Serial EEPROMs microperipheral products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 certified Printed on recycled paper Information contained in this publicatio
223. ements on every falling edge of the RB5 TCLK3 pin In either mode the TMR3ON bit must be set for the timer to increment When TMR3ON is clear the timer will not increment or set the TMRGIF bit Timer3 has two modes of operation depending on the CA1 PR3 bit TCON2 lt 3 gt These modes One capture and one period register mode Dual capture register mode The PIC17C4X has up to two 16 bit capture registers that capture the 16 bit value of TMR3 when events are detected on capture pins There are two capture pins RBO CAP1 and RB1 CAP2 one for each capture reg ister The capture pins are multiplexed with PORTB pins An event can be arising edge afalling edge every 4th rising edge every 16th rising edge Each 16 bit capture register has an interrupt flag asso ciated with it The flag is set when a capture is made The capture module is truly part of the Timer3 block Figure 12 7 and Figure 12 8 show the block diagrams for the two modes of operation TABLE 12 4 REGISTERS BITS ASSOCIATED WITH PWM Value on Value on all ddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Power on Reset Note1 16h Bank 3 TCON1 CA2ED1 CA2EDO 1 CA1EDO T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 17h Bank 3 TCON2 PWM2ON PWM1ON CA1 PR3 TMR3ON
224. er Up Timer Requirements 186 Table 19 5 TimerO Clock Requirements 187 Table 19 6 Timer1 Timer2 and Timer3 Clock Requirements 187 Table 19 7 Capture 188 Table 19 8 PWM Requirements 188 Table 19 9 Synchronous Transmission Requirements 189 Table 19 10 Synchronous Receive Requirements 189 Table 19 11 Memory Interface Write Requirements Not Supported in PIC17LC4X Devices 190 Table 19 12 Memory Interface read Requirements Not Supported in PIC17LC4X Devices 191 Table 20 1 Pin Capacitance per Package 193 Table 20 2 Oscillator Frequencies 195 Table E 1 Pin Compatible Devices 221 LIST OF EQUATIONS Equation 8 1 16 x 16 Unsigned Multiplication Algorithm sese 50 Equation 8 2 16 x 16 Signed Multiplication Algorithm eene 51 DS30412C page 234 1996 Microchip Technology Inc PIC17C4X ON LINE SUPPORT Microchip provides two methods of on line support These are the Microchip BBS and the Microchip World Wide Web WWW site Use Microchip s Bulletin Board Service BBS to get current information and help about Microchip products Microchip provides the BBS communication channel for you to use in extending your t
225. erminate the long write 5 Verify the memory location table read 7 1 1 TERMINATING LONG WRITES An interrupt source or reset are the only events that terminate a long write operation Terminating the long write from an interrupt source requires that the inter rupt enable and flag bits are set The GLINTD bit only enables the vectoring to the interrupt address If the TOCKI RAO INT or TMRO interrupt source is used to terminate the long write the interrupt flag of the highest priority enabled interrupt will terminate the long write and automatically be cleared Note 1 If an interrupt is pending the TABLWT is aborted an NOP is executed The highest priority pending interrupt from the TOCKI RAO INT or TMRO sources that is enabled has its flag cleared Note 2 l the interrupt is not being used for the program write timing the interrupt should be disabled This will ensure that the interrupt is not lost nor will it termi nate the long write prematurely If a peripheral interrupt source is used to terminate the Note Programming requirements must be met ape d flag bi b See timing specification in electrical spec long write the interrupt enable an ag Its must be ifications for the desired device Violating set The interrupt flag will not be automatically cleared these specifications including tempera upon the vectoring to the interrupt vector address ture may result in EPROM locations
226. ers Re WREG RES3 RESO MULWE ARG2L ARGIL ARG2L gt PRODH PRODL MOVPF PRODH RESI EQUATION 8 1 16 x 16 UNSIGNED MOVPF PRODL RESO MULTIPLICATION ALGORITHM 1 MULWE ARG2H 1 ARG2H gt RES3 RESO ARGI1H ARG1L ARG2H ARG2L PRODH PRODL 516 PRODH RES3 ARGIH ARG2H 27 MOVPF PRODL RES2 ARG1H ARG2L 28 E 11 WREG ARGIL ARG2H 27 MULWE ARG2H ARG1L ARG2H gt ARG1L ARG2L PRODH PRODL PRODL WREG ADDWF 51 Add cross MOVFP PRODH WREG products ADDWFC 52 WREG ADDWFC 53 ARG1H WREG MULWE ARG2L 1 ARG2L gt PRODH PRODL MOVFP RODL WREG ADDWE 51 Add cross MOVFP PRODH WREG products ADDWFC RES2 F CLRF WREG F ADDWFC RES3 F DS30412C page 50 1996 Microchip Technology Inc PIC17C4X Example 8 4 shows the sequence to do an 16 x 16 EXAMPLE 8 4 16x 16 SIGNED MULTIPLY signed multiply Equation 8 2 shows the algorithm that ROUTINE used The 32 bit result is stored in four registers MOVEP WREG RES3 RESO To account for the sign bits of the argu MULWF ARG2L ARG1L ARG2L gt ments each argument pairs most significant bit MSb PRODH PRODL is tested and the appropriate subtractions are done MOVPF PRODH RESI MOVPF PRODL RESO EQUATION 8 2 16 x 16 SIG
227. g the TXSTA lt 7 gt bit 13 3 1 USART SYNCHRONOUS MASTER TRANSMISSION The USART transmitter block diagram is shown in Figure 13 3 The heart of the transmitter is the transmit serial shift register TSR The shift register obtains its data from the read write transmit buffer TXREG TXREG is loaded with data in software The TSR is not loaded until the last bit has been transmitted from the previous load As soon as the last bit is transmitted the TSR is loaded with new data from TXREG if available Once TXREG transfers the data to the TSR occurs in one Tcv at the end of the current BRG cycle TXREG is empty and the TXIF PIR lt 1 gt bit is set This interrupt can be enabled disabled by setting clearing the TXIE bit PIE lt 1 gt will be set regardless of the state of bit TXIE and cannot be cleared in software It will reset only when new data is loaded into TXREG While TXIF indicates the status of TXREG TRMT TXSTA lt 1 gt shows the status of the TSR TRMT is a read only bit which is set when the TSR is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR is empty The TSR is not mapped in data memory so it is not available to the user Transmission is enabled by setting the TXEN TXSTA lt 5 gt bit The actual transmission will not occur until TXREG has been loaded with data The first data bit will be shifted out on the next available rising edge
228. ged in plastic packages per mit the user to program them once In addition to the program memory the configuration bits must also be programmed 2 3 Quick Turnaround Production QTP Devices Microchip offers a QTP Programming Service for fac tory production orders This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi lized The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory Certain code and prototype verification procedures apply before produc tion shipments are available Please contact your local Microchip Technology sales office for more details 2 4 Serialized Quick Turnaround Production SQTP Devices Microchip offers a unique programming service where a few user defined locations in each device are pro grammed with different serial numbers The serial num bers may be random pseudo random or sequential Serial programming allows each device to have a unique number which can serve as an entry code password or ID number ROM devices do not allow serialization information in the program memory space For information on submitting ROM code please con tact your regional sales office 2 5 Read Only Memory ROM Devices Microchip offers masked ROM versions of several of the highest volume parts thus giving customers a low cost option for high vo
229. gend TTL input TABLE 9 6 REGISTERS BITS ASSOCIATED WITH PORTC Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 11h Bank 1 PORTC AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO XXXX XXXX uuuu uuuu 10h Bank 1 DDRC Data direction register for PORTC 1111 1111 1111 1111 Legend x unknown u unchanged Note 1 Other non power up resets include external reset through MCLR and the Watchdog Timer Reset 1996 Microchip Technology Inc DS30412C page 59 PIC17C4X 9 4 PORTD and DDRD Registers PORTD is an 8 bit bi directional port The correspond ing data direction register is DDRD A 1 in con figures the corresponding port pin as an input A 0 in the DDRC register configures the corresponding port pin as an output Reading PORTD reads the status of the pins whereas writing to it will write to the port latch PORTD is multiplexed with the system bus When operating as the system bus PORTD is the high order byte of the address data bus AD15 AD8 The timing for the system bus is shown in the Electrical Character istics section Note This port is configured as the system bus when the device s configuration bits are selected to Microprocessor or Extended Microcontroller modes In the two other microcontroller modes this port is a gen eral purpose
230. general purpose arithmetic unit It performs arithmetic and Boolean functions between data in the working register and any register file The ALU is 8 bits wide and capable of addition sub traction shift and logical operations Unless otherwise mentioned arithmetic operations are two s comple ment in nature The WREG register is an 8 bit working register used for ALU operations All PIC17C4X devices except the PIC17C42 have an 8x8 hardware multiplier This multiplier generates a 16 bit result in a single cycle Depending on the instruction executed the ALU may affect the values of the Carry C Digit Carry DC and Zero Z bits in the STATUS register The C and DC bits operate as a borrow and digit borrow out bit respec tively in subtraction See the SUBLW and SUBWF instructions for examples Although the ALU does not perform signed arithmetic the Overflow bit OV can be used to implement signed math Signed arithmetic is comprised of a magnitude and a sign bit The overflow bit indicates if the magni tude overflows and causes the sign bit to change state Signed math can have greater than 7 bit values mag nitude if more than one byte is used The use of the overflow bit only operates on bit6 MSb of magnitude and bit7 sign bit of the value in the ALU That is the overflow bit is not useful if trying to implement signed math where the magnitude for example is 11 bits If the signed math values are greater tha
231. h PORTA does not have a corresponding Data Direction Register DDR Reading PORTA reads the status of the pins The pin is multiplexed with TMRO clock input and RA4 and RAS are multiplexed with the USART func tions The control of RA4 and RAS as outputs is auto matically configured by the USART module 9 1 1 USING RA2 RA3 AS OUTPUTS The and pins are open drain outputs To use the RA2 or the RAS pin s as output s simply write to the PORTA register the desired value A will cause the pin to drive low while a 1 will cause the pin to float hi impedance An external pull up resistor should be used to pull the pin high Writes to PORTA will not affect the other pins Note When using the or pin s as out put s read modify write instructions such as BCF BSF BTG on PORTA are not rec ommended Such operations read the port pins do the desired operation and then write this value to the data latch This may inadvertently cause the RA2 or pins to switch from input to output or vice versa It is recommended to use a shadow regis ter for PORTA Do the bit operations on this shadow register and then move it to PORTA FIGURE 9 1 AND BLOCK DIAGRAM DATA BUS RD PORTA Q2 Note I O pins have protection diodes to VDD and Vss 1996 Microchip Technology Inc DS30412C page 53 PIC17C4X FIGURE 9 2
232. h impedance to 0 ns ToeH2adD to AD lt 15 0 gt driven 0 25 15 ns TadV2oeH Data in valid before OET 35 ns data setup time 163 ToeH2adl data in invalid data hold time 0 ns 164 ALE pulse width 0 25Tcv 8 ns 165 ToeL OE pulse width 0 5 35 ns 166 TalH2alH to cycle time Tcv 8 ns 167 Tacc Address access time 0 75 Tcv 40 ns 168 Toe Output enable access time 0 5 Tcv 60 ns OE low to Data Valid These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested This specification guaranteed by design 530412 162 1996 Microchip Technology Inc PIC17CAX Applicable Devices 42 R42 42A 43 R43 44 18 0 PIC17C42 DC AND AC CHARACTERISTICS The graphs and tables provided in this section are for design guidance and are not tested or guaranteed In some graphs or tables the data presented are outside specified operating range e g outside specified VoD range This is for infor mation only and devices are ensured to operate properly only within the specified range The data presented in this section is a statistical summary of data collected on units from different lots over a period of time
233. he RB5 TCLK3 pin Figure 12 1 and Figure 12 2 are the control registers for the operation of Timer1 Timer2 and Timer3 as well as PWM1 PWMe Capture1 and Capture2 FIGURE 12 1 TCON1 REGISTER ADDRESS 16h BANK 3 R W 0 R W 0 R W 0 R W 0 R W 0 HR W 0 R W 0 RW O CA2ED1 CA2EDO CA1ED1 CAT1EDO T16 TMR3CS TMR2CS TMR1CS Readable bit bit7 bitO W Writable bit n Value at POR reset bit 7 6 CA2ED1 CA2EDO Capture2 Mode Select bits 00 Capture on every falling edge 01 Capture on every rising edge 10 Capture on every 4th rising edge 11 Capture on every 16th rising edge bit 5 4 CA1ED1 CA1EDO Capture1 Mode Select bits 00 Capture on every falling edge 01 Capture on every rising edge 10 Capture on every 4th rising edge 11 Capture on every 16th rising edge bit3 6 2 Mode Select bit 1 Timer1 and Timer2 form a 16 bit timer 0 Timer1 and Timer2 are two 8 bit timers bit2 TMR3CS Timer3 Clock Source Select bit 1 TMR3 increments off the falling edge of the RB5 TCLK3 pin 0 2 TMR3 increments off the internal clock bit1 TMR2CS Timer2 Clock Source Select bit 1 TMR2 increments off the falling edge of the RB4 TCLK12 pin 0 TMR2 increments off the internal clock bitO TMR1CS Timeri Clock Source Select bit 1 TMR1 increments off the falling edge of the RB4 TCLK12 pin 0 TMR1 increments off the internal clock 1996 Microchip Techn
234. he current through the external pull up resistor can be estimated as 2 R For capacitive loads The current can be estimated for an individual I O pin as CL VDD e f CL Total capacitive load on the I O pin f 2 average frequency on the pin switches The capacitive currents are most significant when the device is configured for external execution includes extended microcontroller mode The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the in SLEEP mode all I O pins hi impedance state and tied VoD or Vss For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula IR VDD 2Rext mA with in kOhm 1996 Microchip Technology Inc DS30412C page 149 PIC17C4X Applicable Devices 42 R42 42 43 43 44 17 2 DC CHARACTERISTICS PIC17C42 16 Commercial Industrial PIC17C42 25 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature DC CHARACTERISTICS 40 C lt TA lt 85 for industrial and OC lt lt 70 for commercial Operating voltage VDD range as described in Section 17 1 Parameter No Characteristic Min Max Units Conditions Input Low Voltage ports with TTL buffer Vss 0 8 V with Schmitt Trigger
235. hese parameters are for design guidance only and are not tested These parameters are for design guidance only and are tested nor characterized Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC17CXX devices be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 These specifications are for the programming of the on chip program memory EPROM through the use of the table write instructions The complete programming specifications can be found in PIC17CXX Programming Specifications Literature number DS30139 5 The MCLR VPP pin may be kept in this range at times other than programming but is not recommended 6 For TTL buffers the better of the two specifications may be used DS30412C page 180 1996 Technology Inc PIC17C4X Applicable Devices 42 42 42 43 R43 44 DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt lt 40 Operating voltage VDD range as described in Section 19 1 Parameter No Sym Characteristic Min Typt Max Unit Conditions Inte
236. ide the timing desig nation for the Decode Read Execute Write etc of 02 Instruction Read Cycle or NOP each instruction cycle The following diagram shows Q3 Instruction Execute the relationship of the Q cycles to the instruction cycle Q1 Instruction Decode Cycle or forced NOP Q4 Instruction Write Cycle or NOP Each instruction will show the detailed Q cycle opera tion for the instruction FIGURE 15 2 Q CYCLE ACTIVITY Q1 02 03 04 01 02 03 04 01 02 Q3 04 Tcy2 1996 Microchip Technology Inc DS30412C page 109 PIC17CAX TABLE 15 2 PIC17CXX INSTRUCTION SET Mnemonic Description Cycles 16 bit Opcode Status Notes Operands MSb LSb Affected BYTE ORIENTED FILE REGISTER OPERATIONS ADD WREG to f OV C DC Z ADD WREG and Carry bit to f OV C DC Z AND WREG with f Clear f or Clear f and Clear WREG Complement f Compare f with WREG skip if f WREG Compare f with WREG skip if f gt WREG Compare f with WREG skip if f lt WREG Decimal Adjust WREG Register Decrement f OV C DC Z Decrement f skip if 0 None Decrement f skip if not 0 None Increment f OV C DC Z Increment f skip if 0 None Increment f skip if not 0 None Inclusive OR WREG with f Move f to p Move p to f Move WREG to f None Multiply WREG with f None Negate WREG OV
237. interrupt internal phase clocks twice every instruction cycle This causes a delay from the time a falling edge appears on EXAMPLE 12 3 READING FROM TMR3 to the time is actually incremented For the external clock input timing requirements see the MOVER d THEO sgread Tow ban Electrical Specification section Figure 12 9 shows the MOVER HA TMEHT peed nig tmr timing diagram when operating from an external clock E i eee Kemp TO Ta Wreg g g p g CPFSLT TMR3L WREG tmr01 lt wreg 12 2 4 READING WRITING TIMER3 RETURN return TMR3L TMPLO read low Since Timer3 is a 16 bit timer and only 8 bits at a time MOVER QMBOH CIMEHA gread high cen RETURN return can be read or written care should be taken when reading or writing while the timer is running The best method to read or write the timer is to stop the timer per orm any read or write operation and then restart Timer3 using the bit However if it is neces sary to keep Timer3 free running care must be taken For writing to the 16 bit Example 12 2 be used For reading the 16 bit TMR3 Example 12 3 may be used Interrupts must be disabled during this rou tine FIGURE 12 9 TMR1 TMR2 TMR3 OPERATION IN EXTERNAL CLOCK MODE io1 o2 oa oa o1 oa oa oa 1020304 2 0304102 03042102103104 TCLK12 TMR1 TMR2 TMR3 PR1 PR2 or PR3H PR3L WR TMR
238. interrupt will be generated when enabled In counter mode the clock comes from the RB5 TCLK3 pin When operating in the dual capture mode the period registers become the second 16 bit capture register 10 5 Role of the Timer Counters The timer modules are general purpose but have ded icated resources associated with them and Timer2 are the time bases for the two Pulse Width Modulation PWM outputs while Timer3 is the time base for the two input captures 1996 Microchip Technology Inc DS30412C page 65 PIC17C4X NOTES IRIS 395 104 Mi DS30412C page 66 1996 Technology Inc PIC17C4X 11 0 TIMERO The TimerO module consists of a 16 bit timer counter TMRO The high byte is TMROH and the low byte is TMROL A software programmable 8 bit prescaler makes an effective 24 bit overflow timer The clock source is also software programmable as either the internal instruction clock or the RA1 TOCKI pin The control bits for this module are in register TOSTA Figure 11 1 FIGURE 11 1 TOSTA REGISTER ADDRESS 05h UNBANKED RW 0 R W 0 RW 0 R W 0 0 0 RW O U 0 INTEDG TOSE TOCS PS3 PS2 PS1 PSO R Readable bit bit7 bit0 W Writable bit U Unimplemented Read as 0 Value at POR reset bit 7 INTEDG RAO INT Pin Interrupt Edge Select bit This bit selects the edge upon which the interrupt
239. ion of the operation of the INTSTA register Added note to discussion of interrupt operation Tightened electrical spec D1 10 Corrected steps for setting up USART Asynchronous Reception DS30412C page 212 1996 Microchip Technology Inc PIC17C4X PIC16 17 MICROCONTROLLERS PIC14000 Devices APPENDIX E E 1 2 Suoyesedwoy 1 9315 Mv 02 00071014 10 924 uoneJqieo josueg eunjejeduje 012 1060 1 008 4055 0105 did uid gz SeJnjee DS30412C page 213 1996 Microchip Technology Inc PIC17C4X PIC16C5X Family of Devices E 2 dOSS uid 02 2105 did upiqedeo Juano uBiu pue 4284019 epoo L 9 LOId 9 dOSS uld 02 O1OS did 9 1 4055 2105 did uid 8z 8999191 929999191 4088 105 did uid 8z 28291014 dOSS uid 02 2105 did 9 1 4055 105 uid 8z 95291014 68291014 dOSS uid 02 2105 did uid 8 VvrSHO9LOld dOSS uid 02 2105 did 9 1 4055 2105 did uid 8L VvSO9LOld 929121 4 9105 did uid 8 soJneoJ 04291014
240. ismatch outputs of RB7 RBO are OR ed together to generate the PORTB Interrupt RBIF PIR lt 7 gt This interrupt can wake the device from SLEEP The user in the interrupt service routine can clear the inter rupt by a Read Write PORTB such as MOVPF PORTB PORTB This will end mismatch condition b Then clear the RBIF bit A mismatch condition will continue to set the RBIF bit Reading then writing PORTB will end the mismatch condition and allow the RBIF bit to be cleared This interrupt on mismatch feature together with soft ware configurable pull ups on this port allows easy interface to a key pad and make it possible for wake up on key depression For an example refer to AN552 in the Embedded Control Handbook The interrupt on change feature is recommended for wake up on operations where PORTB is only used for the interrupt on change feature and key depression operation FIGURE 9 4 BLOCK DIAGRAM OF RB lt 7 4 gt AND RB lt 1 0 gt PORT PINS Peripheral Data in RBPU lt 7 gt Match Signal from other port pins Port Input Latch Data Bus RD_DDRB Q2 1 02 WR DDRB 04 Note pins have protection diodes to and Vss WR PORTB 04 1996 Microchip Technology Inc DS30412C page 55
241. ive buffer is full 0 Receive buffer is empty DS30412C page 24 1996 Technology Inc PIC17C4X 5 4 Interrupt Operation Global Interrupt Disable bit GLINTD CPUSTA 4 enables all unmasked interrupts if clear or disables all interrupts if set Individual interrupts can be disabled through their corresponding enable bits in the INTSTA register Peripheral interrupts need either the global peripheral enable PEIE bit disabled or the specific peripheral enable bit disabled Disabling the peripher als via the global peripheral enable bit disables all peripheral interrupts GLINTD is set on reset interrupts disabled The RETF IE instruction allows returning from interrupt and re enable interrupts at the same time When an interrupt is responded to the GLINTD bit is automatically set to disable any further interrupt the return address is pushed onto the stack and the PC is loaded with interrupt vector There are four interrupt vectors to reduce interrupt latency The peripheral interrupt vector has multiple interrupt sources Once in the peripheral interrupt service rou tine the source s of the interrupt can be determined by polling the interrupt flag bits The peripheral interrupt flag bit s must be cleared in software before re enabling interrupts to avoid continuous interrupts The PIC17C4X devices have four interrupt vectors These vectors and their hardware priority are shown in
242. ize PORTC The Bank Select Register BSR must be selected to Bank 1 for the port to be initialized EXAMPLE 9 2 INITIALIZING PORTC MOVLB 1 Select Bank 1 PORTC Initialize PORTC data latches before setting H the data direction register MOVLW OxCF Value used to initialize data direction MOVWF DDRC Set RC lt 3 0 gt as inputs 2 RC lt 5 4 gt outputs 2 RC 7 6 as inputs FIGURE 9 6 BLOCK DIAGRAM OF RC lt 7 0 gt PORT PINS to D Bus IR INSTRUCTION READ Data Bus Input RD PORTC WR PORTC RD DDRC WR DDRC EX EN DATA ADDR OUT SYS BUS SYS Control Note I O pins have protection diodes to VDD and Vss DS30412C page 58 1996 Microchip Technology Inc PIC17C4X TABLE 9 5 PORTC FUNCTIONS Name Bit Buffer Type Function RCO ADO bitO TTL Input Output or system bus address data pin RC1 AD1 bit1 TTL Input Output or system bus address data pin RC2 AD2 bit2 TTL Input Output or system bus address data pin RC3 AD3 bit3 TTL Input Output or system bus address data pin RC4 AD4 bit4 TTL Input Output or system bus address data pin RC5 AD5 bit5 TTL Input Output or system bus address data pin RC6 AD6 bit6 TTL Input Output or system bus address data pin RC7 AD7 bit7 TTL Input Output or system bus address data pin Le
243. kkkk Description Subroutine call within 8K page First return address PC 1 is pushed onto the stack The 13 bit value is loaded into PC bits lt 12 0 gt Then the upper eight bits of the PC are copied into PCLATH Call is a two cycle instruction See LCALL for calls outside 8K memory space Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Execute NOP lt 7 0 gt Execute NOP Example HERE CALL THERE Before Instruction PC Address HERE After Instruction PC TOS Address THERE Address HERE 1 CLRF Clear f Syntax 1 5 Operands 0 lt lt 255 Operation 00h f se 0 1 00h gt dest Status Affected None Encoding 0010 100s ffff ffff Description Clears the contents of the specified reg ister s s 0 Data memory location and WREG are cleared 5 1 Data memory location f is cleared Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register f and other specified register Example CLRF FLAG REG Before Instruction FLAG REG 0x5A After Instruction FLAG REG 0x00 1996 Microchip Technology Inc DS30412C page 117 PIC17C4X CLRWDT Clear Watchdog Timer Syntax label CLRWDT Operands None Operation 00h 0 WDT postscaler 1oTO 1 gt PD Status Affected TO PD Encoding 0000 0000 0000 0100
244. le bit U Unimplemented Value for Erased Device x unknown Note 1 This bit does not exist on the PIC17C42 Reading this bit will return an unknown value x 1996 Microchip Technology Inc DS30412C page 99 PIC17CAX 14 1 Configuration Bits The PIC17CXX has up to seven configuration locations Table 14 1 These locations can be programmed read as 07 or left unprogrammed read as 1 to select various device configurations Any write to a configura tion location regardless of the data will program that configuration bit A TABLWT instruction is required to write to program memory locations The configuration bits can be read by using the TABLRD instructions Reading any configuration location between FEOOh and FEO7h will read the low byte of the configuration word Figure 14 1 into the TABLATL register The TAB LATH register will be FFh Reading a configuration location between FEO8h and FEOFh will read the high byte of the configuration word into the TABLATL regis ter The TABLATH register will be FFh Addresses FEOOh thorough FEOFh are only in the pro gram memory space for microcontroller and code pro tected microcontroller modes A device programmer will be able to read the configuration word in any pro cessor mode See programming specifications for more detail TABLE 14 1 CONFIGURATION LOCATIONS Bit Address FOSCO FOSC1 WDTPSO FEO2h
245. led or disabled by the TXIE bit PIE lt 1 gt TXIF will be set regardless of TXIE and cannot be reset in software It will reset only when new data is loaded into TXREG While TXIF indicates the status of the TXREG the TRMT TXSTA 1 bit shows the status of the TSR TRMT is a read only bit which is set when the TSR is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR is empty Note is not mapped in data memory 50 it is not available to the user Transmission is enabled by setting the TXEN TXSTA lt 5 gt bit The actual transmission will not occur until TXREG has been loaded with data and the baud rate generator BRG has produced a shift clock Figure 13 5 The transmission can also be started by first loading TXREG and then setting TXEN Normally when transmission is first started the TSR is empty so a transfer to TXREG will result in an immediate transfer to TSR resulting in an empty TXREG A back to back transfer is thus possible Figure 13 6 Clearing TXEN during a transmission will cause the transmission to be aborted This will reset the transmitter and the RA5 TX CK pin will revert to hi impedance In order to select 9 bit transmission the TX9 TXSTA lt 6 gt bit should be set and the ninth bit should be written to TX9D 5 lt 0 gt The ninth bit must be written before writing the 8 bit data to the TXREG This is because a data w
246. lize the SPBRG register for the appropriate ing reception baud rate 8 Read RCREG for the 8 bit received data 2 Enable the asynchronous serial port by clearing 9 f an overrun error occurred clear the error by the SYNC bit and setting the SPEN bit clearing the OERR bit 3 If interrupts are desired then set the RCIE bit Note To terminate a reception either clear the 4 f9 bit reception is desired then set the RX9 bit SREN and CREN bits or the SPEN bit 5 Enable the reception by setting the CREN bit This will reset the receive logic so that it 6 The RCIF bit will be set when reception com ROBE PSE ene recens pletes and an interrupt will be generated if the RCIE bit was set FIGURE 13 8 ASYNCHRONOUS RECEPTION RX Start Start Start pin bit bito Y GS Stop bit SS bit 55 Stop I Rcv shift Rcv buffer 189 55 SS Word 3 Read Rev 44 55 55 55 RCREG RCIF interrupt flag SS OERR bit SS SS SS CREN 5 Note This timing diagram shows three words appearing on the input The RCREG receive buffer is read after the third word causing the OERR overrun bit to be set TABLE 13 6 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on all Address Name Bit 7 Bit 6 Bit 5
247. low time 25 m ns i These parameters characterized but not tested T Data in column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested These parameters for design guidance only and are tested nor characterized Note 1 Measurements are taken in EC Mode where CLKOUT output is 4 x Tosc 1996 Microchip Technology Inc DS30412C page 185 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 FIGURE 19 4 RESET WATCHDOG TIMER OSCILLATOR START UP AND POWER UP TIMER TIMING VDD MCLR Internal POR PWRT Timeout OSC Timeout Internal RESET Watchdog Timer RESET Address Data TABLE 19 4 RESET WATCHDOG TIMER OSCILLATOR START UP AND POWER UP TIMER REQUIREMENTS Parameter No Sym Characteristic Min Typt Max Units Conditions 30 TmcL MCLR Pulse Width low 100 ns VDD 5V 31 Twdt Watchdog Timer Time out Period 5 12 25 ms VDD 5V Prescale 1 32 Tost Oscillation Start up Timer Period 1024Tosc ms OSC1 period 33 Tpwrt Power up Timer Period 40 96 200 ms VDD 5V 35 TmcL2adl MCLR to System Inter PIC17CR42 42A 100 ns face bus AD15 AD0 gt 43 R43 44 invalid PIC17LCR42 120 ns 42A 43 R43 44 amp These pa
248. lse width modulation PWM outputs Duty Cycle registers peo PWxDCL lt 7 6 gt are provided The PWM1 output uses Timer1 as its PWxDCH Write time base while PWM2 may be software configured to use either Timer2 as the time base The SI iM outputs are on the RB2 PWM1 and RB3 PWM2 Slave RCy PWMx Comparator Each PWM output has a maximum resolution of ZN 10 bits At 10 bit resolution the PWM output frequency TMR2 Note 1 is 24 4 kHz 25 MHz clock and at 8 bit resolution the EIN uM PWMxON PWM output frequency is 97 7 kHz The duty cycle of Comparator lear Ti the output can vary from 0 to 100 43 pin and Latch D C Figure 12 5 shows a simplified block diagram of the PWM module The duty cycle register is double buff Note 1 8 bit timer is concatenated with 2 bit internal Q clock ered for glitch free operation Figure 12 6 shows how a or 2 bits of the prescaler to create 10 bit time base glitch could occur if the duty cycle registers were not double buffered The user needs to set the PWM1ON bit TCON2 lt 4 gt to enable the PWM1 output When the bit is set the RB2 PWM pin is configured as PWM1 output and forced as an output irrespective of the data direc tion bit DDRB lt 2 gt When the PWMION bit is clear the pin behaves as a port pin and its direction is con trolled by its data direction bit DDRB lt 2 gt Similarly the PWM2O
249. lume mature products For information on submitting ROM code please con tact your regional sales office 1996 Microchip Technology Inc DS30412C page 7 PIC17C4X NOTES E E OMM DS30412C page 8 1996 Microchip Technology Inc PIC17C4X 3 0 ARCHITECTURAL OVERVIEW The high performance of the PIC17C4X can be attrib uted to a number of architectural features found in RISC microprocessors To begin with the PIC17C4X uses a modified Harvard architecture This architecture has the program and data accessed from separate memories So the device has a program memory bus and a data memory bus This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory accesses over the same bus Separating program and data memory further allows instructions to be sized differently than the 8 bit wide data word PIC17C4X opcodes are 16 bits wide enabling single word instructions The full 16 bit wide program memory bus fetches a 16 bit instruction in a single cycle A two stage pipeline overlaps fetch and execution of instruc tions Consequently all instructions execute in a single cycle 121 ns 33 MHz except for program branches and two special instructions that transfer data between program and data memory The can address up to 64K x 16 of program memory space The PIC17C42 and PIC17C42A integrate 2K
250. n 00h gt WDT 0 gt postscaler 1o 0 PD Status Affected TO PD Encoding 0000 0000 0000 0011 Description The power down status bit PD is cleared The time out status bit TO is set Watchdog Timer and its prescaler are cleared The processor is put into SLEEP mode with the oscillator stopped Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register PCLATH Example SLEEP Before Instruction PD 2 After Instruction TO 11 PD 0 T IfWDT causes wake up this bit is cleared SUBLW Subtract WREG from Literal Syntax abel SUBLW k Operands lt lt 255 Operation k WREG WREG Status Affected OV C DC 2 Encoding 1011 0010 kkkk kkkk Description WREG is subtracted from the eight bit literal k The result is placed in WREG Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to literal k WREG Example 1 SUBLW 0x02 Before Instruction WREG 1 G 2 After Instruction WREG 1 C result is positive 2 0 2 Before Instruction WREG 2 C 7 After Instruction WREG 0 C 1 result is zero Z 1 3 Before Instruction WREG 3 C 7 After Instruction WREG FF 2scomplement C 0 resultis negative 2 1 1996 Microchip Technology Inc DS30412C page 135 PIC17C4X SUBWF Subtract WREG
251. n 7 bits 15 24 or 31 bit the algorithm must ensure that the low order bytes ignore the overflow status bit Care should be taken when adding and subtracting signed numbers to ensure that the correct operation is executed Example 3 1 shows an item that must be taken into account when doing signed arithmetic on an ALU which operates as an unsigned machine EXAMPLE 3 1 SIGNED MATH Hex Value Signed Value Unsigned Value Math Math FFh 127 255 014 1 1 7 126 FEh 0 00h Carry bit 1 Signed math requires the result in REG to be FEh 126 This would be accomplished by subtracting one as opposed to adding one Simplified block diagrams are shown in Figure 3 1 and Figure 3 2 The descriptions of the device pins are listed in Table 3 1 1996 Microchip Technology Inc DS30412C page 9 PIC17C4X PIC17C42 BLOCK DIAGRAM 1 FIGURE 3 199135 1531 HANIL dALYVLS 050 18584 NO HOIVH3N39 39019 TORINO L gt ANY 18588 Te 0 2010 OL S IVNOIS 1061409 91 1 pue D1HOd lt 0 91 gt 39v4 WALSAS HO1V1 IOu WOHd3 9LX c lt 91 gt 41d AYOWAW 1 1
252. n from subroutine The stack is popped and the top of the stack TOS is loaded into the program counter Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register PCL Forced NOP NOP Execute NOP Remember reading PCL causes PCLATH to be updated This will be the high address of where the RETURN instruc tion is located Example RETURN After Interrupt PC TOS RLCF Rotate Left f through Carry Syntax abel RLCF fd Operands lt lt 255 d e 0 1 Operation fen gt d lt n 1 gt f lt 7 gt 2 d lt 0 gt Status Affected C Encoding 0001 101d ffff ffff Description The contents of register are rotated one bit to the left through the Carry Flag If d is 0 the result is placed in WREG If d is 1 the result is stored back in register f Cr register f Words 1 Cycles 1 Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example RLCF REG 0 Before Instruction REG 1110 0110 0 After Instruction REG 1110 0110 WREG 1100 1100 1 DS30412C page 132 1996 Microchip Technology Inc PIC17C4X RLNCF Rotate Left f no carry Syntax label RLNCF fd Operands 0 lt f lt 255 de 0 1 Operation fen gt d lt n 1 gt f lt 7 gt d lt 0 gt Status Affected None Encoding 0010 0019 ffff Description Th
253. n into Gen Stack Level 1 eral Purpose RAM and the Special Function Registers SFRs The operation of the SFRs that control the Stack Level 16 core are described here The SFRs used to control the peripheral modules are described in the section dis Reset Vector cussing each individual peripheral module INT Pin Interrupt Vector 6 1 Program Memory Organization Timer Interrupt Vector PIC17C4X devices have a 16 bit program counter Pin Interrupt Vector capable of addressing a 64K x 16 program memory Peripheral Interrupt Vector space The reset vector is at 0000h and the interrupt vectors are at 0008h 0010h 0018h and 0020h Figure 6 1 FFh PIC17C42 PIC17CR42 17 42 FFFh PIC17C43 PIC17CR43 6 1 1 PROGRAM MEMORY OPERATION The PIC17C4X can operate in one of four possible pro gram memory configurations The configuration is selected by two configuration bits The possible modes are User Memory Space 9 Microprocessor Microcontroller Extended Microcontroller 1FFFh Protected Microcontroller PIC17C44 The microcontroller and protected microcontroller modes only allow internal execution Any access beyond the program memory reads unknown data The protected microcontroller mode also enables the code protection feature FOSCO FOSC1 WDTPSO WDTPS1 PMO Reserved PM1 Reserved The extended microcontroller mode accesses both the internal progr
254. n regarding device applications and the like is intended for suggestion only and may be superseded by updates No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information or infringement of patents or other intellectual property rights arising from such use or otherwise Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed implicitly or otherwise under any intellectual property rights The Microchip logo and name are registered trademarks of Microchip Technology Inc in the U S A and other countries All rights reserved All other trademarks mentioned herein are the property of their respective companies 1999 Microchip Technology Inc
255. nc PIC17CAX Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20 11 TYPICAL IPD vs VoD WATCHDOG ENABLED 25 C 5 Les FIGURE 20 12 MAXIMUM IPD vs VoD WATCHDOG ENABLED 5 5 Volts Volts 1996 Microchip Technology Inc DS30412C page 199 PIC17CAX Applicable Devices 42 42 42A 43 43 44 FIGURE 20 13 WDT TIMER TIME OUT PERIOD vs VDD WDT Period ms Volts Volts Jede rie D lt lt lt lt lt lt EO LLLLOL LLLILLOLELLULLLLLOCLLEE ELOOLOOL EHLUO AGG COLLO EFLLOUQLLLELEL O LC OSCOXILSE DS30412C page 200 1996 Technology Inc PIC17C4X Applicable Devices 42 42 42 43 R43 44 FIGURE 20 15 loH vs VDD 5V 2 0 2 5 3 0 3 5 4 0 4 5 5 0 Volts FIGURE 20 16 101 vs VoL Max 40 C Min 85 C VDD Volts 1996 Microchip Technology Inc DS30412C page 201 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 FIGURE 20 17 vs VoL VDD 5V
256. ndustrial DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 lt lt 85 for industrial and 0 lt TA 70 commercial Parameter No Sym Characteristic Min Typf Max Units Conditions D001 Supply Voltage 2 5 6 0 V D002 VDR RAM Data Retention 1 5 V Device in SLEEP mode Voltage Note 1 D003 VPOR start voltage to Vss V See section on Power on Reset for ensure internal details Power on Reset signal D004 SvDD VDD rise rate to 0 060 mV ms See section on Power on Reset for ensure internal details Power on Reset signal D010 IDD Supply Current 3 6 mA Fosc 4 MHz Note 4 0011 Note 2 6 12 mA Fosc 8 MHz 0014 95 150 uA 32 kHz disabled EC configuration D020 IPD Power down B 10 40 uA VDD 5 5V enabled 0021 Current Note 3 lt 1 5 HA 5 5 disabled These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data The supply current is mainly a function of the operating voltage and frequency Other factors such as I O pin loading and switching rate oscillator type internal code execution pattern and temperatur
257. ned to lt gt Register bit field In the set of italics User defined term font is courier 1996 Microchip Technology Inc DS30412C page 107 PIC17C4X Table 15 2 lists the instructions recognized by the MPASM assembler Note 1 Any unused opcode is Reserved Use of any reserved opcode may cause unex pected operation Note 2 The shaded instructions are not available in the PIC17C42 All instruction examples use the following format rep resent a hexadecimal number Oxhh where h signifies a hexadecimal digit To represent a binary number 0000 0100b where b signifies a binary string FIGURE 15 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations 15 9 8 7 OPCODE d f FILE 0 for destination WREG 1 for destination f 8 bit file register address Byte to Byte move operations 15 13 12 8 7 OPCODE p FILE f FILE eripheral register file address p f bit file register address 8 Bit oriented file register operations 15 1110 87 OPCODE b BIT f FILE 3 bit address 8 bit file register address 5 f Literal and control operations 15 8 7 OPCODE k literal 8 bit immediate value Call and GOTO operations 15 13 12 OPCODE literal 13 bit immediate value 15 1 Special Function Registers as Source Destination The PIC17C4X s orthogonal instructi
258. nization for the PIC17C42 and Figure 6 6 for all of the other PIC17C4X devices Instructions and MOVFP provide the means to move values from the peripheral area P to any loca tion in the register file and vice versa The defini tion of the range is from Oh to 1Fh while the range is Oh to FFh The P range has six more loca tions than peripheral registers eight locations for the 17 42 device which can be used as General pose Registers This can be useful in some applications where variables need to be copied to other locations in the general purpose RAM such as saving status infor mation during an interrupt The entire data memory can be accessed either directly or indirectly through file select registers FSRO and FSR1 Section 6 4 Indirect addressing uses the appropriate control bits of the BSR for accesses into the banked areas of data memory The BSR is explained in greater detail in Section 6 8 6 2 1 GENERAL PURPOSE REGISTER GPR All devices have some amount of GPR area The GPRs are 8 bits wide When the GPR area is greater than 232 it must be banked to allow access to the additional memory space Only the PIC17C43 and PIC17C44 devices have banked memory in the GPR area To facilitate switching between these banks the MOVLR bank instruction has been added to the instruction set GPRs are not initial ized by a Power on Reset and are unchanged on all other re
259. nized with the processor clock Use of one of the PWM outputs as the clock source to the TCLKx input will supply a synchronized clock In general when using an external clock source for PWM its frequency should be much less than the device frequency Fosc DS30412C page 76 1996 Microchip Technology Inc PIC17C4X 12 1 3 31 MAX RESOLUTION FREQUENCY FOR EXTERNAL CLOCK INPUT The use of an external clock for the PWM time base or Timer2 limits the PWM output to maxi mum resolution of 8 bits The PWxDCL 7 6 bits must be kept cleared Use of any other value will distort the PWM output All resolutions are supported when inter nal clock mode is selected The maximum attainable frequency is also lower This is a result of the timing requirements of an external clock input for a timer see the Electrical Specification section The maximum PWM frequency when the timers clock source is the RB4 TCLK12 pin is shown in Table 12 3 standard res olution mode 12 2 Timer3 Timer3 is a 16 bit timer consisting of the TMR3H and TMR3L registers TMR3H is the high byte of the timer and TMR3L is the low byte This timer has an associ ated 16 bit period register PR3H CA1H PR3L CA1L This period register can be software configured to be a second 16 bit capture register When the TMR3CS bit 1 lt 2 gt is clear the timer increments every instruction cycle Fosc 4 When TMR3CS is set the timer incr
260. nk by PORTA and PORTB combined 150 mA Maximum current sourced by PORTA and PORTB combined ss 100 mA Maximum current sunk by PORTC PORTD and PORTE combined 150 mA Maximum current sourced by PORTC PORTD and PORTE combined 100 mA Note 1 Power dissipation is calculated as follows Pdis VDD x IDD X x X VoL x IOL Note 2 Voltage spikes below Vss at the MCLR pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 1000 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss T NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 1996 Microchip Technology Inc DS30412C page 147 oc 1 4 v 3 PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 TABLE 17 1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION COMMERCIAL DEVICES OSC PIC17C42 16 PIC17C42 25 RC VDD 4 5V to 5 5V VDD 4 5V to 5 5V IDD 6 mA max IDD 6 mA max IPD
261. obally enabling interrupts has inverse polarity Addition of a test mode pin 23 In circuit serial programming is not imple mented APPENDIX B COMPATIBILITY To convert code written for PICT6CXX to PIC17CXX the user should take the following steps 1 Remove any TRIS and OPTION instructions and implement the equivalent code 2 Separate the interrupt service routine into its four vectors 3 Replace with MOVFP 1 4 Replace MOVWF REG2 with 1 REG2 Addr 1 lt 201 REG2 Addr 2 lt 20 Note If REG1 and REG2 are both at addresses greater then 20h two instructions are required MOVFP WREG MOVPF WREG REG2 5 Ensurethat all bit names and register names are updated to new data memory map location 6 Verify data memory banking 7 Verify mode of operation for indirect addressing 8 Verify peripheral routines for compatibility 9 Weak pull ups are enabled on reset To convert code from the PIC17C42 to all the other PIC17C4X devices the user should take the following steps 1 If the hardware multiply is to be used ensure that any variables at address 18h and 19h are moved to another address Ensure that the upper nibble of the BSR was not written with a non zero value This may cause unexpected operation since the RA
262. ock Timing Memory Interface Read Timing Memory Interface Write Timing PWM Timing 2 RESET Watchdog Timer Oscillator Start up Timer and Power up Timer 157 TimerO Clock Timings 158 Timer2 and Timer3 Clock Timing 158 USART Module Synchronous Receive 160 USART Module Synchronous Transmission 160 17 43 44 Absolute Maximum Ratings 175 Capture Timing 2 188 CLKOUT and I O Timing 185 DC Characteristics External Clock Timing 184 Memory Interface Read Timing 191 Memory Interface Write Timing Parameter Measurement Information 183 RESET Watchdog Timer Oscillator Start up Timer and Power up Timer Timing 186 TimerO Clock Timing 187 Timer2 and Timer3 Clock Timing 187 Timing Parameter Symbology 182 USART Module Synchronous Receive PERSEO NE RP 189 USART Module Synchronous Transmission TIMING ccena 189 EPROM Memory Access Time Order Suffix 31 Extended Microcontroller T Extended Microcontroller Mode 31 External Memory Interface 31 External Program Memory Waveforms
263. of XT Oscillator VS nid xe sites te akisa 196 Typical IDD vs Frequency External Clock 25 C rte deseen 197 Maximum IDD vs Frequency External Clock 125 C to 40 C 197 Typical IPD vs Watchdog Disabled 25 198 Maximum IPD vs Watchdog Disabled eae 198 Typical IPD vs Watchdog Enabled 259 199 Maximum IPD vs Watchdog 199 Timer Time Out Period vs 200 vs VDD 200 vs VDD 5V 201 IOL vs VoL VDD 201 IOL vs VoL VDD 5V 202 VTH Input Threshold Voltage of Pins TTL vs 202 VTH VIL of I O Pins Schmitt Trigger E gas a eren 203 VTH Input Threshold Voltage of OSC1 Input In XT and LF Modes vs VDD 203 LIST OF TABLES Table 1 1 Table 3 1 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 5 1 Table 6 1 PIC17CXX Family of Devices 6 Pinout Descriptions 12 Time Out in Various Situations 16 STATUS Bits and Their Significance 16 Reset Condition for the Program Counter and the CPUSTA Register 16 Initialization Conditions For Special
264. ology Inc DS30412C page 71 PIC17C4X FIGURE 12 2 TCON2 REGISTER ADDRESS 17h BANK 3 R 0 0 RW 0 0 R W 0 R W 0 R W 0 HR W O 2 PWM2ON 1 1 TMR2ON TMR1ON R Readable bit bit7 bitO W Writable bit Value at POR reset bit 7 2 Capture2 Overflow Status bit This bit indicates that the capture value had not been read from the capture register pair CA2H CA2L before the next capture event occurred The capture register retains the oldest unread capture value last capture before overflow Subsequent capture events will not update the capture register with the Timer3 value until the capture register has been read both bytes 1 Overflow occurred on Capture register 0 No overflow occurred on Capture2 register bit 6 CA10VF Capture1 Overflow Status bit This bit indicates that the capture value had not been read from the capture register pair PR3H CA2H PR3L CA2L before the next capture event occurred The capture register retains the old est unread capture value last capture before overflow Subsequent capture events will not update the capture register with the TMR3 value until the capture register has been read both bytes 1 Overflow occurred on Capture1 register 0 No overflow occurred on Capture1 register bit 5 PWM2ON PWM2 On bit 1 PWM2 is enabled The RB3 PWM2 pin ignores the state of the DD
265. on Asynchronous mode Don t care bit 4 CREN Continuous Receive Enable bit This bit enables the continuous reception of serial data Asynchronous mode 1 Enable reception 0 Disables reception Synchronous mode 1 Enables continuous reception until CREN is cleared CREN overrides SREN 0 Disables continuous reception bit 3 Unimplemented Read as 0 bit 2 FERR Framing Error bit 1 Framing error Updated by reading RCREG 0 No framing error bit 1 OERR Overrun Error bit 1 Overrun Cleared by clearing CREN 0 No overrun error bit 0 RX9D 9th bit of receive data can be the software calculated parity bit DS30412C page 84 1996 Technology Inc PIC17C4X FIGURE 13 3 USART TRANSMIT 4 r Write to TXREG De TXSTA lt 0 gt ig TXIE Data Bus FIGURE 13 4 USART RECEIVE Interrupt Master Slave Async Sync E enable Bit Count e START Detect SREN CREN Majority Start Bit Detect Async Sync
266. on set allows read and write of all file registers including special function registers There are some special situations the user should be aware of 15 1 1 ALUSTA AS DESTINATION If an instruction writes to ALUSTA the Z C DC and OV bits may be set or cleared as a result of the instruction and overwrite the original data bits written For exam ple executing CLRF ALUSTA will clear register ALUSTA and then set the Z bit leaving 0000 01005 the register 15 1 2 PCL AS SOURCE OR DESTINATION Read write or read modify write on PCL may have the following results Read PC Write PCL PCH PCLATH dest PCLATH gt PCH 8 bit destination value PCL Read Modify Write ALU operand PCLATH PCH 8 bit result gt PCL Where PCH program counter high byte not an addressable register PCLATH Program counter high holding latch dest destination WREG or f 15 1 3 BIT MANIPULATION All bit manipulation instructions are done by first read ing the entire register operating on the selected bit and writing the result back read modify write The user should keep this in mind when operating on special function registers such as ports DS30412C page 108 1996 Microchip Technology Inc PIC17C4X 15 2 Cycle Activity The 4 Q cycles that make up an instruction cycle Tcy can be generalized as Each instruction cycle Tcy is comprised of four Q cycles Q1 Q4 The Q cycles prov
267. onal throughput Reduces code size requirements for multiply 1 WREG algorithms MULWF ARG2 ARG2 gt PRODH PRODL The performance increase allows the device to be used BTFSC ARG2 SB Test Sign Bit in applications previously reserved for Digital Signal SUBWF PRODH F PRODH PRODH Processors ARG1 Table 8 1 shows a performance comparison between dnd ips Ww the PIC17C42 and all other PIC17CXX devices which PROD re ODE have the single cycle hardware multiply E Example 8 1 shows the sequence to do an 8 x 8 unsigned multiply Only one instruction is required when one argument of the multiply is already loaded in the WREG register TABLE 8 1 PERFORMANCE COMPARISON Time Routine Device Program Memory Cycles Max Words 25 MHz 33 MHz 8 x 8 unsigned PIC17C42 13 69 11 04 us N A All other PIC17CXX devices 1 1 160 ns 121 ns 8 x 8 signed PIC17C42 N A other PIC17CXX devices 6 6 960 ns 727 ns 16 x 16 unsigned 17 42 21 242 38 72 us N A All other PIC17CXX devices 24 24 3 84 us 2 91 us 16 x 16 signed PIC17C42 52 254 40 64 us N A other PIC17CXX devices 36 36 5 76 us 4 36 us 1996 Microchip Technology Inc DS30412C page 49 PIC17C4X Example 8 3 shows the sequence to do a 16 x 16 EXAMPLE 8 3 16 x 16 MULTIPLY ROUTINE unsigned multiply Equation 8 1 shows the algorithm that is used The 32 bit result is stored in 4 regist
268. or system bus Write WR control pin Legend TTL TTL input TABLE 9 10 REGISTERS BITS ASSOCIATED WITH PORTE Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 15h Bank 1 PORTE RE2 WR RE1 OE REO ALE xxx uuu 14h Bank 1 DDRE Data direction register for PORTE 2111 Ses 114 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by PORTE Note 1 Other non power up resets include external reset through and the Watchdog Timer Reset AE a a 1996 Microchip Technology Inc DS30412C page 63 PIC17CAX 9 5 Programming Considerations EXAMPLE 9 5 READ MODIFY WRITE INSTRUCTIONS ON AN 9 5 1 BI DIRECTIONAL PORTS l O PORT Any instruction which writes operates internally as a Initial PORT settings PORTB 7 4 Inputs read followed by a write operation For example the and BSF instructions read the register into the CPU execute the bit operation and write the result back to the register Caution must be used when these instructions are applied to a port with both inputs and outputs defined For example a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read PORTB 3 0 Outputs PORTB 7 6 have pull ups and are not connected to other circuitry PORT latch PORT pins 5404054 040404 04 into the CPU Then the BS
269. ormal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as coming out of the pin 4 These specifications are for the programming of the on chip program memory EPROM through the use of the table write instructions The complete programming specifications can be found in PIC17CXX Programming Specifications Literature number 0530139 The MCLR Vpp pin may be kept in this range at times other than programming but this is not recommended For TTL buffers the better of the two specifications may be used DS30412C page 150 1996 Technology Inc PIC17CAX Applicable Devices 42 R42 42A 43 R43 44 Standard Operating Conditions unless otherwise stated Operating temperature DC CHARACTERISTICS 40 C amp TA lt 85 for industrial and lt lt 70 for commercial Operating voltage VDD range as described in Section 17 1 Parameter No Sym Characteristic Min Max Units Conditions Output Low Voltage ports except RA2 and 0 V loL2 4 with TTL buffer 0 4 V 6 mA VDD 4 5V Note 6 RA2 and RA3 3 0 V 60 0 mA VDD 5 5V OSC2 CLKOUT 0 4 2mA VDD 4 5V and modes Output High Voltage Note 3 ports except RA2 and 0 9 V 2 mA with TTL buffer 24
270. output 4 x Tosc Tcv DS30412C page 156 1996 Technology Inc PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING MCLR Internal POR PWRT Time out OSC Time out Internal RESET Watchdog Timer RESET Address Data TABLE 17 4 RESET WATCHDOG TIMER OSCILLATOR START UP AND POWER UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 30 TmcL MCLR Pulse Width low 100 ns 31 Twdt Watchdog Timer Time out Period 5 12 25 ms Prescale 1 32 Tost Oscillation Start up Timer Period 1024 Tosc 8 ms Tosc OSC1 period 33 Tpwrt Power up Timer Period 40 96 200 ms 35 TmcL2adl MCLR to System Interface bus 100 ns AD15 ADO invalid These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested These parameters for design guidance only and are not tested nor characterized 5 This specification ensured by design 1996 Microchip Technology Inc DS30412C page 157 PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 17 5 TIMERO CLOCK TIM
271. oy an advanced RISC architecture The PIC17CXX has enhanced core features 16 level deep stack and multiple internal and external interrupt sources The separate instruction and data buses of the Harvard architecture allow a 16 bit wide instruction word with a separate 8 bit wide data The two stage instruction pipeline allows all instructions to execute in a single cycle except for program branches which require two cycles A total of 55 instructions reduced instruction set are available in the PIC17C42 and 58 instructions in all the other devices Additionally a large register set gives some of the architectural innovations used to achieve a very high performance For mathematical intensive applica tions all devices except the PIC17C42 have a single cycle 8 x 8 Hardware Multiplier PIC17CXX microcontrollers typically achieve a 2 1 code compression and a 4 1 speed improvement over other 8 bit microcontrollers in their class PIC17C4X devices have up to 454 bytes of RAM and 33 I O pins In addition the PIC17C4X adds several peripheral features useful in many high performance applications including Four timer counters Two capture inputs Two PWM outputs A Universal Synchronous Asynchronous Receiver Transmitter USART These special features reduce external components thus reducing cost enhancing system reliability and reducing power consumption There are four oscillator options of which the single pin RC os
272. perands 0 lt 1 lt 255 0 lt 0 lt 7 Operation 1 f lt b gt Status Affected None Encoding 1000 Obbb ffff ffff Description Bit b in register f is set Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register f Example BSF FLAG REG 7 Before Instruction FLAG REG 0x0A After Instruction FLAG REG 0x8A BTFSC Bit Test skip if Clear Syntax abel BTFSC Operands lt lt 255 lt lt 7 Operation skip if f lt b gt 0 Status Affected Encoding 1001 lbbb ffff ffff Description If bit b in register is 0 then the next instruction is skipped If bit b is 0 then the next instruction fetched during the current instruction exe cution is discarded and a NOP is exe cuted instead making this a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute NOP register f If skip Q1 Q2 Q3 Q4 Forced NOP NOP Execute NOP Example HERE BTFSC FLAG 1 FALSE TRUE Before Instruction PC address HERE After Instruction If FLAG lt 1 gt 0 PC address TRUE If FLAG lt 1 gt 1 address FALSE 1996 Microchip Technology Inc DS30412C page 115 PIC17C 4 55 Bit Test skip if Set Syntax label BTFSS 1 Operands 0 lt 1 lt 127 0 lt lt 7 Operation skip if f lt b gt 1 Status Affected Encoding 1001
273. prior to the SLEEP instruc tion then a word may be received during SLEEP On completely receiving the word the RSR will transfer the data to RCREG setting RCIF and if the RCIE bit is set the interrupt generated will wake the chip from SLEEP If the global interrupt is enabled the program will branch to the interrupt vector 0020h Steps to follow when setting up a Synchronous Slave Reception 1 Enable the synchronous master serial port by setting the SYNC and SPEN bits and clearing the CSRC bit If interrupts are desired then set the RCIE bit If 9 bit reception is desired then set the RX9 bit To enable reception set the CREN bit The RCIF bit will be set when reception is com plete and an interrupt will be generated if the RCIE bit was set 6 Read RCSTA to get the ninth bit if enabled and determine if any error occurred during reception 7 Read the 8 bit received data by reading RCREG 8 If any error occurred clear the error by clearing the CREN bit D Note abort reception either clear the the SREN when single receive mode or the CREN bit when in continu ous receive mode This will reset the receive logic so that it will be in the proper state when receive is re enabled 1996 Microchip Technology Inc DS30412C page 97 PIC17C4X
274. programmer It connects to the PC via one of the COM RS 232 ports MPLAB Integrated Development Environment software makes using the programmer simple and efficient PICSTART Plus is not recommended for production programming PICSTART Plus supports all PIC12C5XX PIC14000 PIC16C5X PIC16CXXX and PIC17CXX devices with up to 40 pins Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket 1996 Microchip Technology Inc DS30412C page 143 PIC17C4X 16 6 PICDEM 1 Low Cost PIC16 17 Demonstration Board The PICDEM 1 is a simple board which demonstrates the capabilities of several of Microchip s microcontrol lers The microcontrollers supported are PIC16C5X PIC16C54 to PIC16C58A PIC16C61 PIC16C62X PIC16C71 PIC16C8X PIC17C42 PIC17C43 and PIC17C44 All necessary hardware and software is included to run basic demo programs The users can program the sample microcontrollers provided with the PICDEM 1 board on PROMATE II or PICSTART 16B programmer and easily test firm ware The user can also connect the PICDEM 1 board to the PICMASTER emulator and download the firmware to the emulator for testing Additional pro totype area is available for the user to build some addi tional hardware and connect it to the microcontroller socket s Some of the features include RS 232 interface a potentiometer for simulated analog input push button switches and eight LEDs connected
275. pt is responded to the GLINTD bit is automatically set to disable any further interrupt the return address is pushed onto the stack and the PC is loaded with the interrupt vector address There are four interrupt vectors Each vector address is for a specific interrupt source except the peripheral interrupts which have the same vector address These sources are External interrupt from the RAO INT pin TMRO Overflow TOCKI edge occurred Any peripheral interrupt When program execution vectors to one of these inter rupt vector addresses except for the peripheral inter rupt address the interrupt flag bit is automatically cleared Vectoring to the peripheral interrupt vector address does not automatically clear the source of the interrupt In the peripheral interrupt service routine the source s of the interrupt can be determined by testing the interrupt flag bits The interrupt flag bit s must be cleared in software before re enabling interrupts to avoid infinite interrupt requests All of the individual interrupt flag bits will be set regard less of the status of their corresponding mask bit or the GLINTD bit For external interrupt events there will be an interrupt latency For two cycle instructions the latency could be one instruction cycle longer The return from interrupt instruction RETFIE can be used to mark the end of the interrupt service routine When this instruction is executed the stack
276. ption Register file address 00h to FFh Peripheral register file address 00h to 1Fh Table pointer control i 0 do not change i 1 increment after instruction execution Table byte select t 0 perform operation on lower byte t 1 perform operation on upper byte literal field constant data Working register accumulator Bit address within an 8 bit file register Literal field constant data or label Don t care location 0 or 1 The assembler will generate code with x O It is the recommended form of use for compatibility with all Microchip software tools Destination select 0 store result in WREG 1 store result in file register f Default is d 1 Unused encoded as 0 Destination select 0 store result in file register f and in the WREG 1 store result in file register f Default is s 1 Label name ALU status bits Carry Digit Carry Zero Overflow Global Interrupt Disable bit CPUSTA lt 4 gt Table Pointer 16 bit Table Latch 16 bit consists of high byte TBLATH and low byte TBLATL Table Latch low byte Table Latch high byte Top of Stack Program Counter Bank Select Register Watchdog Timer Counter Time out bit PD Power down bit dest Destination either the WREG register or the speci fied register file location Options Contents Assig
277. r Instruction If CNT PC If CNT PC 0x00 Address ZERO 0x00 Address NZERO DS30412C page 140 1996 Microchip Technology Inc PIC17C4X Exclusive OR Literal with XORLW WREG Syntax label XORLW Operands 0 lt k lt 255 Operation WREG XOR k gt WREG Status Affected Z Encoding 1011 0100 kkkk kkkk Description The contents of WREG XOR ed with the 8 bit literal k The result is placed in WREG Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to literal k WREG Example XORLW OxAF Before Instruction WREG 0xB5 After Instruction WREG OxiA XORWF Exclusive OR WREG with f Syntax label XORWF Operands 0 lt 1 lt 255 0 1 Operation WREG XOR f dest Status Affected Z Encoding 0000 110d ffff ffff Description Exclusive OR the contents of WREG with register f If d is 0 the result is stored WREG If d is 1 the result is stored back in the register Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example XORWF 1 Before Instruction REG OxAF WREG 0 5 After Instruction REG 0x1A WREG 0xB5 1996 Microchip Technology Inc DS30412C page 141 PIC17C4X NOTES SE DS30412C page 142 1996 Microchip Technology Inc PIC17CAX 16 0 DEVELOPMENT SUPPORT 16 1 Developmen
278. rameters are characterized but not tested T Data column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested t These parameters are for design guidance only and are not tested nor characterized 8 This specification ensured by design DS30412C page 186 1996 Technology Inc PIC17C4X Applicable Devices 42 42 42 43 843 44 FIGURE 19 5 TIMERO CLOCK TIMINGS RA1 TOCKI TABLE 19 5 TIMERO CLOCK REQUIREMENTS Sym Characteristic Min Typt Max Units Conditions 40 TtOH TOCKI High Pulse Width No Prescaler 0 5TCY 208 ns With Prescaler 10 ns 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5Tcv 208 ns With Prescaler 10 ns 42 Period Greater of ns value 20 ns 40 8 1 2 4 256 N These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested This specification ensured by design FIGURE 19 6 TIMER1 TIMER2 AND TIMER3 CLOCK TIMINGS TCLK12 or TCLK3 TABLE 19 6 TIMER1 TIMER2 AND TIMER3 CLOCK REQUIREMENTS
279. re TX9 9 bit Transmit Enable bit 1 Selects 9 bit transmission 0 Selects 8 bit transmission TXEN Transmit Enable bit 1 Transmit enabled 0 Transmit disabled bit 6 bit 5 SREN CREN overrides TXEN in SYNC mode bit4 SYNC USART mode Select bit Synchronous Asynchronous 1 Synchronous mode 0 Asynchronous mode bit 3 2 bit 1 Unimplemented Read as 0 1 TSR empty 0 TSR full bit 0 TRMT Transmit Shift Register TSR Empty bit TX9D 9th bit of transmit data can be used to calculated the parity in software W Writable bit Value at POR reset x unknown bito 1996 Microchip Technology Inc DS30412C page 83 PIC17C4X FIGURE 13 2 RCSTA REGISTER ADDRESS 13h BANK 0 R W 0 R W 0 R W 0 R W 0 U 0 R 0 R 0 RX9 SREN CREN FERR OERR RX9D R Readable bit bit7 bit 0 W Writable bit n Value at POR reset x unknown bit 7 SPEN Serial Port Enable bit 1 Configures RA5 RX DT and RA4 TX CK pins as serial port pins 0 Serial port disabled bit 6 RX9 9 bit Receive Enable bit 1 Selects 9 bit reception 0 Selects 8 bit reception bit5 SREN Single Receive Enable bit This bit enables the reception of a single byte After receiving the byte this bit is automatically cleared Synchronous mode 1 Enable reception 0 Disable reception Note This bit is ignored in synchronous slave recepti
280. re also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tristated pulled to or Vss TOCKI VDD MCLR VDD enabled disabled as specified Current consumed from the oscillator and driving external capacitive or resistive loads needs to be con sidered For the RC oscillator the current through the external pull up resistor R can be estimated as 2 For capacitive loads the current can be estimated for an individual I O pin as CL VDD 1 CL Total capacitive load on the I O pin f average frequency the I O pin switches The capacitive currents are most significant when the device is configured for external execution includes extended microcontroller mode The power down current in SLEEP mode does not depend on the oscillator type Power down current is mea sured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VDD and Vss For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula IR VDD 2Rext mA with Rext in kOhm 1996 Microchip Technology Inc DS30412C page 177 PIC17C4X Applicable Devices 42 42 42A 43 R43 44 19 2 DC CHARACTERISTICS PIC17LC42A 43 LC44 Commercial Industrial PIC17LCR42 43 Commercial I
281. result is mented If d is 0 the result is placed in placed in WREG WREG If is 1 the result is placed Words 1 back in register f If the result is not 0 the next instruction 1 which is already fetched is discarded Q Cycle Activity and an NOP is executed instead making Q1 Q2 Q3 Q4 it a two cycle instruction Decode Read Execute Write to Words 1 literal k WREG Cycles 1 2 Example IORLW 0x35 Q Cycle Activity Before Instruction Q1 Q2 Q3 Q4 WREG 0x9A Decode Read Execute Write to After Instruction register f destination WREG OxBF If skip Q1 Q2 Q3 Q4 Forced Execute Example HERE INFSNZ REG 1 ZERO NZERO Before Instruction REG REG After Instruction REG E REG 1 REG 1 Address ZERO REG 0 Address NZERO DS30412C page 124 1996 Microchip Technology Inc PIC17C4X IORWF Inclusive OR WREG with f Syntax label IORWF Operands 0 lt lt 255 d e 0 1 Operation WREG f dest Status Affected Z Encoding 0000 100d ffff ffff Description Inclusive OR WREG with register If d is 0 the result is placed in WREG If d is 1 the result is placed back in regis ter Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example IORWF RESULT O Before Instruction RESULT 0x13 WREG 0x91 After Instruction RESULT 0x
282. rich directive language to support programming of the PIC16 17 Directives are helpful in making the development of your assemble source code shorter and more maintainable 16 11 Software Simulator MPLAB SIM The MPLAB SIM Software Simulator allows code development in a PC host environment It allows the user to simulate the PIC16 17 series microcontrollers on an instruction level On any given instruction the user may examine or modify any of the data areas or provide external stimulus to any of the pins The input output radix can be set by the user and the execution can be performed in single step execute until break or in a trace mode MPLAB SIM fully supports symbolic debugging using MPLAB C and MPASM The Software Simulator offers the low cost flexibility to develop and debug code out side of the laboratory environment making it an excel lent multi project software development tool 16 12 C Compiler MPLAB C The MPLAB C Code Development System is a complete C compiler and integrated development environment for Microchip s PIC16 17 family of micro controllers The compiler provides powerful integration capabilities and ease of use not found with other compilers For easier source level debugging the compiler pro vides symbol information that is compatible with the MPLAB IDE memory display PICMASTER emulator software versions 1 13 and later 16 13 Fuzzy Logic Development System fuzzyTECH MP fuzzyTECH MP fuz
283. rite to TXREG can result in an immediate transfer of the data to the TSR if the TSR is empty Steps to follow when setting up an Asynchronous Transmission 1 Initialize the SPBRG register for the appropriate baud rate 2 Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit 3 Ifinterrupts are desired then set the TXIE bit 4 If 9 bit transmission is desired then set the TX9 bit 5 Load data to the TXREG register f 9 bit transmission is selected the ninth bit should be loaded in TX9D 7 Enable the transmission by setting TXEN starts transmission Writing the transmit data to the TXREG then enabling the transmit setting TXEN allows transmission to start sooner then doing these two events in the opposite order Note To terminate a transmission either clear the SPEN bit or the TXEN bit This will reset the transmit logic so that it will be in the proper state when transmit is re enabled 1996 Microchip Technology Inc DS30412C page 89 PIC17C4X FIGURE 13 5 ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG s BRG output Shift clock 3 TX RA5 TX CK Start Sc j Bit 7 8 Stop Bit i Word 1 TXIF bit 55 Wordi Transmit Shift Reg TRMT bit FIGURE 13 6 ASYNCHRONOUS MASTER TRANSMISSION BACK TO BACK
284. rnal Program Memory Programming Specs Note 4 D110 VPP Voltage MCLR VPP pin 12 75 13 25 V 5 D111 Supply voltage during 4 75 5 0 5 25 V programming D112 Current into MCLR VPP pin 251 50 mA D113 IppP Supply current during 30 mA programming D114 TPROG Programming pulse width 10 100 1000 us Terminated via internal external interrupt or a reset These parameters characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested t These parameters are for design guidance only and are not tested nor characterized Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC17CXX devices be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified lev els represent normal operating conditions Higher leakage current may be measured at different input volt ages 3 Negative current is defined as coming out of the pin 4 These specifications are for the programming of the on chip program memory EPROM through the use of the table write instructions The complete programming specifications can be found in PIC17CXX Programming Specifications Literature number 0530139 5 The MCLR VPP pin may be kept in this range at times other than programming but is not recommen
285. rogramming specifications can be found in PIC17CXX Programming Specifications Literature number 0530139 The MCLR Vpp pin may be kept in this range at times other than programming but this is not recommended 6 For TTL buffers the better of the two specifications may be used e 1996 Microchip Technology Inc DS30412C page 151 PIC17C4X Applicable Devices 42 R42 42 43 43 44 CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt lt 40 Operating voltage VDD range as described in Section 17 1 Parameter No Characteristic Min Typt Max Unit Conditions Internal Program Memory Programming Specs Note 4 D110 VPP Voltage MCLR VPP pin 12 75 13 25 V Note 5 D111 voltage during 4 75 5 0 5 25 V programming D112 Current into MCLR VPP pin 251 50 mA D113 IppP Supply current during 30 mA programming D114 TPROG Programming pulse width 10 100 1000 us Terminated via internal exter nal interrupt or a reset i These parameters characterized but not tested T Data Typ column is at 5V 25 C unless otherwise stated These parameters for design guidance only and are not tested t These parameters are for design guidance only and are not tested nor characterized Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a
286. rom the period match value to Oh the TMR1IF flag is set and an interrupt will be generated when enabled In counter mode the clock comes from the RB4 TCLK12 pin which can also be selected to be the clock for the Timer2 module can be concatenated to TMR2 to form a 16 bit timer The TMR1 register is the LSB and 2 is the MSB When in the 16 bit timer mode there is a corre sponding 16 bit period register PR2 PR1 When the TMR2 TMR1 value rolls over from the period match value to Oh the TMR1IF flag is set and an interrupt will be generated when enabled 10 3 Timer2 Overview The TMR2 module is an 8 bit timer counter with an 8 bit period register PR2 When the TMR2 value rolls over from the period match value to Oh the TMR2IF flag is set and an interrupt will be generated when enabled In counter mode the clock comes from the RB4 TCLK12 pin which can also be selected to be the clock for the TMR1 module can be concatenated to TMR2 to form a 16 bit timer The TMR2 register is the MSB and TMR is the LSB When in the 16 bit timer mode there is a corre sponding 16 bit period register PR2 PR1 When the TMR2 TMR1 value rolls over from the period match value to Oh the TMR1IF flag is set and an interrupt will be generated when enabled 10 4 Timer3 Overview The Tlmer3 module is a 16 bit timer counter with a 16 bit period register When the TMR3H TMR3L value rolls over to Oh the TMRSIF bit is set and an
287. s 4 1 2 POWER UP TIMER The Power up Timer provides a fixed 96 ms time out nominal on power up This occurs from rising edge of the POR signal and after the first rising edge of MCLR detected high The Power up Timer operates on an internal RC oscillator The chip is kept in RESET as long as the PWRT is active In most cases the PWRT delay allows the VDD to rise to an acceptable level The power up time delay will vary from chip to chip and to VDD and temperature See DC parameters for details FIGURE 4 1 SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT External Reset WDT WDT Module Time Out Reset VDD rise detect Power On Reset OST PWRT OST Chip Reset D of gt 10 bit Ripple counter PWRT iss 10 bit Ripple counter Enable RWRT Enable OST T This RC oscillator is shared with the WDT when not in a power up sequence Power_Up Enable the PWRT timer only during Power_Up Power_Up Wake_Up XT LF Enable the OST if it is Power_Up or Wake_Up from SLEEP and OSC type is XT or LF 1996 Microchip Technology Inc DS30412C page 15 PIC17C4X 413 OSCILLATOR START UP TIMER OST The Oscillator Start up Timer OST provides a 1024 oscillator cycle 1024Tosc delay after MCLR is detected high or a wake up from S
288. s ALU or destination PCH PCLATH c Write instructions on PCL Any instruction that writes to PCL 8 bit data data bus PCL PCLATH PCH d Read Modify Write instructions on PCL Any instruction that does a read write modify operation on PCL such as ADDWF PCL Read PCL data bus ALU Write 8 bit result data bus gt PCL PCLATH gt PCH e RETURN nstruction PCH Stack lt MRU gt lt 15 0 gt Using Figure 6 12 operation of the and PCLATH for coTo and CALL instructions is a follows CALL GOTO instructions A 13 bit destination address is provided in the instruction opcode Opcode 12 0 PC 12 0 lt 15 13 gt PCLATH lt 7 5 gt Opcode lt 12 8 gt PCLATH lt 4 0 gt The read modify write only affects the PCL with the result PCH is loaded with the value in the PCLATH For example ADDWF PCL Will result in a jump within the current page If WREG 30h and PCLATH 03h before instruction PC 0320h after the instruction To accomplish a true 16 bit computed jump the user needs to compute the 16 bit destination address write the high byte to PCLATH and then write the low value to PCL The following PC related operations do not change PCLATH LCALL RETLW and RETF instructions b Interrupt vector is forced onto the PC c Read modify write instructions on PCL e g BSF PCL
289. s over to 0000h On overflow the TMRO Interrupt Flag bit TOIF is set The TMRO interrupt can be masked by clearing the corresponding TMRO Interrupt Enable bit TOIE The TMRO Interrupt Flag bit TOIF is automati cally cleared when vectoring to the TMRO interrupt vec tor FIGURE 11 2 TIMERO MODULE BLOCK DIAGRAM Prescaler 7 8 stage RA1 TOCKI Fosc 4 async ripple counter 11 2 Using 0 with External Clock When the external clock input is used for 0 it is synchronized with the internal phase clocks Figure 11 3 shows the synchronization of the external clock This synchronization is done after the prescaler The output of the prescaler PSOUT is sampled twice in every instruction cycle to detect a rising or a falling edge The timing requirements for the external clock are detailed in the electrical specification section for the desired device 11 2 1 DELAY FROM EXTERNAL CLOCK EDGE Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time is actually incremented Figure 11 3 shows that this delay is between 3Tosc and 7 Thus for example mea suring the interval between two edges e g period will be accurate within 4Tosc 121 ns 33 MHz Interrupt on overflow sets TOIF INTSTA lt 5 gt Synchronization TMROH lt 8 gt TMROL lt 8 gt
290. s the proper device option can be selected using the information in the PIC17C4X Product Selec tion System section at the end of this data sheet When placing orders please use the PIC17C4X Product Identification System at the back of this data sheet to specify the correct part number For the PIC17C4X family of devices there are four device types as indicated in the device number 1 C as in PIC17C42 These devices have EPROM type memory and operate over the standard voltage range 2 LC as in PIC17LC42 These devices have EPROM type memory operate over an extended voltage range and reduced frequency range 3 CR as in PIC17CR42 These devices have ROM type memory and operate over the stan dard voltage range 4 LCR as in PIC17LCR42 These devices have ROM type memory operate over an extended voltage range and reduced frequency range 2 1 UV Erasable Devices The UV erasable version offered in CERDIP package is optimal for prototype development and pilot pro grams The UV erasable version can be erased and repro grammed to of the configuration modes Microchip s PRO MATE programmer supports pro gramming of the PIC17C4X Third party programmers also are available refer to the Third Party Guide for a list of sources 2 2 One Time Programmable OTP Devices The availability of OTP devices is especially useful for customers expecting frequent code changes and updates The OTP devices packa
291. s 125 L GALE ce cn EE 125 Long Writes 45 External Interface External Memory Waveforms Memory Map Different Modes Mode Memory ACCESS Organization Program Memory Program Memory Microcontroller Microprocessor Minimizing Current Consumption 1996 Microchip Technology Inc DS30412C page 227 PIC17C4X C Compiler MPSIM Software Simulator MU EET m st netten Multiply Examples 16x 16 Routine 50 16 x 16 Signed Routine 51 8 x 8 Routine 49 8 x 8 Signed Routine 49 aor esercito pee d 129 N 130 130 OERH i ones eI eiim 84 Opcode Field Descriptions 1 OSG Selection siet egeo m titii d ds 99 Oscillator Configuration essen Crystal External Cloe External Crystal Circuit External Parallel Resonant Crystal Circuit 102 External Series Resonant Crystal Circuit 102 RC Freq erngies 165 195 Oscillator Start up Time Figure 18 Oscillator Start up Timer OST OS T
292. s clear In this mode the Capture1 register consisting of high byte PR3H CA1H and low byte PRSL CA1L is con figured as the period control register for TMR3 Capture1 is disabled in this mode and the correspond ing Interrupt bit CA1IF is never set TMR3 increments until it equals the value in the period register and then resets to 0000h Capture2 is active in this mode The CA2ED1 and CA2EDO bits determine the event on which capture will occur The possible events are Capture on every falling edge Capture on every rising edge Capture every 4th rising edge Capture every 16th rising edge When a capture takes place an interrupt flag is latched into the CA2IF bit This interrupt can be enabled by set ting the corresponding mask bit CA2IE The Peripheral Interrupt Enable bit PEIE must be set and the Global Interrupt Disable bit GLINTD must be cleared for the interrupt to be acknowledged The CA2IF interrupt flag bit must be cleared in software When the capture prescale select is changed the pres caler is not reset and an event may be generated Therefore the first capture after such a change will be ambiguous However it sets the time base for the next capture The prescaler is reset upon chip reset Capture pin RB1 CAP2 is a multiplexed pin When used as a port pin Capture2 is not disabled However the user can simply disable the Capture2 interrupt by clear ing CA2IE If RB1 CAP2 is used as an output pin the
293. same package type and VDD Vss and MCLR pin locations are said to be pin compatible This allows these different devices to operate in the same socket Compatible devices may only requires minor software modification to allow proper operation the application socket ex PIC16C56 and PIC16C61 devices Not all devices in the same package size are pin compatible for example the PIC16C62 is compatible with the PIC16C63 but not the PIC16C55 Pin compatibility does not mean that the devices offer the same features As an example the PIC16C54 is pin compatible with the PIC16C71 but does not have an A D converter weak pull ups on PORTB or interrupts TABLE E 1 PIN COMPATIBLE DEVICES Pin Compatible Devices Package PIC12C508 PIC12C509 8 pin PIC16C54 PIC16C54A 18 pin PIC16CR54A 20 pin PIC16C56 PIC16C58A PIC16CR58A PIC16C61 PIC16C554 PIC16C556 16 558 PIC16C620 16 621 16 622 PIC16C710 PIC16C71 PIC16C711 PIC16F83 PIC16CR83 PIC16C84 PIC16F84A PIC16CR84 PIC16C55 28 pin PIC16C57 PIC16CR57B PIC16C62 PIC16CR62 16 62 PIC16C63 28 pin PIC16C72 PIC16C73 PIC16C73A PIC16C64 PIC16CR64 PIC16C64A 40 pin 16 65 PIC16C65A PIC16C74 PIC16C74A 17 42 PIC17CR42 17 42 40 pin PIC17C43 PIC17CR43 PIC17C44 PIC16C923 PIC16C924 64 68 pin 1996 Microchip Technology Inc DS30412C page 221 PIC17C4X NOTES DS30412
294. set Most other registers are forced to a reset state on Power on Reset POR on MCLR or WDT Reset and on MCLR reset during SLEEP They are not affected by a WDT Reset during SLEEP since this reset is viewed as the resumption of normal operation The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 4 3 These bits are used in software to determine the nature of reset See Table 4 4 for a full description of reset states of all reg isters Note While the device is in a reset state the internal phase clock is held in the Q1 state Any processor mode that allows external execution will force the REO ALE pin as a low output and the RE1 OE and RE2 WR pins as high outputs A simplified block diagram of the on chip reset circuit is shown in Figure 4 1 4 1 Power on Reset POR Power up Timer PWRT and Oscillator Start up Timer OST 4 1 1 POWER ON RESET POR The Power on Reset circuit holds the device in reset until VDD is above the trip point in the range of 1 4V 2 3V The PIC17C42 does not produce an internal reset when VDD declines All other devices will produce an internal reset for both rising and falling VDD To take advantage of the POR just tie the MCLR VPP pin directly or through a resistor to VDD This will eliminate external RC components usually needed to create Power on Reset A minimum rise time for VDD is required See Electrical Specifications for detail
295. sets 6 2 2 SPECIAL FUNCTION REGISTERS SFR The SFRs are used by the CPU and peripheral func tions to control the operation of the device Figure 6 5 and Figure 6 6 These registers are static RAM The SFRs can be classified into two sets those associ ated with the core function and those related to the peripheral functions Those registers related to the core are described here while those related to a peripheral feature are described in the section for each peripheral feature The peripheral registers are in the banked portion of memory while the core registers are in the unbanked region To facilitate switching between the peripheral banks the MOVLB bank instruction has been provided DS30412C page 32 1996 Microchip Technology Inc PIC17CAX FIGURE 6 5 PIC17C42 REGISTER FILE FIGURE 6 6 PIC17CR42 42A 43 R43 44 MAP REGISTER FILE MAP Addr Unbanked Addr Unbanked 00h INDFO 00h INDFO 01h FSRO 01h FSRO 02h PCL 02h PCL 03h PCLATH 03h PCLATH 04h ALUSTA 04h ALUSTA 05h TOSTA 05h TOSTA 06h CPUSTA 06h CPUSTA 07h INTSTA 07h INTSTA 08h INDF1 08h INDF1 09h FSR1 09h FSR1 0Ah WREG 0Ah WREG OBh TMROL OBh TMROL OCh TMROH 0Ch TMROH ODh TBLPTRL ODh TBLPTRL OEh TBLPTRH OEh TBLPTRH OFh BSR OFh BSR BankO 1
296. sets 0000 0000 except the PIC17C42 Power on Reset xxxx xxxx and All other resets uuuu uuuu 5 The PRODL and PRODH registers are not implemented on the PIC17C42 DS30412C page 34 1996 Microchip Technology Inc PIC17CAX TABLE 6 3 SPECIAL FUNCTION REGISTERS Cont d Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other Reset resets 3 Bank 2 10h TMR1 XXXX uuuu uuuu 11 TMR2 Timer2 XXXX XXXX uuuu uuuu 12h TMR3L TMR3 register low byte XXXX XXXX uuuu uuuu 13h register high byte XXXX XXXX uuuu uuuu 14h PR1 Timer1 period register XXXX XXXX uuuu uuuu 15h PR2 Timer2 period register XXXX XXXX uuuu uuuu 16h PR3L CA1L Timer3 period register low byte capture1 register low byte XXXX XXXX uuuu uuuu 17h PR3H CA1H period register high byte capture1 register high byte XXXX XXXX uuuu uuuu Bank 3 10h PW1DCL DC1 DCO xx uu 11 PW2DCL DC1 DCO TM2PW2 12h PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 XXXX XXXX uuuu uuuu 13h PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 XXXX XXXX uuuu uuuu 14h CA2L Capture2 low byte XXXX XXXX uuuu uuuu 15h CA2H Capture2 high byte XXXX XXXX uuuu uuuu 16h TCON1 2 1 CA2EDO CA1ED1 CA1EDO T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 171 TCON2 CA2OVF
297. sign guidance only and are not tested 5 This specification ensured design DS30412C page 158 1996 Technology Inc PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17 7 CAPTURE TIMINGS CAP1 and CAP2 Capture Mode TABLE 17 7 CAPTURE REQUIREMENTS Parameter No Sym Characteristic Min Max Units Conditions 50 Capture1 and Capture2 input low time 10 ns 51 TccH Capture1 and Capture input high time 10 ns 52 TccP Capture1 and Capture2 input period 2 6 ns N prescale value N 4 16 i These parameters are but not tested T Data column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and not tested 5 This specification ensured design FIGURE 17 8 PWM TIMINGS PWM1 and PWM2 PWM Mode TABLE 17 8 PWM REQUIREMENTS Parameter No Sym Characteristic Min Typt Units Conditions 53 TccR PWM1 and 2 output rise time 10 35 8 ns 54 PWM1 PWM2 output fall time 10 35 ns These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters for design guidance only and are not tested 5 This specifi
298. so be used with the PICDEM 3 board to test firm ware Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket s Some of the features include an RS 232 interface push button switches a potentiometer for simulated analog input a thermistor and separate headers for connection to an external LCD module and a keypad Also provided on the PICDEM 3 board is an LCD panel with 4 commons and 12 segments that is capable of displaying time temperature and day of the week The PICDEM 3 pro vides an additional RS 232 interface and Windows 3 1 software for showing the demultiplexed LCD signals on a PC A simple serial interface allows the user to con struct a hardware demultiplexer for the LCD signals PICDEM 3 will be available in the 3rd quarter of 1996 16 9 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8 bit microcon troller market MPLAB is a windows based application which contains Afull featured editor Three operating modes editor emulator simulator A project manager Customizable tool bar and key mapping status bar with project information Extensive on line help MPLAB allows you to Edit your source files either assembly or C One touch assemble or compile and download to PIC16 17 tools automatically updates all project information
299. specific information AA Year code last 2 digits of calendar year BB Week code week of January 1 is week 01 C Facility code of the plant at which wafer is manufactured Chandler Arizona U S A S Tempe Arizona U S A D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note n the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information Standard OTP marking consists of Microchip part number year code week code facility code mask rev and assembly code For OTP marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price DS30412C page 210 1996 Microchip Technology Inc PIC17C4X APPENDIX A MODIFICATIONS The following is the list of modifications over the PIC16CXX microcontroller family 1 16 17 19 20 Control Status bits and registers have been Instruction word length is increased to 16 bit This allows larger page sizes both in program memory 8 Kwords verses 2 Kwords and regis ter file 256 bytes versus 128 bytes Four modes of operation microcontroller pro tected microcontroller extended microcontroller and microprocessor 22 new instructions The MOVF TRIS and OP
300. ss data memory not a physical register 01h FSRO Indirect data memory address pointer 0 XXXX XXXX uuuu uuuu 02h PCL Low order 8 bits of PC 0000 0000 0000 0000 0380 PCLATH Holding register for upper 8 bits of PC 0000 0000 uuuu 04h ALUSTA FS3 FS2 FS1 FSO OV Z DC 1111 xxxx 1111 uuuu 05h TOSTA INTEDG TOSE TOCS PS3 PS2 PS1 50 0000 000 0000 000 06h 2 CPUSTA STKAV GLINTD TO PD 11 11 11 qq 07h INTSTA PEIF TOCKIF TOIF INTF PEIE TOCKIE TOIE INTE 0000 0000 0000 0000 08h INDF1 Uses contents of FSR1 to address data memory not a physical register 09h FSR1 Indirect data memory address pointer 1 XXXX XXXX uuuu uuuu WREG Working register XXXX XXXX uuuu uuuu OBh TMROL TMRO register low byte XXXX XXXX uuuu uuuu 0Ch TMROH TMRO register high byte XXXX XXXX uuuu uuuu ODh TBLPTRL Low byte of program memory table pointer 4 4 OEh TBLPTRH High byte of program memory table pointer 4 4 OFh BSR Bank select register 0000 0000 0000 0000 Bank 0 10h PORTA RBPU RA5 RA4 RA3 RA2 1 RAO INT 0 xxxx O uu uuuu 11 DDRB Data direction register for PORTB 1111 1111 1111 1111 12h PORTB data latch XXXX XXXX uuuu uuuu 13h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00u 14h RCREG Serial port receive register XXXX XXXX uuuu uuuu 15h TXSTA CSRC TX9 TXEN SYNC TX9D 0000 1 0000 1u
301. stination for any instruction If the ALUSTA register is the destination for an instruction that affects the Z DC or C bits then the write to these three bits is disabled These bits are set or cleared according to the device logic Therefore the result of an instruction with the ALUSTA register as destination may be different than intended For example CLRF ALUSTA Will clear the upper four bits and set the Z bit This leaves the ALUSTA register as 0000u1uu where u unchanged It is recommended therefore that only BSF SWAPF and Movwr instructions be used to alter the ALUSTA register because these instructions do not affect any status bit To see how other instructions affect the sta tus bits see the Instruction Set Summary Note 1 The C and DC bits operate as a borrow out bit in subtraction See the SUBLW and SUBWF instructions for examples Note 2 The overflow bit will be set if the 2 s com plement result exceeds 127 is less than 128 Arithmetic and Logic Unit ALU is capable of carrying out arithmetic or logical operations on two operands or a single operand All single operand instructions oper ate either on the WREG register or a file register For two operand instructions one of the operands is the WREG register and the other one is either a file register or an 8 bit immediate constant FIGURE 6 7 ALUSTA REGISTER ADDRESS 04h UNBANKED R W 1
302. strial PIC17CR42 42A 43 R43 44 33 Commercial Industrial PIC17LCR42 42A 43 R43 44 08 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature DC CHARACTERISTICS 40 C amp TA lt 85 for industrial and lt lt 70 for commercial Operating voltage VDD range as described in Section 19 1 Parameter Characteristic i Conditions Input Low Voltage ports with TTL buffer 4 5V VDD 5 5V 2 5V VDD 4 5V with Schmitt Trigger buffer MCLR OSC1 in and RC Note1 mode OSC1 in XT and LF mode Input High Voltage ports with TTL buffer 2 0 4 5V VDD 5 5V 1 4 0 2VDD 2 5V VDD 4 5V with Schmitt Trigger buffer 0 8 MCLR 0 8VDD Note1 OSC1 XT and LF mode Hysteresis of 0 15VDD Schmitt Trigger inputs Input Leakage Current Notes 2 3 ports except RA2 Vss lt VPIN VDD I O Pin at hi impedance PORTB weak pull ups disabled MCLR Vss VPIN RA2 RA3 Vss lt VRA2 VRA3 lt 12V OSC1 TEST EC RC modes Vss lt VPIN lt VDD OSC1 TEST XT LF modes RF gt 1 see Figure 14 2 MCLR VMCLR VPP 12V when not programming D070 IPURB PORTB weak pull up current 60 200 400 Vss RBPU 0 4 5V lt VDD lt 6 0V These parameters are characterized but not tested t Data in Typ column is at 5V 2
303. synchronous Transmitter 89 B Bank Select Register BSR 42 Banking odi er ee E rites 42 Baud Rate Formula 86 Baud Rate Generator BRG 86 Baud Rates Asynchronous 88 Synchronous Mode 87 C IM irc E e 114 Bit Manipulation 108 Block Diagrams On chip Reset Circuit 15 PIC17C42 RAO and RA2 and RA4 and RA5 RB3 RB2 Port Pins 56 RB7 RB4 RB1 RBO Port Pins 55 RC7 RCO Port Pins 58 Timer3 with One Capture and One Period Register 78 TMR1 and TMR2 in 16 bit Timer Counter Mode 74 TMR1 and TMR2 in Two 8 bit Timer Counter Mode 73 TMR3 with Two Capture Registers 79 104 BORROW UT EE IE LEE 9 mener 86 Brown out Protection 2 18 ten ee edet a OP 115 34 42 Operation 42 BTESQ 115 Nit V A Et 116 BUG om oie en Cs et Y Re edes rt ROREM 116 C c REA 9 36 C Compiler MP C
304. t Tools The PIC16 17 microcontrollers are supported with a full range of hardware and software development tools PICMASTER PICMASTER CE Real Time In Circuit Emulator Low Cost PIC16C5X and PIC16CXXX In Circuit Emulator PRO MATE Universal Programmer PICSTART Plus Entry Level Prototype Programmer PICDEM 1 Low Cost Demonstration Board PICDEM 2 Low Cost Demonstration Board PICDEM 3 Low Cost Demonstration Board MPASM Assembler MPLAB SIM Software Simulator MPLAB C C Compiler Fuzzy logic development system fuzzy TECH MP 16 2 PICMASTER High Performance Universal In Circuit Emulator with MPLAB IDE The PICMASTER Universal In Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers the PIC12C5XX 14000 PIC16C5X PIC16CXXX and PIC17CXX families PICMASTER is supplied with the MPLAB Integrated Development Environment IDE which allows editing make and download and source debugging from a single environment Interchangeable target probes allow the system to be easily reconfigured for emulation of different proces sors The universal architecture of the PICMASTER allows expansion to support all new Microchip micro controllers PICMASTER Emulator System has been designed as a real time emulation system with advanced features that are generally found on more expensive
305. t clock is supplied The second word will remain in TXREG TXIF will not be set When the first word has been shifted out of TSR TXREG will transfer the second word to the TSR and the TXIF flag will now be set If TXIE is enabled the interrupt will wake the chip from SLEEP and if the global interrupt is enabled then the program will branch to interrupt vector 0020h Steps to follow when setting up a Synchronous Slave Transmission 1 Enable the synchronous slave serial port by set ting the SYNC and SPEN bits and clearing the CSRC bit 2 Clear the CREN bit If interrupts are desired then set the TXIE bit 4 f 9 bit transmission is desired then set the TX9 bit 5 Start transmission by loading data to TXREG 6 f 9 bit transmission is selected the ninth bit should be loaded in TX9D 7 Enable the transmission by setting TXEN Writing the transmit data to the TXREG then enabling the transmit setting TXEN allows transmission to start sooner then doing these two events in the reverse order Note To terminate transmission either clear the SPEN bit or the TXEN bit This will reset the transmit logic so that it will be in the proper state when transmit is re enabled 13 4 2 USART SYNCHRONOUS SLAVE RECEPTION Operation of the synchronous master and slave modes are identical except in the case of the SLEEP mode Also SREN is a don t care in slave mode If receive is enabled CREN
306. t is 0 the next instruction which is already fetched is discarded and an NOP is executed instead mak ing it a two cycle instruction Description Words 1 Cycles 1 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example HERE DECFSZ CNT 1 GOTO LOOP CONTINUE Before Instruction PC Address HERE After Instruction CNT CNT 1 If CNT 0 PC Address CONTINUE If CNT 0 Address HERE 1 1996 Microchip Technology Inc DS30412C page 121 PIC17C4X DCFSNZ Decrement f skip if not 0 Syntax DCFSNZ Operands 0 lt lt 255 d 0 1 Operation f 1 dest skip if not 0 Status Affected None Encoding 0010 0114 ffff ffff Description The contents of register f are decre mented If d is 0 the result is placed in WREG If d is 1 the result is placed back in register f If the result is not 0 the next instruction which is already fetched is discarded and an NOP is executed instead mak ing it a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination If skip Q1 Q2 Q3 Q4 Forced NOP NOP Execute NOP Example HERE DCFSNZ TEMP 1 ZERO NZERO Before Instruction TEMP VALUE 2 After Instruction TEMP VALUE TEMP VALUE 1 If TEMP VALUE 0 PC Address ZERO ITEMP VALUE 0 PC Address NZERO
307. t this bit bit 4 GLINTD Global Interrupt Disable bit This bit disables all interrupts When enabling interrupts only the sources with their enable bits set can cause an interrupt 1 Disable all interrupts 0 Enables all un masked interrupts bit3 TO WDT Time out Status bit 1 After power up or by a CLRWDT instruction 0 2 A Watchdog Timer time out occurred bit2 PD Power down Status bit 1 After power up or by the CLRWDT instruction 0 By execution of the SLEEP instruction bit 1 0 Unimplemented Read as 0 1996 Microchip Technology Inc DS30412C page 37 PIC17CAX 62 23 TMROSTATUS CONTROL REGISTER TOSTA This register contains various control bits INTEDG is used to control the edge upon which a sig nal on the RAO INT pin will set the RBO INT interrupt flag The other bits configure the TimerO prescaler and clock source Figure 11 1 FIGURE 6 9 05 REGISTER ADDRESS 05h UNBANKED RW 0 R W O0 R W O0 R W O0 R W O 0 RW O 0 0 INTEDG 05 TOCS PS3 PS2 PS1 50 R Readable bit bit7 bit0 W Writable bit U Unimplemented reads as 0 n Value at POR reset bit 7 INTEDG RAO INT Pin Interrupt Edge Select bit This bit selects the edge upon which the interrupt is detected 1 Rising edge of RAO INT pin generates interrupt 0 Falling edge of RAO INT pin generates interrupt bit6 TOSE TimerO Clock Input Edge
308. ta bits and one stop bit The most common data for mat is 8 bits An on chip dedicated 8 bit baud rate gen erator can be used to derive standard baud rate frequencies from the oscillator The USART s transmit ter and receiver are functionally independent but use the same data format and baud rate The baud rate generator produces a clock x64 of the bit shift rate Par ity is not supported by the hardware but can be imple mented in software and stored as the ninth data bit Asynchronous mode is stopped during SLEEP The asynchronous mode is selected by clearing the SYNC bit TXSTA lt 4 gt The USART Asynchronous module consists of the fol lowing important elements Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver 13 2 1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 13 3 The heart of the transmitter is the transmit shift register TSR The shift register obtains its data from the read write transmit buffer TXREG is loaded with data in software The TSR is not loaded until the stop bit has been transmitted from the previous load As soon as the stop bit is transmitted the TSR is loaded with new data from the if available Once TXREG transfers the data to the TSR occurs in one Tcv at the end of the current BRG cycle the TXREG is empty and an interrupt bit TXIF PIR lt 1 gt is set This interrupt can be enab
309. ted Operating temperature 40 C lt lt 85 for industrial and lt TA 70 for commercial Parameter No Sym Characteristic Min Typf Units Conditions D001 VDD Supply Voltage 4 5 6 0 V D002 VDR RAM Data Retention 1 5 V Device in SLEEP mode Voltage Note 1 D003 VPOR VDD start voltage to Vss V See section on Power on Reset for ensure internal details Power on Reset signal D004 SvDD VDD rise rate to 0 060 mV ms See section on Power on Reset for ensure internal details Power on Reset signal D010 IDD Supply Current 3 6 mA Fosc 4 MHz Note 4 0011 Note 2 6 12 mA Fosc 8 MHz 0012 11 124 mA Fosc 16 MHz 0013 19 38 mA Fosc 25 MHz 0015 25 50 mA Fosc 33 MHz D014 95 150 uA Fosc 32 kHz WDT enabled EC osc configuration D020 IPD Power down 10 40 uA 5 5V WDT enabled 0021 Current Note 3 lt 1 5 VDD 5 5 WDT disabled These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data The supply current is mainly a function of the operating voltage and frequency Other factors such as pin loading and switching rate oscillator type internal code execution pattern and temperatu
310. the 8 bit literal K The result is placed in WREG Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Execute Write to WREG Example ANDLW 0x5F Before Instruction WREG 0 After Instruction WREG 0x03 1996 Microchip Technology Inc DS30412C page 113 PIC17C4X BCF Bit Clear f Syntax label Operands lt lt 255 0 lt 0 lt 7 Operation 0 gt lt gt Status Affected Encoding 1000 lbbb ffff Description Bit b in register f is cleared Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write register f register f Example BCF FLAG REG 7 ANDWF AND WREG with f Syntax abel ANDWF Operands 0 lt 1 lt 255 de 0 1 Operation WREG AND f dest Status Affected 7 Encoding 0000 101d ffff Description The contents of WREG are AND ed with register f If d is 0 the result is stored in WREG If d is 1 the result is stored back in register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Execute Write to register f destination Example ANDWF REG 1 Before Instruction WREG 0x17 REG 0xC2 After Instruction WREG 0x17 REG 0x02 Before Instruction FLAG REG 0xC7 After Instruction FLAG REG 0x47 DS30412C page 114 1996 Microchip Technology Inc PIC17C4X BSF Bit Set f Syntax label BSF f b O
311. timings involved with the oscillator start up timer In this example the low frequency crystal start up time is larger than power up time TPWRT Tosc1 time for the crystal oscillator to react to an oscillation level detectable by the Oscillator Start up Timer ost Tosr 1024Tosc down R 40 is recommended to ensure that the voltage drop across R does not exceed 0 2V max leakage current spec on the MCLR VPP pin is 5 uA A larger voltage drop will degrade VIH level on the FIGURE 4 6 USING ON CHIP POR MCLH VPP pin 3 R121000 to 1 will limit any current flowing into MCLR from external capaci tor C in the event of MCLR VPP pin breakdown due to Electrostatic Dis charge ESD or Electrical Overstress EOS PIC17CXX FIGURE 4 9 BROWN OUT PROTECTION FIGURE 4 7 BROWN OUT PROTECTION CIRCUIT 2 CIRCUIT 1 R1 5 Q1 He E 40 PIC17CXX PIC17CXX This brown out circuit is less expensive albeit less accurate Transistor Q1 turns off when VDD is below a certain level such that R1 vui ME guy E T This circuit will activate reset when VDD goes below Vz 0 7V where Vz Zener voltage DS30412C page 18 1996 Technology Inc PIC17C4X TABLE 4 4 INITIALIZATION CONDITIONS FOR SPECIAL
312. timized system 16 16 TrueGauge Intelligent Battery Management The TrueGauge development tool supports system development with the MTA11200B TrueGauge Intelli gent Battery Management IC System design verifica tion can be accomplished before hardware prototypes are built User interface is graphically oriented and measured data can be saved in a file for exporting to Microsoft Excel 16 17 Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products The HCS eval uation kit includes an LCD display to show changing codes a decoder to decode transmissions and a pro gramming interface to program test transmitters 1996 Microchip Technology Inc DS30412C page 145 PIC17CAX DEVELOPMENT TOOLS FROM MICROCHIP TABLE 16 1 LOOSOEWA 10090 94 VIN VIN LOE 006 00250 V N V N V N 100 5 leues V N V N VIN z Ajunoes Ajunoes 5 e1vA33S 19npoid sjequunu ped 10 suleis s jueuidoje ep jejeredes 4954008 IVIN Jejquiessy INSVdIN e oqe
313. tor Start up Timer OST PIC17CR43 4K 454 Watchdog Timer WDT with its own on chip RC PIC17C44 8K 454 oscillator for reliable operation PIC17C42T 2K 232 e Code protection Hardware Multiplier Power saving SLEEP mode Not available on the PIC17C42 Selectable oscillator options Interrupt capability CMOS Technology 16 levels deep hardware stack L TM CMOS EPROM ROM Direct indirect and relative addressing modes EOW HOWER high speed technology Internal External program memory execution Fully static design 64K x 16 addressable program memory space Wide operating voltage range 2 5V to 6 0V Peripheral Features Commercial and Industrial Temperature Range 33 I O pins with individual direction control Low power consumption High current sink source for direct LED drive lt 5 mA BV 4 MHz RA2 and are open drain high voltage 100 uA typical 4 5V 32 kHz 12V high current 60 mA lt 1 uA typical standby current 5V Two capture inputs and two PWM outputs Captures are 16 bit max resolution 160 ns PWM resolution is 1 to 10 bit TMRO 16 bit timer counter with 8 bit programma ble prescaler TMR1 8 bit timer counter TNOT recommended for new designs use 17 42 1996 Microchip Technology Inc DS30412C page 1 mm 1 1 AMA PIC17C4X Pin Diagrams RC4 AD4 RCS ADS RC6 AD6 RC7 AD7 Vss Vss RBO CAP1 RB1 CAP2
314. ture2 register the master overflow bit is transferred to the slave overflow bit CA2OVF and then the master bit is reset The user can then read TCON2 to determine the value of 2 The operation of the Capture1 feature is identical to Capture2 as described in Section 12 2 1 FIGURE 12 8 TIMER3 WITH TWO CAPTURE REGISTERS BLOCK DIAGRAM CA1ED1 CA1EDO 1 lt 5 4 gt 2 Edge Select Prescaler Select 1 Fosc 4 TMR3ON 2 lt 2 gt Enable De Capture Enable Set PIR lt 2 gt PR3H CA1H PR3L CA1L Set TMRSIF lt 6 gt mll TMR3H TCON1 lt 2 gt Edge Select Select RB1 CAP2 Set CA2IF PIR lt 3 gt CA2ED1 CA2EDO TCON1 lt 7 6 gt gt TABLE 12 5 REGISTERS ASSOCIATED WITH CAPTURE Valueon Value on all Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Power on other resets Reset Note1 16h Bank3 CA2ED1 CA2EDO 1 CA1EDO T16 TMR2CS TMR1CS 0000 0000 0000 0000 17h 2 2 PWM2ON PWM1ON THR2ON TMR1ON 0000 0000 0000 0000 12h Bank 2 TMR3L register low b
315. uency Hz 1996 Microchip Technology Inc DS30412C page 167 PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 18 9 TYPICAL IPD vs WATCHDOG DISABLED 25 C 5 5 VDD Volts DS30412C page 168 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18 11 TYPICAL IPD vs VoD WATCHDOG ENABLED 25 C TEF VDD Volts FIGURE 18 12 MAXIMUM IPD vs WATCHDOG ENABLED 5 5 Volts 0830412 169 1996 Microchip Technology Inc PIC17C4X Applicable Devices 42 R42 42A 43 43 44 FIGURE 18 13 WDT TIME OUT PERIOD vs WDT Period ms Min 40 C 5 5 Volts 1 5 Volts ILCBC RL LGLCLLLYELIRR OOOLLLL CEELOELLLLELEEEHIQQII LLLOULL EIL LOL L CTZTCIQC COQ ECLLLLOUTI I EGORELLLL EULLLEGLOLUL LOLLULCE CRLE CESILALILG RLCOBDILLLOOTELOOQRPERECL DS30412C page 170 1996 Technology Inc PIC17C4X Applicable Devices 42 R42 42A
316. write incremented EXAMPLE 7 1 TABLE WRITE Note If an interrupt is pending or occurs during the TABLWT the two cycle table write FERME fiscus completes The RAO INT or TOCKI 5 4 0 Lis interrupt flag is automatically cleared MOVLW LOW TBL ADDR the pending peripheral interrupt is MOVWE TBLPTRL acknowledged MOVLW HIGH DATA Load HI byte TLWT 1 WREG TABLATCH MOVLW LOW DATA Load LO byte TABLWT 0 0 WREG in TABLATCH write to program memory H Ext SRAM FIGURE 7 5 TABLWT WRITE TIMING EXTERNAL MEMORY 03 ara as lo as os ra AD15 ADO Instruction fetched TABLWT INST PC 1 Instruction executed TABLWT 1 TABLWT cycle2 Data write E Note f external write GLINTD 1 Enable bit 1 1 Flag bit Do table write The highest pending interrupt is cleared DS30412C page 46 1996 Technology Inc PIC17C4X FIGURE 7 6 CONSECUTIVE TABLWT WRITE TIMING EXTERNAL MEMORY Q4 Q4 Q4 Q4 Q4 Q4 AD15 ADO 7 6 eX Instruction i i fetched i TABLWT1 TABLWT2 i INST PC 2 INST PC 3 pee INST PC 1 TABLWT1 1 1
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318. x 16 of EPROM program memory on chip while the PIC17CR42 has 2K x 16 of ROM program memory on chip The PIC17C43 integrates 4K x 16 of EPROM program memory while the PIC17CR43 has x 16 of ROM program memory The 17 44 integrates 8K x 16 EPROM program memory Program execution can be internal only microcontrol ler or protected microcontroller mode external only microprocessor mode or both extended microcon troller mode Extended microcontroller mode does not allow code protection The PIC17CXX can directly or indirectly address its register files or data memory All special function regis ters including the Program Counter PC and Working Register WREG are mapped in the data memory The PIC17CXX has an orthogonal symmetrical instruction set that makes it possible to carry out any operation on any register using any addressing mode This symmetrical nature and lack of special optimal sit uations make programming with the PIC17CXX simple yet efficient In addition the learning curve is reduced significantly One of the PIC17CXX family architectural enhance ments from the PIC16CXX family allows two file regis ters to be used in some two operand instructions This allows data to be moved directly between two registers without going through the WREG register This increases performance and decreases program mem ory usage The PIC17CXX devices contain an 8 bit ALU and work ing register The ALU is a
319. y RCREG is a dou ble buffered register i e it is a two deep FIFO It is possible for two bytes of data to be received and trans ferred to the RCREG FIFO and a third byte to begin shifting into the RSR On the clocking of the last bit of the third byte if RCREG is still full then the overrun error bit OERR RCSTA lt 1 gt is set The word in the RSR will be lost RCREG can be read twice to retrieve the two bytes in the FIFO The OERR bit has to be cleared in software This is done by clearing the CREN bit If OERR bit is set transfers from RSR to RCREG are inhibited so it is essential to clear OERR bit if it is set The 9th receive bit is buffered the same way as the receive data Reading the RCREG register will allow the RX9D and FERR bits to be loaded with values for the next received data therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old FERR and RX9D information Steps to follow when setting up a Synchronous Master Reception 1 Initialize the SPBRG register for the appropriate baud rate See Section 13 1 for details 2 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC 3 If interrupts are desired then set the RCIE bit 4 f9 bit reception is desired then set the RX9 bit 5 If a single reception is required set bit SREN For continuous reception set bit CREN 6 The RCIF bit will be set when reception is com plete and
320. ycle begins with the program counter incre menting in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write Xo yf Internal phase clock OSC2 CLKOUT RC mode Fetch INST PC Execute INST PC 1 Fetch INST PC 1 Execute INST PC Fetch INST 2 Execute INST EXAMPLE 3 2 INSTRUCTION PIPELINE FLOW TcyO 1 Tcy2 Tcy3 MOVLW 55h Fetch 1 Execute 1 MOVWF PORTB Fetch 2 Execute 2 CALL SUB 1 Fetch 3 Execute 3 BSF PORTA BIT3 Forced NOP Fetch 4 Flush Fetch SUB 1 Execute SUB 1 Instruction address SUB 1 All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed DS30412C page 14 1996 Microchip Technology Inc PIC17C4X 4 0 RESET PIC17CXX differentiates between various kinds of reset Power on Reset POR MCLR reset during normal operation WDT Reset normal operation Some registers are not affected in any reset condition their status is unknown on POR and unchanged in any other re
321. yte XXXX XXXX uuuu uuuu 13h Bank 2 register high byte XXXX XXXX uuuu uuuu 16h Bank 1 PIR RBIF TMR3IF TMR2IF TMR1IF CA2IF 0000 0010 0000 0010 17 1 RBIE TMR2IE TMR1IE CA2IE 0000 0000 0000 0000 07h Unbanked INTSTA PEIF TOCKIF TOIF INTF PEIE TOCKIE TOIE INTE 0000 0000 0000 0000 06h Unbanked CPUSTA STKAV GLINTD TO PD 11 11 11 qq 16h Bank 2 PR3L CA1L Timer3 period register low byte capture1 register low byte XXXX uuuu uuuu 17h Bank 2 PR3H CA1H Timer3 period register high byte capture1 register high byte XXXX XXXX uuuu uuuu 14h Bank 3 CA2L Capture2 low byte XXXX XXXX uuuu uuuu 15h Bank 3 CA2H Capture2 high byte XXXX XXXX uuuu uuuu Legend x unknown u unchanged unimplemented read as 0 q value depends on condition shaded cells are not used by Capture Note 1 Other non power up resets include external reset through MCLR and WDT Timer Reset 1996 Microchip Technology Inc DS30412C page 79 PIC17C4X 12 2 3 EXTERNAL CLOCK INPUT FOR TIMER3 EXAMPLE 12 2 WRITING TO TMR3 When TMR3CS is set the 16 bit TMR3 increments on BSF CPUSTA GLINTD Disable interrupt the falling edge of clock input The input on the MOVEP RAM TMRSL MOVFP RAM TMR3H RB5 TCLK3 pin is sampled and synchronized by the CPUSTA GLINTD Done enable
322. zy logic development tool is avail able in two versions a low cost introductory version MP Explorer for designers to gain a comprehensive working knowledge of fuzzy logic system design and a full featured version fuzzyTECH MP edition for imple menting more complex systems Both versions include Microchip s fuzzyLAB demon stration board for hands on experience with fuzzy logic Systems implementation 16 14 MP DriveWay Application Code Generator MP DriveWay is an easy to use Windows based Appli cation Code Generator With MP DriveWay you can visually configure all the peripherals in a PIC16 17 device and with a click of the mouse generate all the initialization and many functional code modules in C language The output is fully compatible with Micro chips MPLAB C C compiler The code produced is highly modular and allows easy integration of your own code MP DriveWay is intelligent enough to maintain your code through subsequent code generation 16 15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designers Kit supports all Microchip 2 wire and 3 wire Serial EEPROMs The kit includes everything necessary to read write erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials The Total Endurance Disk is included to aid in trade off analysis and reliability calculations The total kit can significantly reduce time to market and result in an op

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MICROCHIP PIC17C4X handbook

MICROCHIP PIC17C4X handbook

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