MAXIM MAX3831/MAX3832 handbook
Contents
1. TQFP EP Chip Information TRANSISTOR COUNT 14 134 12 MAXIM 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator Package Information VIEW BOTTOM VIEW a T Pa MAX EXPOSED PAD CORNER TAB DETAIL AVI ZA XI ZI VI PROPRIETARY INFORMATION PACKAGE DUTLINE 64L 10 10 1 0 MM TQFP EXPOSED PAD 21 0084 MAXIM 13 cESEXVW LESEXVIW MAXS3831 MAX3832 4H3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator Package Information continued NOTES ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14 5 1988 DATUM PLANE H JIS LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE DIMENSIONS 21 AND EL DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE MOLD PROTRUSION IS 0254 MM ON D1 AND E1 DIMENSIONS THE TOP OF PACKAGE IS SMALLER THAN THE BOTTOM OF PACKAGE BY 0 15 MILLIMETERS DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 008mm TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION CONTROLLING DIMENSION MILLIMETER THIS OUTLINE CONFORMS TO PUBLICATION 95 REGISTRATION MO 136 VARIATION AJ EXPOSED DIE PAD SHALL BE COPLANAR WITH BOTTOM OF PACKAGE WITHIN 2 MILS C05 MM LEADS SHALL BE COPLANAR WITHIN 004 INCH JEDEC VARIATION a on DIMENSIONS IN MILLIMETERS a oe 18 5 EN 045 SVIAMAILSVI2. amp 100 20 CT TERES 2 50 amp 0 0 50 25 0 25 50 75 10 40 25 0 25 50 75 100 TEMPERATURE C TEMPERATURE MAXIM 5 MAXS3831 MAX3832 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator Pin Description PIN NAME FUNCTION 1 16 25 28 29 32 43 48 GND Supply Ground 49 60 63 2 5 10 13 17 24 38 55 Vcc 3 3V Supply Voltage 59 64 3 SDO Negative CML Serial Data Output 2 488Gbps 4 SDO Positive CML Serial Data Output 2 488Gbps Line Loopback Enable When this TTL input is forced low the CML serial data inputs SDI 6 LBEN route directly to the CML serial data outputs SDO No other inputs or outputs are affected An internal 15kQ pull up resistor pulls LBEN high for normal operation See Test Loopbacks Self Test Enable When this TTL input is forced low the built in pattern generator generates a standard OC 12 SONET like frame of 12 A1s 12 A2s and 9696 bytes of 27 1 pseudo 7 TEST random bits This also enables an internal serial system loopback path The CML inputs 501 and the SCLK and the LVDS inputs are ignored in this mode An internal 15kQ pull up resistor pulls TEST high for normal operation 8 501 Positive CML Serial Data Input 2 488Gbps 9 SDI egative CML Serial Data Input 2 488Gbps 11 SCLKI Positive CML Serial Clock Input 2 488GHz
3. PROPRIETARY INFORMATION 64L TOFP EXPOSED PAD DOCURENT CONTROL NO 2 P ER 14 MAXIM 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator NOTES MAXIM 15 cESEXVW LESEXVIW MAXS3831 MAX3832 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 16 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 1999 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products
4. amp the latest literature http www maxim ic com or phone 1 800 998 8800 For small orders phone 1 800 835 8769 cESEXVW LESEXVIW MAXS3831 MAX3832 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage Input Voltage LVDS TTL CML Input Voltage Vcc 0 8V to FIL FIL TTL Output Voltage LVDS Output Voltage See 0 5V to Vcc 0 5V 0 5V to 0 5V to 5 0V 0 5V to Vcc 0 5V Voc 0 5V 0 5V is 0 5V to Vcc 0 5V CML Output Currents ssssssssseeeeeeeee 22mA Continuous Power Dissipation TA 85 Note 1 64 TQFP EP derate 40 0mW C above 85 2 6W Operating Temperature 0 C to 85 C Storage Temperature Range 60 C to 150 C Lead Temperature soldering 105 300 C Note 1 Based on empirical data from the MAX3831 MAX3832 evaluation kit Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not
5. and the frame search continues Figure 6 In frame will be declared if two consecutive framing patterns are found at the correct byte locations within the SONET frame 9720 bytes If this pattern is not pre 7 cESEXVW LESEXVIW MAXS3831 MAX3832 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator RSETES 155MHz RCLKI 155MHz FIL MAXIM ROLK 622MHz PATTERN ENERATOR MAX3831 MAX3832 FREQUENCY ENERATOR LINE LOOPBACK 2 488Gbps SYSTEM LOOPBACK TEST 2 488Gbps 2 488GHz SCLKI DETECTOR ee CLOCK GENERATOR ROTATE SCLKI 622MHz 0 155MHz RSETFR DATA OUTPUT OF ELASTIC STORE AT t ty DATA OUTPUT OF ELASTIC STORE ATt gt to Figure 5 Example of Elastic Store Function sent at the correct location false frame the state machine will return to the frame_search state described above While in the in_frame state each frame will be checked for a framing pattern at the correct location Four consecutive false frames will cause the state machine to return to the frame_search state described above The false frame counter is reset with three or fewer consecutive false frames Built in Self Test with On Chip Serial Loopback An on chip pattern generator can be enabled to pr
6. 12 SCLKI egative CML Serial Clock Input 2 488GHz 14 PCLKO egative LVDS Parallel Clock Output 622 08MHz MAX3831 155 52MHz MAX3832 15 PCLKO Positive LVDS Parallel Clock Output 622 08MHz MAX3831 155 52MHz MAX3832 18 23 26 27 N C o Connection Frame Reset When this TTL input is forced low the frame detector and pattern generator 30 HSETFR are reset The LOF output is also asserted low An internal 15kQ pull up resistor pulls RSETFR high for normal operation 31 LOF TTL Loss of Frame Output Asserts low in a loss of frame condition 33 THIEN 3 State Enable When this TTL input is forced low all TTL and LVDS outputs go into a high impedance state An internal 15kQ pull up resistor pulls TRIEN high for normal operation 34 36 39 41 PDO4 to PDO1 egative LVDS Parallel Data Output 622Mbps 35 37 40 42 PDO4 to PDO1 Positive LVDS Parallel Data Output 622Mbps 44 46 50 52 PDIA to PDI1 egative LVDS Parallel Data Input 622Mbps 45 47 51 53 014 to PDI1 Positive LVDS Parallel Data Input 622Mbps Parallel System Loopback Enable When this TTL input is forced low the LVDS parallel 54 PLBEN inputs route through the elastic store to the LVDS parallel outputs This bypasses the high speed mux and demux An internal 15kQ pull up resistor pulls PLBEN high for normal oper ation 56 RCLKI egative LVDS Reference Clock Input 155 52MHz 57 RCLKI Positive LVDS Reference Clock Input 155 52MHz MAXIM 3 3V
7. 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator Pin Description continued PIN NAME FUNCTION Elastic Store Reset The elastic buffer is centered on a rising edge of RSETES maximizing 58 HSETES he elastic store range Data must be present for 10us before applying a pulse of at least 10ns An internal 15kQ pull up resistor pulls RSETES high for normal operation 61 FIL egative PLL Filter Capacitor Input Connect a O 33pF capacitor between FIL and FIL 62 FIL Positive PLL Filter Capacitor Input Connect a 0 33uF capacitor between FIL and FIL E Exposed Paddle Ground This must be soldered to a circuit board for proper thermal performance see Package Information Detailed Description The MAX3831 MAX3832 use a 4 1 mux and 1 4 demux with an elastic store buffer to simplify SDH SONET interconnect I O routing The 622Mbps low voltage dif ferential signal LVDS parallel inputs pass through the 10 bit elastic store buffer which accommodates 7 5ns skew on any single input relative to the 155MHz refer ence clock input RCLKI This reference clock is required to synthesize the internal 2 488GHz clock used to drive the elastic store and 4 1 multiplexer All TTL and LVDS outputs can be placed in a high imped ance state See Figure 4 for a functional diagram The 4 1 mux bit interleaves the parallel data providing a 2 488Gbps CML serial output to the optical or electr
8. 50 SDI v 400mVp p MIN ID 4200mVp p MAX Figure 2 Definition of the CML Input tsciK 1 fscik PD01 PD04 NOTE SIGNAL SHOWN IS DIFFERENTIAL FOR EXAMPLE SCLKI SCLKI SCLKI Figure 3 Timing Parameters 4 MAXIM 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator Typical Operating Characteristics Vcc 3 3V TA 25 C unless otherwise noted SERIAL DATA OUTPUT EYE DIAGRAM SERIAL DATA OUTPUT JITTER SUPPLY CURRENT vs TEMPERATURE D e e e e MAX3831 2 toc03 cESEXVW LESEXVIW A 223 4 PRBS PATTERN e e SUPPLY CURRENT mA S WIDEBAND RMS JITTER 2 48ps 100 50ps div 5ps div 50 25 0 25 50 75 100 TEMPERATURE C ELASTIC STORE RANGE SERIAL DATA HOLD TIME 2 10 E 100 g a B 8 2 6 80 8 m 60 gt Ex ERROR FREE OPERATION E ao 0 40 lt E 2 5 4 20 a CHANNEL ALIGNED TO RCLKI E 0 uper gt 10 20 0 02 04 06 08 10 12 14 16 50 25 0 25 50 75 100 DATA TO RCLKI DELAY AT RESET ns TEMPERATURE MAX3831 PARALLEL CLOCK TO DATA OUTPUT SERIAL DATA SETUP TIME PROPAGATION DELAY vs TEMPERATURE 100 300 5 3 2 3 30 H 250 t zl 200 60 E 150 5 amp tu 40
9. Voc Voc 0 6 0 4 Differential Input Voltage Swing Figure 2 400 1200 mVp p Differential Input Impedance 85 100 115 Q 2 MAXIM 13 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator DC ELECTRICAL CHARACTERISTICS continued Vcc 3 0V to 3 6V LVDS differential load 1000 196 CML load 500 1 to Vcc all TTL inputs are open TA 0 C to 85 C unless otherwise noted Typical values are at TA 25 C and Vcc 3 3V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TTL INPUTS AND OUTPUTS Input Voltage High 2 0 V Input Voltage Low VIL 0 8 V Input Current High 2 0 250 50 HA Input Current Low liL Vip 20 550 100 HA Output Voltage High 200A 2 4 V Output Voltage Low VOL loL 2mA 0 4 V Output Impedance TRIEN GND 6 Note 2 When TEST GND the pattern generator will consume an additional 30mA Note 3 Guaranteed by design and characterization AC ELECTRICAL CHARACTERISTICS Vcc 3 0 to 3 6V LVDS differential load 1000 196 CML load 500 1 to Vcc all TTL inputs are open TA 0 C to 85 C unless otherwise noted Typical values are at TA 25 C and Vcc 3 3V Note 4 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4 1 MULTIPLEXER WITH CLOCK GENERATOR Parallel Input Data Rate 622 08 Mbps Max
10. AA MAXILLA AVLAZCLAI 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator General Description The MAX3831 MAX3832 are 4 1 multiplexers muxes and 1 4 demultiplexers demuxes with automatic chan nel assignment Operating from a single 3 3V supply the mux receives four parallel 622Mbps SDH SONET channels These channels are bit interleaved to gener ate a serial data stream of 2 488Gbps for interfacing to an optical or an electrical driver A 10 bit wide elastic buffer tolerates up to 7 5ns skew between any parallel data input and the reference clock An external 155MHz reference clock is required for the on chip PLL to synthesize a high frequency 2 488GHz clock for tim ing the outgoing data streams The MAX3831 MAX3832 s demux receives 2 488Gbps serial data and the 2 488GHz clock from an external clock data recovery device MAX3876 converting it to four 622Mbps LVDS outputs The MAX3831 provides a 622MHz LVDS clock output and the MAX3832 pro vides a 155MHz LVDS clock output An internal frame detector looks for a 622Mbps SDH SONET framing pat tern and rolls the demux to maintain proper channel assignment at the outputs These devices also include an embedded pattern gen erator that enables a full speed built in self test BIST Two different loopback modes provide system test flexi bility A TTL loss of frame monitor is included The MAX3831 MAX3832 are available in 64 pin TQFP EP e
11. i cal driver The CML serial input receives the 2 488Gbps data the demux deinterleaves it to 622Mbps and sends the data to the frame detector The frame detector monitors one 622Mbps channel and rolls the demux into the proper channel assignment The MAX3831 MAX3832 include high speed built in self test BIST which also allows testing of the 622Mbps parallel system loopback and the 2 488Gbps line loopback Elastic Store Buffer Each parallel data input PDI1 to PDI4 passes through its respective 10 bit elastic store buffer Following an elastic store reset this buffer accommodates 7 5ns of skew on any input relative to the 155MHz reference clock Figure 5 illustrates the elastic store buffer rela tionship with RCLKI The Elastic Store Range graph in the Typical Operating Characteristics shows the amount of data skew tolerated Following a 10us power up period the locations of the individual data channel bit transitions are acquired guaranteeing data preservation The output of this block passes directly into the 4 1 mux After power up the elastic store buffer must be reset by applying a low pulse on RSETES for at least 10ns MAXIM Due to the inherent uncertainty of the data transitions between the parallel data inputs there is no bit or frame alignment between these inputs However the demux ensures proper channel assignment is maintained Bit Interleaved Multiplexer Demultiplexer The MAX3831 MAX3832 use a bit inter
12. implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability DC ELECTRICAL CHARACTERISTICS Vcc 3 0V to 3 6V LVDS differential load 1000 196 CML load 500 1 to Vcc all TTL inputs are open TA 0 C to 85 C unless otherwise noted Typical values are at TA 25 Vcc 3 3V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS i MAX3831 440 580 Supply Current Icc pean Y pr A MAX3832 480 614 US LVDS INPUTS AND OUTPUTS Input Voltage Range VIN 0 2400 mV Differential Input Threshold VIDTH 100 100 mV Threshold Hysteresis VHYST 90 mV Input Impedance RIN 85 100 115 Q Input Common Mode Current los LVDS input Vos 1 2V 270 UA Output Voltage High VOH 1 475 V Output Voltage Low VOL 0 925 V Differential Output Voltage Figure 1 250 400 mV Change in Magnitude of Differential Output Voltage for AlVool 25 mV Complementary States Output Offset Voltage Vos 1 125 1 275 V Change in Magnitude of Output Offset Voltage for Complementary AlVos 25 mV States TRIEN GND gt 1 MQ Differential Output Impedance RIEN Vcc 80 120 Q Output Current Short outputs together Note 3 12 mA CML INPUTS AND OUTPUTS Differential Output Voltage VODp p 640 800 1000 mVp p Differential Output Impedance 85 100 115 Q Output Common Mode Voltage Vcc 0 2 V Single Ended Input Voltage Range
13. imum Parallel Input Skew tes Note 5 7 5 ns Serial Data Output Rate 2 48832 Gbps Serial Data Output Rise Fall Time tr tf 2096 to 80 120 ps Serial Data Output Random Jitter SRJ Note 6 20 pm 40 pSp p nus Data Output Deterministic SDJ Note 7 8 18 pSp p 1 4 DEMULTIPLEXER Serial Data Input Rate 2 48832 Gbps Serial Data Setup Time tsu Figure 3 100 ps Serial Data Hold Time tH Figure 3 100 ps Parallel Data Output Rate PDO 622 08 Mbps MAX3831 622 08 Parallel Clock Output Frequency PCLKO MHz MAX3832 155 52 PCLKO to PDO_ Delay tcLK Q MAX3831 Figure 100 90 300 ps LVDS Output Rise Fall Time 20 to 80 350 ps LVDS Differential Skew SKEW1 Any differential pair 65 ps LVDS Channel to Channel Skew skEW2 PDO1 to PDO4 100 ps LVDS Three State Enable Time 30 ns Note 4 AC characteristics are guaranteed by design and characterization Note 5 Relative to the positive edge of the 155MHz reference clock PDI1 to PDI4 aligned to RCLKI at reset Note 6 Measured with a reference clock jitter of 1psmMs Note 7 Deterministic jitter is the arithmetic sum of pattern dependent jitter and pulse width distortion MAXIM 3 cESEXVW LESEXVIW MAXS3831 MAX3832 13 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator 1000 SINGLE ENDED OUTPUT DIFFERENTIAL OUTPUT Figure 1 Definition of the LVDS Output 200mV MIN BB 600mV
14. leave deinterleave mux demux To guarantee channel assignment one of the four channels is inverted before multiplexing to pro vide a reference for the frame detector during demulti plexing After demultiplexing the same channel is inverted back to the original data format Frame Detector After a 2 5Gbps serial data is bit deinterleaved into four 622Mbps channels an SDH SONET frame detector monitors the fourth channel looking for the 32 bit pat tern A1A1A2A2 in the OC 12 header To maintain cor rect channel assignment the demux outputs rotate until this 32 bit overhead pattern is reliably detected A loss of frame output LOF indicates when the received data is in or out of frame When LOF goes high the frame pattern is detected and the demux outputs are correct ly assigned When LOF is low the frame detection cir cuitry is searching for the correct frame A RSETFR TTL active low is included to reset the frame detector when necessary The frame detector uses an algorithm to detect an in frame condition and a loss of frame condition this algo rithm is implemented to meet the SONET in frame and false frame specs The frame search state will occur upon start up or reset In this state the frame detector scans through the incoming serial data searching for the framing pattern in the channel 4 output of the demux While in this state if the framing pattern is not found within 250us the demux channels are shifted rolled
15. ling the pattern generator and accepting data from the parallel input channels Test Loopbacks Two additional test loopbacks are provided parallel system loopback and serial line loopback Parallel System Loopback In parallel system loopback four 622Mbps parallel input channels are phase aligned by an associated 10 bit elastic store and routed to the output LVDS buffers This loopback is controlled by setting PLBEN low Normal data transmission is resumed when PLBEN goes high internally pulled high Serial Line Loopback Serial line loopback is used for testing the performance of the optical transceiver and the transmission link The received 2 488Gbps data stream is routed to the trans mit CML output buffer Line loopback is enabled when LBEN is asserted low When LBEN is left open internally pulled high normal serial data transmission resumes LVDS Parallel Interface The MAX3831 parallel interface includes four OC 12 data inputs a 155MHz reference clock input four 622Mbps parallel data outputs and a 622MHz parallel clock output MAX3832 fPCLKO 155MHz All parallel inputs and outputs are LVDS compatible to minimize power dissipation speed transition time and improve noise immunity The 155MHz input signal at RCLKI requires a duty cycle between 40 and 60 The LVDS outputs go into a high impedance state when TRIEN is forced low This simplifies system checks by allowing vectors to be forced on the L VDS outpu
16. o duce a 622Mbps SDH SONET like transport overhead followed by a pseudorandom bit sequence This consists of 12 A1s 12 A2s and a pseudorandom bit stream PRBS 27 1 When TEST is low this pattern is distrib uted to all parallel inputs bypassing the LVDS input buffers Note this pattern is skewed by one 622MHz MAXIM 13 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator START UP OR RESET START 250 5 TIMER r FRAME SEARCH TIMER TIMED OUT ROLL DATA FRAME PATTERN DETECTED 1 FRAME DETECTED EN RESET BYTE AND FRAME FRAME PATTERN DETECTED FRAME PATTERN DETECTED IN FRAME um GN FRAME PATTERN DETECTED FRAME FRAME PATTERN PATTERN DETECTED DETECTED Figure 6 Frame Detection Flow Diagram MAXIM 9 cESEXVW LESEXVIW MAXS3831 MAX3832 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator clock cycle between each channel In this test mode ser ial data is internally looped back to the demux All frame detect logic is exercised using this mode The CML inputs SDIx and SCLKI and LVDS inputs PDI x are ignored in this mode After the BIST mode is enabled the loss of frame flag LOF goes high indicating that the self test has passed In normal operation TEST is left open internally pulled high disab
17. res 8 and 9 Observe the com mon mode input voltage specifications AC coupling is required if a Vcc other than 3 3V is used to maintain the input common mode level Figure 8 MAXIM 13 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator PECL OUTPUT MAXIM MAX3831 MAX3832 MAXIM YN MAX3831 N Y MAX3832 SELECT SUCH THAT THE CORRECT PECL COMMON MODE LEVEL IS ACHIEVED TYPICAL PECL OUTPUT CURRENT 14m4 Figure 8 PECL to CML Interface Figure 9 Direct Coupling of a PECL Output into the MAX3831 MAX3832 Layout Techniques For best performance use good high frequency layout techniques Filter voltage supplies keep ground con nections short and use multiple vias where possible Use controlled impedance transmission lines to inter face with the MAX3831 MAX3832 high speed inputs and outputs Place power supply decoupling as close to Vcc as possible To reduce feedthrough take care to isolate the input signals from the output signals MAXIM 11 cESEXVW LESEXVIW MAXS3831 MAX3832 3 3V 2 5Gbps SDH SONET 4 Channel Interconnect Mux Demux ICs with Clock Generator Pin Configuration TOP VIEW 64 63 62 61 60 59 58 571 56 55 94 531 521 51 MAXIMA MAX3831 MAX3832 24
18. ts CML Serial Interface The MAX3831 MAX3832 provide a 2 488Gbps serial data stream to a driver and accept 2 488Gbps serial data and a 2 488GHz clock signal from an external clock and data recovery device MAX3876 The high speed interface is CML compatible resulting in lower system power dissipation and excellent performance Figure 7 10 A MAXIM MAX3831 T MAX3832 M m MAX3876 Figure 7 CML to CML Interface Applications Information Low Voltage Differential Signal Inputs Outputs The MAX3831 MAX3832 have LVDS inputs and outputs for interfacing with high speed digital circuitry All LVDS inputs and outputs are compatible with the IEEE 1596 3 LVDS specification This technology uses 250mv to 400mV differential low voltage amplitudes to achieve fast transition times minimize power dissipation and improve noise immunity For proper operation the parallel clock and data LVDS outputs PCLKO PCLKO PDO_ PDO require 1000 differential DC termination between the inverting and noninverting outputs Do not terminate these out puts to ground The parallel data LVDS inputs PDI_ PDI_ are internally terminated with 1000 differential input resistance and therefore do not require external termination Interfacing with PECL ECL Input Levels When interfacing with differential PECL input levels it is important to attenuate the signal while still maintaining 50Q termination Figu
19. xposed paddle packages and are specified over the upper commercial 0 C to 85 temperature range Pin Configuration appears at end of data sheet TEST ETES FIL FIL 155MHz REF LKl CLOCKINPUT L 1 TO PDI4 1 TO PDM PDO1 TO PDO4 PDO1 TO PDO4 PCLKO PCLKO TRIEN MAX3831 CMOS MAX3832 OVERHEAD MAXIM Features 3 3V Single Supply 1 45W Power Dissipation MAX3831 4 Channel Mux Demux with Fully Integrated 2 488GHz Clock Generator Frame Detection Maintains Channel Assignment 7 5ns Elastic Store Range 2 5ps RMS Serial Data Output Random Jitter 8ps Serial Data Output Deterministic Jitter 622Mbps LVDS Parallel Input Output 2 488Gbps Serial CML Input Output On Chip Pattern Generator Provides High Speed BIST System Test Flexibility System Loopback Line Loopback Loss of Frame Indicator 9 9 9 9 Applications SDH SONET Backplanes High Speed Parallel Links ATM Switching Networks Line Extenders Intrarack Subrack Dense Digital Cross Interconnects Connects Ordering Information PART TEMP RANGE PIN PACKAGE MAX3831UCB 0 C to 85 C 64 TQFP EP MAX3832UCB 0 C to 85 C 64 TQFP EP MAXIM Typical Application Circuit SCLKI SCLKI SDI 501 50 CML MAXIM MAX3876 2 5Gbps CDR SD0 LBEN RSETFR 2 5Gbps OPTICAL TRANSCEIVER Maxim Integrated Products 1 For free samples
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MAXIM MAX3831/MAX3832 handbook