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ANALOG DEVICES AD15700 1 MSPS 16-/14-Bit Analog I/O Port handbook

1. ANALOG DEVICES 1 MSPS 16 14 Bit Analog 1 0 Port AD15700 FEATURES 16 Bit A D Converter 1 MSPS S N D 90 dB Typ 250 kHz No Pipeline Delay 14 Bit D A Converter Settling Time 1 ps S N 92 dB Typ 2 80 MHz Amplifiers 30 V s Slew Rate Rail to Rail Input and Output Output Current 15 mA 2 Gain Setting Center Tapped Resistors Resistor Ratio Tracking 2 ppm C Unipolar Operation SPI QSPI MICROWIRE DSP Compatible 132 mW Typical Power Dissipation APPLICATIONS Optical MEMS Mirror Control Industrial Process Control Data Acquisition Instrumentation Communication GENERAL DESCRIPTION The AD15700 is a precision component to interface analog input and output channels to a digital processor It is ideal for area limited applications that require maximum circuit density The AD15700 contains the functionality of a 16 bit 1 MSPS charge redistribution SAR analog to digital converter that operates from a 5 V power supply The high speed 16 bit sampling ADC incor porates a resistor input scaler that allows various input ranges an internal conversion clock error correction circuits and both serial and parallel system interface ports The AD15700 also contains a 14 bit serial input voltage output DAC that operates from a 5 V supply and has a settling time of 1 us Two single or split supply voltage feedback amplifiers with rail to rail input and output characteristics featuring 80 MHz of small signal bandw
2. 100 tr C AVDD IMPULSE DVDD IMPULSE 0 lt 0 1 0 01 OVDD ALL MODES 0 001 0 10 100 1000 10000 100000 1000000 SAMPLING RATE SPS TPC 14 Operating Currents vs Sample Rate REV A 17 AD15700 14 BIT D A CONVERTER TA 25 2 5V WU INL LSB DNL LSB o 0 25 AE ELO LLL LLL LLLA LLL 0 50 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Decimal CODE Decimal TPC 16 Integral Nonlinearity vs Code TPC 19 Differential Nonlinearity vs Code 0 50 0 50 0 25 0 25 INL LSB DNL LSB o 0 25 0 25 TEMPERATURE TEMPERATURE TPC 17 Integral Nonlinearity vs Temperature TPC 20 Differential Nonlinearity vs Temperature LINEARITY ERROR LSB LINEARITY ERROR LSB SUPPLY VOLTAGE V REFERENCE VOLTAGE V TPC 18 Linearity Error vs Supply Voltage TPC 21 Linearity Error vs Reference Voltage 18 REV A AD15700 VREF 2 5V tn 1 tc m o tc l tc 1 tc 9 0 LL z lt 2 5 tc N TEMPERATURE TEMPERATURE C TPC 22 Gain Error vs Temperature TPC 25 Zero Code Error vs Temperature 250 450 400 5 350 m t SUPPLY 200 300 VOLTAGE 2 2 gt gt n a REFERENCE VOLTAGE 200 150 180 40 TEMPERATU
3. 2 TPC 34 Output Saturation Voltage vs 85 TPC 37 Output Saturation Voltage vs 85 DIFFERENCE V DIFFERENCE FROM Vegg Ri 9 DIFFERENCE FROM V DIFFERENCE FROM Vgc V 9 TPC 36 Output Saturation Voltage vs 9 40 TPC 39 Output Saturation Voltage vs 40 REV A 21 AD15700 lt 1 i d T 1 2 z 5 lt tn 2 2 1 5 0 5 2 5 4 5 6 5 2 INPUT VOLTAGE TPC 43 Differential Input Voltage 1 V Characteristics 1 z lt o a tn 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH lt o LLL LL LLL 1 F LL a 40 30 20 10 0 10 20 30 40 50 60 70 80 90 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH TEMPERATURE C TPC 41 Open Loop Gain Ao vs Temperature TPC 44 Differential Gain and Phase Vs 5 V 100 30 1 e 10 o 5 5 z g E 3 2 gt E 1 2 0 3 10 100 1 10 100 1M 10M FREQUENCY Hz TPC 42
4. DISTORTION NOISE PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage Offset Drift Input Bias Current Input Offset Current Open Loop Gain INPUT CHARACTERISTICS Common Mode Input Resistance Differential Input Resistance Input Capacitance Input Voltage Range Input Common Mode Voltage Range Common Mode Rejection Ratio Differential Input Voltage OUTPUT CHARACTERISTICS Output Voltage Swing Low Output Voltage Swing High Output Voltage Swing Low Output Voltage Swing High Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio G 1 lt 0 4 V p p 54 80 G 1 2 V Step 27 32 G 1 Vo 2 Step 10 pF 125 fc 1 MHz Vo 2 V p p G 2 fc 100 kHz 2 V G 2 1 kHz f 100 kHz 1 kHz R 1 1 Vcc 25 Vout 2 5 V Tmn to Tmax VcM Vcc 25 Vout 2 5 V VcM Vcc 25 Vout 2 5 V Tmn to Tmax Vom 2 1 5 V to 3 5 V Tmn to Tmax 280 1 6 0 5 to 5 5 0 2 to 5 2 0 V to 5 V 70 0 V to 3 8 V 80 10 1 Sourcing Sinking 2 Vs 0Vto 1V or 5Vto6V OPERATINGTEMPERATURERANGE Specifications subject to change without notice Max 1
5. E M AD15700 ADSP 2101 ADSP 2103 to DAC Interface Figure 33 shows a serial interface between the DAC and the ADSP 2101 ADSP 2103 The ADSP 2101 ADSP 2103 should be set to operate in the SPORT Serial Port Transmit Alternate Framing Mode The ADSP 2101 ADSP 2103 is programmed through the SPORT Control Register and should be configured as follows internal clock operation active low framing 16 bit word length The first two bits are DON T CARE as the DAC will keep the last 14 bits Transmission is initiated by writing a word to the Tx Register after the SPORT has been enabled Because of the edge triggered difference an inverter is required at the SCLKs between the DSP and the DAC TFS ADSP 2101 ADSP 2103 SCLK ADDITIONAL PINS OMITTED FOR CLARITY Figure 33 ADSP 2101 ADSP 2103 to DAC Interface 68HC11 68L11 to DAC Interface Figure 34 shows a serial interface between the DAC and the 68HC11 68L11 microcontroller SCK of the 68HC11 68L11 drives the SCLK of the DAC while the MOSI output drives the serial data lines SDIN CS signal is driven from one of the port lines The 68 11 68 1 is configured for master mode 1 CPOL 0 and CPHA 0 Data appearing on the MOSI output 15 valid on the rising edge of SCK PC6 6 11 68L11 MOSI ADDITIONAL PINS OMITTED FOR CLARITY Figure 34 68HC11 68L11 to DAC Interface MICROWIRE to DAC Interface Figure 35 shows an interface between the DAC and any
6. Open Loop Gain vs Vout TPC 45 Input Voltage Noise vs Frequency 22 REV NORMALIZED GAIN dB NORMALIZED GAIN dB CLOSED LOOP GAIN dB FREQUENCY MHz TPC 46 Unity Gain 3 dB Bandwidth 10 FREQUENCY MHz TPC 47 Closed Loop Gain vs Temperature FREQUENCY Hz TPC 48 Closed Loop Gain vs Supply Voltage REV A 93 015700 OPEN LOOP GAIN dB PHASE Degree e e e FREQUENCY MHz TPC 49 Open Loop Frequency Response TOTAL HARMONIC DISTORTION dBc FUNDAMENTAL FREQUENCY Hz TPC 50 Total Harmonic Distortion vs Frequency 41 2 5V V 1 TOTAL HARMONIC DISTORTION dBc FUNDAMENTAL FREQUENCY Hz TPC 51 Total Harmonic Distortion vs Frequency G 42 015700 COMMON MODE REJECTION RATIO dB 1 FUNDAMENTAL FREQUENCY Hz TPC 52 Lar
7. Processor Interface The circuit in Figure 5a uses serial interfacing to minimize the number of signals that connect to the digital circuits External logic such as a state machine is used to generate clocks and other timing signals for the interface Ideally the clocks supplied to the converters are discontinuous and operate at the maximum frequency supported by the converter and the processor Discontinuous clocks that are quiet during critical times minimize degradation caused by voltage transients on the digital interface It is best to keep the clocks quiet during ADC conversion and when the DAC output 15 sampled by the external system Often the processor cannot tolerate a discontinuous clock and therefore a separate continuous clock or clocks that 15 synchronous with the converter clocks must be generated Separate clocks for the DAC and ADC are used to maximize the data transfer rate to each converter ADC operates at a maximum rate of 40 MHz while the DAC can operate up to 25 MHz ADC CIRCUIT INFORMATION ADC is a fast low power single supply precise 16 bit analog to digital converter ADC It features different modes to optimize performances according to the applications In warp mode it is capable of converting 1 000 000 samples per second 1 MSPS ADC provides the user with an on chip track hold successive approximation ADC that does not exhibit any pipeline or latency making it ideal for multiple m
8. When LOW full accuracy is maintained independent of the minimum conversion rate Mode Selection When HIGH and WARP LOW this input selects a reduced power mode In this mode the power dissipation is approximately proportional to the sampling rate Serial Parallel Selection Input When the Parallel Port 15 selected when HIGH the Serial Interface Mode 15 selected and some bits of the DATA bus are used as a serial port Bit 0 and Bit 1 of the Parallel Port Data Output Bus When SER PAR is HIGH these outputs are in high impedance When SER PAR is HIGH EXT INT is LOW and RDC SDIN is LOW which is the serial master read DIVSCLK 0 1 after Convert Mode These inputs part of the Serial Port are used to slow down if desired the internal serial clock that clocks the data output In the other serial modes these inputs are not used When SER PAR is LOW this output is used as Bit 4 of the Parallel Port Data Output Bus When SER PAR 15 HIGH this input part of the Serial Port is used as a digital select input for choosing the internal or an external data clock called respectively Master and Slave Mode With EXT INT tied LOW the internal clock is selected on SCLK output With EXT INT set to a logic HIGH output data is synchronized to an external clock signal connected to the SCLK input and the external clock is gated by C8 ADC When SER PAR is LOW this output is used as Bit 5 of the Parallel Port Data Output Bus When SER PAR 15
9. 11425 10 eee 1 62285 x10 202 288 5 2 s 1 21714 107 2 With C2 set to 100 pF the bandwidth is 1 2 MHz Without C2 the bandwidth of the filter is 2 6 MHz To utilize the ADC s maximum 9 6 MHz bandwidth the components external to the ADC are eliminated In this case the ADC is configured for its 0 to 2 REF input range and the resulting equivalent input circuit is shown in Figure 5b ANALOG ADC INPUT 3750 1000 Figure 5b Analog Input Circuit Analog Output Section The output circuitry consists of a DAC RC filter and an amplifier The circuit uses the DAC s output resistance of 6 25 20 to form single pole RC filter with an external capacitor C1 One of the AD15700 s internal center tapped resistors and one of its op amps form an amplifier with a gain of two The gain is used to bring the DAC s maximum range of REF volts up to 2 REF V ANALOG OUTPUT Figure 6 Analog Output Circuit Voltage Reference Input The AD15700 uses an external 2 5 V or 3 0 V voltage reference Because of the dynamic input impedance of the A D and the code dependent impedance of the D A the reference inputs must be driven by a low impedance source Decoupling consisting of a parallel combination of 47 and 0 1 capacitors is recom mended Suitable references include the ADR421 for 2 5 V output and the AD780 for selectable 2 5 V or 3 0 V output Both of these feature low noise and low temperature drift REV A
10. 12 E12 11 G10 G9 E10 K10 D12 K9 E7 H8 G5 H5 J7 J5 K5 L5 M5 Mnemonic DGND ADC D 8 or SDOUT D 9 or SCLK D 10 or SYNC D 11 or RDERROR D 12 15 BUSY DGND ADC RD CS ADC RESET PD AGND ADC REF REFGND INGND INA INB INC IND Type Description Digital Power Ground When SER PAR is LOW this output is used as Bit 8 of the Parallel Port Data Output Bus When SER PAR is HIGH this input part of the serial port is used as a serial data output synchronized to SCLK Conversion results are stored in an on chip register The ADC provides the conversion result MSB first from its internal shift register The DATA format is determined by the logic level of OB 2C In Serial Mode when EXT INT is LOW SDOUT is valid on both edges of SCLK In Serial Mode when EXT INT is HIGH If INVSCLK is LOW SDOUT is updated on SCLK rising edge and valid on the next falling edge If INVSCLK is HIGH SDOUT is updated on SCLK falling edge and valid on the next rising edge When SER PAR is LOW this output is used as Bit 9 of the Parallel Port Data Output Bus When SER PAR 15 HIGH this input part of the Serial Port is used as a serial data clock input or output dependent upon the logic state of the EXT INT pin The active edge where the data SDOUT 15 updated depends upon the logic state of the INVSCLK pin When SER PAR is LOW this output is used as Bit 10 of the Parallel Port Data Outp
11. 5 LL E g gt B 102 4 I ca o a 104 lt 106 0 100 200 300 400 500 FREQUENCY kHz TEMPERATURE TPC 7 FFT Plot TPC 10 SNR THD vs Temperature 16 0 110 15 5 105 m 100 5 15 0 e 2 95 2 145 a 2 5m z 85 80 14 0 o 75 13 5 70 65 13 0 60 1000 1000 FREQUENCY kHz FREQUENCY kHz TPC 8 SNR S N D and ENOB vs Frequency TPC 11 THD Harmonics and SFDR vs Frequency 16 0 15 5 15 0 3 a o e 2 z 5 145 cc 6 lt a oc 14 0 a I o 13 5 13 0 1000 60 50 40 30 20 10 0 FREQUENCY kHz INPUT LEVEL dB TPC 9 SNR vs Input Frequency TPC 12 THD Harmonics vs Input Level 16 REV A 015700 ty DELAY ns OVDD EBENEN BENE HN He a POWER DOWN OPERATING CURRENTS nA 0 50 100 150 200 ES CL PF C TPC 13 Typical Delay vs Load Capacitance C TPC 15 Power Down Operating Currents vs Temperature 100000 AVDD WARP NORMAL 10000 H DVDD WARP NORMAL 1000
12. ADC has a maximum integral nonlineariy of 2 5 LSB with no missing codes 3 Two Precision Resistor Networks with 2 ppm C Ratio Tracking for Gain Setting 4 Low Power Consumption Typically 132 mW at maximum performance levels 5 Industrial Temperature Range 40 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD15700 SPECIFICATIONS 16 BIT ELECTRICAL CHARACTERISTICS SSS ANALOG INPUT Voltage Range VIND VINGND 4 REF 0 V to 4 REF 2 REF See Table I Common Mode Input Voltage VINGND 0 1 0 5 Analog Input CMRR 100 kHz 74 Input Impedance See Table THROUGHPUT SPEED Complete Cycle In Warp Mode Throughput Rate In Warp Mode Time between Conversions In Warp Mode Complete Cycle In Normal Mode Throughput Rate In Normal Mode kSPS Complete Cycle In Impulse Mode Us Throughput Rate In Impulse Mode kSPS DC ACCURACY Integral Linearity Error LSB No Missing Codes Bits Transition Noise LSB Bipolar Zero Tm to Tax 5 V Range Normal or LSB Impulse Modes Other Range or Mode of FSR of FSR of FSR of FSR Bipolar Full Scale Error Tm to Tax Unipolar Zero Error Tm to Tmax Unipolar Full Scale Error Ty to Tmax Power Supply Sensitivity AVDD 5 V 5 LSB AC ACCURACY Signal to Noise frn 20 kHz dB fin 250 kHz Spurious Free D
13. Bit FSR 1 LSB 9 999695 V 4 999847 V 2 499924 V 19 099847 V 4 999924 V 2 499962 V Midscale 1 LSB 5 000153 V 2 570076 V 1 257038 V 0001 Midscale 5 2 5 1 25 0000 Midscale 1 LSB 4 999847 V 2 499924 1 249962 V FFFF FSR 1 LSB 9 999695 V 4 999847 V 2 499924 V 152 6 uV 76 3 38 15 uV 8001 FSR 10 V 5 V 2 5 V OV OV 8000 NOTES is also the code for an overrange analog input This is also the code for an underrange analog input 28 REV 015700 Analog Inputs The ADC is specified to operate with six full scale analog input ranges Connections required for each of the four analog inputs IND INC INB INA and the resulting full scale ranges are shown in Table I The typical input impedance for each analog input range is also shown Figure 9 shows a simplified analog input section of the ADC IND INC INB INA AGND Figure 9 Simplified Analog Input four resistors connected to the four analog inputs form a resistive scaler that scales down and shifts the analog input range to a common input range of 0 V to 2 5 V at the input of the switched capacitive ADC By connecting the four inputs INA INB INC and IND to the input signal the ground or a 2 5 V reference other analog input ranges can be obtained The diodes shown in Figure 9 provide ESD protection for the four analog inputs The inputs INB INC and IND have a high voltage protectio
14. HIGH this input part of the Serial Port is used to select the active state of the SYNC signal When LOW SYNC is active HIGH When HIGH SYNC is active LOW When SER PAR is LOW this output is used as Bit 6 of the Parallel Port Data Output Bus When SER PAR 15 HIGH this input part of the Serial Port is used to invert the SCLK signal It is active in both Master and Slave Mode When SER PAR is LOW this output is used as Bit 7 of the Parallel Port Data Output Bus When SER PAR 15 HIGH this input part of the serial port is used as either an external data input or a read mode selection input depending on the state of EXT INT When EXT INT is HIGH RDC SDIN could be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDOUT line The digital data level on SDIN 15 output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence When EXT INT is LOW RDC SDIN is used to select the read mode When RDC SDIN is HIGH the previous data is output on SDOUT during conversion When RDC SDIN is LOW the data can be output on SDOUT only when the conversion is complete Input Output Interface Digital Power Ground Input Output Interface Digital Power Nominally at the same supply as the supply of the host interface 5 V or 3 3 V Digital Power Nominally at 5 V AT 015700 ADC PIN FUNCTION DESCRIPTIONS continued Pin No 10 H12 G12 G11 I
15. Read Previous Conversion during Convert EXT INT 1 INVSCLK 0 RD 0 CS ADC RD BUSY 135 186 157 SCLK 2 3 14 15 16 17 18 lt Y 9X XX son Ce 155 Figure 22 Slave Serial Data Timing for Reading Read after Convert REV A 33 AD15700 While the ADC 15 performing bit decision it is important that voltage transients not occur on digital input output pins or degradation of the conversion result could occur This is particu larly important during the second half of the conversion phase because the ADC provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase For this reason it is recommended that when an external clock is being provided it is a discontinuous clock that is toggling only when BUSY 15 low or more importantly that it does not transition during the latter half of BUSY high External Discontinuous Clock Data Read after Conversion Though the maximum throughput cannot be achieved using this mode it is the most recommended of the serial slave modes Figure 22 shows the detailed timing diagrams of this method After a conversion is complete indicated by BUSY returning low the result of this conversion can be read while both CS ADC and RD are low The data is shifted out MSB first with 16 clock pulses and is valid on both the rising and falling edge of the clock Among
16. The remaining 10 bits of the data word drive switches SO to S9 of a 10 bit voltage mode R 2R ladder network 10 BIT R 2R LADDER FOUR MSBS DECODED INTO 15 EQUAL SEGMENTS Figure 31 DAC Architecture With this type of DAC configuration the output impedance is independent of code while the input impedance seen by the reference is heavily code dependent The output voltage 15 dependent on the reference voltage as shown in the following equation Vrs XD where D is the decimal data word loaded to the DAC register and N is the resolution of the DAC For a reference of 2 5 V the equation simplifies to the following 2 5xD 16 384 giving a 1 25 V with midscale loaded and 2 5 V with full scale loaded to the DAC The LSB size is Vggp 16 384 REV A 015700 Serial Interface The DAC is controlled by a versatile 3 wire serial interface that operates at clock rates up to 25 MHz and is compatible with SPI QSPI MICROWIRE and DSP interface standards The timing diagram can be seen in Figure 3 Input data is framed by the chip select input CS_DAC After a high to low transition on CS data is shifted synchronously and latched into the input register on the rising edge of the serial clock SCLK Data is loaded MSB first in 14 bit words After 14 data bits have been loaded into the serial input register a low to high transition on CS_DAC transfers the contents of the shift register to
17. as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD15700 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality 10 WARNING ESD SENSITIVE DEVICE REV A 015700 ADC PIN FUNCTION DESCRIPTIONS Pinout page 42 H9 J8 J9 M12 6 L7 L8 M7 L9 M8 M9 L10 MIO 11 M11 L12 K11 K12 J10 J11 J12 REV A AGND_ADC AVDD BYTESWAP OB 2C IMPULSE SER PAR D 0 1 D 2 3 or DIVSCLK 0 1 D 4 or EXT INT D 5 or INVSYNC D 6 or INVSCLK D 7 or RDC SDIN Analog Power Ground Pin Input Analog Power Pin Nominally 5 V Parallel Mode Selection 8 16 Bit When LOW the LSB is output on D 7 0 and the MSB is output on D 15 8 When HIGH the LSB is output on D 15 8 and the is output on D 7 0 Straight Binary Binary Twos Complement When OB 2C is HIGH the digital output is straight binary when LOW the MSB is inverted resulting in a twos complement output from its internal shift register Mode Selection When HIGH and IMPULSE LOW this input selects the fastest mode the maximum throughput is achievable and a minimum conversion rate must be applied in order to guarantee full specified accuracy
18. digital inputs forced to OVDD or OGND respectively Specifications subject to change without notice Table I Analog Input Configuration Input Voltage Range IND 4R INC 4R INBQR INA R Input Impedance 4 REF 1 63 2 REF 948 REF 7110 0 V to 4 REF 948 0 V to 2 REF 7110 0 V to REF Note 2 NOTES analog input impedance this range the input is high impedance REV A 3 AD15700 16 ADC TIMING CHARACTERISTICS aoc to 85 c avon ovon 5 v 0 00 2 7 V to 5 25 V unless otherwise noted Parameter Min Typ Max Unit Refer to Figures 14 and 15 Convert Pulsewidth 5 Time between Conversions 1 1 25 1 5 Note 1 Warp Mode Normal Mode Impulse Mode CNVST LOW to BUSY HIGH Delay 30 BUSY HIGH All Modes Except in Master Serial Read after 0 75 1 1 25 Convert Mode Warp Mode Normal Mode Impulse Mode Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time Warp Mode Normal Mode Impulse Mode 0 75 1 1 25 Acquisition Time RESET Pulsewidth Refer to Figures 16 17 and 18 Parallel Interface Modes CNVST LOW to DATA Valid Delay 0 75 1 1 25 Warp Mode Normal Mode Impulse Mode DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid 40 Bus Relinquish Time Refer to Figures 20 and 21 Master Serial Interface Modes CS ADC LOW to SYNC Valid Delay CS ADC LOW to Internal SCLK Valid Delay CS ADC LOW to SDOUT Delay CNVST LOW to SYNC Delay Read During Con
19. expected there is some degradation in signal quality at the higher frequency When the output signal has a peak to peak swing of 1 45 V swinging from 50 mV to 1 5 V the THD is 55 dB SFDR 60 dB This circuit could also used to drive the analog input of a single supply high speed ADC whose input voltage range 1s referenced to ground e g 0 V to 2 V or 0 V to 4 V In this case a back termination resistor 15 not necessary assuming a short physical distance from transistor to so the emitter of the external transistor would be connected directly to the ADC input The available output voltage swing of the circuit would therefore be doubled LM ALY Pet Tt NT ther ee Los ML Figure 46 Output Signal Swing of Low Distortion Line Driver at 2 MHz 47dBm VERTICAL SCALE 10dB DIV START 0Hz STOP 20MHz Figure 47 THD of Low Distortion Line Driver at 2 MHz m ME 015700 AD15700 PINOUT TOP VIEW 3 4 5 6 7 8 9 10 11 12 COMMON COMMON RPAD1 1 2 COMMON COMMON 1 2 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON 2 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON F D11 BUSY RDERROR G DGND D9 ADC SCLK RUN D6 D7 CS RDC SDN D3 D5 IMPULSE nm DIVS
20. ho durs 42 C W DVDD to 7V Maximum Junction Temperature 150 C ADC Digital Inputs 0 3 V to DVDD 0 3 V Operating Temperature Range 409 to 85 VDD DAC to AGND DAC 0 3 V to 6 V Storage Temperature Range 659 to 150 DAC Digital Input Voltage to Lead 223 15 DGND 0 3 V to DVDD 0 35 V Stresses above those listed under Absolute Maximum Ratings may cause perma VOUT DAC to AGND DAC 0 3 V to DVDD 03 V nent damage to the device This is a stress rating only and functional operation of AGND DAC DAC 0 3 V to 0 3 V the device at these or any other conditions above those indicated in the operational n sections of this specification 15 not implied Exposure to absolute maximum rating DAC Input Current to Any DAC Pin Except Supplies 10 conditions for extended periods may affect device reliability ORDERING GUIDE Model Temperature Range Package Option AD15700BCA 409 to 85 144 Lead CSPBGA AD15700 PCB 28730 Evaluation Board ADDS 2191 EZLITE ADDS 21535 EZLITE ADDS 21160M EZLITE ADDS 21161N EZLITE 25 Evaluation Kit One of the DSP Evaluation Kits is required for operation of the AD15700 PCB Evaluation Board CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high
21. logic HIGH reset the ADC Current conversion if any is aborted If not used this pin could be tied to DGND Power Down Input When set to a logic HIGH power consumption is reduced and conversions are inhibited after the current one 15 completed Start Conversion falling edge on CNVST puts the internal sample hold into the hold state and initiates a conversion In impulse mode IMPULSE HIGH and WARP LOW if CNVST 15 held low when the acquisition phase tg 15 complete the internal sample hold is put into the hold state and a conversion is immediately started Must be Tied to Analog Ground Reference Input Voltage Reference Input Analog Ground Analog Input Ground Analog Inputs Refer to Table I for input range configuration 12 REV 015700 DAC PIN FUNCTION DESCRIPTIONS A6 VOUT DAC Analog Output Voltage from the DAC A3 C3 C4 AGND DAC Ground Reference Point for Analog Circuitry A2 VREF This is the voltage reference input for the DAC Connect to external reference ranges from 2 V to VDD Bl CS DAC This is an active low logic input signal The chip select signal is used to frame the serial data input 1 SCLK Clock Input Data is clocked into the input register on the rising edge of SCLK Duty cycle must be between 40 and 6096 E2 DIN Serial Data Input This device accepts 14 bit words Data is clocked into the input register on the rising edge of SCLK E3 DGND DAC Digital Ground Ground reference for digital cir
22. the DAC Data can only be loaded to the part while CS_DAC is low Unipolar Output Operation The DAC is capable of driving unbuffered loads of 60 kQ Unbuffered operation results in low supply current typically 300 mA and a low offset error The DAC provides a unipolar output swing ranging from 0 V to VREF Figure 32 shows a typical unipolar output voltage circuit The code table for this mode of operation is shown in Table IV 5V 2 5V SERIAL INTERFACE UNIPOLAR OUTPUT OP AMP Figure 32 Unipolar Output Table IV Unipolar Code Table DAC Latch Contents MSB LSB 11 1111 1111 1111 10 0000 0000 0000 00 0000 0000 0001 VREF X 1 16384 00 0000 0000 0000 0V Assuming a perfect reference the worst case output voltage may be calculated from the following equation Analog Output VREF X 16383 16384 VREF X 8192 16384 1 2 VREF D 24 X Vii Vor INL where Vour Unipolar Mode Worst Case Output D Decimal Code Loaded to DAC Reference Voltage Applied to Part Gain Error in Volts Vzsg Zero Scale Error Volts INL Integral Nonlinearity in Volts REV A Output Amplifier Selection In a single supply application selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail in this case AGND This can result in some degradation of the specified performance unless the applic
23. the last code transition The deviation is measured from the middle of each code to the true straight line Differential Nonlinearity Error DNL In an ideal ADC code transitions are 1 LSB apart Differential nonlinearity is the maximum deviation from this ideal value It is often specified in terms of resolution for which no missing codes are guaranteed Full Scale Error The last transition from 011 10 to 011 11 twos comple ment coding should occur for an analog voltage 1 1 2 L SB below the nominal full scale 2 499886 V for the 2 5 V range The full scale error is the deviation of the actual level of the last transition from the ideal level Bipolar Zero Error The difference between the ideal midscale input voltage 0 V and the actual voltage producing the midscale output code Unipolar Zero Error In unipolar mode the first transition should occur at a level 1 2 LSB above analog ground The unipolar zero error is the deviation of the actual transition from that point Spurious Free Dynamic Range SFDR The difference in decibels dB between the rms amplitude of the input signal and the peak spurious signal Effective Number of Bits ENOB A measurement of the resolution with a sine wave input It is related to S N D by the following formula ENOB s I N D 1 76 6 02 and is expressed in bits Total Harmonic Distortion THD The rms sum of the first five harmonic components to the rms value
24. the positive supply Q5 turns on and routes the tail current away from the pair and to the NPN pair During this transition region the amplifier s input current will change magnitude and direction Reusing the same tail current ensures that the input stage has the same transconductance which determines the amplifier s gain and bandwidth in both regions of operation Switching to the NPN pair as the common mode voltage 1s driven beyond 1 V within the positive supply allows the amplifier to provide useful operation for signals at either end of the supply voltage range and eliminates the possibility of phase reversal for input signals up to 500 mV beyond either power supply Offset voltage will also change to reflect the offset of the input pair in control The transition region is small on the order of 180 mV These sudden changes in the dc parameters of the input stage can produce glitches that will adversely affect distortion eS OUTPUT STAGE COMMON MODE FEEDBACK Figure 39 Simplified Schematic of Input Stage REV A 39 015700 Overdriving the Input Stage Sustained input differential voltages greater than 3 4 V should be avoided as the input transistors may be damaged Input clamp diodes are recommended if the possibility of this condition exists The voltages at the collectors of the input pairs set to 200 mV from the power supply rails This allows the amplifier to remain in linear operation for input vo
25. 2 1400 85 Unit MHz V us ns dBc dBc nV VHz pA VHz pA VHz Degrees REV A Parameter DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 lt 0 4 V p p Slew Rate G 1 Vo 2 V Step Settling Time to 0 196 G 1 2 Step 10 pF DISTORTION NOISE PERFORMANCE Total Harmonic Distortion fc 1 MHz Vo 2 V p p G 2 fc 100 kHz 2 V G 2 Input Voltage Noise f 1 kHz Input Current Noise f 100 kHz f 1 kHz Differential Gain 1 Differential Phase 1 DC PERFORMANCE Input Offset Voltage 0 V Vour 0 V Tmn to Tmax Offset Drift Vem 0 V Input Bias Current Vem 0 V Vour 0 V Tmn to Tmax Input Offset Current Open Loop Gain Vom 0 V Vour 2 V Tmn to Tmax INPUT CHARACTERISTICS Common Mode Input Resistance Differential Input Resistance Input Capacitance Input Voltage Range Input Common Mode Voltage Range Common Mode Rejection Ratio Vem 2 V to 5 V 2 V to 3 5 V Differential Input Voltage OUTPUT CHARACTERISTICS Output Voltage Swing Low 10 Output Voltage Swing High Output Voltage Swing Low 1 Output Voltage Swing High Output Current Short Circuit Current Sourcing Sinking Capacitive Load Drive 2 POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio Vs 5 V to 6 V or 5 V to 6 V OPERATING TEMPERATURE R
26. ANGE 40 Specifications subject to change without notice REV A 9 Typ Max 280 1 6 5 5 to 5 5 5 2 to 5 2 80 90 6 1600 85 AD15700 AMPLIFIER ELECTRICAL CHARACTERISTICS o ESA Unit MHz V us ns dBc dBc pA VHz pA VHz Degrees 015700 RESISTOR DIVIDER ELECTRI CAL CHARACTERISTI CS T 25 C unless otherwise noted Resistance Temperature Coefficient of Resistance ppm C Resistance Ratio of Two Halves Resistance Ratio Tracking ppm C Power Dissipation mW At higher temperatures linearly derates to 0 mW at 175 C Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Amplifier Supply Voltage VS1 52 12 6 V Analog Inputs Amplifier Input Voltage Common Mode 0 5 V IND INB 11 V to 30 V Amplifier Differential Input Voltage 3 4 V INA REF INGND REFGND AGND 0 3 V to AVDD 03 Amplifier Output Short Circuit ADC Ground Voltage Differences Duration Observe Power Derating Curves AGND_ADC DGND_ADC OGND 0 3 V Resistor Instantaneous Voltage Drop 50 V ADC Supply Voltages Internal Power Dissipation T Max T A 0rA AVDD DVDD 7V Thermal Resistance AVDD to DYDD AVDD to OVDD CSP BGA aces
27. CLK1 INVSYNC 2 AGND DIVSCLKO EXT INT ADC 12 3 4 5 6 7 8 9 10 11 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON lt o 42 REV 10 00 BSC SQ 1 70 REV OUTLINE DIMENSIONS 144 Lead Chip Scale Ball Grid Array CSPBGA BC 144 Dimensions shown in millimeters A1 CORNER INDEX AREA 76543219 12 111 e TOP VIEW 000000000000 000000000000 gt DETAIL 8 80 BSC DETAIL A 0 85 MIN 0 25 MIN 0 55 0 12 MAX 0 50 BNET COPLANARITY 0 45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO 205AC NOTES 1 THE ACTUAL POSITION OF THE BALL POPULATION IS WITHIN 0 15 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES 2 THE ACTUAL POSITION OF EACH BALL IS WITHIN 0 08 OF ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION 015700 AD15700 Revision History Location Page 2 03 Data Sheet changed from REV 0 to REV A Edit fo FUNCTIONAL BLOCK DIAGRAM 83 87303 206202 3 9 SYA 9 1 Edits to AMPLIFIER ELECTRICAL CHARACTERISTICS 44135 335323 3 122332 R We oe de
28. DC keeps the conversion process running by itself It should be noted that the analog input has to be settled when BUSY goes low Also at power up CNVST should be brought low once to initiate the conversion process In this mode the ADC could sometimes run slightly faster than the guaranteed limits in the impulse mode of 666 kSPS This feature does not exist in warp or normal modes Although CNVST is a digital signal it should be designed with special care with fast clean edges and levels with minimum overshoot and undershoot or ringing It is a good thing to shield the CNVST trace with ground and also to add a low value serial resistor 1 e 50 2 termination close to the output of the com ponent that drives this line REV A For applications where the SNR is critical CNVST signal should have a very low jitter One way to achieve that 1s to use a dedicated oscillator for CNVST generation or at least to clock it with a high frequency low jitter clock RESET BUSY DATA CNVST Figure 15 RESET Timing DIGITAL INTERFACE The ADC has a versatile digital interface it can be interfaced with the host system by using either a serial or parallel interface The serial interface is multiplexed on the parallel data bus The ADC digital interface also accommodates both 3 V or 5 V logic by simply connecting the OVDD supply pin of the ADC to the host system interface digital supply Finally by using the OB 2C input pin both str
29. MICROWIRE compatible device Serial data is shifted out on the falling edge of the serial clock and into the DAC on the rising edge of the serial clock No glue logic is required as the DAC clocks data into the input shift register on the rising edge MICROWIRE SO SCLK ADDITIONAL PINS OMITTED FOR CLARITY Figure 35 MICROWIRE to DAC Interface 80C51 80L51 to DAC Interface serial interface between the DAC and the 80 51 801 51 microcontroller 15 shown in Figure 36 TxD of the microcontroller drives the SCLK of the DAC while RxD drives the serial data line of the DAC 3 3 is a bit programmable pin on the serial port that is used to drive CS DAC 38 80 51 80L51 ADDITIONAL PINS OMITTED FOR CLARITY Figure 36 80C51 80L51 to DAC Interface The 80C51 80L51 provides the LSB first while the DAC expects the MSB of the 14 bit word first Care should be taken to ensure the transmit routine takes this into account Usually it can be done through software by shifting out and accumulating the bits in the correct order before inputting to the DAC Also 80C51 outputs 2 byte word 16 bit data Thus the first two bits after rearrangement should be DON T CARE as they will be dropped from the DAC s 14 bit word When data is to be transmitted to the DAC P3 3 is taken low Data on RxD is valid on the falling edge of TxD so the clock must be inverted as the DAC clocks data into the input shift register on the rising edg
30. P 21065L Using the Serial Master Mode APPLICATION HINTS Layout The AD15700 s ADC has very good immunity to noise on the power supplies as can be seen in Figure 12 However care should still be taken with regard to grounding layout The printed circuit board that houses the AD15700 should be designed so the analog and digital sections are separated and confined to certain areas of the board This facilitates the use of ground planes that can be easily separated Digital and analog ground planes should be joined in only one place preferably underneath the AD15700 or at least as close as possible to the AD15700 If the AD15700 is in a system where multiple devices require analog to digital ground connections the connection should still be made at one point only a star ground point which should be established as close as possible to the AD15700 It is recom mended to avoid running digital lines under the device as these will couple noise onto the die The analog ground plane should be allowed to run under the switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and should never run near analog signal paths Crossover of digital and analog signals should be avoided Traces on different but close layers of the board should run at right angles to each other This will reduce the effect of feedthrough through the board The power supply lines to the AD 15700 sh
31. RE C VOLTAGE V TPC 23 Supply Current vs Temperature TPC 26 Supply Current vs Reference Voltage or Supply Voltage 400 25 2 5 5V 2 T 300 oc tr 14 2 gt 250 tc 2 s 200 150 0 2048 4096 6144 8192 10240 12288 14336 16384 DIGITAL INPUT VOLTAGE V CODE Decimal TPC 24 Supply Current vs Digital Input Voltage TPC 27 Reference Current vs Code REV A 19 AD15700 t Qo lt tn 5 2 COMMON MODE VOLTAGE V TPC 28 Typical Vos Distribution 9 Va 5 TPC 31 Input Bias Current vs Common Mode Voltage 2 2 E E 1 1 5 5 LL LL LL 30 20 10 0 10 20 30 40 50 60 70 80 90 0 05 1 0 15 20 25 30 3 5 40 45 5 0 TEMPERATURE COMMON MODE VOLTAGE V TPC 29 Input Offset Voltage vs Temperature TPC 32 Vos vs Common Mode Voltage INPUT BIAS mA SUPPLY CURRENT AMPLIFIER mA 650 600 40 30 20 10 0 10 20 30 40 50 60 70 80 90 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE TEMPERATURE TPC 30 Input Bias Current vs Temperature TPC 33 Supply Current vs Temperature 20 REV A 015700 AMPLIFIER DIFFERENCE FROMV V DIFFERENCE FROM Vgc V 0
32. REV A The capacitor Cs is typically 60 pF and is mainly the ADC sampling capacitor This one pole filter with a typical 3 dB cutoff frequency of 9 6 MHz reduces undesirable aliasing effects and limits the noise coming from the inputs CMRR dB FREQUENCY kHz Figure 10 Analog Input CMRR vs Frequency Except when using the 0 V to 2 5 V analog input voltage range the ADC has to be driven by a very low impedance source to avoid gain errors That can be done by using the driver amplifier When using the 0 V to 2 5 V analog input voltage range the input impedance of the ADC is very high so the ADC can be driven directly by a low impedance source without gain error That allows putting an external one pole RC filter between the output of the amplifier output and the ADC analog inputs to even further improve the noise filtering done by the ADC analog input circuit However the source impedance has to be kept low because it affects the ac performances especially the total harmonic distortion The maximum source impedance depends on the amount of total THD that be tolerated The THD degra dation is a function of the source impedance and the maximum input frequency as shown in Figure 11 THD dB FREQUENCY kHz Figure 11 THD vs Analog Input Frequency and Input Resistance 0 V to 2 5 V Only 29 015700 Driver Amplifier Choice Although the ADC is easy to drive the driver amplifier needs to meet
33. aight binary or twos complement coding can be used The two signals CS ADC and RD control the interface When at least one of these signals 15 high the interface outputs are in high impedance Usually 5 allows the selection of each in multicircuit applications and 15 held low in a single ADC design RD is generally used to enable the conversion result on the data bus CS 0 BUSY t gt DATA BUS PREVIOUS CONVERSION DATA NEW DATA Figure 16 Master Parallel Data Timing for Reading Continuous Read 234 015700 PARALLEL INTERFACE The ADC is configured to use the parallel interface when the SER PAR is held low The data can be read either after each conversion which is during the next acquisition phase or during the following conversion as shown respectively in Figures 18 and 19 When the data is read during the conversion however it is recommended that it be read only during the first half of the conversion phase That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry CSZ ADC RD DATA BUS CURRENT CONVERSION lis Figure 17 Slave Parallel Data Timing for Reading Read after Convert CS 0 CNVST BUSY DATA BUS Figure 18 Slave Parallel Data Timing for Reading Read during Convert The BYTESWAP pin allows a glueless interface to an 8 bit bu
34. al 2 5 V voltage reference The voltage reference input REF of the ADC has a dynamic input impedance Therefore it should be driven by a low impedance source with an efficient decoupling between REF and REFGND inputs This decoupling depends on the choice of the voltage reference but usually consists of a low ESR tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance 47 is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages e The low noise low temperature drift ADR421 or AD780 voltage references e The low power ADR291 voltage reference e The low cost AD1582 voltage reference 30 Care should also be taken with the reference temperature coefficient of the voltage reference which directly affects the full scale accuracy if this parameter matters For instance a 15 ppm C tempco of the reference changes the full scale by 1 LSB C Scaler Reference Input Bipolar Input Ranges When using the ADC with bipolar input ranges a buffer amplifier is required to isolate the REFIN pin from the signal dependent current in the AIN pin A high speed op amp can be used with a single 5 V power supply without degrading the performance of the ADC The buffer must have good settling characteristics and provide low total noise within the input bandwidth of the ADC Power Supply The ADC uses three sets of power supply pins an analog 5 V supply AVDD a di
35. al signal processor ADC is designed to interface either with a parallel 8 bit or 16 bit wide interface or with a general purpose serial port or I O ports on a microcontroller A variety of external buffers can be used with the ADC to prevent digital noise from coupling into the ADC The following sections illustrate the use of the ADC with an SPI equipped microcontroller the ADSP 21065L and ADSP 218x signal processors SPI Interface MC68HC11 Figure 25 shows an interface diagram between the ADC and an SPI equipped microcontroller like the MC68HC11 To accommodate the slower speed of the microcontroller the ADC acts as a slave device and data must be read after conversion This mode also allows the daisy chain feature The convert command could be initiated in response to an internal timer interrupt The reading of output data one byte at a time if necessary could be initiated in response to the end of conversion signal BUSY going low using an interrupt line of the microcontroller The serial peripheral interface SPI on the MC68HC11 is configured for master mode MSTR 1 Clock Polarity Bit CPOL 0 Clock Phase Bit CPHA 1 and SPI Interrupt Enable SPIE 1 by writing to the SPI Control Register SPCR The IRQ is configured for edge sensitive only operation IRQE 1 in OPTION register MC68HC11 AD15700 SER PAR EXT INT ADDITIONAL PINS OMITTED FOR CLARITY Figure 25 Interfacing the AD15700 to SPI Int
36. at least the following requirements e The driver amplifier and ADC analog input circuit must be able together to settle for a full scale step of the capacitor array at a 16 bit level 0 001594 e The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the ADC The noise coming from the driver is first scaled down by the resistive scaler according to the analog input voltage range used and is then filtered by the ADC analog input circuit one pole low pass filter made by R 2 R1 and CS The SNR degradation due to the amplifier 1s SNRross log where 15 3 dB input bandwidth in MHz of the ADC 9 6 MHz or the cutoff frequency of the input filter if any 15 used 0 V to 2 5 V range N is the noise factor of the amplifier 1 if in buffer configuration 18 the equivalent input noise voltage of the op amp in nV NHz FSR is the full scale span 1 e 5 V for 2 5 V range For instance when using the 0 V to 5 V range a driver like the AD15700 s internal op amp with an equivalent input noise of 15 nV VHz and configured as a buffer followed by 3 2 MHz RC filter the SNR degrades by about 1 3 dB e The driver needs to have a THD performance suitable to that of the ADC Figure 11 gives the THD versus frequency that the driver should preferably exceed Voltage Reference Input The ADC uses an extern
37. ation does not use codes near zero The selected amp needs to have very low offset voltage the DAC LSB is 152 with a 2 5 V reference to eliminate the need for output offset trims Input bias current should also be very low as the bias current multiplied by the DAC output impedance approximately 6 will add to the zero code error Rail to rail input and output performance is required For fast settling the slew rate of the op amp should not impede the settling time of the DAC Output impedance of the DAC is constant and code independent but in order to minimize gain errors the input impedance of the output amplifier should be as high as possible The amplifier should also have a 3 dB band width of 1 MHz or greater The amplifier adds another time constant to the system thus increasing the settling time of the output higher 3 dB amplifier bandwidth results in a faster effective settling time of the combined DAC and amplifier Force Sense Buffer Amplifier Selection These amplifiers can be single supply or dual supply low noise amplifiers low output impedance at high frequencies is pre ferred be able to handle dynamic currents of up to 20 mA Reference and Ground As the input impedance is code dependent the reference pin should be driven from a low impedance source The DAC oper ates with a voltage reference ranging from 2 V to Vpp Although DAC s full scale output voltage is determined by the reference re
38. conversion phase begins SWA and SWB are opened first The capacitor array and the dummy capacitor are then disconnected from the inputs and connected to the REFGND input Therefore the differ ential voltage between the output of the resistive scaler and INGND captured at the end of the acquisition phase is applied to the comparator inputs causing the comparator to become unbalanced 207 AD15700 4R IND O pen 4R REFGND O INC O 2R MSB INB O 32768C 16384C R INA O INGND C SWITCHES CONTROL CONTROL LOGIC OUTPUT CODE 65536C Figure 7 ADC Simplified Schematic By switching each element of the capacitor array between REFGND or REF the comparator input varies by binary weighted voltage steps VREF 2 VREF 4 VREF 65536 The control logic toggles these switches starting with the MSB first in order to bring the comparator back into a balanced condition After the completion of this process the control logic generates the ADC output code and brings BUSY output low in this mode is 666 kSPS When operating at 100 SPS for example it typically consumes only 15 uW This feature makes ADC ideal for battery powered applications Transfer Functions Using the OB 2C digital input the ADC offers two output codings straight binary and twos complement The ideal transfer characteristic for the ADC 15 shown in Figure 8 and Table III Modes of Operation ADC feat
39. cuitry VDD DAC Analog Supply Voltage 5 10 AMPLIFIER PIN FUNCTION DESCRIPTIONS C9 J1 IN1 2 AI Positive Input Voltage 9 G1 IN1 2 AI Negative Input Voltage B12 K4 2 AO Amplifier Output Voltage A11 F3 VS1 2 P Analog Positive Supply Voltage B10 B11 VS1 2 P Analog Negative Supply Voltage G3 H3 RESISTOR PIN FUNCTION DESCRIPTIONS B9 L4 RA1 2 Resistor End Terminal A8 M4 RB1 2 Resistor Center Tap D9 L1 RC1 2 Resistor End Terminal A7 3 RPAD1 2 Resistor Die Pad Tie to Analog Ground COMMON PIN FUNCTION DESCRIPTIONS Al A4 A5 A10 A12 2 8 Cl COMMON P Common Floating Net Connecting 69 Pins Not electrically C2 C5 C8 C10 C12 D1 D8 connected within the module Tie at least one of these pins 010 D11 E4 E6 E8 E9 F2 to Analog Ground F4 F10 G2 G4 G6 G8 H1 H2 H4 H6 H7 J2 4 J6 K1 K3 L2 L3 L6 M2 NOTES AI Analog Input AI O Bidirectional Analog AO Analog Output DI Digital Input DI O Bidirectional Digital DO Digital Output P Power REV A NL 015700 ADC DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error INL Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale The point used as negative full scale occurs 1 2 LSB before the first code transition Positive full scale is defined as a level 1 1 2 LSB beyond
40. e of the serial clock The 80C51 80L51 transmits its data in 8 bit bytes with only eight falling clock edges occurring in the transmit cycle As the DAC requires a 14 bit word P3 3 or any one of the other programmable bits is the CS DAC input signal to the DAC so P3 3 should be brought low at the beginning of the 16 bit write cycle 2 X 8 bit words and held low until the 16 bit 2 X 8 cycle is completed After that P3 3 15 brought high again and the new data loads to the DAC Again the first two bits after rearranging should be DON T CARE APPLICATIONS Optocoupler Interface The digital inputs of the DAC are Schmitt triggered so they can accept slow transitions on the digital input lines This makes these parts 1deal for industrial applications where it may be necessary for the DAC to be isolated from the controller via optocouplers Figure 37 illustrates such an interface 5V 2 REGULATOR Vpp SCLK _ __ 7 Vpp CS O __ LI 4 7 Vpp DIN __ V Figure 37 DAC in an Optocoupler Interface REV A 015700 Decoding Multiple DACs CS DAC pin of the DAC can be used to select one of a number of DACs devices receive the same serial clock and serial data but only one device will receive the 5 DAC signal at any one time The DAC addressed will be determined by the decoder There will be some digital feedthr
41. erface ADSP 21065L in Master Serial Interface As shown in Figure 26 AD15700s can be interfaced to the ADSP 21065L using the serial interface in master mode without any glue logic required This mode combines the advantages of reducing the wire connections and the ability to read the data during or after conversion at maximum speed transfer DIVSCLK 0 1 both low The ADC is configured for the internal clock mode EXT INT low and acts therefore as the master device The convert com mand can be generated by either an external low jitter oscillator or as shown by a FLAG output of the ADSP 21065L or by a frame output TFS of one serial port of the ADSP 21065L which can be used like a timer The serial port on the ADSP 21065L is configured for external clock 5 0 rising edge active 1 external late framed sync signals IRFS 0 LAFS 1 1 and active high LRFES 0 The serial port of the ADSP 21065L is configured by writing to its receive control register SRCTL see the ADSP 2106x SHARC User s Manual Because the serial port within the ADSP 21065L will be seeing a discontinuous clock an initial word reading has to be done after the ADSP 21065L has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation REV A ADSP 21065L SHARC RCLK FLAG ORTFS ADDITIONAL PINS OMITTED FOR CLARITY Figure 26 Interfacing to the ADS
42. ferences below 2 V will result in reduced accuracy Table IV outlines the analog output voltage for particular digital codes Power On Reset The DAC has a power on reset function to ensure the output is at a known state upon power up On power up the DAC register contains all zeros until data is loaded from the serial register However the serial register 15 not cleared on power up so its contents are undefined When loading data initially to the DAC 14 bits or more should be loaded to prevent erroneous data appearing on the output If more than 14 bits are loaded only the last 14 are kept and if fewer than 14 are loaded bits will remain from the previous word If the DAC needs to be interfaced with data shorter than 14 bits the data should be padded with zeros at the LSBs Power Supply and Reference Bypassing For accurate high resolution performance it is recommended that the reference and supply pins be bypassed with a 10 nF tantalum capacitor in parallel with a 0 1 nF ceramic capacitor MICROPROCESSOR INTERFACING Microprocessor interfacing to the DAC is via a serial bus that uses standard protocol compatible with DSP processors and microcontrollers The communications channel requires a 3 wire interface consisting of a clock signal a data signal and a synchronization signal The DAC requires a 14 bit data word with data valid on the rising edge of SCLK The DAC update may be done automatically when all the data is clocked in
43. ge Signal Response 0 1 1 10 100 200 FREQUENCY MHz TPC 53 Rout vs Frequency FREQUENCY Hz TPC 54 vs Frequency POWER SUPPLY REJECTION RATIO dB FREQUENCY Hz TPC 55 vs Frequency 5 10 2 5V 6V p p 1 NN NESSUN NEGA NI A __ 1 11121111 10ps DIV 1V DIV TPC 56 Output Voltage RENS 650mV 5 1V DIV 10ps DIV TPC 57 Output Voltage Phase Reversal Behavior 24 REV AD15700 m SE A a Lp RESET i m M 10p s DIV 10p s DIV TPC 58 Output Swing TPC 60 Output Swing 500mV DIV 500mV DIV 200mV DIV 20mV DIV hi eJ 50ns DIV 50ns DIV TPC 59 1 V Step Response TPC 61 100 mV Step Response REV A 25 AD15700 CIRCUIT OPERATION The AD15700 contains precision components for interfacing analog I O to a processor Configuration for particular applications can be made with short external interconnect
44. gital 5 V core supply DVDD and a digital input output interface supply OVDD The OVDD supply allows direct interface with any logic working between 2 7 V and 5 25 V To reduce the number of supplies needed the digital core DVDD can be supplied through a simple RC filter from the analog supply The ADC is independent of power supply sequencing and thus free from supply voltage induced latchup Additionally it is very insensitive to power supply variations over a wide frequency range as shown in Figure 12 75 70 PSRR dB e e eo 45 40 35 1 10 100 1000 10000 FREQUENCY kHz Figure 12 vs Frequency POWER DISSIPATION In impulse mode the ADC automatically reduces its power consumption at the end of each conversion phase During the acquisition phase the operating currents are very low which allows a significant power savings when the conversion rate 15 reduced as shown in Figure 13 This feature makes the ideal for very low power battery applications This does not take into account the power if any dissipated by the input resistive scaler which depends on the input voltage range used and the analog input voltage even in power down mode There is no power dissipated when the 0 V to 2 5 V is used or when both the analog input voltage is 0 V and a unipolar range 0 V to 5 V or 0 V to 10 V is used It should be noted that the digital interface remains active even during the acquisi
45. headroom to each rail If low distortion 1s required in single supply applications for signals that swing close to ground an emitter follower circuit can be used at the amplifier output Figure 43 Low Distortion Line Driver for Single Supply Ground Referenced Signals ptt Tt et A NN ALN _ 7104 1 Figure 44 Output Signal Swing of Low Distortion Line Driver at 500 kHz VERTICAL SCALE 10dB DIV START 0Hz Figure 45 THD of Low Distortion Line Driver at 500 kHz STOP 5MHz REV A Figure 43 shows the amplifier configured as a single supply gain of two line driver With the output driving a back terminated 50 Q line the overall gain from to is unity In addition to minimizing reflections the 50 back termination resistor pro tects the transistor from damage if the cable 15 short circuited The emitter follower which is inside the feedback loop ensures that the output voltage from the amplifier stays about 700 mV above ground Using this circuit very low distortion is attain able even when the output signal swings to within 50 mV of ground The circuit was tested at 500 kHz and 2 MHz Figures 44 and 45 show the output signal swing and frequency spectrum at 500 kHz At this frequency the output signal at which has a peak to peak swing of 1 95 V 50 mV to 2 V hasa THD of 68 dB SEDR 77 dB Figures 46 and 47 show the output signal swing and frequency spectrum at 2 MHz As
46. idth and 10 offset drift provide ADC and DAC buffering capability The center tapped 3 resistors are precision resistor networks with 2 ppm C ratio tracking that provide low gain drift when used for scaling The ADC DAC and amp functions are electrically isolated from each other to provide maximum design flexibility Input and output signal conditioning circuits for the converters can be easily configured with short interconnects under the device at the board level The AD15700 15 available in a 10 mm CSPBGA package REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM VDD DAC Q DGND_DAC 14 BIT DAC m AGND DAC AD15700 Q SERIAL PORT SWITCHED 2 C SER PAR BUSY PARALLEL RD OB 2C AVDD WARP CNVST IMPULSE DVDD DGND ADC RA2 RB2 RC2 PRODUCT HIGHLIGHTS 1 Fast Throughput ADC AD15700 incorporates a high speed 1 MSPS 16 bit SAR ADC 2 Superior ADC INL The 16 bit
47. inimum BUSY HIGH Width Maximum Warp BUSY HIGH Width Maximum Normal BUSY HIGH Width Maximum Impulse TO OUTPUT PIN IN SERIAL INTERFACE MODES THE SYNC SCLK AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF OTHERWISE THE LOAD IS 60pF MAXIMUM Figure 1 Load Circuit for Digital Interface Timing SDOUT SYNC SCLK Outputs C 10 pF Figure 2 Voltage Reference Levels for Timing REV A AD15700 14 BIT DAC ELECTRICAL CHARACTERISTICS 40 to 8576 DAC 5 V 2 5 V unless otherwise noted Parameter Min Typ Max Unit STATIC PERFORMANCE Resolution 1 LSB Vggp 2 153 when VREF lt 2 5 Relative Accuracy INL Differential Nonlinearity Guaranteed Monotonic Gain Error Gain Error Temperature Coefficient Zero Code Error Zero Code Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time To 1 2 LSB of FS 10 pF Digital to Analog Glitch Impulse LSB Change around the Major Carry Digital Feedthrough All 1s Loaded to DAC DAC Output Impedance Tolerance Typically 20 Power Supply Rejection Ratio AVpp 10 DAC REFERENCE INPUT Reference Input Range Reference Input Resistance LOGIC INPUTS Input Current VINL Input Low Voltage VINH Input High Voltage Input Capacitance Hysteresis Voltage REFERENCE Reference 3 dB Bandwidth All 1s Loaded Reference Feedthrough 0s Loaded Vrer 1V p p at 100 kHz Signal
48. ltages up to 500 mV beyond the supply voltages Driving the input common mode voltage beyond that point will forward bias the collector junction of the input transistor resulting in phase reversal Sustaining this condition for any length of time should be avoided as it is easy to exceed the maximum allowed input differential voltage when the amplifier is in phase reversal Output Stage Open Loop Gain and Distortion Versus Clearance from Power Supply amplifier features rail to rail output stage The output transistors operate as common emitter amplifiers providing the output drive current as well as a large portion of the amplifier s open loop gain Ph DIFFERENTIAL DRIVE FROM INPUT STAGE asma QU Figure 40 Output Stage Simplified Schematic The output voltage limit depends on how much current the output transistors are required to source or sink For applica tions with very low drive requirements a unity gain follower driving another amplifier input for instance the amplifier typically swings within 20 mV of either voltage supply As the required current load increases the saturation output voltage will increase linearly as X Rc where is the required load current and is the output transistor collector resistance For the amplifier the collector resistances for both output tran sistors are typically 25 As the current load exceeds the rated output current of 15 mA the a
49. mount of base drive current required to drive the output transistor into saturation will reach its limit and the amplifier s output swing will rapidly decrease The open loop gain of the amplifier decreases approximately linearly with load resistance and also depends on the output voltage Open loop gain stays constant to within 250 mV of the positive power supply 150 mV of the negative power supply and then decreases as the output transistors are driven further into saturation The distortion performance of the amplifiers differs from conventional amplifiers an amplifier s distortion performance degrades as the output voltage amplitude increases 40 Used as a unity gain follower the amplifier output will exhibit more distortion in the peak output voltage region around Vcc 0 7 V This unusual distortion characteristic is caused by the input stage architecture and 15 discussed in detail in the section covering Input Stage Operation Output Overdrive Recovery Output overdrive of an amplifier occurs when the amplifier attempts to drive the output voltage to a level outside its normal range After the overdrive condition is removed the amplifier must recover to normal operation in a reasonable amount of time As shown in Figure 41 the amplifier recovers within 100 ns from negative overdrive and within 80 ns from positive overdrive Figure 41 Overdrive Recovery Driving Capacitive Loads Capacitive loads inte
50. n 11 V to 30 V to allow wide input voltage range Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs including INA 0 V to 5 V This will cause these diodes to become for ward biased and start conducting current These diodes can handle a forward biased current of 120 mA maximum For instance when using the 0 V to 2 5 V input range these condi tions could eventually occur on the input INA when the input buffer s U1 supplies are different from AVDD In such case an input buffer with a short circuit current limitation can be used to protect the part This analog input structure allows the sampling of the differential signal between the output of the resistive scaler and INGND Unlike other converters the INGND input is sampled at the same time as the inputs By using this differential input small signals common to both inputs are rejected as shown in Figure 10 which represents the typical CMRR over frequency For instance by using INGND to sense a remote signal ground differences of ground potentials between the sensor and the local ADC ground are eliminated During the acquisition phase for ac signals the ADC behaves like a one pole RC filter consisting of the equivalent resistance of the resistive scaler R 2 in series with The resistor is typically 100 Q and is lumped component made up of some serial resistor and the on resistance of the switches
51. n dd wa ed a b ARR 9 Edit to ADC PIN PUNCTION DESCRIPTIONS re OR ie cod 11 Edt NU a Ae ha eee 21 Chances to OUTLINE DIMENSIONS 3 53 wd d C66 5 n CORES EES 43 44 REV C03025 0 2 03 A PRINTED IN U S A
52. nts which minimizes potential feedthrough between digital activity and the critical conversion decisions In read after conversion mode it should be noted that unlike other modes the signal BUSY returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer BUSY width SLAVE SERIAL INTERFACE External Clock The ADC 15 configured to accept an externally supplied serial data clock on the SCLK pin when the EXT INT pin is held high In this mode several methods can be used to read the data The external serial clock is gated by 5 ADC and the data are output when both CS ADC and RD are low Thus depending on CS ADC the data can be read after each conversion or during the following conversion The external clock can be either a continuous or discontinuous clock discontinuous clock can be either normally high or normally low when inactive Figure 22 and Figure 24 show the detailed timing diagrams of these methods REV A 015700 EXT INT 0 RDC SDIN 0 INVSCLK INVSYNC 0 CS_ADC RD BUSY SYNC SCLK SDOUT Figure 20 Master Serial Data Timing for Reading Read after Convert 0 RDC SDIN 1 INVSCLK INVSYNC 0 CS ADC RD CNVST gt ts BUSY gt bo ty 24 be SCLK 2 3 14 15 16 t lt 1 16 23 Figure 21 Master Serial Data Timing for Reading
53. o This specification indicates how the output of the DAC 15 affected by changes in the power supply voltage Power supply rejection ratio is quoted in terms of percent change in output per percent change in for full scale output of the DAC is varied by 10 Reference Feedthrough This is a measure of the feedthrough from the input to the DAC output when the DAC 15 loaded with 08 A 100 kHz 1 V is applied to Reference feedthrough is expressed in mV p p REV A Typical Performance Characteristics AD15700 16 BIT D A CONVERTER INL LSB NUMBER OF UNITS 0 0 16384 32768 49152 65536 3 0 2 7 24 2 1 1 8 1 5 1 2 0 9 0 6 0 3 0 0 CODE NEGATIVE INL LSB TPC 1 Integral Nonlinearity vs Code TPC 4 Typical Negative INL Distribution 314 Units DNL LSB 0 16384 32768 49152 65536 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 8007 CODE CODE IN HEXADECIMAL TPC 5 Histogram of 16 384 Conversions of a DC Input at the Code Transition NUMBER OF UNITS 0 0 0 0 0 3 0 6 0 9 1 2 1 5 1 8 2 1 2 4 2 7 3 0 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 8007 POSITIVE INL LSB CODE IN HEXADECIMAL TPC 3 Typical Positive INL Distribution 314 Units TPC 6 Histogram of 16 384 Conversions of a DC Input at the Code Center REV A 15 AD15700 98 FS 1 MSPS fin 45 5322kHz SNR 89 45dB THD 100 05dB SFDR 100 49dB 3 SINAD 89 1dB 400
54. of a full scale input signal expressed in decibels Signal to Noise Ratio SNR ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency excluding harmonics and dc The value for SNR is expressed in decibels Signal to Noise Distortion Ratio S N D The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for S N D is expressed in decibels Aperture Delay A measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion Transient Response The time required the ADC to achieve its rated accuracy after a full scale step function is applied to its input 14 DAC DEFINITION SPECIFICATIONS Relative Accuracy For the DAC relative accuracy or integral nonlinearity INL is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function A typical INL versus code plot can be seen in TPC 16 Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity TPC 19 illustrates a typical DNL versus code plot Gain E
55. ough from the digital input lines Using a burst clock will minimize the effects of digital feedthrough on the analog signal channels Figure 38 shows a typical circuit SCLK O DIN O ENABLE O CODED O ADDRESS DECODER Figure 38 Addressing Multiple DACs H lt 8500 e sh oue m R8 4 _ AMPLIFIER THEORY OF OPERATION The amplifiers are single and dual versions of high speed low power voltage feedback amplifiers featuring an innovative archi tecture that maximizes the dynamic range capability on the inputs and outputs Linear input common mode range exceeds either supply voltage by 200 mV and the amplifiers show no phase reversal up to 500 mV beyond supply The output swings to within 20 mV of either supply when driving a light load 300 mV when driving up to 5 mA amplifier provides an impressive 80 MHz bandwidth when used as a follower and 30 V ms slew rate at only 800 mA supply current Careful design allows the amplifier to operate with a supply voltage as low as 2 7 V Input Stage Operation A simplified schematic of the input stage appears in Figure 39 For common mode voltages up to 1 1 V within the positive supply V to 3 9 on a single 5 V supply tail current I2 flows through the PNP differential pair 013 and 017 Q5 is cut off no bias current 1s routed to the parallel NPN differential pair Q2 and Q3 As the common mode voltage is driven within 1 1 V of
56. ould use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines Good decoupling is also impor tant to lower the supply impedance presented to the AD15700 and reduce the magnitude of the supply spikes Decoupling ceramic capacitors typically 100 nF should be placed on each power supply pin AVDD DVDD and OVDD close to and ideally right up against these pins and their corresponding ground pins Additionally low ESR 10 nF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple The DVDD supply of the AD15700 can be either a separate supply or come from the analog supply AVDD or from the digital interface supply OVDD When the system digital supply is noisy or fast switching digital signals are present it is recommended if no separate supply is available to connect the DVDD digital supply to the analog supply AVDD through an RC filter and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry When DVDD is powered from the system supply it is useful to insert a bead to further reduce high frequency spikes 35 AD15700 The AD15700 s ADC has five different ground pins INGND REFGND AGND DGND OGND INGND used to sense the analog input signal REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents AGND is
57. ract with an amplifier s output impedance to create an extra delay in the feedback path This reduces circuit stability and can cause unwanted ringing and oscillation given value of capacitance causes much less ringing when the amplifier is used with a higher noise gain The capacitive load drive of the amplifier can be increased by adding a low valued resistor in series with the capacitive load Introducing a series resistor tends to isolate the capacitive load from the feedback loop thereby diminishing its influence Figure 42 shows the effect of a series resistor on capacitive drive for varying voltage gains As the closed loop gain is increased the larger phase margin allows for larger capacitive loads with less overshoot Adding a series resistor at lower closed loop gains accomplishes the same effect For large capacitive loads the frequency response of the amplifier will be dominated by the roll off of the series resistor and capacitive load 1000 Vs 5 200mV STEP WITH 3096 OVERSHOOT 100 CAPACITIVE LOAD pF CLOSED LOOP GAIN V V Figure 42 Capacitive Load Drive vs Closed Loop Gain REV A 015700 High Performance Single Supply Line Driver Even though the amplifier swings close to both rails the amplifier has optimum distortion performance when the signal has a common mode level halfway between the supplies and when there is about 500 mV of
58. rror Gain error is the difference between the actual and ideal analog output range expressed as a percent of the full scale range It is the deviation in slope of the DAC transfer characteristic from ideal Gain Error Temperature Coefficient This is a measure of the change in gain error with changes in temperature It is expressed in ppm C Zero Code Error Zero code error 1s a measure of the output error when zero code is loaded to the DAC register Zero Code Temperature Coefficient This is a measure of the change in zero code error with a change in temperature It is expressed in mV C Digital to Analog Glitch Impulse Digital to analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state It is normally specified as the area of the glitch in nV s and is measured when the digital input code is changed by 1 LSB at the major carry transition A plot of the glitch impulse is shown in Figure 28 Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated CS_DAC 1s held high while the CLK and DIN signals are toggled It is specified in nV s and is measured with a full scale code change on the data bus i e from all Os to all 1s and vice versa A typical plot of digital feedthrough is shown in Figure 27 Power Supply Rejection Rati
59. s As shown in Figure 19 the LSB byte is output on D 7 0 and the MSB is output on D 15 8 when 15 low When BYTESWAP is high the LSB and MSB are swapped and the LSB is output on D 15 8 and the MSB is output on D 7 0 By connecting BYTESWAP an address line the 16 data bits can be read in two bytes on either D 15 8 or D 7 0 199 CS ADC RD Figure 19 8 Bit Parallel Interface SERIAL INTERFACE ADC is configured to use the serial interface when the SER PAR is held high The ADC outputs 16 bits of data MSB first on the SDOUT pin This data is synchronized with the 16 clock pulses provided on the SCLK pin The output data 15 valid on both the rising and falling edge of the data clock MASTER SERIAL INTERFACE Internal Clock The ADC is configured to generate and provide the serial data clock SCLK when the EXT INT pin 15 held low It also generates a SYNC signal to indicate to the host when the serial data is valid serial clock SCLK and the SYNC signal can be inverted if desired Depending on RDC SDIN input the data can be read after each conversion or during conversion Figures 20 and 21 show the detailed timing diagrams of these two modes Usually because the ADC is used with a fast throughput the mode master read during conversion is the most recommended serial mode when it can be used In read during conversion mode the serial clock and data toggle at appropriate insta
60. s method During a conversion while both CS ADC and RD are low the result of the previous conversion can be read The data 15 shifted out MSB first with 16 clock pulses and is valid on both the rising and falling edge of the clock The 16 bits have to be read before the current conversion is complete If that is not done RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading There is no daisy chain feature in this mode and RDC SDIN input should always be tied either high or low reduce performance degradation due to digital activity a fast discontinuous clock of at least 25 MHz when impulse mode is used and 32 MHz when normal or 40 MHz when warp mode is used is recommended to ensure that all the bits are read during the first half of the conversion phase It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated That allows the use of a slower clock speed like 18 MHz in impulse mode 21 MHz in normal mode and 26 MHz in warp mode INVSCLK 0 RD 0 14 15 16 gt 8 0 Figure 24 Slave Serial Data Timing for Reading Read Previous Conversion during Convert mA REV A 015700 MICROPROCESSOR INTERFACING ADC is ideally suited for traditional dc measurement appli cations supporting a microprocessor and ac signal processing applications interfacing to a digit
61. s under the device ANALOG INPUT 0 2V TO 2REF ADR421 OR AD780 2 5V OR 3 0V REF 47 0 14 F SUPPLY 5V 0 1 pF I AGND DIGITAL SUPPLY 3 3V OR 5V DGND ANALOG OUTPUT 0 2V TO 2REF NOTES 1 FORMS AN R C FILTER WITH THE 6 25 NOMINAL OUTPUT RESISTANCE OF THE DAC 2 C2 FORMS PART OF THE ADC INPUT FILTER SEE ANALOG INPUT SECTION TYPICAL CONNECTION DIAGRAM Figure 4 shows how using a minimum of external devices the com ponents within the AD15700 can be interconnected to form a complete analog interface to a processor The circuit implements signal conditioning that includes buffering filtering and voltage scaling AD15700 AGND_ADC DVDD DGND_ADC SER PAR WARP RDC SIN INVSCLK INVSYNC EXT INT DIVSCLK1 DIVSCLKO IMPULSE CS ADC RD BYTESWAP Figure 4 Typical Connection Diagram 26 DSP uP REV A 015700 Analog Input Section Made up of a buffer amplifier an RC filter and an ADC the analog input circuit allows measurement of voltages ranging from 0 2 V to 2 REF V When placed in the 0 V to REF input range the circuit has the configuration shown in Figure 5a ANALOG INPUT Figure 5 Analog Input Circuit The filter is made up of one of the AD15700 s internal center tapped resistors an external capacitor C2 plus the ADC s internal resistance and capacitance The transfer function of this filter is given by 8
62. the advantages of this method is that the conversion perfor mance is not degraded because there are no voltage transients on the digital interface during the conversion process Another advan tage is to be able to read the data at any speed up to 40 MHz which accommodates both slow digital host interface and the fastest serial reading Finally in this mode only the ADC provides a daisy chain feature using the RDC SDIN input pin for cascading multiple converters together This feature 15 useful for reducing component count and wiring connections when desired as for instance in isolated multiconverter applications An example of the concatenation of two devices 15 shown in Figure 23 Simultaneous sampling 15 possible by using a common CNVST signal It should be noted that the RDC SDIN input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT Therefore the MSB of the upstream converter just follows the LSB of the downstream converter on the next SCLK cycle 1 CS ADC CNVST BUSY lt 155 gt t lt ty SDOUT BUSY AD15700 NO 2 UPSTREAM BUSY AD15700 NO 1 DOWNSTREAM RDC SDIN SDOUT RDC SDIN SDOUT CNVST CNVST CS ADC SCLK CS ADC SCLK SCLK INO CS ADC IN O CNVST IN O Figure 23 Two AD15700s in a Daisy Chain Configuration External Clock Data Read during Conversion Figure 24 shows the detailed timing diagrams of thi
63. the ground to which most internal ADC analog signals are referenced This ground must be connected with the least resistance to the analog ground plane DGND must be tied to the analog or digital ground plane depending on the configuration OGND is connected to the digital system ground The layout of the decoupling of the reference voltage is important The decoupling capacitor should be close to the ADC and connected with short and large traces to minimize parasitic inductances 5 OUT 0 5V DIV o Figure 29 Large Signal Settling Time 36 lt our 1V DIV Vout 50mV DIV GAIN 216 89 Figure 30 Small Signal Settling Time DAC Circuit Information DAC is a single 14 bit serial input voltage output It operates from a single supply ranging from 2 7 V to 5 V and consumes typically 300 mA with a supply of 5 V Data 15 written to the devices a 14 bit word format via a 3 or 4 wire serial interface To ensure a known power up state the parts were designed with a power on reset function In unipolar mode the output is reset to Digital to Analog Section DAC architecture consists of two matched DAC sections A simplified circuit diagram is shown in Figure 21 The four MSBs of the 14 bit data word are decoded to drive 15 switches 1 to E15 Each of these switches connects one of 15 matched resistors to either AGND or VREF
64. tion phase To reduce the operating digital supply currents even further the digital inputs need to be driven close to the power rails 1 DVDD and DGND OVDD should not exceed DVDD by more than 0 3 V REV A 015700 100000 WARP NORMAL 10000 1000 100 10 5 IMPULSE 1 0 1 1 10 100 1000 10000 100000 1000000 SAMPLING RATE SPS Figure 13 Power Dissipation vs Sample Rate CONVERSION CONTROL Figure 14 shows the detailed timing diagrams of the conversion process The ADC is controlled by the signal CNVST which initiates conversion Once initiated it cannot be restarted or aborted even by the power down input PD until the conver sion is complete CNVST signal operates independently of CS ADC and RD signals BUSY t t gt tc t gt MODE ACQUIRE 17 gt Figure 14 Basic Conversion Timing In impulse mode conversions can be automatically initiated If CNVST is held low when BUSY is low the ADC controls the acquisition phase and then automatically initiates a new conversion By keeping CNVST low the A
65. to Noise Ratio Reference Input Capacitance Code 0000g Code 3FFFy POWER REQUIREMENTS Vpp Ipp Power Dissipation Reference input resistance is code dependent minimum at 2555 y Specifications subject to change without notice 6 REV AD15700 Von 5 5 Veer 2 5 V AGND DEND 0 V All Specifications 14 DAC TIMING CHARACTERISTICS to unless otherwise noted MHz max SCLK Cycle Frequency ty ns min SCLK Cycle Time to ns min SCLK High Time ns min SCLK Low Time t4 ns min CS DAC Low to SCLK High Setup t5 ns min CS DAC High to SCLK High Setup tg ns min SCLK High to CS DAC Low Hold Time t7 ns min SCLK High to CS_DAC High Hold Time tg ns min Data Setup Time to ns min Data Hold Time tio ns min CS_DAC High Time between Active Periods NOTES 1 Guaranteed by design Not production tested 2 Sample tested during initial release and after any redesign or process change that may affect this parameter All input signals are measured with tr tf 5 ns 10 to 90 of 3 V and timed from a voltage level of 1 6 V Specifications subject to change without notice SCLK CS DAC DIN Figure 3 Timing Diagram REV A 7 AD15700 9 V Supply T 25 C V 5 V Ri 1 to 2 5 V 2 5 AMPLIFIER ELECTRICAL CHARACTERISTICS unless otherwise noted Parameter DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth Slew Rate Settling Time to 0 196
66. ultiplexed channel applications It is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler The ADC can be operated from a single 5 V supply and be inter faced to either 5 V or 3 V digital logic ADC CONVERTER OPERATION The ADC is a successive approximation analog to digital con verter based on a charge redistribution DAC Figure 7 shows the simplified schematic of the ADC The input analog signal 15 first scaled down and level shifted by the internal input resistive scaler which allows both unipolar ranges 0 V to 2 5 V 0 V to 5 V and 10 V and bipolar ranges 2 5 5 V and 10 V The output voltage range of the resistive scaler is always 0 V to 2 5 V The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional LSB capacitor The comparator s negative input is connected to a dummy capacitor of the same value as the capacitive DAC array During the acquisition phase the common terminal of the array tied to the comparator s positive input is connected to AGND via SWA independent switches are connected to the output of the resistive scaler Thus the capacitor array is used as a sampling capacitor and acquires the analog signal Similarly the dummy capacitor acquires the analog signal on INGND input When the acquisition phase is complete and the CNVST input goes or 15 low a conversion phase is initiated When the
67. ures three modes of operation warp normal and impulse Each of these modes is more suitable for specific applications warp mode allows the fastest conversion rate up to 1 MSPS However in this mode and this mode only the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms If the time between two con secutive conversions is longer than 1 ms for instance after power up the first conversion result should be ignored This mode makes the ADC ideal for applications where both high accuracy and fast sample rate are required ADC CODE Straight Binary 000 010 The normal mode 15 the fastest mode 800 kSPS without any 000 001 limitation about the time between conversions This mode makes 000 000 the ADC ideal for asynchronous applications such as data FS acquisition systems where both high accuracy and fast sample rate are required FS 1LSB 5 116 FS 0 5LSB 5 1 5LSB ANALOG INPUT impulse mode the lowest power dissipation mode allows Figure 8 ADC Ideal Transfer Function power saving between conversions The maximum throughput Table III Output Codes and Ideal Input Voltages Digital Output Code Hexadecimal Straight Twos Binary Complement Analog Input Description 0 V to 2 5 V 38 15 uV 10V 305 2 5 V 152 6 uV 2 5 V 76 3 uV 0 V to 10 V 152 6 uV OVto5 V 76 3 UV Full Scale Range Least Significant
68. ut Bus When SER PAR 15 HIGH this input part of the Serial Port is used as a digital output frame synchronization for use with the internal data clock EXT INT Logic LOW When a read sequence is initiated and INVSYNC is LOW SYNC is driven HIGH and remains HIGH while SDOUT output 15 valid When a read sequence is initiated and INVSYNC is High SYNC is driven LOW and remains LOW while SDOUT output is valid When SER PAR 15 LOW this output is used as Bit 11 of the Parallel Port Data Output Bus When SER PAR is HIGH and EXT INT is HIGH this output part of the Serial Port is used as an incomplete read error flag In Slave Mode when a data read is started and not complete when the following conversion is complete the current data is lost and RDERROR is pulsed high Bit 12 to Bit 15 of the Parallel Port Data Output Bus When SER PAR is HIGH these outputs are in high impedance Busy Output Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on chip shift register The falling edge of BUSY could be used as a data ready clock signal Must be Tied to Digital Ground Read Data When CS ADC and RD are both LOW the interface parallel or serial output bus is enabled Chip Select When CS ADC and RD are both LOW the interface parallel or serial output bus is enabled 5 is also used to gate the external serial clock Reset Input When set to a
69. vert 25 275 525 Warp Mode Normal Mode Impulse Mode SYNC Asserted to SCLK First Edge Delay Internal SCLK Period Internal SCLK HIGH Internal SCLK LOW SDOUT Valid Setup Time SDOUT Valid Hold Time SCLK Last Edge to SYNC Delay CS ADC HIGH to SYNC HI Z CS ADC HIGH to Internal SCLK HI Z CS ADC HIGH to SDOUT HI Z BUSY HIGH in Master Serial Read after Convert See Table II CNVST LOW to SYNC Asserted Delay 0 75 1 1 25 Master Serial Read after Convert SYNC Deasserted to BUSY LOW Delay Refer to Figures 22 and 24 Slave Serial Interface Modes External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW NOTES Warp Mode only the maximum time between conversions is 1 ms otherwise there is no required maximum time In Serial Interface Modes the SYNC SCLK and SDOUT timings are defined with a maximum load C of 10 pF otherwise the load is 60 pF maximum In serial master Read during Convert Mode See Table II Specifications subject to change without notice 4 REV A 015700 Table II Serial Clock Timings in Master Read after Convert DIVSCLK 1 DIVSCLK 0 SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay M
70. ynamic Range fn 250 kHz Total Harmonic Distortion fin 20 kHz fin 250 kHz fin 20 kHz fin 250 kHz 60 dB Input Signal to Noise Distortion 3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Full Scale Step REFERENCE External Reference Voltage Range External Reference Current Drain MSPS Throughput DIGITAL INPUTS Logic Levels Vir Vin Ir 2 REV A 1015700 Parameter Min Typ Max Unit DIGITAL OUTPUTS Data Format Parallel or Serial 16 Bit Pipeline Delay Conversion Results Available Immediately after Completed Conversion VoL Ismk 1 6 mA 0 4 IsouRCE 570 OVDD 0 6 POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current AVDD DVDD OVDD Power Dissipation 6 666 kSPS Throughput 100 SPS Throughput 1 MSPS Throughput In Power Down Mode TEMPERATURE RANGE Specified Performance to 40 85 C NOTES LSB means Least Significant Bit With the 5 V input range one LSB is 152 588 uV l hese specifications do not include the error contribution from the external reference All specifications in dB are referred to a full scale input FS Tested with an input signal at 0 5 dB below full scale unless otherwise specified 4 Warp Mode Tested in Parallel Reading Mode l ested with the 0 V to 5 V range and VIN VINGND 0 V Impulse Mode 5With OVDD below DVDD 0 3 V and all

ANALOG DEVICES AD15700 1 MSPS 16-/14-Bit Analog I/O Port handbook

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