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ANALOG DEVICES AD13280 handbook

1. ert nsult Analog Devices Application AN 501 Aperture Uncertainty and ADC System Performance 71 70 5MHz 69 68 Ain 10MHz 67 66 65 20MHz o 62 61 60 37MHz 59 58 ooo oo e NNN 02386 019 Figure 19 SNR vs Jitter Rev C Page 15 of 28 013280 POWER SUPPLIES Care should be taken when selecting a power source Linear supplies are strongly recommended Switching supplies tend to have radiated components that may be received by the AD13280 Each of the power supply pins should be decoupled as close as possible to the package using 0 1 chip capacitors The AD13280 has separate digital and analog power supply pins The analog supplies are denoted and the digital supply pins are denoted DVcc AVcc and DVcc should be separate power supplies because the fast digital output swings can couple switching current back into the analog supplies Note that AVcc must be held within 596 of 5 V The AD13280 is specified for DVcc 3 3 V because this is a common supply for digital ASICs OUTPUT LOADING Care must be taken when designing the data receivers for the AD13280 The digital outputs drive an internal series resistor for example 100 Q followed by a gate like 75LCX574 To minimize cap
2. 2 5 AGNDA 2 ENCODEA ENCODEA DOA LSB 5 D2A N 2 4 5 DGNDA 2 02386 002 Table 3 Pin Funct 5 Pin No e c esc 1 35 SHIELD 2 3 9 10 13 16 AGNDA 4 A IN 5 A IN 6 AMP OUT A 7 AMP IN A 1 8 AMP IN A 2 11 AVEEA 12 AVCCA 14 ENCODEA 15 ENCODEA 17 DVCCA 18 19 37 38 NC 20 to 25 28 to 33 DOA to D11A 26 27 DGNDA 34 DROUTA 36 DROUTB 39 to 42 45 to 52 DOB to D11B 43 44 DGNDB 53 DVCCB Internal Ground Shield Between Channels Inverting Differential Input Gain 1 Noninverting Differential Input Gain 1 Single Ended Amplifier Output Gain 2 No Connect Digital Outputs for ADC A DO LSB A Channel Digital Ground Data Ready A Output Data Ready B Output Digital Outputs for ADC B DO LSB B Channel Digital Ground com AD A Channel Analog Ground A and B grounds should be connected as close to the device as possible Analog Input for A Side ADC Nominally 0 5 V Analog Input for A Side ADC Nominally 1 0 V A Channel Analog Negative Supply Voltage Nominally 5 0 V or 5 2 V A Channel Analog Positive Supply Voltage Nominally 5 0 V Complement of ENCODEA Differential input Encode Input Conversion initiated on rising edge A Channel Digital Positive Supply Voltage Nominally 5 0 V 3 3 V B Channel Dig
3. Current Full 38 49 DVcc Supply Voltage Full IV 3 135 33 3 465 V Rev C Page 5 of 28 013280 AD13280AZ Parameter Temperature TestLevel Min Typ Max Unit DVcc Current Full 34 46 mA Icc Total Supply Current per Channel Full 375 459 mA Power Dissipation Total Full 3 7 43 Power Supply Rejection Ratio PSRR Full V 0 01 96 FSR 96 VS All ac specifications tested by driving ENCODE and ENCODE differentially Single ended input AMP IN x 1 1 V p p AMP IN x 2 GND 2 Gain tests are performed on the AMP IN x 1 input voltage range 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency as determined by FFT analysis is reduced by 3 dB 4 For differential input IN 1 V and IN 1 V p p signals are 180 out of phase For single ended input IN 2 V and IN GND 5 Minimum and maximum conversion rates allow for variation in encode duty cycle of 5096 596 6 Analog input signal power at 1 dBFS signal to noise ratio SNR is the ratio of signal level to total noise first five harmonics removed Encode 80 MSPS SNR is reported in dBFS related back to converter full scale 7 Analog input signal power at 1 dBFS signal to noise and distortion SINAD is the ratio of signal level to total noise harmonics Encode 80 MSPS SINAD is reported in dBFS related back to converter full scale 8 Analog input signal at
4. ezezejen 02386 020 Figure 20 Evaluation Board Mechanical Layout Rev C Page 17 of 28 013280 J13 SMA AGNDA AGNDA 5 E68q E66 67 595422250 AGNDB 5VAA 2446 422 5VAB 10 22 60 272 2825 I lt AGNDB AGNDB T Avec 59 0 1 AGENDA 7 12 E lt lt lt lt lt EE Fog AGNDB 5VAA 1 AVccB 5VAB C35 C34 C17 C38 AGNDB o tur T AGNDA AGNDA AGNDB ENCODEA ENCODEA ENCODEB ENCODEB T 15 55 T AGNDA ENCODEA T ENCODEA ENCODEB ENCODEB DB QUT AGNDA AGNDB AGNDB OUT 3 3VDB DVccA U1 DVccB C36 C10 18 AD13280AZ 52 C18 C37 T D11B MSB D11B T o tuF NC1A NC D10B D10B 20 50 DOA DOA LSB D9B D9B 21 49 DGNDB DONDA DiA D1A D8B D8B 22 48 D2A D2A D7B D7B 23 47 D3A D3A D6B 24 46 D4A D4A D5B 25 45 D5A D5A lt DGNDA 26 5 44 5 A 2 Aeneas fo a zz DRAOUT DRBOUT E560 E55 LIDB E65 DGNDAV E48 470 470 470 3VDA 20 3VAA 20 20 BJ10 100MHz 100MHz C29 C12 10uF O 1pF DGNDA 470 3VDB
5. 28 B5B 5 DGNDB 2 BIB R36 1000 26 B6B LSB BOB R35 1000 25 Em 27 25 DUT 3 3VDB F2B R34 1000 EIE 23 aos R33 1000 FOB DGNDB R32 1000 B10B R31 1000 DGNDB B11B MSB DGNDB Figure 22 Evaluation Board Rev C Page 19 of 28 AD13280 02386 022 013280 R42 J5 1000 ENCODE C1 C7 SMA 0 1uF 0 1yF BJ3 mem 6 ENCODEA Oi R1 ENCODEA BJ4 AGNDA 500 Ca 0 1 AGNDA AGNDA MC10EP16 NC NO CONNECT AGNDA R56 DGNDA 33o V J12 c2 R55 DGNDA SMA 0 1uF 0 1uF 9 R41 250 AGNDA MC10EP16 NC NO CONNECT V DGNDA MC100EPT23 DENDA NC NO CONNECT R52 1009 J10 ENCODE C22 C24 DGNDA SMA 0 1 0 1 C ENCODEB E38 R54 ENCODEB E29 AGNDB 7500 28 OE1 L 0 1uF E36 AGNDB 10 16 O E14 NC NO CONNECT AGNDB E45 DGNDB 3a 23 R39 C25 DGNDB DGNDB SMA 0 1uF 0 1 DGNDB 26 801 0802 0803 AGNDB Di DES BUFLATB MC10EP16 NC NO CONNECT DGNDB DGNDB MC100EPT23 NC NO CONNECT Figure 23 Evaluation Board Rev C Page 20 of 28 AGNDA 02386 023 DEVICES 11 08 00 Di EVALUATION BOARD NDB 5 5 H3 3VDB E Figure 25 Top Layer Rev C Page 21 of 28 013280 920 98 20 Figure 26 GND1 120 9820 Figure 27 GND2 Rev C
6. ENCODE pulse should be left in a Logic 1 state to achieve the rated performance Pulse width low is the minimum time the ENCODE pulse should be left in a low state At a given clock rate these specifications define an acceptable encode duty cycle Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit Maximum Conversion Rate The encode rate at which parametric testing is performed Output Propagation Delay The delay between a differential crossing of the ENCODEA signal and the ENCODEA signal and the time at which all output data bits are within valid logic levels Overvoltage Recovery Time The amount of time required for the converter to recover to 0 0296 accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage Signal to Noise and Distortion SINAD The ratio of the rms signal amplitude set at 1 dB below full scale to the rms value of the sum of all other spectral compo nents
7. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implie lute iti nay affect maximum extende device 013280 EXPLANATION OF TEST LEVELS 1 10096 production tested II 10096 production tested at 25 C and sample tested at specified temperatures AC testing done on a sample basis III Sample tested only IV Parameter guaranteed by design and characterization testing V Parameter is a typical value only VI 100 production tested with temperature at 25 C and sample tested at temperature extremes ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features 4 patented or proprietary protection circuitry damage C Rev C Page 7 of 28 013280 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGNDB 2 ENCODEB 2 ENCODEB AGNDB 3 0118 MSB m 5 lt eo m 5 gt gt gt lt lt a 59 58 53 AGNDB 61 AMP IN B 2 62 AMP IN B 1 63 AMP OUT B 64 AD13280 TOP VIEW 4 Not to Scale IDENTIFIER AMP OUT A 6 AMP IN A 1 AMP IN A 2 8 AGNDA 9 AGNDA 2
8. 25 x 45 0 008 0 20 3PLS 0 007 0 18 1 0 235 5 97 0 020 0 508 0 055 1 40 0 017 0 432 0 050 1 27 0 014 0 356 0 045 1 14 RO G DIMENSIONS ARE IN INCHES ENS 2 SES ARE ROUN OFF INCH EQUIVALE Q S ONLY ANDARE NO RIATE S DESIGN S Figure 30 68 Lead Ceramic Leaded Chip Carrier with Nonconductive Tie Bar CLCC ES 68 1 Dimensions shown in inches and millimeters 0 235 5 97 0 960 24 38 0 010 0 25 0 950 24 13 SQ gt 0 008 0 20 0 940 23 88 0 007 0 18 ra 4 070 0 800 TOP VIEW 190 30 23 27 18 20 32 PINS DOWN 180 29 97 TOE DOWN MIN BSC 29 72 ANGLE 0 8 DEGREES 0 010 0 254 30 0 050 1 27 i H 0 060 1 52 1 1 52 DETAIL A 0 020 0 508 0 050 1 27 DETAIL A 0 040 1 02 ROTATED 90 CCW 0175 0 055 1 40 0 020 0 508 0 050 1 27 0 017 0 432 0 045 1 14 0 014 0 356 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 31 68 Lead Ceramic Leaded Chip Carrier CLCC ES 68 C Dimensions shown in inches and millimeters 012908A Rev C Page 25 of 28 013280 ORDERING GUIDE Model Temperature Range Package Description Package Option
9. AD13280AZ 25 to 85 68 Lead Ceramic Leaded Chip Carrier CLCC ES 68 C AD13280AF 25 C to 85 68 Lead Ceramic Leaded Chip Carrier with Nonconductive Tie Bar CLCC ES 68 1 AD13280 PCB Evaluation Board with AD13280AZ 1 Referenced temperature is case temperature 2 Z is a package indicator the part is not RoHS compliant ww BDTI com ADI Rev C Page 26 of 28 013280 NOTES ww BDTI com ADI 013280 NOTES ww BDTI com ADI 2002 2008 Analog Devices Inc rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners DEVICES er ee Rev C Page 28 of 28
10. Equal attention to system level signal paths must be provided in order to realize significant perform ance improvements Rev C Page 14 of 28 APPLICATIONS INFORMATION ENCODING THE AD13280 The AD13280 encode signal must be a high quality extremely low phase noise source to prevent degradation of performance Maintaining 12 bit accuracy at 80 MSPS places a premium on encode clock phase noise SNR performance can easily degrade 3 dB to 4 dB with 37 MHz input signals when using a high jitter clock source See Analog Devices Application Note AN 501 Aperture Uncertainty and ADC System Performance for com plete details For optimum performance the AD13280 must be clocked differentially The encode signal is usually ac coupled into the ENCODE and ENCODE pins via a transformer or capacitors These pins are biased internally and require no additional bias Figure 17 shows one preferred method for clocking AD13280 The clock source low jitter is converted from single ended to differential using an RF transformer The back to back Schottky diodes across the transformer secondary limit clock excursions into the AD13280 to approximately 0 8 V p p differential This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD13280 and limits the noise presented to the ENCODE inputs A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limited resistor
11. GND AMP IN x 2 200 when AMP IN x 1 is open Each channel has two analog inputs AMP IN A 1 and AMP IN A 2 or AMP IN B 1 and AMP IN B 2 Use AMP IN A 1 or AMP IN B 1 when an input of 0 5 V full scale is desired Use AMP IN A 2 or AMP IN B 2 when 1 V full scale is desired Each channel has an AMP OUT that must be tied to either a noninverting or inverting input of a differential amplifier with the remaining input grounded For example Side A AMP OUT A Pin 6 must be tied to A IN Pin 5 with A IN Pin 4 tied to ground for converting eration or AMP OUT A Pi d A IN i ING Each channel of the AD13280 is designed with two optional differential inputs A IN A IN and B IN B IN The inputs provide system designers with the ability to bypass the AD8045 amplifier and drive the AD8138 directly The AD8138 differen tial ADC driver can be deployed in either a single ended or differential input configuration The differential analog inputs have a nominal input impedance of 620 and nominal full scale input range of 1 2 V p p The AD8138 amplifier drives a differential filter and the custom analog to digital converter The differential input configuration provides the lowest even order harmonics and signal to noise SNR performance improvement of up to 3 dB SNR 73 dBFS Exceptional care was taken in the layout of the differential input signal paths The differential input transmission line characteristics are matched and balanced
12. Page 22 of 28 803A 2 Ee cr n a 0 aa ua an a a E D 8243 8 en m TUO 89MA ET n atarua 5 1 STARUB MES EL eee a S a gi 19 0 S 3 Pen x 8 ear ao aud 8 eam avo aa 53 8 TUOARQ o m hu Poroci en g om 888 oon eto c E s T ATAUS 50 u 1 a TUOARQ TUO 5 E n n a 5 ena AONA 19 AQVE E Figure 28 Bottom Silk Figure 29 Bottom Layer Rev C Page 23 of 28 02386 028 02386 029 AD13280 013280 BILL OF MATERIALS LIST FOR EVALUATION BOARD Table 4 Component Qty Name Reference Value Description Manufacturing Part Number 2 74LCX16374MTD U7 U8 Latch 741 16374 Fairchild 1 AD13280AZ U1 AD13280 AD13280AZ 2 ADP3330 U5 U6 Regulator ADP3330ART 3 3RL7 10 BJACK BJ1 to BJ10 Banana jacks 108 0740 001 Johnson Components 2 BRESO805 R41 R53 250 0805 SM resistor ERJ 6GE
13. achieve exceptional channel matching impedance control and performance while maintaining excellent isolation and providing for significant board area savings Multiple options are provided for driving the analog input including single ended differential and optional series fil tering The AD13280 also offers users a choice of analog input signal ranges to further minimize additional external signal conditioning while remaining general purpose The AD13280 operates with 5 0 V for the analog signal condi tioning with a separate 5 0 V supply for the analog to digital conversion and 3 3 V digital supply for the output stage Each channel is completely independent allowing operation with independent encode and analog inputs and maintaining minimal crosstalk and interference The AD13280 is available in a 68 lead ceramic gull wing package The components are manufactured using the Analog Devices Inc high speed complementary bipolar process XFCB ww BDTI com ADI Rev C Page 3 of 28 013280 SPECIFICATIONS 5 V 5 V DVcc 43 3 V applies to each ADC with front end amplifier unless otherwise noted Table 1 AD13280AZ Parameter Temperature TestLevel Min Typ Max Unit RESOLUTION 12 Bits DC ACCURACY No Missing Codes Full IV Guaranteed Offset Error 25 C 2 2 1 0 2 2 96 FS Full VI 22 1 0 2 2 96 FS Offset Error Channel Match Full VI 1 0 0 1 1 0 96 Gai
14. cond ADI 10 35 60 85 11 0 135 16 0 18 5 21 0 23 5 26 0 FREQUENCY MHz Figure 11 Pass Band Ripple to 25 MHz 02386 010 Rev C Page 11 of 28 013280 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency as determined by the FFT analysis is reduced by 3 dB Aperture Delay The delay between a differential crossing of the ENCODEA signal and the ENCODEA signal and the instant at which the analog input is sampled Aperture Uncertainty Jitter The sample to sample variation in aperture delay Differential Analog Input Resistance Differential Analog Input Capacitance and Differential Analog Input Impedance The real and complex impedances measured at each analog input port The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer Differential Analog Input Voltage Range The peak to peak differential voltage that must be applied to the converter to generate a full scale response Peak differential voltage is computed by observing the voltage from the other pin which is 180 degrees out of phase Peak to dim differential is computed by rotating the input phase 180 degree the peak measuyem i ifferend ist between both p 5 Differential Nonlinearity The deviation of any code from an ideal 1 LSB step ENCODE Pulse Width Duty Cycle Pulse width high is the minimum amount of time that the
15. typically ies with the pr CLOCK SOURCE HSMS2812 DIODES 02386 017 Figure 17 Crystal Clock Oscillator Differential Encode If alow jitter ECL PECL clock is available another option is to ac couple a differential ECL PECL signal to the encode input pins as shown below A device that offers excellent jitter per formance is the MC100LVEL16 or within the same family from Motorola ECL PECL 02386 018 VT Figure 18 Differential ECL for Encode AD13280 JITTER CONSIDERATION The signal to noise ratio for any ADC can be predicted When normalized to ADC codes Equation 1 accurately predicts the SNR based on three terms These are jitter average DNL error and thermal noise Each of these terms contributes to the noise within the converter 2 2 1 V rms SNR 20x log 1 2 N 2 1 where fanaroc is the analog input frequency ty mms is the rms jitter of the encode rms sum of encode source and internal encode circuitry isthe average DNL of the ADC typically 0 50 LSB Nis the number of bits in the ADC rms is the analog input of the ADC typically 5 LSB For a 12 bit analog to digital converter like the AD13280 aperture jitter can greatly affect the SNR performance as the analog frequency is increased The chart below shows a family of curves that demonstrates the expected SNR performance of the AD13280 as jitter increases Ehe erived from Eq
16. 1 dBFS SFDR is the ratio of converter full scale to worst spur Both input tones at 7 dBFS two tone intermodulation distortion IMD rejection is the ratio of either tone to the worst third order intermodulation product 10 Channel to channel isolation tested with A channel grounded and a full scale signal applied to channel Digital output logic levels DVcc 3 3 V 10 pF Capacitive loads gt 10 pF degrades performance 12 Supply voltage recommended operating range AVcc may be varied from 4 85 V to 5 25 V However rated ac harmonics performance is valid only over the range AVcc 5 0 V to 5 25 V TIMING DIAGRAM N 3 Ain 2 fi 4 te ENCODE 7 FETTEN frc a ENCODE TRE c d idt 522 4 te top uim X gt DRY 8 2 Rev C Page 6 of 28 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Ratings ELECTRICAL AVcc Voltage OVto7V AVe Voltage 7Vto0V DVcc Voltage OVto7V Analog Input Voltage Vee to Analog Input Current 10 mA 10 10 mA Digital Input Voltage ENCODE 0 to Vcc ENCODE ENCODE Differential Voltage 4V max Digital Output Current 10 10 ENVIRONMENTAL Operating Temperature Range Case 40 C to 85 C Maximum Junction Temperature 175 C Lead Temperature Soldering 10 sec 300 C Storage Temperature Range Ambient 65 C to 150 C Typical thermal impedance for ES package 9 2 2 C W 24 3 C W
17. 20 c30 C16 10pF To 1uF DGNDB DUT_3 3VDA DUT_3 3VDB U1 C4 C21 mer e AGNDB AGNDB Figure 21 Evaluation Board Rev C Page 18 of 28 470 20 100MHz 02386 021 R47 00 24 n R48 22 00 21 V DGNDA 20 19 18 LSB DOA DIA ud 16 15 14 13 12 1 10 9 8 7 6 5 4 D10A 3 MSB 2 1 23 R50 27 22 00 DGNDB 21 V DGNDB 20 19 DUT 3 3VDB 18 LSB DOB DiB 17 16 15 14 13 12 11 DGNDB 10 9 DUT 3 3VDB 7 6 DGNDB B 4 D10B 3 MSB D11B 2 1 500 LATCHB E57 74LCX16374 DGNDA gt R18 DNI FOA R17 DNI FIA F2A R40 DNI F3A DUT_3 3VDA R44 1000 BOA LSB R45 1000 DGNDA 2 R46 1000 B2A R15 1000 B3A R14 1000 B4A R13 1000 B5A Denna gt R24 1000 B6A R23 1000 B7A DUT_3 3VDA R22 1000 B8A R21 1000 B9A DGNDA R20 1000 B10A R19 1000 B11A MSB MSB B11A 15 10uF BOA DGNDA B8A B7A B6A B5A LSB F3A F2A F1A DGNDA N m A DGNDA D DB R11 DNI J2 FOB R10 DNI H40DN ne 3 3VDB 40 DGNDB gt d 39 R30 DNI 9 MSB R29 DNI EUH c14 B10B 38 10pF 37 F3B l E DUT 3 3VDB R28 1000 DGNDB 35 158 7 R27 1000 34 TE 505 DGNDB B5B 32 R26 100 R12 1000 ESA B3B E63 R9 1000 m 29 R25 1000
18. 5 eene 18 Changes to Figure 21 19 Changes to Figure 22 20 Changes to Figure 23 wal Changes to Figure 28 and 29 24 Updated Outline Dimensions eerte 25 Changes to the Ordering Guide sss 26 Input and Output 13 Thery of Operation es peii en mentiri 14 Using the Single Ended Input sss 14 Using the Differential 14 Applications Information 15 Encoding the 13280 n ettet 15 Jitter 1 15 Power Supplies ERR ep E ettet pred 16 Output Loading 16 Evaluation Board RE pec ee 17 Layout Informations t reU 17 Bill of Materials List for Evaluation Board 24 Outline Dimensions eee 25 Ordering Guide 26 8 02 Rev 0 to Rev dits to Specifications Rev Page 2 of 28 013280 GENERAL DESCRIPTION The AD13280 is a complete dual channel signal processing solution that includes on board amplifiers references ADCs and output termination components to provide optimized system performance The AD13280 has on chip track and hold circuitry and uses an innovative multipass architecture to achieve 12 bit 80 MSPS performance The AD13280 uses innovative high density circuit design and laser trimmed thin film resistor networks to
19. ANALOG DEVICES Dual Channel 12 Bit 80 MSPS ADC with Analog Input Signal Conditioning AD13280 FEATURES Dual 80 MSPS minimum sample rate Channel to channel matching 190 gain error 90 dB channel to channel isolation DC coupled signal conditioning 80 dB spurious free dynamic range Selectable bipolar inputs 1 V and 0 5 V ranges Integral single pole low pass Nyquist filter Twos complement output format 3 3 V compatible outputs 1 85 W per channel APPLICATIONS Radar processing optimized for I Q baseband operation Phased array receivers Multichannel multimode receivers GPS antijamming receivers Communications receivers PRODUCT HIGHLIGHTS 1 Guaranteed sample rate of 80 MSPS 2 Input signal conditioning gain and impedance match 3 Single ended differential or off module filter option 4 Fully tested characterized full channel performance FUNCTIONAL BLOCK DIAGRAM AMP IN A 1 AMP IN A 2 H D8A 30 4 ENCODEA ENCODEA D9A 010 MSB Rev C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered tradema
20. J2 Power to the analog supply pins is connected via banana jacks The analog supply powers the associated components and the analog section of the AD13280 The digital outputs of the AD13280 are powered via banana jacks with 3 3 V Contact the factory if additional layout or applications assistance is required AD13280 LAYOUT INFORMATION The schematics of the evaluation board Figure 21 Figure 22 and Figure 23 represent a typical implementation of the AD13280 The pinout of the AD13280 is very straightforward and facilitates ease of use and the implementation of high frequency high resolution design practices It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device All capacitors can be standard high quality ceramic chip capacitors Care should be taken when placing the digital output runs Because the digital outputs have such a high slew rate the capacitive loading on the digital outputs should be minimized Circuit traces for the digital outputs should be kept short and should connect directly to the receiving gate Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate ANALOG DEVICES 11 08 09 DUAL ADC EVALUATION BOARD 6505561 C tema ene TIES Hee RAQUT
21. MSPS 9MHz AND 10MHz 7dBFS SFDR 82 77dBc 10 15 20 25 FREQUENCY MHz Figure 6 Two Tone 9 MHz and 10 MHz 30 35 40 02386 003 02386 004 02386 005 dB Rev C Page 10 of 28 ENCODE 80MSPS 10MHz 1dBFS SNR 69 19dBFS SFDR 79 55dBc ey 3 n Anm m rpm p 5 10 15 20 25 FREQUENCY MHz 30 Figure 7 Single Tone 10 MHz ENCODE 80MSPS 37MHz 1d SNR 68 38dBFS SFDR 57 81dBc BFS X ny PEKER TP PRI Y f 5 10 15 20 25 30 35 40 FREQUENCY MHz Figure 8 Single Tone 37 MHz ENCODE 80MSPS Ain 19MHz AND 20MHz 7dBFS SFDR lt 74 41dBc 5 10 15 20 25 30 35 40 FREQUENCY MHz Figure 9 Two Tone 19 MHz and 20 MHz 02386 006 02386 007 02386 008 013280 3 ODE 80MSPS ENCODE 80MSPS MAX 0 688 CODES INL MAX 0 562 CODES MIN 0 385 CODES 2 INL MIN 0 703 CODES 1 1 2 3 5 0 512 1024 1536 2048 2560 3072 3584 4096 5 0 512 1024 1536 2048 2560 3072 3584 4096 8 Figure 10 Differential Nonlinearity Figure 12 Integral Nonlinearity ENCODE 80MSPS ROLL OFF 0 0459dB dBFS C
22. YJ 240V Panasonic 4 BRESO805 R38 R39 R55 R56 33 0805 SM resistor ERJ 6GEYJ 333V Panasonic 28 CAP2 C1 C2 C5 to C10 0 1 uF 0805 SM capacitor GRM 40X7R104K025BL C12 C16 to C18 C20 to C26 C28 C31 to C38 2 CAP2 C13 C27 0 47 uF 0805 SM capacitor VJ1206U474MFXMB Vishay 2 H40DM J1 J2 2 x 20 40 pin male connector TSW 120 08 G D 6 IND2 L1toL6 470 SM inductor 2743019447 4 MC10EP16 U2 U3 U9 U11 Clock drivers MC10EP16D ON Semiconductor 2 MC100EPT23 U4 U10 ECL TTL clock drivers SY100EP23L ON Semiconductor 8 POLCAP2 C3 C11 C14 10 uF Tantalum polar capacitor T491C106MO016AT Kemet C15 C19 C29 C30 4 RES2 R47 to R50 00 0805 SM resistor ERJ 6GEY OR 00V Panasonic 6 RES2 R1 R2 R5 R7 R8 R54 500 0805 SM resistor ERJ 6GEYJ 510V Panasonic 32 RES2 R3 R4 R6 R9 R12 to 100 0 0805 SM resistor ERJ 6GEYJ 101V Panasonic R15 19 toR C P CO 46 R51 R 12 SMA oJ SMA tors 1 1 201 4 Standoff Standoff 313 2477 016 Johnson Components 4 Screws Screws standoff MPMS 004 0005 PH Building Fasteners 1 PCB AD13280 evaluation board GS03361 Rev C Page 24 of 28 AD13280 OUTLINE DIMENSIONS 0 035 0 889 2 00 50 80 0 040 1 02 45 TOE DOWN ANGLE 0 8 DEGREES 0 800 20 32 0 960 24 38 F 0 010 0 254 BSC TOP VIEW 0 950 24 13 SQ PINS DOWN 0 940 23 88 0 050 1 27 Jp 0 020 0 508 DETAIL A ROTATED 90 CCW 0 015 0 30 0 010 0
23. acitive loading there should be only one gate on each output pin An example of this is shown in the evaluation board schematic see Figure 20 The digital outputs of the AD13280 have a constant output slew rate of 1 V ns typical CMOS gate combined with a trace has a load of approximately 10 Therefore as each bit switches 10 mA 10 pF x 1 V 1 ns of dynamic current per bit flows in or out of the device A full scale transition can cause up to 120 mA 12 bits x 10 mA bit of transient current through the output stages These switching currents are confined between ground and the DVCC pin Standard TTL gates should be avoided because they can appreciably add to the dynamic switching currents of the AD13280 It should also be noted that extra capacitive loading increases output timing and invalidates timing specifications Digital output timing is guaranteed with 10 pF loads ww BDTI com ADI Rev C Page 16 of 28 EVALUATION BOARD The AD13280 evaluation board see Figure 20 is designed to provide optimal performance for evaluation of the AD13280 analog to digital converter The board encompasses everything needed to ensure the highest level of performance for evaluating the AD13280 The board requires an analog input signal encode clock and power supply inputs The clock is buffered on board to provide clocks for the latches The digital outputs and out clocks are available at the standard 40 pin connectors J1 and
24. el Min Typ Max Unit Analog Input 37 MHz 25 C 1 63 65 dBFS Min 61 5 dBFS Max 63 dBFS SINAD Analog Input 10 MHz 25 C 1 66 69 dBFS Min 63 5 dBFS Max 66 dBFS Analog Input 21 MHz 25 C 1 64 68 5 dBFS Min 63 dBFS Max 64 dBFS Analog Input 37 MHz 25 C 1 54 59 dBFS Min 53 dBFS Max 54 dBFS SPURIOUS FREE DYNAMIC RANGE Analog Input 10 MHz 25 C 1 75 80 dBFS Min 70 75 Analog Input 21 MHz 25 C 1 68 75 dBFS Min 67 67 Analog Input 37 MHz 25 C 56 62 dBFS Min 55 55 SINGLE EN Pass Ban 25 C O 0 dB Pass Band Ripple to 2 7 25 C 0 dB DIFFERENTIAL ANALOG INPUT Pass Band Ripple to 10 MHz 25 C V 0 3 dB Pass Band Ripple to 25 MHz 25 C V 0 82 dB TWO TONE IMD REJECTION fin 9 1 MHz and 10 1 MHz f and are 7 dBFS 25 C 75 80 dBc Min 71 74 19 1 MHz 20 7 MHz f and are 7 dBFS 25 C V 77 dBc fin 36 MHz and 37 MHz f and 7 dBFS 25 C V 60 dBc CHANNEL TO CHANNEL ISOLATION 25 C IV 90 dB TRANSIENT RESPONSE 25 C V 25 ns DIGITAL OUTPUTS Logic Compatibility CMOS DVc 3 3 V Logic 1 Voltage Full 2 5 0 2 Logic 0 Voltage Full 1 0 2 0 5 V DVcc 5V Logic 1 Voltage Full V DVcc 0 3 V Logic 0 Voltage Full V 0 35 V Output Coding Twos complement POWER SUPPLY AVcc Supply Voltage Full IV 4 85 5 0 5 25 V AVcc Current Full 313 364 mA AVe Supply Voltage Full IV 5 25 5 0 4 75
25. gital converter The internal reference voltage of the custom ADC is designed to track the offsets and drifts and is used to ensure matching over an extended temperature range of operation The reference voltage is connected to the output common mode input on the AD8138 This reference voltage sets the output common mode on the AD8138 at 2 4 V which is the midsupply level for the ADC The custom ADC has complementary analog input pins AIN and AIN Each analog input is centered at 2 4 V and should swing 0 55 V around this reference Because AIN and AIN are 180 degrees out of phase the differential analog input signal is 2 2 V peak to peak Both analog inputs are buffered prior to the first track and hold The custom ADC digital outputs drive 100 series resistors see Figure 16 The result is a 12 bit parallel digital CMOS compatible word coded as a twos complement USING THE SINGLE ENDED INPUT The AD13280 has been designed with user ease of operation in mind Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance The standard inputs are 0 5 V and 1 0 V The user can select the input impedance of the AD13280 on any input by using the other inputs as alternate locations for the GND The following is a summary of the impedance options available at each input location AMP IN x 1 100 O when AMP IN x 2 is open AMP IN x 1 50 O when AMP IN x 2 is shorted to
26. including harmonics but excluding dc SINAD can be ported in dB is degrad in dBFS al t is ES The ratio of the rms signal amplitude set at 1 dB below full scale to the rms value of the sum of all other spectral com ponents excluding the first five harmonics and dc SNR can be reported in dB that is degrades as signal level is lowered or in dBFS always related back to converter full scale Spurious Free Dynamic Range SFDR The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component The peak spurious component may or may not be a harmonic Transient Response The time required for the converter to achieve 0 0296 accuracy when a one half full scale step function is applied to the analog input Two Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product reported in dBc Rev C Page 12 of 28 013280 INPUT AND OUTPUT STAGES AVcc ENCODE O O ENCODE AMP IN X 2 1000 AMP IN X 1 TOAD8045 5 1000 8 3 Figure 13 Single Ended Input Stage Figure 15 ENCODE Inputs DVcc DVcc CURRENT MIRROR CURRENT MIRROR Figure 14 DR Digital Output Stage Figure 16 Digital Output Stage 02386 015 02386 016 Rev C Page 13 of 28 013280 THEORY OF OPERATION The AD13280 is a high dynamic range 12 bit 80 MHz pipeline delay three pipelines anal
27. ital Positive Supply Voltage Nominally 5 0 V 3 3 V Rev C Page 8 of 28 013280 Pin No Mnemonic Description 54 57 60 61 67 68 AGNDB B Channel Analog Ground A and B grounds should be connected as close to the device as possible 55 ENCODEB Encode Input Conversion initiated on rising edge 56 ENCODEB Complement of ENCODEB Differential input 58 AVCCB B Channel Analog Positive Supply Voltage Nominally 5 0 V 59 AVEEB B Channel Analog Negative Supply Voltage Nominally 5 0 V or 5 2 V 62 AMP IN B 2 Analog Input for B Side ADC Nominally 1 0 V 63 AMP IN B 1 Analog Input for B Side ADC Nominally 0 5 V 64 AMP OUT B Single Ended Amplifier Output Gain 2 65 B IN Noninverting Differential Input Gain 1 66 Inverting Differential Input Gain 1 ww BDTI com ADI Rev C Page 9 of 28 013280 TYPICAL PERFORMANCE CHARACTERISTICS 10 ENCODE 80MSPS Ain 5MHz 1dBFS 20 SNR 69 4dBFS 30 SFDR 81 9dBc 40 50 60 80 90 110 120 130 0 5 10 15 20 25 30 35 40 FREQUENCY MHz Figure 4 Single Tone amp 5 MHz 0 40 ENCODE 80MSPS 18MHz 1dBFS 20 SNR 69 79dBFS 30 SFDR 76 81dBc 40 50 60 80 90 100 110 120 130 0 5 10 15 20 25 30 35 40 FREQUENCY MHz Figure 5 Single Tone amp 18 MHz ENCODE 80
28. n Error 25 C 3 1 0 1 96 FS Full VI 5 0 2 0 5 0 96 FS Gain Error Channel Match 25 C 1 5 0 5 1 5 VI 3 0 1 0 3 0 Min Vi 5 1 0 5 96 SINGLE ENDED ANALOG INPUT Input Voltage Range AMP IN X 1 Full V 0 5 V AMP IN X 2 Full V 1 0 V Input Resistance AMP IN X 1 Full IV 99 100 AMP IN X 2 IV 198 200 Capacitance 25 V Analog nour AY A Ful V C DIFFERENTIAL Analog Signal Input Range A IN to A IN and B IN to B IN Full V 1 V Input Impedance 25 C V 618 Analog Input Bandwidth Full V 50 MHz ENCODE INPUT ENCODE Differential Input Voltage Full IV 0 4 V p p Differential Input Resistance 25 C V 10 kO Differential Input Capacitance 25 C V 2 5 pF SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 80 MSPS Minimum Conversion Rate Full IV 30 MSPS Aperture Delay t4 25 C V 0 9 ns Aperture Delay Matching 25 C IV 250 500 ps Aperture Uncertainty Jitter 25 C V 0 3 ps rms ENCODE Pulse Width High at Max Conversion Rate 25 C IV 4 75 6 25 8 ns ENCODE Pulse Width Low at Max Conversion Rate 25 C IV 4 75 6 25 8 ns Output Delay top Full V 5 ns Encode Rising to Data Ready Rising Delay Full V 8 5 ns SNR 6 Analog Input 10 MHz 25 C 1 66 5 70 dBFS Min 64 5 dBFS Max 66 3 dBFS Analog Input 21 MHz 25 C 1 66 5 70 dBFS Min 64 dBFS Max 66 3 dBFS Rev C Page 4 of 28 013280 AD13280AZ Parameter Temperature TestLev
29. og to digital converter ADC The custom analog input section provides input ranges of 1 V p p and 2 V p p and input impedance configurations of 50 100 and 200 The AD13280 employs four monolithic Analog Devices com ponents per channel AD8045 AD8138 AD8031 and a custom ADC IC along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 12 bit analog to digital converter ADC In the single ended input configuration the input signal is passed through a precision laser trimmed resistor divider allowing the user to externally select operation with a full scale signal of 0 5 V or 1 0 V by choosing the proper input terminal for the applica tion The result of the resistor divider is to apply a full scale input of approximately 0 4 V to the noninverting input of the internal AD8045 amplifier The AD13280 analog input includes an AD8045 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifier inputs and outputs The AD8045 amplifier provides a high input impedance and gain for driving the AD8138 in a single ended to differential amplifier configuration The AD8138 has a 3 dB bandwidth at 300 e differential signaljwitht nic d a differential amplifier A 8 differe balance the differential inputs to the custom ADC maximizing the performance of the device The AD8031 provides the buffer for the internal reference analog to di
30. rks are the property of their respective owners AMP IN B 2 1 64 AMP OUT B ENCODEB ENCODEB 02386 001 DOB D1B D2B D3B D4B D5B D6B LSB Figure 1 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2002 2008 Analog Devices Inc All rights reserved 013280 TABLE OF CONTENTS Features oe oe LU LE uer 1 Applications anoo testet IRURE REP 1 Product Highlights hr tte te 1 Functional Block Diagram 1 Revision History 2 General Description Acosta nate 3 Specifications ice e eee tee mend 4 TIMING Dia stam ade ea 6 Absolute Maximum 7 Explanation of Test 2 7 ESD 7 Pin Configuration and Function 8 Typical Performance Characteristics 10 Terminology detecte ete teet as 12 REVISION HISTORY 4 08 Rev B to Rev C Updated Outline Dimensions Changes to the 11 05 Rev A totRe Updated Format eiie Changes to Features and Product Highlights 1 Changes to General Description 3 Changes to Table iioii nee dites 4 Changes 8 Changes to Theory 14 Changes to Equation 1 22 15 Changes to Table

ANALOG DEVICES AD13280 handbook

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