ANALOG DEVICES AD12401 12-Bit 400 MSPS A/D Converter handbook
Contents
1. SO 20 ihe 9 2 m E22 pes EE URN m G ares 5 8 ka 3 8 Figure 33 Silkscreen Figure 36 Evaluation Adapter Board Analog and Digital Layers 5 x TEA 8 a pr Mat yee 0 a Ons Om reos or 569 95 sa Qaa om 9 wo 9 sx Om m E ov d we 8 c B 5 t vet 2 3 8 Figure 34 Bottom Silkscreen Figure 37 Evaluation Adapter Board Bottom Silkscreen Rev A Page 25 of 28 AD12401 LAYOUT GUIDELINES The AD12401 requires a different approach from traditional high speed ADC system layouts While the AD12401 s internal PCB isolates digital and analog grounds these planes are tied together through the products aluminum case structure Therefore the decision to isolate the analog and digital grounds on the system PCB has additional factors to consider For example if the AD12401 is attached with conductive thermal interface material to the system PCB there is essentially no benefit to keeping the analog and digital ground planes separate If neither thermal interface material nor nonconductive interface material is used system architects must consider the ground loop that is created if analog and digital planes are tied together directly under the AD12401 This EMI based decision must be considered on a case by case basis and is largely dependent on the other sources of EMI in the system One c2. 5 AC Specifications ENCODE 326 5 6 Absolute Maximum Ratings sentent 8 Explanation of Test Levels see 8 8 Pin Configuration and Function 10 RCTI T 13 Typical Performance Characteristics sss 15 Theory of Operati Ony teet tritt tie tetigere 18 REVISION HISTORY 4 06 Rev 0 to Rev A Changes to Features and Product Highlights 1 Changes to eT mter Changes to Table 2 Changes to Table 4 Changes to Table 7 Changes to Figure 5 Changes to Table 9 itte tei etit Added Gain Select Section sunci 20 Added GAIN Section 21 Charges t Figure 25 ite 23 Changes to the Ordering Guide sss 28 7 05 Revision 0 Initial Version Time Interleaving 18 Analog e ec ttti mee ent ms 18 Clock IDDUE oc tonto ovas tS 18 Digital OUtpUts 19 Power Supplies teet tite et A 19 Start Up and BEER S lI UNE 19 19 19 E 20 Thermal Considerations eene 20 Package Integrity Mounting Guidelines 20 AD12401 Evaluation Kit sees 21 Data Outputs 21 Layout Guidelines tete 26 PCB Int rfac
3. E220 1 5V SENSE 05649 023 012401 AD1240X PEA P2 A 1 Lh 2 lt 5 gt lS 4 lt g Uu DB8 g o 5 104655 9 2 21 z lt DGND QSE 60 01 L D A K DGND DB4 23 lt 1 w 104655 9 104655 9 V V DGND DGND V DGND QSE 60 01 CL D A K 1 Figure 25 Evaluation Board Rev A Page 23 of 28 AD12401 e A B oo 5 L Figure 26 Power Plane 1 Figure 29 Second Ground Plane i Figure 27 Power Plane 2 e e eve K R t 5 E H e e e U Si EM e Cv 2 S Z es nann ar ae s ERUIT Figure 28 First Ground Plane Figure 31 Bottom Side Copper Rev A Page 24 of 28 05649 028 05649 029 05649 030 012401 GS083550A SCH 6508552 GS 8353A 5 enone ANALOG DEVICES e 8 012400 EVAL ADAPTER BOARD 8 oe 3 gt MADE IN USA 2 Figure 32 Top Mask Figure 35 Evaluation Adapter Board Top Silkscreen AZ gt va k sy on We O YU Ga m Cos a L o g ve 2 uie es Agr De ao v
4. dc Analog Input Power 18 dBm ac ENCODE Input Voltage 6V dc ENCODE Input Power 12 dBm ac Logic Inputs 0 3 V to 4 V Storage Temperature Range Ambient 65 C to 150 C Operating Temperature Range 0 C to 60 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability EXPLANATION OF TEST LEVELS Table 6 Level Description 100 production tested 100 production tested at 25 C and sample tested at specified temperatures Sample tested only IV Parameter is guaranteed by design and characterization testing V Parameter is a typical value only VI 10096 production tested at 25 guaranteed by design and characterization testing for industrial temperature range 100 production tested at temperature extremes for military devices ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic disc
5. 10 20 30 40 50 60 70 100 180 200 ANALOG INPUT LEVEL dB INPUT Figure 14 Second Third Harmonics and Image Spur vs Analog Input Level Figure 17 VD Supply Current vs Frequency 400 MSPS 70 MHz Rev A Page 16 of 28 ANALOG INPUT LEVEL 5 20 05649 043 0 100 0 530 0 960 1 390 1 820 2 250 2 680 3 110 3 540 3 970 4 400 ANALOG INPUT FREQUENCY Figure 18 Low Frequency Gain Flatness Rev A Page 17 of 28 AD12401 AD12401 THEORY OF OPERATION The AD12401 uses two high speed 12 bit ADCs in a time interleaved configuration to double the sample rate while maintaining a high level of dynamic range performance The digital output of each ADC channel is calibrated using a proprietary digital postprocessing technique Advanced Filter Bank AFB AFB is implemented using a state of the art field programmable gate array FPGA and provides a wide bandwidth and wide temperature match for any gain phase and clock timing errors between each ADC channel TIME INTERLEAVING ADCS When two ADCs are time interleaved gain and or phase mismatches between each channel produce an image spur at fs 2 fam and an offset spur as shown in Figure 19 These mismatches can be the result of any combination of device tolerance temperature and frequency deviations IMAGE SPUR 40 x x OFFSET SPUR dB o 05649
6. 323 326 329 323 326 329 MSPS Encode Pulse Width High te 60 C V 1 53 1 53 ns Encode Pulse Width Low tz 60 C V 1 53 1 53 ns DIGITAL OUTPUT PARAMETERS Valid Time tv Full IV 5 0 5 0 ns Propagation Delay tro 60 V 8 7 8 7 ns Rise Time tr 20 to 80 60 C V 0 3 0 3 ns Fall Time tr 20 to 80 60 V 0 3 0 3 ns DR Propagation Delay teor 60 V 11 8 11 8 ns Data to DR Skew tpp 60 C V 3 1 3 1 ns Pipeline Latency Full IV 74 74 Cycles Start Up Time Full IV 29 44 87 29 44 87 ms Postprocessing Configuration Time Full IV 3 4 3 4 sec APERTURE DELAY ta 60 C V 2 3 2 3 ns APERTURE UNCERTAINTY Jitter tj 60 C V 0 4 0 4 ps rms All ac specifications tested with a single ended 2 0 V p p encode on ENCODE and ENCODE floating 2 The image spur is included in the SINAD measurement 3 The image spur is not included in the SFDR specification image spur is at fs 2 Aw the offset spur is at fs 2 5 F1 70 MHz F2 73 MHz Parts are tested with 326 MSPS encode Device can be clocked at lower encode rates but specifications are not guaranteed Specifications are guaranteed by design for encode 326 MSPS 1 7 Pipeline latency is exactly 74 cycles with an additional teo required for data to emerge Rev A Page 7 of 28 AD12401 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Value VA to AGND 5V VC to DGND 4V VD to DGND 1 6 V max Analog Input Voltage 6V
7. 60 72 dBFS 128 MHz Full 60 66 dBFS Offset Spur Analog Input 1 0 dBFS 60 V 65 dBFS Two Tone IMD F1 F2 6 dBFS 60 C V 75 dBc ANALOG INPUT Frequency Range Full 10 160 MHZ DIGITAL INPUT DR EN Minimum Time Low Full IV 5 6 ns Rev A Page 5 of 28 AD12401 AD12401 360KWS Parameter Case Temp Test Level Min Typ Max Unit SWITCHING SPECIFICATIONS Conversion Rate Full IV 356 360 364 MSPS Encode Pulse Width High 60 V 1 38 ns Encode Pulse Width Low teL 60 C V 1 38 ns DIGITAL OUTPUT PARAMETERS Valid Time tv Full IV 4 5 ns Propagation Delay 60 V 8 7 ns Rise Time ta 2096 to 80 60 C V 0 3 ns Fall Time tr 20 to 80 60 C V 0 3 ns DR Propagation Delay teor 60 V 11 5 ns Data to DR Skew tpp 60 C V 2 8 ns Pipeline Latency Full IV 74 Cycles Start Up Time Full IV 29 44 87 ms Postprocessing Configuration Time Full IV 3 1 sec APERTURE DELAY ta 60 C V 2 3 ns APERTURE UNCERTAINTY Jitter tj 60 V 0 4 ps rms All ac specifications tested with a single ended 2 0 V p p encode on ENCODE and ENCODE floating 2 The image spur is included in the SINAD specification 3 The image spur is not included in the SFDR specification image spur is at fs 2 Aw the offset spur is at 5 2 5F1270 MHz F2 73 MHz Parts are tested with 360 MSPS encode Device can be clocked at lower encode rates but specificati
8. PERFORMANCE CHARACTERISTICS 1 SNR 63 26dB SNR 60 74dB SFDR 76 77dBc SFDR 71 57dBc SINAD 62 97dB SINAD 60 29dB IMAGE SPUR 76 69dBc IMAGE SPUR 82 52dBc 05649 006 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz FREQUENCY MHz Figure 6 FFT fs 400 MSPS Aw 10 123 MHz 1 0 dBFS Figure 9 FFT fs 400 MSPS 175 123 MHz 1 0 dBFS X Image Spur N Interleaved Offset Spur X Image Spur N Interleaved Offset Spur 0 SNR 62 61dB SFDR 78 03dBc SINAD 62 4108 22 IMAGE SPUR 86 28dBc 30 40 50 8 60 70 80 90 i 8 aoc RAIMA m a JUIN GR Ae ln E 5 m W INN i kal c uu id Vi 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz FREQUENCY MHz Figure 7 FFT fs 400 MSPS Aw 70 123 MHz 1 0 dBFS Figure 10 Two Tone Intermodulation Distortion X Image Spur N Interleaved Offset Spur 25 1 MHz and 28 1 MHz fs 400 MSPS X Image Spur N Interleaved Offset Spur 0 SNR 61 54dB ET SFDR 74 03dBc SINAD 60 92dB 20 IMAGE SPUR lt 75 09dBc 30 40 50 5 60 70 80 90 m E e licia iid alicia ica 8 24 MA A A TN ili 5 i ao liu M dul LA LA LE 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60
9. ended sine wave at 10 dBm connected to the ENCODE SMA is recommended A low jitter clock source 0 5 ps is recommended to properly evaluate the AD12401 DATA OUTPUTS The AD12401xxxKWS digital outputs are available at the 80 pin connector P2 on the evaluation board The AD12401 KIT comes with a buffer memory FIFO board connected to P2 which provides the interface to the parallel port of a PC The Dual Analyzer software is compatible with Windows 95 Windows 98 Windows 2000 and Windows The buffer memory FIFO board can be removed and an external logic analyzer or other data acquisition module can be connected to this connector if required Adapter Card The AD12401 is attached to an adapter card that interfaces to the evaluation board through a 120 pin connector P1 which is on the top side of the evaluation board Digital Postprocessing Control The evaluation board has a 2 pin jumper labeled AFB that allows the user to enable disable the digital postprocessing The digital postprocessing is active when the AFB jumper is applied When the jumper is removed the FPGA is set to a passthrough mode which demonstrates to the user the performance of the AD12401 without the digital postprocessing RESET The 124015 FPGA configuration is stored in EEPROM and loaded into the FPGA when power is applied to the AD12401 The RESET switch SW1 active low allows the user to reload the FPGA in case of a low vo
10. 018 120 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz Figure 19 Image Spur due to Mismatches Between Two Interleaved ADCs No AFB Digital Postprocessing Figure 20 shows the performance of a similar converter with on board AFB postprocessing implemented The 44 dBFS image spur has been reduced to 77 dBFS and as a result the dynamic range of this time interleaved ADC is no longer limited by the channel matching dB o 5 IMAGE SPUR OFFSET SPUR 05649 019 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz Figure 20 AD12401 with AFB Digital Postprocessing The relationship between image spur and channel mismatches is captured in Table 10 for specific conditions Table 10 Image Spur vs Channel Mismatch Gain Error Aperture Delay Error ps Image Spur dBc 1 15 40 0 25 2 7 54 0 2 14 62 0 025 0 5 70 For a more detailed description of time interleaving in ADCs and design example using the AD12401 see Advanced Digital Post Processing Techniques Enhance Performance in Time Interleaved ADC Systems which was published in the August 2003 edition of the Analog Dialogue www analog com analogDialogue ANALOG INPUT The AD12401 analog input is ac coupled using a proprietary transformer front end circuit that provides 1 dB of gain flatness over the first Nyquist zone and a 3 dB bandw
11. 5 dBFS SINAD Analog Input 10 MHz Full 59 63 5 57 61 5 dBFS 1 0dBFS 70 MHz Full 58 5 63 56 5 61 dBFS 128 MHz Full 57 5 61 5 55 5 59 5 dBFS 175 MHz Full 55 60 53 58 dBFS Spurious Free Dynamic Range Analog Input 10 MHz Full 69 85 69 85 dBFS 1 0dBFS 70 MHz Full 69 80 69 80 dBFS 128 MHz Full 66 72 66 72 dBFS 175 MHz Full 62 68 62 68 dBFS Image Spur Analog Input 10 MHz Full 60 75 60 75 dBFS 1 0dBFS 70 MHz Full 60 72 60 72 dBFS 128 MHz Full 60 66 60 66 dBFS 175 MHz Full 57 63 57 63 dBFS Offset Spurt Analog Input 1 0 dBFS 60 V 65 65 dBFS Two Tone IMD F1 F2 6 dBFS 60 V 75 75 dBc ANALOG INPUT Frequency Range Full IV 10 175 10 175 MHz DIGITAL INPUT DR_EN Minimum Time Low Full IV 5 0 5 0 ns SWITCHING SPECIFICATIONS Conversion Rate Full IV 396 400 404 396 400 404 MSPS Encode Pulse Width High te 60 V 1 25 1 25 ns Encode Pulse Width Low te 60 C V 1 25 1 25 ns Rev A Page 4 of 28 AD12401 AD12401 400KWS AD12401 400JWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit DIGITAL OUTPUT PARAMETERS Valid Time tv Full IV 3 9 3 9 ns Propagation Delay ter 60 C V 87 8 7 ns Rise Time tr 20 to 80 60 C V 0 3 0 3 ns Fall Time tr 20 to 80 60 C V 0 3 0 3 ns DR Propagation Delay teor 60 V 11 2 11 2 ns Data to DR Skew tpp 60 C V 2 5 2 5 ns Pipeline Latency Full IV 74 74 Cycles Start Up T
12. 80 100 120 140 160 180 200 FREQUENCY MHz FREQUENCY MHz Figure 8 FFT fs 400 MSPS Aw 128 123 MHz 1 0 dBFS Figure 11 Two Tone Intermodulation Distortion X Image Spur Interleaved Offset Spur 70 1 MHz and 73 1 MHz fs 400 MSPS X Image Spur N Interleaved Offset Spur Rev A Page 15 of 28 AD12401 HARMONICS dBc ARMONIC ru M M ML Adi UN Ail 0 180 200 20 40 60 80 100 120 140 160 180 uin 05649 042 05649 012 ANALOG INPUT FREQUENCY MHz Figure 12 Two Tone Intermodulation Distortion 172 1 MHz and 175 1 MHz f 400 MSPS SFDR 70 dBc X Image Spur N Interleaved Offset Spur 0 5 64 5 0 4 64 0 0 3 63 5 0 2 63 0 0 1 j 0 1 0 2 0 3 60 5 0 4 60 0 0 5 59 5 0 50 100 150 20 7107 35 0 59 3 83 6 108 132 157 181 205 229 Figure 15 Harmonics vs Analog Input Frequency o N a GAIN dB SNR dBFS N o a o 05649 016 05649 040 FREQUENCY MHz ANALOG INPUT FREQUENCY MHz Figure 13 Interleaved Gain Flatness Figure 16 SNR vs Analog Input Frequency 100 1 0 THIRD HARMONIC 95 0 9 90 5 0 8 2 m 85 u 2 0 7 2 5 80 SECOND gt 2 a 0 6 575 E a 7 0 5 70 e 65 E 8 i 3 60 5 036 0
13. B2 Channel B Data Bit 2 Complement output bit 35 DB3 Channel B Data Bit 3 True output bit 36 DB2 Channel B Data Bit 2 True output bit 37 DBT Channel B Data Bit 1 Complement output bit 38 DBO Channel B Data Bit 0 Complement output bit DBO is LSB 39 DB1 Channel B Data Bit 1 True output bit 40 DBO Channel B Data Bit 0 True output bit DBO is LSB 41 to 48 VD Digital Supply 1 5 V 53 DATT Channel Data Bit 11 Complement output bit 54 DA10 Channel A Data Bit 10 Complement output bit 55 DA11 Channel A Data Bit 11 True output bit 56 DA10 Channel A Data Bit 10 True output bit 57 DA9 Channel A Data Bit 9 Complement output bit 58 DAS Channel Data Bit 8 Complement output bit 59 DA9 Channel A Data Bit 9 True output bit 60 DA8 Channel A Data Bit 8 True output bit 61 DA7 Channel A Data Bit 7 Complement output bit 62 DA6 Channel A Data Bit 6 Complement output bit 63 DA7 Channel A Data Bit 7 True output bit 64 DA6 Channel A Data Bit 6 True output bit 65 DA5 Channel A Data Bit 5 Complement output bit 66 DA4 Channel A Data Bit 4 Complement output bit 67 DAS Channel Data Bit 5 True output bit 68 DA4 Channel A Data Bit 4 True output bit Rev A Page 11 of 28 AD12401 Pin No Mnemonic Description 69 DA3 Channel A Data Bit 3 Complement output bit 70 DA2 Channel A Data Bit 2 Complement output bit 71 Channel A Data Bit 3 True output bit 72 DA2 Channel A Data B
14. DC Harmonic Distortion Second The ratio of the rms signal amplitude to the rms value of the second harmonic component reported in dBFS Harmonic Distortion Third The ratio of the rms signal amplitude to the rms value of the third harmonic component reported in dBFS Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit Maximum Conversion Rate The maximum ENCODE rate at which the image spur calibration degrades no more than 1 dB when the image spur is 70 dB Minimum Conversion Rate The minimum ENCODE rate at which the image spur calibration degrades no more than 1 dB when the image spur is 70 dB Offset Error The dc offset imposed on the input signal by the ADC reported in LSB codes Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE or zero crossing of a single ended ENCODE Pipeline Latency The number of clock cycles the output data lags the correspond ing clock cycle Power Supply Rejection Ratio PSRR The ratio of power supply voltage change to the resulting ADC output voltage change Rev A Page 13 of 28 AD12401 Signal to Noise and Distortion SINAD The ratio of the rms signal amplitude set 1 dB below full scale to the rms value of the sum of all other spectral components including harmonics but excluding dc and image spur Si
15. ONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES THE DR EN PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12401 IF APPLIED ASYNCHRONOUSLY DR EN MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE DR EN PIN IS SET HIGH AGAIN DRA AND DRB RESUME ON THE NEXT VALID DRA AFTER DR EN IS RETURNED HIGH IF THIS FEATURE IS NOT REQUIRED TIE THIS PIN TO 3 3V THROUGH A 3 74kQ RESISTOR OR LEAVE IT FLOATING Figure 3 Timing Diagram teor 7 05649 003 Figure 4 Highlighted Timing Diagram Rev A Page 9 of 28 05649 004 AD12401 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 119 VA PIN 120 VA VA VA AGND AGND DNC DNC HIL GAIN DNC DNC DNC AGND AGND AGND JOHNSON SMA 50 O CONNECT NO 142 0711 821 PIN79 DNC PIN 80 DR_EN DAI DAI DA3 DA3 T 2 56 STUDS 4 DAS DAS END VIEW DA7 B BOARD DA9 DA11 11 DNC DNC VD CONNECTOR QTE 060 01 L D A K TR PIN 39 DB1 PIN 40 DBI DB3 DB3 DBS DB5 DB7 DB7 DB9 DB9 A BOTTOM VIEW LEFT SIDE VIEW DB11 DB11 DNC NOTE DNC 1 FOR MATING CONNECTOR USE INC DNC PART NO QSE 60 01 L D A K DNC INTEGRAL GROUND PLANE CONNECTIONS DNC SECTION A DGND PINS 121 124 RESET SECTION B DGND PINS 125 128 ve SECTION C AGND
16. PINS 129 132 PIN 1 vc 2 Figure 5 Pin Configuration Rev A Page 10 of 28 05649 005 Table 9 Pin Function Descriptions AD12401 Pin No Mnemonic Description 1to4 VC Digital Supply 3 3 V 5 RESET LVTTL 0 device reset Minimum width 200 ns Device resumes operation after 600 ms maximum 6 to 9 11 13 15 DNC Do Not Connect 49 to 52 79 96 to 102 104 to108 10 DRB Channel B Data Ready Complement output 12 DRB Channel B Data Ready True output 14 OROUT Overrange Complement output 16 OROUT Overrange True Output 1 overranged 0 normal operation 17 0811 Channel Data Bit 11 Complement output bit 18 DB10 Channel B Data Bit 10 Complement output bit 19 DB11 Channel B Data Bit 11 True output bit 20 DB10 Channel B Data Bit 10 True output bit 21 DB9 Channel B Data Bit 9 Complement output bit 22 DB8 Channel B Data Bit 8 Complement output bit 23 DB9 Channel B Data Bit 9 True output bit 24 DB8 Channel B Data Bit 8 True output bit 25 DB7 Channel B Data Bit 7 Complement output bit 26 DB6 Channel B Data Bit 6 Complement output bit 27 DB7 Channel B Data Bit 7 True output bit 28 DB6 Channel B Data Bit 6 True output bit 29 DB5 Channel B Data Bit 5 Complement output bit 30 DB4 Channel B Data Bit 4 Complement output bit 31 DB5 Channel B Data Bit 5 True output bit 32 DB4 Channel B Data Bit 4 True output bit 33 DB3 Channel B Data Bit 3 Complement output bit 34 D
17. ZIRIAD 12401 KIT f v fS ANALOG DEVICES 12 Bit 400 MSPS A D Converter AD12401 FEATURES FUNCTIONAL BLOCK DIAGRAM Up to 400 MSPS sample rate SFDR of 70 dBFS 128 MHz VSWR of 1 1 5 High or low gain grades Wideband ac coupled input signal conditioning Enhanced spurious free dynamic range Single ended or differential ENCODE signal LVDS output levels Twos complement output data APPLICATIONS Communications test equipment Radar and satellite subsystems Phased array antennas digital beams CLK DISTRIBUTION PROCESSING DBO DB11 Ain ADC B CLOCK DISTRIBUTION DIVIDE BY 2 ENC ENC OROUT Multichannel multimode receivers n 22 Figure 1 Secure communications Wireless and wired broadband communications Wideband carrier frequency systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD12401 is a 12 bit analog to digital converter ADC with a transformer coupled analog input and digital post processing for enhanced SFDR The product operates at up to l Guaranteed sample rate up to 400 MSPS 2 Input signal conditioning with optimized dynamic performance to 175 MHz 005649 001 400 MSPS conversion rate with outstanding dynamic performance in wide aid 3 High and low gain grades available 4 Additional performance options available sample rates gt 400 MSPS or second Nyquist zone operation contact sales The AD12401 requires a 3 7 V analog supply and 3 3 V and 1 5 V d
18. atching perspective the most important consideration is external thermal influences It is possible for thermal imbalances in the end application to adversely affect the dynamic performance Due to the temperature dependence of the image spur substantial deviation from the factory cali bration conditions can have a detrimental effect Unbalanced thermal influences can cause gradients across the module and performance degradation can result Examples of unbalanced thermal influences can include large heat dissipating elements near one side of the AD12401 or obstructed airflow that does not flow uniformly across the module The thermal sensitivity of the module can be affected by a change in thermal gradient across the module of 2 C TYPICAL JUNCTION CASE l AMBIENT NO AIRFLOW 100 LFM 300 LFM AIRFLOW CONDITION TEMPERATURE C 05649 021 Figure 22 Typical Temperature vs Airflow with No Module Board Interface Material Normalized to 60 C Module Case Temperature 110 100 TYPICAL JUNCTION 90 80 70 60 CASE 50 40 AMBIENT 30 20 NO AIRFLOW 100 LFM 300 LFM AIRFLOW CONDITION TEMPERATURE C 05649 022 Figure 23 Typical Temperature vs Airflow with T flex Module Board Interface Material Normalized to 60 C Module Case Temperature Ambient PACKAGE INTEGRITY MOUNTING GUIDELINES The AD12401 is a printed circuit board PCB based module designed to provide m
19. board the power supply cables a 225 MHz buffer memory FIFO board and the Dual Analyzer software The user must supply a clock source an analog input source a 1 5 V power supply a 3 3 V power supply a5 V power supply and a 3 8 V power supply The clock source and analog input source connect directly to the AD12401 The power supply cables included and a parallel port cable not included connect to the evaluation board The AD12401 works on the same evaluation board as the AD12400 and the AD12500 GS08054 Power Connector Power is supplied to the board via a detachable 12 lead power strip three 4 pin blocks Table 11 Power Connector Supply Description VA 3 7 Analog supply for the ADC 950 mA typ VC3 3V Digital supply for the ADC outputs 400 mA typ VD1 5V Digital supply for the FPGA 1 25 A max 0 7 A typ VB5 0V Digital supply for the buffer memory board 400 mA typ 1 The power supply cable has an approximately 100 mV drop The VD supply current is dependent on the analog input frequency see Figure 17 Analog Input The analog input source connects directly to an SMA on the AD12401 H L GAIN The H L GAIN select jumper Pin 103 should be on for low gain mode AD12401 xxxKWS The H L GAIN select jumper should be removed for high gain mode AD12401 xxxJWS AD12401 ENCODE The single ended or differential ENCODE signal connects directly to SMA connector s on the AD12401 A single
20. described in the Package Integrity Mounting Guidelines section the module should be secured to the motherboard using 2 56 nuts washer use is optional The torque on the nuts should not exceed 32 inch ounces Using a thermal grease at the standoffs results in better thermal coupling between the board and module Depending on the ambient conditions airflow can be necessary to ensure the components in the module do not exceed their maximum operating temperature For reliability the most sensitive component has a maximum junction temperature rating of 125 C Figure 22 and Figure 23 provide a basic guideline for two key thermal management decisions the use of thermal interface material between the module bottom cover mother board and airflow Figure 21 characterizes the typical thermal profile of an AD12401 that is not using thermal interface material Figure 22 provides the same information for a configuration that uses gap filling thermal interface material In this case Thermagon T flex 600 Series 0 040 thickness was used These profiles show that the maximum die temperature is reduced by approximately 2 C when thermal interface material is used Figure 22 and Figure 23 also provide a guideline for determining the airflow requirements for given ambient conditions For example a goal of 120 C die temperature in a 40 C ambient environment without the use of thermal interface material requires an airflow of 100 LFM From a channel m
21. ding it resulted from an overrange input If the OROUT pin is low the operation is normal Rev A Page 19 of 28 AD12401 GAIN SELECT The AD12401 is graded out for the gain mode and should be ordered accordingly the AD12401 xxxKWS is calibrated in the low gain mode and the AD12401 xxxJWS is calibrated in the high gain mode Performance is not guaranteed if either grade is used in the wrong gain mode The high gain mode sets the analog input voltage to approximately 1 6 V p p The low gain mode sets the analog input voltage to approximately 3 2 V p p For high gain mode the user should pull Pin 103 H L_GAIN up to 3 3 V using a 4 02 resistor For low gain mode the user should ground Pin 103 THERMAL CONSIDERATIONS The module is rated to operate over a case temperature of 0 C to 60 C To maintain the tight channel matching and reliability of the AD12401 care must be taken to ensure that proper thermal and mechanical considerations have been made and addressed to ensure case temperature is kept within this range Each application requires evaluation of the thermal manage ment as applicable to the system design This section provides information that should be used in the evaluation of the AD12401 s thermal management for each specific use In addition to the radiation of heat into its environment the AD12401 module enables the flow of heat through the mounting studs and standoffs as they contact the motherboard As
22. e neue ien uH ee PU 26 O tline Dimensions iioii ttti 28 Ordering Guide esee emitte eene iis 28 Rev A Page 2 of 28 012401 SPECIFICATIONS DC SPECIFICATIONS VA 3 7 V VC 3 3 V VD 1 5 V 0 C Tcasz lt 60 C unless otherwise noted Table 1 AD12401 xxxKWS AD12401 xxxJWS Parameter CaseTemp TestLevel Min Typ Max Min Typ Unit RESOLUTION 12 Bits ACCURACY No Missing Codes Full IV Guaranteed Offset Error Full 12 12 12 12 LSB Gain Error 10 MHz Full 10 10 10 10 FS Differential Nonlinearity DNL 60 C V 0 3 0 3 LSB Integral Nonlinearity INL 60 C 0 5 0 5 LSB TEMPERATURE DRIFT Gain Error 60 C V 0 02 0 02 ANALOG INPUT AIN Full Scale Input Voltage Range 60 C V 3 2 1 6 V p p Flatness 10 MHz to 175 Full IV 0 5 1 0 5 1 dB Input VSWR 50 300 kHz to 175 MHz 60 V 1 5 1 5 Analog Input Bandwidth 60 V 480 480 MHz POWER SUPPLY Supply Voltage VA Full IV 3 6 3 8 3 6 3 8 V VC Full IV 3 2 34 3 2 34 V VD Full IV 1 45 1 55 1 45 1 55 V Supply Current Iva VA 3 7 V Full 0 95 1 2 095 12 Ivc VC 3 3 V Full 400 500 400 500 mA VD 1 5 V Full 0 8 1 2 0 8 1 2 Total Power Dissipation Full 5 7 6 8 5 7 6 8 W ENCODE INPUTS Differential Inputs ENC ENC Input Voltage Full IV 0 4 0 4 V Input Resistance 60 C V 100 100 Q Input Capacitance 60 C V 35 35 pF Common Mode Voltage 60 V t3 3 V Single Ended Inputs ENC Input Volta
23. echanical stability and to support the intricate channel to channel matching necessary to achieve high dynamic range performance The module should be secured to the motherboard using 2 56 nuts washer use is optional The torque on the nuts should not exceed 32 inch ounces Rev A Page 20 of 28 The SMA edge connectors AIN and ENC ENC are surface mounted to the board to achieve minimum height of the module When attaching and routing the cables one must ensure they are stress relieved and do not apply stress to the SMA connector board The presence of stress on the cables can degrade electrical performance and mechanical integrity of the module In addition to the routing precautions the smallest torque necessary to achieve consistent performance should be used to secure the system cable to the AD12401 s SMA connectors The torque should never exceed 5 inch pounds Any disturbances to the AD12401 structure including removing the covers or mounting screws invalidates the calibration and results in degraded performance See the Outline Dimensions section for mounting stud dimensions see Figure 38 for PCB interface locations Mounting stud length typically accommodates a PCB thickness of 0 093 Consult sales if board thickness requirements exceed this dimension AD12401 EVALUATION KIT The AD12401 KIT offers an easy way to evaluate the AD12401 The AD12401 KIT includes the AD12401 mounted on an adapter card the AD12401 evaluation
24. erenced to the center of the QTE terminal strip on the AD12401 and the mounting holds for the screws which holds the AD12401 to the second level assembly board The relationship of these locating tabs is based on information provided by Samtec connector supplier and should be verified with Samtec by the customer Mating and unmating forces the knifing or peeling action of applying force to one end or one side must be avoided to prevent damage to the connector and guidepost Rev A Page 26 of 28 3 1 184 30 0673 R 0470 R1 19 6x X i N D 2 o a 000 0000 41 1 025 26 0164 2 L9 1 184 30 0673 0 396 10 0456 2x 0 000 0000 0 105 2 6670 2x Figure 38 Top View of Interface PCB Assembly Rev A Page 27 of 28 J 1 025 26 0164 2x 0 0 DATUM CENTER OF CONNECTOR 05649 038 AD12401 AD12401 OUTLINE DIMENSIONS 3 190 lt 2 890 A TOP VIEW 2 590 MAX 2 328 TYP JOHNSON SMA 50 OHM CONNECT NO 142 0711 821 0 700 0 175 0 600 0 200 E SAMTEC CONNECTOR QTE 060 01 L D A K TR T 2 56 STUDS 4 A 2 060 BOTTOM VIEW 2 040 Y 1773 0 505 TYP 2 lt e gt E 3 Figure 39 Non Hermetic Hybrid Surface M
25. ge Full IV 0 4 2 0 4 2 V p p Input Resistance 60 C V 50 50 Q LOGIC INPUTS RESET Logic 1 Voltage Full 2 0 2 0 V Logic 0 Voltage Full IV 0 8 0 8 V Source 60 C IV 3 4 6 34 6 Sink li 60 C IV 0 9 1 0 9 1 mA LOGIC INPUTS DR EN Logic 1 Voltage Full IV 1 7 1 7 V Logic 0 Voltage Full IV 0 7 0 7 V Source liu 60 C IV 20 50 20 50 UA Sink li 60 C IV 30 160 30 160 UA Rev Page 3 of 28 AD12401 AD12401 xxxKWS AD12401 xxxJWS Parameter CaseTemp TestLevel Min Typ Max Min Typ Max Unit LOGIC OUTPUTS DRA DRB OUTPUT BITS Differential Output Voltage Full IV 247 350 454 247 350 454 mV Output Common Mode Voltage Full IV 1 125 1 25 1 375 1 125 125 1 375 V Output High Voltage 60 C IV 1 602 1 602 V Output Low Voltage 60 IV 0 898 0 898 V Tested using input frequency of 70 MHz see Figure 17 Refer to Table 8 for logic convention on all logic inputs 3 Digital output logic levels VC 3 3 V Cioap 8 pF 2 5 V LVDS Rr 100 AC SPECIFICATIONS ENCODE 400 MSPS 3 7 V VC 3 3 V VD 1 5 ENCODE 400 MSPS 0 C lt Tcase lt 60 C unless otherwise noted Table 2 AD12401 400KWS AD12401 400JWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE SNR Analog Input 10 MHz Full 62 64 60 62 dBFS 1 0dBFS 70 MHz Full 61 5 63 5 59 5 61 5 dBFS 128 MHz Full 60 63 58 61 dBFS 175 MHz Full 60 62 5 57 5 60
26. gnal to Noise Ratio SNR The ratio of the rms signal amplitude set at 1 dB below full scale to the rms value of the sum of all other spectral compo nents excluding the first five harmonics and Spurious Free Dynamic Range SFDR The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component except the image spur The peak spurious component may or may not be a harmonic It can be reported in dBc that is degrades as signal level is lowered or dBFS always related back to converter full scale Total Noise Calculated as Stm SNRape Signal apes gt x0 001x10 10 where Zis the input impedance FS is the full scale of the device for the frequency in question SNR is the value of the particular input level Signal is the signal level within the ADC reported in dB below full scale This value includes both thermal and quantization noise Two Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product reported in dBc Two Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component The peak spurious component may or may not be an IMD product It can be reported in dBc that is degrades as signal level is lowered or in dBFS always related back to converter full scale Rev A Page 14 of 28 012401 TYPICAL
27. harges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev A Page 8 of 28 LS ESD SENSITIVE DEVICE Table 7 Output Coding Twos Complement AD12401 Table 8 Option Pin List with Necessary Associated Circuitry An V Logic Code KWS JWS Digital Output Pin Active Level Default Associated Circuitry 4095 16 08 011111111111 Name Hah Level Within Part RESET LOW LVTTL High 3 74 Pull Up DR EN High LVTTL High Weak Pull Up gt 16 2048 0 0 0000 0000 0000 2047 0 000781 to 0 0003905 1111 1111 1111 ENCODE PECL 0 1 6 to 0 8 1000 0000 0000 Pa ENCODE Figure 2 ENCODE Equivalent Circuit N 1 1 N 2 N 3 teL tg lfg ENC Lie m RC a ATM RTM 5 8 C my 187 aa Pa IU IU 400MHZ J A f LA ALL AL D A A K J 4 74 CLOCK CYCLES 1 DRA it DRA vans Sant ae 1 DRB Eae EE 477 EEE Pa DRB ar me PUES Veni monat ES feu NA it DR EN NOTES 1 DATA LOST DUE TO ASSERTION OF DR EN LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID 2 IF A SINGLE ENDED SINE WAVE IS USED FOR ENCODE USE THE ZERO CROSSING POINT AC COUPLED AS THE 5096 POINT AND APPLY THE SAME TIMING INFORMATION 3 THE DR EN PIN IS USED TO SYNCHR
28. idth of 480 MHz This front end circuit provides a VSWR of 1 5 50 over the first Nyquist zone and the typical full scale input is 3 2 V p p The Mini Circuits HELA 10 amplifier module can be used to drive the input at these power levels CLOCK INPUT The AD12401 requires a 400 MSPS ENCODE that is divided by 2 and distributed to each ADC channel 180 out of phase from each other Internal ac coupling and bias networks provide the framework for flexible clock input requirements that include single ended sine wave single ended PECL and differential PECL While the AD12401 is tested and calibrated using a single ended sine wave properly designed PECL circuits that provide fast slew rates gt 1 V ns and minimize ringing result in comparable dynamic range performance Aperture jitter and harmonic content are two major factors to consider when designing the input clock circuit for the AD12401 The relationship between aperture jitter and SNR can be characterized using the following equation The equation assumes a full scale single tone input signal SNR 2 1 1 2 LAIR RW 201 20 f x Ot pens H lt 15 42 2 where fa input frequency tms aperture jitter N ADC resolution bits ADCDNL LSB Vyorstrms ADC input noise LSB rms Rev A Page 18 of 28 Figure 21 displays the application of this relationship to a full scale single tone input signal on the AD12401 whe
29. igital supplies and provides a flexible ENCODE signal that can be differential or single ended No external reference is 5 Proprietary Advanced Filter Bank AFB digital post processing from V Corp Technologies Inc The AD12401 package style is an enclosed 2 9 x 2 6 x 0 6 module Performance is rated over a 0 to 60 C case temperature range Rev Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property their respective owners One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved AD12401 TABLE OF CONTENTS F atu tes E E 1 AP PlICALLONS 1 Functional Block Diagram sse 1 General Description e E 1 Product Highlights 1 Revision HIStory 2 Specifications R RD 3 DC Spe ifications aiins 3 AC Specifications ENCODE 400 5 4 AC Specifications ENCODE 360 5
30. ime Full IV 29 44 87 29 44 87 ms Postprocessing Configuration Time Full IV 2 8 2 8 sec APERTURE DELAY ta 60 C V 2 3 2 3 ns APERTURE UNCERTAINTY Jitter ty 60 C V 0 4 0 4 ps rms All ac specifications tested with a single ended 2 0 V p p encode on ENCODE and ENCODE floating 2 The image spur is included in the SINAD measurement 3 The image spur is not included in the SFDR specification image spur is at fs 2 Aw the offset spur is at fs 2 1 70 MHz F2 73 MHz Parts are tested with 400 MSPS encode Device can be clocked at lower encode rates but specifications are not guaranteed Specifications are guaranteed by design for encode 400 MSPS 1 7 Pipeline latency is exactly 74 cycles with an additional required for data to emerge AC SPECIFICATIONS ENCODE 360 MSPS VA 3 7 V VC 3 3 V VD 1 5 V encode 360 MSPS 0 C lt Tcase lt 60 C unless otherwise noted Table 3 AD12401 360KWS Parameter Case Temp Test Level Min Typ Max Unit DYNAMIC PERFORMANCE SNR Analog Input 10 MHz Full 62 64 dBFS 1 0dBFS 70 MHz Full 61 5 63 5 dBFS 128 MHz Full 60 63 dBFS SINAD Analog Input 10 MHz Full 59 63 5 dBFS 1 0dBFS 70 MHz Full 58 5 63 dBFS 128 MHz Full 57 5 61 5 dBFS Spurious Free Dynamic Range Analog Input 10 MHz Full 69 85 dBFS 1 0dBFS 70 MHz Full 69 80 dBFS 128 MHz Full 66 72 dBFS Image Spur Analog Input 10 MHz Full 60 75 dBFS 1 0dBFS 70 MHz Full
31. it 2 True output bit 73 DAT Channel A Data Bit 1 Complement output bit 74 DAO Channel A Data Bit 0 Complement output bit DAO is LSB 75 DA Channel Data 1 True output bit 76 DAO Channel A Data Bit 0 True output bit DAO is LSB 77 DR_EN Data Ready Enable Typically DNC See the DR_EN section 78 DRA Channel A Data Ready Complement output 80 DRA Channel A Data Ready True output 103 H L GAIN Gain Select Pin Ground for low gain mode KWS pull up to 3 3 V for high gain mode JWS 81 to 95 109 to 112 AGND Analog Ground 12910132 11310120 Analog Supply 3 7 V 121 to 1281 DGND Digital Ground 1 Internal ground plane connections Section A Pin 121 to Pin 124 Section B Pin 125 to Pin 128 Section C AGND Pin 129 to Pin 132 Rev A Page 12 of 28 012401 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency as determined by the FFT analysis is reduced by 3 dB Aperture Delay The delay between the 50 point on the rising edge of the ENCODE command and the instant at which the analog input is sampled Analog Input VSWR 50 VSWR is a ratio of the transmitted and reflected signals The VSWR can be related to input impedance T 21 Zs Zi T Zs where Z actual load impedance Zs reference impedance VSWR 1 1 Aperture Uncertainty Jitter The sample to sample variation i
32. ltage condition or a power supply glitch Depressing the RESET switch pulls the data ready and output bits high The RESET switch should remain low for minimum of 200 ns On the rising edge of the RESET pulse the AD12401 starts loading the configuration into the on module FPGA The reload process requires a maximum of 600 ms to complete Valid signals on the data ready pins indicate the reset process is complete The AD12401 is not compatible with the HSC ADC EVAL DC SC hardware or software Rev A Page 21 of 28 AD12401 Table 12 Evaluation Board Bill of Materials BOM Item No Qty Ref Des Device Package Value Mfg 1 2 C3 C5 Capacitors 603 0 1 uF 25V 2 2 Capacitors 805 10 uF 6 3 V 3 1 R9 Resistor 603 4 02 196 4 1 AFB 2 Pin Header Jumper Pin Strip Molex GC Weldon 5 1 P2 80 Pin Dual Connector Assembly Surface Mount Post Header AMP 6 1 SW1 Switch Push Button SPST 6MM Panasonic 7 3 J2 J3 J4 4 Pin Header Power Connecters Pin Strip Wieland 8 1 P1 60 Pin Dual Socket Assembly Surface Mount Samtec 9 1 PCB AD12401 Interface Board GS08054 PCB 02k 4 02kQ EE SPARE1 9 SPARE2 a 4 02kQ HIL GAIN lav 4 02kQ Crt NYQ NYQ t 4 02kQ JP2 E12 0 o JP3 E13 0 0 DGND SELECTD DIGITAL ANALOG l 10uF l O 1uF DGND DGND c5 i fn DGND DGND Figure 24 Evaluation Board Rev A Page 22 of 28 J E17 0 0 EVQ PAC85R v7 DGND
33. n aperture delay Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step Distortion Image Spur The ratio of the rms signal amplitude to the rms signal ampli tude of the image spur reported in dBFS The image spur a result of gain and phase errors between two time interleaved conversion channels is located at fs 2 fam Distortion Offset Spur The ratio of the rms signal amplitude to the rms signal ampli tude of the offset spur reported in dBFS The offset spur a result of offset errors between two time interleaved conversion channels is located at fs 2 Effective Number of Bits ENOB Calculated from the measured SNR based on the equation SNR 1 76 dB 6 02 ENCODE Pulse Width Duty Cycle Pulse width high is the minimum amount of time the ENCODE pulse should be left in Logic 1 state to achieve rated perform ance pulse width low is the minimum time the ENCODE pulse should be left in low state Full Scale Input Power Expressed in dBm Computed using the equation POWER cutt scate 10 log V Full Scale Zuur x 0 001 Full Scale Input Voltage Range The maximum peak to peak input signal magnitude that results in a full scale response 0 dBFS on a single tone input signal case Any magnitude increase from this value results in an overrange condition Gain Error The difference between the measured and ideal full scale input voltage range of the A
34. ons are not guaranteed Specifications are guaranteed by design for encode 360 MSPS 1 7 Pipeline latency is exactly 74 cycles with an additional tep required for data to emerge AC SPECIFICATIONS ENCODE 326 MSPS VA 3 7 V VC 3 3 V VD 1 5 ENCODE 326 MSPS 0 C lt Tcase lt 60 C unless otherwise noted Table 4 AD12401 326KWS AD12401 326JWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE SNR Analog Input 10 MHz Full 62 64 60 62 dBFS 1 0dBFS 70 MHZ Full 61 5 63 5 59 5 61 5 dBFS 128 MHz Full 60 63 58 61 dBFS SINAD Analog Input 10 MHz Full 59 63 5 57 61 5 dBFS 1 0dBFS 70 MHz Full 58 5 63 565 61 dBFS 128 MHz Full 57 5 61 5 55 5 59 5 dBFS Spurious Free Dynamic Range Analog Input 10 MHz Full 69 85 69 85 dBFS 1 0dBFS 70 MHZ Full 69 80 69 80 dBFS 128 MHz Full 66 72 66 72 dBFS Image Spur Analog Input 10 MHz Full 60 75 60 75 dBFS 1 0 dBFS 70 MHz Full 60 72 60 72 dBFS 128 MHz Full 60 66 60 66 dBFS Offset Spur Analog Input 1 0 dBFS 60 V 65 65 dBFS Two Tone IMD F1 F2 6 dBFS 60 C V 75 75 Rev Page 6 of 28 AD12401 AD12401 326KWS AD12401 326JWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit ANALOG INPUT Frequency Range Full 10 140 10 140 MHZ DIGITAL INPUT DR EN Minimum Time Low Full 6 2 6 2 nS SWITCHING SPECIFICATIONS Conversion Rate Full IV
35. ounted Parts WS Suffix Dimensions shown in inches Tolerances 0 xxx 5 mils ORDERING GUIDE Model Temperature Range Package Description AD12401 326KWS 0 to 60 Case 2 9 x 2 6 x 0 6 Module AD12401 326JWS 0 to 60 C Case 2 9 x 2 6 x 0 6 Module AD12401 360KWS 0 to 60 C Case 2 9 x 2 6 x 0 6 Module AD12401 400KWS 0 to 60 C Case 2 9 x 2 6 x 0 6 Module AD12401 400JWS 0 to 60 C Case 2 9 x 2 6 x 0 6 Module AD12401 KIT Evaluation Kit The encode rate and gain mode must be selected when ordering the AD12401 KIT The standard AD12401 KIT is configured for low gain mode at 400 MSPS 2006 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05649 0 4 06 A ANALOG Rev A Page 28 of 28
36. re the DNL was assumed to be 0 4 LSB and the input noise was assumed to be 0 8 LSB rms The vertical marker at 0 4 ps displays the SNR at the jitter level present in the AD12401 evaluation system including the jitter associated with the AD12401 itself SNR dB B Ain 180MHz 05649 020 0 01 02 03 04 05 06 07 08 09 10 APERTURE JITTER ps rms Figure 21 SNR vs Aperture Jitter In addition to jitter the harmonic content of the single ended sine wave clock sources must be controlled The clock source used in the test and calibration process has a harmonic per formance that is better than 60 dBc Additionally when using PECL or other square wave clock sources unstable behavior such as overshoot and ringing can affect phase matching and degrade the image spur performance DIGITAL OUTPUTS The AD12401 s digital postprocessing circuit provides two parallel 12 bit 200 MSPS data output buses By providing two output busses that operate at one half the conversion rate the AD 12401 eliminates the need for large expensive high power demultiplexing circuits The output data format is twos com plement maintaining the standard set by other high speed ADCs such as the AD9430 and AD6645 Data ready signals are provided for facilitating proper timing in the data capture circuit POWER SUPPLIES The AD12401 requires three different supply voltages a 1 5 V supply for the digital postproces
37. ritical consideration is that a 12 bit perform ance requirement 74 dBc requires keeping conducted EMI currents referenced to the input of the AD12401 below 4 5 uA All the characterization and testing of the AD12401 is performed using a system that isolated these ground planes If thermal interface material is used in the final system design the following layout factors need to be considered open solder mask on the area that contacts the interface material and the thickness of the ground plane While this should be analyzed in each specific system design the use of solder mask can negate any advantage achieved by using the thermal interface material and its use should be carefully considered The ground plane thickness does not have a major impact on the thermal per formance but if design margin is slight additional thickness can yield incremental improvements PCB INTERFACE Figure 38 provides the mounting hole footprint for assembling the AD12401 to the second level assembly The diagram is referenced to the center of the mating QTE connector Refer to the QTE QSE series connector documentation at www samtec com for the SMT footprint of the mating connector The top view of the second level assembly footprint provides a diagram of the second level assembly locating tab locations for mating the Samtec QTE 060 01 L A K TR terminal strip on the AD12401 to a QSE 060 01 L A K TR socket on the second level assembly The diagram is ref
38. s the user to reload the FPGA in case of a low digital supply voltage condition or a power supply glitch Pulling the RESET pin low pulls the data ready and output bits high until the FPGA is reloaded The RESET pin should remain low for a minimum of 200 ns On the rising edge of the reset pulse the AD12401 starts loading the configuration into the FPGA The reload process requires a maximum of 87 ms to complete Valid signals on the data ready pins indicate the reset process is complete In addition system designers must be aware of the thermal conditions of the AD12401 at startup If large thermal imbalances are present the AD12401 can require additional time to stabilize before providing specified image spur performance DR EN The DR EN pin is used to synchronize the collection of data into external buffer memories DR EN must be held low for a minimum amount of time see Table 2 through Table 4 for each ENCODE rate to ensure correct operation The function shuts off DRA and DRB until the DR EN pin is set high again DRA and DRB resume on the next valid DRA after DR EN is released If this feature is not required tie this pin to 3 3 V through a 3 74 OVERRANGE The differential OROUT pins are used to determine if the AD12401 input is overranged OROUT timing is identical to the Channel B data If the OROUT pin is high then the Channel B data coincident with the overrange indication or the Channel A data immediately prece
39. sing circuit a 3 3 V supply to facilitate digital I O through the system and a 3 8 V supply for the analog conversion and clock distribution circuits The AD12401 incorporates two key features that result in solid PSRR performance First on board linear regulators are used to provide an extra level of power supply rejection for the analog circuits The linear regulator used to supply the ADCs provides an additional 60 dB of rejection at 100 kHz Second to address higher frequency noise where the linear regulators rejection degrades the AD12401 incorporates high quality ceramic decoupling capacitors AD12401 While this product was designed to provide good PSRR performance system designers need to be aware of the risks associated with switching power supplies and consider using linear regulators in their high speed ADC systems Switching power supplies typically produces both conducted and radiated energy that result in common differential mode EMI currents Any system that requires 12 bit performance has very little room for errors associated with power supply EMI For exam ple a system goal of 74 dB dynamic range performance on the AD12401 requires noise currents that are less than 4 5 uA and noise voltages of less than 225 uV in the analog input path STARTUP AND RESET The AD12401 s FPGA configuration is stored in the on board EPROM and loaded into the FPGA when power is applied to the device The RESET pin active low allow
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ANALOG DEVICES AD12401 12 Bit 400 MSPS A/D Converter handbook