ANALOG DEVICES AD12400 12-Bit 400 MSPS A/D Converter handbook
Contents
1. Pin Number Mnemonic Function 1 2 3 4 Digital Supply 3 3 V 5 RESET LVTTL 0 Device Reset Minimum Width 200 ns Device resumes operation after 600 ms maximum 6 9 11 13 16 DNC Do Not Connect 49 51 52 79 96 108 10 DRB Channel B Data Ready Complement output 12 DRB Channel B Data Ready True output 17 DB11 Channel B Data Bit 11 Complement output bit 18 DB10 Channel B Data Bit 10 Complement output bit 19 DB11 Channel B Data Bit 11 True output bit 20 DB10 Channel B Data Bit 10 True output bit 21 DB9 Channel B Data Bit 9 Complement output bit 22 DB8 Channel B Data Bit 8 Complement output bit 23 DB9 Channel B Data Bit 9 True output bit 24 DB8 Channel B Data Bit 8 True output bit 25 DB7 Channel B Data Bit 7 Complement output bit 26 DB6 Channel B Data Bit 6 Complement output bit 27 087 Channel B Data Bit 7 True output bit 28 DB6 Channel B Data Bit 6 True output bit 29 DB5 Channel B Data Bit 5 Complement output bit 30 DB4 Channel B Data Bit 4 Complement output bit 31 DB5 Channel B Data Bit 5 True output bit 32 DB4 Channel B Data Bit 4 True output bit 33 DB3 Channel B Data Bit 3 Complement output bit 34 DB2 Channel B Data Bit 2 Complement output bit 35 DB3 Channel B Data Bit 3 True output bit 36 DB2 Channel B Data B2. 15 Time Interleaving 15 Analog 16 16 Digital 16 Power Supplies 16 START UP AND 17 REVISION HISTORY Revision 0 Initial Version Lead 17 Thermal Considerations seen 17 Package Integrity Mounting Guidelines 18 AD12400 Evaluation 19 Power COnDnector 19 Puri e 19 Encode nasa 19 Data Outputs eee mieten 19 Adapter tiores 19 Digital Post Processing Control 19 jj 19 Layout 25 25 Outline 100 entente tenens 27 Ordering 27 Rev 0 Page 2 of 28 SPECIFICATIONS AD12400 DC SPECIFICATIONS Table 1 VA 3 8 V VC 3 3 VD 1 5 V Encode 400 MSPS 0 C lt Tcasz lt 60 C unless otherwise noted AD12400JWS AD12400KWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full IV Guaranteed Guaranteed Offset Error Full
3. D 12400 pv fS ANALOG 12 Bit 400 MSPS DEVICES A D Converter AD12400 FEATURES FUNCTIONAL BLOCK DIAGRAM 400 MSPS sample rate SNR of 63 dBFS 128 MHz AD12400 Q READY SFDR of 70 dBFS 9128 MHz VSWR of 1 1 5 Wideband ac coupled input signal conditioning DAO DA11 Enhanced spurious free dynamic range POST Single ended or differential encode signal aa LVDS output levels a DB0 DB11 Twos complement output data DATA APPLICATIONS READY Communications test equipment CLOCK DISTRIBUTION DIVIDE BY 2 Radar and satellite subsystems Phased array antennas digital beam forming Multichannel multimode receivers Secure communications Wireless and wired broadband communications Wideband carrier frequency systems 03735 0 001 PRODUCT HIGHLIGHTS GENERAL DESCRIPTION x 1 t le rate of 400 MSPS The AD12400 is a 12 bit analog to digital converter with a x transformer coupled analog input and digital post processing 2 Inputsignal conditioning with optimized dynamic for enhanced SFDR The product operates at a 400 MSPS performance to 180 MHz conversion rate with outstanding dynamic performance in wideband carrier systems 3 Additional performance options available contact factory The AD12400 requires 3 8 V analog 3 3 V digital and 1 5 V 4 Proprietary Advanced Filter Bank digital post processing digital supplies and provides a flexible encode signal that can be from VCorp Technologies Inc
4. the knifing or peeling action of applying force to one end or one side must be avoided to prevent damage to the connector and guidepost Rev 0 Page 25 of 28 AD12400 1 184 30 0673 u i 2 5 1 025 26 0164 2 1 1 0 0 DATUM CENTER OF CONNECTOR 000 0000 R 0470 R1 19 6x E 2 H 1 025 26 0164 2x 1 184 30 0673 0 000 0000 0 105 2 6670 2x 2 159 54 8258 2x 0 396 10 0456 2x Figure 37 Top View of Interface PCB Assembly Rev 0 Page 26 of 28 03735 0 035 OUTLINE DIMENSIONS 3 190 2 890 A A 2 590 MAX 2 328 TYP 0 856 TYP TOP VIEW a TYP SIDE VIEW JOHNSON SMA 50 OHM CONNECT NO 142 0711 821 0 600 4 2 56 STUDS 4x 0 175 SAMTEC CONNECTOR QTE 060 01 L D A K TR 1 773 gt 0 505 TYP 2x 1 753 BOTTOM VIEW Figure 38 Outline Dimensions Dimensions shown in inches Tolerances 0 xx 10 mils 0 xxx 5 mils AD12400 ORDERING GUIDE Model Temperature Range Package Description AD12400KWS 0 C to 60 C Case 2 9 x 2 6 x 0 6 AD12400JWS 0 C to 60 C Case 2 9 x 2 6 x 0 6 AD12400 KIT 25 C Evaluation Kit Rev 0 Page 27 of 28 AD12400 2003 Analog Devices Inc All rights re
5. Rev 0 Page 18 of 28 AD12400 EVALUATION KIT The AD12400 KIT offers an easy way to evaluate the AD12400 The AD12400 KIT includes the AD12400KWS mounted on an adapter card the AD12400 evaluation board the power supply cables a 225 MHz Buffer Memory FIFO board and the Dual Analyzer software The user must supply a clock source an analog input source a 1 5 V power supply a 3 3 V power supply a 5 V power supply and a 3 8 V power supply The clock source and analog input source connect directly to the AD12400KWS The power supply cables included and a parallel port cable not included connect to the evaluation board Power Connector Power is supplied to the board via a detachable 12 lead power strip three 4 pin blocks Table 8 Power Connector VA 3 8V Analog supply for the ADC 950 mA typical 3 3 V Digital supply for the ADC outputs 200 mA typical VD 1 5V Digital supply for the FPGA 2 5 A max 1 4 A typical VB 5 0V Digital supply for the Buffer memory board 400 mA typical The power supply cable has approximately 100 mV drop The VD supply current is dependent upon the analog input frequency Refer to Figure 17 Analog Input The analog input source connects directly to an SMA on the AD12400KWS Encode The single ended or differential encode signal connects directly to SMA connector s on the AD12400KWS A single ended sine wave at 10 dBm connected to the Encode SMA is recom
6. differential or single ended No external reference is required The AD12400 package style is an enclosed 2 9 x 2 6 x 0 6 module Performance is rated over a 0 C to 60 C case temperature range Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A or otherwise under any patent or patent rights of Analog Devices Trademarks and Tel 781 329 4700 www analog com registered trademarks are the property of their respective owners Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD12400 TABLE CONTENTS Specifications isisisi ainsin aris n inie E ES 3 DC Specifications aaa 3 AC Specifications saa qq aqa 4 Explanation of Test 5 Absolute Maximum Ratings essent 6 ESD Caution ettet rere Ree tret ie HIER sees 6 Pin Configuration and Function 8 Definitions of Specifications 11 Typical Performance Characteristics 13 Theory of
7. 12 12 12 412 LSB Gain Error 10 MHz Full 10 10 10 10 96FS Differential Nonlinearity 60 C V 0 3 0 3 LSB DNL Integral Nonlinearity INL 60 C V 0 5 0 5 LSB TEMPERATURE DRIFT Gain Error 60 C V 0 02 0 02 C ANALOG INPUT AIN Full Scale Input Voltage 60 C V 32 3 2 V p p Range Frequency Range Full IV 10 180 10 180 MHz Flatness 10 MHz 180 MHz Full IV 0 5 1 0 5 1 dB Input VSWR 50 60 C V 1 5 1 5 10 MHz 180 MHz Analog Input Bandwidth 60 C V 450 450 MHz POWER SUPPLY Supply Voltage VA Full IV 3 6 3 8 3 6 3 8 V Full IV 3 2 3 4 3 2 34 V VD Full IV 1 475 1 575 1 475 1 575 V Supply Current 3 8 V Full 0 95 1 11 0 95 1 11 Ivc VC 3 3 V Full 400 500 400 500 mA lvo VD 1 5 V Full 1 4 1 8 1 4 1 8 A Total Power Dissipation Full 7 0 8 5 7 0 8 5 w ENCODE INPUTS2 Differential Inputs ENC Input Voltage Range Full IV 0 4 0 4 V Input Resistance 60 C V 100 100 Q Input Capacitance 60 C V 4 4 pF Common Mode Voltage 60 C V 3 3 V Single Ended Inputs ENC Input Voltage Full IV 0 4 2 2 5 0 4 2 2 5 V p p Input Resistance 60 C V 50 50 Q LOGIC INPUTS RESET Logic 1 Voltage Full IV 2 0 2 0 V Logic 0 Voltage Full IV 0 8 0 8 V Source lin 60 C V 10 10 uA Source l 60 C V 1 1 mA LOGIC OUTPUTS DRA DRB Output Differential Output Voltage Full IV 247 454 247 454 mV Rev 0 Page 3 of 28 AD12400 AD1240
8. 5 8 5 8 Figure 36 Evaluation Adapter Board Bottom Silkscreen Rev 0 Page 24 of 28 LAYOUT GUIDELINES The AD12400 requires a different approach to traditional high speed analog to digital converter system layouts While the AD124005 internal PCB isolates digital and analog grounds these planes are tied together through the product s aluminum case structure Therefore the decision of isolating the analog and digital grounds on the system PCB has additional factors to consider For example if the AD12400 will be attached with conductive thermal interface material to the system PCB there will be essentially no benefit to keeping the analog and digital ground planes separate If either no thermal interface material or nonconductive interface material is used system architects will have to consider the ground loop that will be created if analog and digital planes are tied together directly under the AD12400 This EMI based decision will have to be considered on a case by case basis and will be largely dependent on the other sources of EMI in the system One critical consideration is that a 12 bit performance requirement 74 dBc will require keeping conducted EMI currents referenced to the input of the AD12400 below 4 5 uA All of the characterization and testing of the AD12400 was performed using a system that isolated these ground planes If thermal interface material is used in the final system design the following layout
9. AD12400 Thermal Management and Measurement Application Note for further details From a channel matching perspective the most important consideration will be external thermal influences It is possible for thermal imbalances in the end application to adversely affect the dynamic performance Due to the temperature dependence of the image spur substantial deviation from the factory calibration conditions can have a detrimental effect Unbalanced thermal influences can cause gradients across the module and performance degradation may result Examples of unbalanced thermal influences may include large heat dissipating elements near one side of the AD12400 or obstructed air flow that does not flow uniformly across the module The thermal sensitivity of the module can be affected by a change in thermal gradient across the module of 2 C Rev 0 Page 17 of 28 AD12400 TYPICAL JUNCTION CASE AMBIENT NO AIR FLOW 100 LFM 300 LFM AIRFLOW CONDITION TEMPERATURE C 03735 0 019 Figure 21 Typical Temperature vs Air Flow with No Module Board Interface Material Normalized to 60 C Module Case Temperature 130 TYPICAL JUNCTION 110 100 80 70 CASE 60 AMBIENT 40 TEMPERATURE C 03735 0 020 NO AIR FLOW 100 LFM 300 LFM AIRFLOW CONDITION Figure 22 Typical Temperature vs Air Flow with T FLEX Module Board Interface Material Normalized
10. MHz i 400 MSPS SNR 62 5dB 0 710 SFDR 69 9dBc SFDR 77 3dBc _20 SINAD 61 198 IMAGE SPUR 73 488 220 30 249 30 ES 40 60 50 70 3 x 2 ua 80 M N 90 t4 5 s 100 MEET ETT i azo i db Aul E 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz Figure 8 FFT fs 400 MSPS An 128 123 MHz 1 0 dBFS Figure 11 Two Tone Intermodulation Distortion 70 1 MHz and 73 1 MHz 400 MSPS Rev 0 Page 13 of 28 AD12400 MAGNITUDE dB 120 SFDR 70dBc 2F1 F2 2F2 F1 ERR 0 20 40 60 80 Li olli 100 120 140 160 180 200 2 03735 0 036 HARMONICS dBc Figure 12 Two Tone Intermodulation Distortion 178 1 MHz and 182 1 MHz fs 400 MSPS SFDR 70 dBc GAIN dB o 0 5 10 7 35 0 59 3 83 6 107 9 132 2 156 5 180 8 205 1 229 4 100 95 FREQUENCY MHz Figure 13 Interleaved Gain Flatness sas d 7 THIRD HARMONIC 7 90 85 IMAGE SPUR 80 75 SECOND HARMONIC DISTORTION dBFS 7
11. dynamic range performance There are two major factors to consider when designing the input clock circuit for the AD12400 aperture jitter and harmonic content The relationship between aperture jitter and SNR can be characterized using the following equation The equation assumes a single tone full scale input signal 2 2 1 1 242 ors SNR 201 fA x0t mus P x E Vx Vuotsims 1 5 2N 2N f 4 Input frequency RMS Aperture jitter N ADC resolution bits e ADC DNL LSB VNOISE ADC input noise LSBrms Figure 20 displays the application of this relationship to full scale single tone input signal on the AD12400 where the DNL was assumed to be 0 4 LSB and the input noise was assumed to be 0 8 LSBrms The vertical marker at 0 4 ps displays the SNR at the jitter level present in the AD12400 evaluation system including the jitter associated with the AD12400 itself Ain LOMHz Ain 65MHz Ain 128MHz SNR dB E Ay 180MHz 03735 0 037 0 01 02 03 04 05 06 07 08 09 10 APERTURE JITTER ps rms Figure 20 SNR vs Aperture Jitter In addition to jitter the harmonic content of single ended sine wave clock sources must be controlled as well The clock source used in the test and calibration process has a harmonic performance that is better than 60 dBc Also when using PECL or other square wave clock sources unstable behavior such as oversh
12. output bit 73 DA1 Channel A Data Bit 1 Complement output bit 74 DAO Channel A Data Bit 0 Complement output bit DAO is LSB 75 DA1 Channel A Data Bit 1 True output bit 76 DAO Channel A Data Bit 0 True output bit DAO is LSB 77 LEAD LAG Typically DNC See LEAD LAG note on Page 17 78 DRA Channel A Data Ready Complement output 80 DRA Channel A Data Ready True output 81 95 109 112 129 132 AGND Analog Ground 113 120 VA Analog Supply 3 8 V 121 128 DGND Digital Ground Internal Ground Plane Connections Section A DGND Pins 121 124 Section B DGND Pins 125 128 Section AGND Pins 129 132 Rev 0 Page 10 of 28 DEFINITIONS SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency as determined by the FFT analysis is reduced by 3 dB Aperture Delay The delay between the 5096 point on the rising edge of the ENCODE command and the instant at which the analog input is sampled Aperture Uncertainty Jitter The sample to sample variation in aperture delay Full Scale Input Voltage Range This is the maximum peak to peak input signal magnitude that will result in a full scale response 0 dBFS on a single tone input signal case Any magnitude increase from this value will result in an over range condition Analog Input VSWR 50 Q The Voltage Standing Wave Ratio is a ratio of the transmitted and reflected signals The
13. to 60 C Module Case Temperature Ambient PACKAGE INTEGRITY MOUNTING GUIDELINES The AD12400 is a printed circuit board PCB based module designed to provide mechanical stability and support the intricate channel to channel matching necessary to achieve high dynamic range performance The module should be secured to the motherboard using 2 56 nuts washer use is optional The torque on the nuts should not exceed 32 inch ounces The SMA edge connectors AIN ENC ENC are surface mounted to the board in order to achieve minimum height of the module When attaching and routing the cables one must ensure they are stress relieved and do not apply stress to the SMA connector board The presence of stress on the cables may degrade electrical performance and mechanical integrity of the module In addition to the routing precautions the smallest torque necessary to achieve consistent performance should be used to secure the system cable to the AD12400 s SMA connectors In no case should the torque exceed 5 inch pounds Any disturbances to the AD12400 structure including removing the covers or mounting screws will invalidate the calibration and result in degraded performance Refer to the Outline Dimensions section for mounting stud dimensions Refer also to Figure 37 for PCB interface locations Mounting stud length will typically accommodate a PCB thickness of 0 093 Consult the factory if board thickness requirements exceed this dimension
14. 0 65 60 0 10 20 ANALOG INPUT LEVEL dB 30 40 50 60 70 03735 0 013 03735 0 012 SNR dBFS Figure 14 2nd 3rd Harmonics and Image Spur vs Analog Input Level 400 MSPS 70 MHz Rev 0 Page 14 of 28 95 90 85 IMAGE SPUR 80 SECOND HARMONIC 75 TH IRD HARMONIC 70 65 Figure 15 Harmonics vs Analog Input Frequency 64 6 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY MHz 64 4 64 2 64 0 63 8 63 6 63 4 63 2 63 0 62 8 0 20 40 60 80 100 120 140 Figure 16 SNR vs Analog Input Frequency 2 2 ANALOG INPUT FREQUENCY MHz 2 1 2 0 19 1 8 17 1 6 1 5 14 VD SUPPLY CURRENT A 1 3 1 2 11 1 0 0 2 180 03735 0 016 0 40 60 80 100 120 140 160 180 200 INPUT FREQUENCY MHz Figure 17 VD Current vs Aw Frequency 03735 0 014 03735 0 015 THEORY OPERATION The AD12400 uses two high speed 12 bit analog to digital converters ADCs in a time interleaved configuration to double the sample rate while maintaining a high level of dynamic range performance The digital output of each ADC channel is calibrated using a proprietary digital post processing technique Advanced Filter Bank
15. 0 0 DGND DGND AGND ce C5 10uF 0 1uF EVQ PAC85R DGND DGND DGND 03735 0 021 E220 1 5V SENSE Figure 23 Evaluation Board Rev 0 Page 20 of 28 GND GND Eb un V V DGND QSE 60 01 L D A K AD12400 1 1 2 I 1 RESET s 5 1 1 ao 1 DNC 9 10 DRB 1 11 12 DRB puc m AAC ONC 15 16 nho dn pex 15 28 5810 BES DBS DBS 23 24 25 26 DB6 27 28 I m 0208 31 32 s i Cem 5872 38 581 37 E DBO I 39 40 0812 21 i2 i GND L3 123 124 Y SE 60 01 L D A K y DGND QSE 60 01 L D A l DGND 1 1 I 41 42 Lsv u 45 46 48 49 50 onc i 52 1 baat 55 56 10 1 PAS gt 57 58 DAS Dae 59 60 DAB ns 5552 83 2 ___ pas s se ona lt lt A ps 5 7 lt b or I DA1 75 76 lt pao 77 78 lt DRA 1 79 80 125 126 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 104655 9 DGND Figure 24 Evaluation Board Rev 0 Page 21 of 28 ant 2400 AMP104655 9 DGND 03735
16. 0 022 AD12400 eo lt lt 03735 0 023 Figure 25 Power Plane 1 Figure 26 Power Plane 2 03735 0 024 Figure 28 Second Ground Plane Rev 0 Page 22 of 28 03735 0 025 03735 0 026 Figure 29 Side Copper vv NUS ee 9 cane bg Figure 30 Bottom Side Copper 99999400990060009906 6000 oeoo e gt EP 1 Figure 31 Top Mask AD12400 x Y Ltd Rom d ND do Loe em B oem ms ee g mot r Oe 2925 k J m ns omer B 9 L 9 8 Figure 32 Top Silkscreen P 8 ve 2 y 9 JN EUER ME oO 000 9 a sum Osa a ga Qua 9 m Ow on an wre mr 4 5 2 Figure 33 Bottom Silkscreen GS08350A SCH GS08352A PCB GS08353A ASY D rires DEVICES AD12400 EVAL ADAPTER BOARD 8 3 MADE IN USA 5 Figure 34 Evaluation Adapter Board Top Silkscreen Rev 0 Page 23 of 28 03735 0 030 AD12400 03735 0 033 Figure 35 Evaluation Adapter Board Analog and Digital Layers z 5 9
17. 0JWS AD12400KWS LOGIC OUTPUTS Output Drive Current Full IV 4 4 4 4 mA Output Common Mode Full IV 1 125 1 375 1 125 1 375 V Voltage Start Up Time Full IV 600 600 ms Tested using input frequency of 70 MHz See Figure 17 for variation vs input frequency 2 All ac specifications tested by driving ENC single ended 3 Refer to Table 5 for logic convention on all logic inputs Digital Output Logic Levels DR V 3 3 V Cio 7 8 pF 3 3 V LVDS R1 100 O Specifications subject to change without notice AC SPECIFICATIONS Table 2 VA 3 8 VC 3 3 V VD 1 5 V Encode 400 MSPS 0 C x Tcas lt 60 C unless otherwise noted AD12400JWS AD12400KWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE SNR Analog Input 10 MHz Full 62 64 4 62 64 4 dBFS 1 0 dBFS 70 MHz Full 61 5 64 61 5 64 dBFS 128 MHz Full 60 63 5 60 63 5 dBFS 180 MHz Full 60 62 5 60 62 5 dBFS SINAD Analog Input 10 MHz Full 61 64 61 64 dBFS 1 0 dBFS 70 MHz Full 60 5 64 60 5 64 dBFS 128 MHz Full 59 62 5 59 62 5 dBFS 180 MHz Full 57 61 57 61 dBFS Spurious Free Dynamic Range Analog Input 10 MHz Full 69 80 69 80 dBFS 1 0 dBFS 70 MHz Full 69 84 69 84 dBFS 128 MHz Full 67 76 67 76 dBFS 180 MHz Full 62 71 62 71 dBFS Image Spur Analog Input 10 MHz Full 60 75 62 75 dBFS 1 0 dBFS 70 MHz Full 60 72 62 72 dBFS 128 MHz Full 56 70 62 70 dBFS 180 MHz Full 54 70 62 70 dBFS Offset Spur 60 C V
18. 65 65 dBFS Analog Input 1 0 dBFS Two Tone IMD F1 F2 6 dBFS 60 C V 75 75 dBc SWITCHING SPECIFICATIONS Conversion Rate Full IV 396 400 404 396 400 404 MSPS Encode Pulsewidth High 60 C V 1 25 1 25 ns Encode Pulsewidth Low t 60 C V 1 25 1 25 ns DIGITAL OUTPUT PARAMETERS Valid Time tv Full IV 1 9 24 3 1 1 9 24 3 1 ns Propagation Delay trp 60 C V 1 20 1 20 ns Rise Time tr 20 to 80 60 C V 1 1 ns Fall Time tr 20 to 80 60 C V 1 1 ns Rev 0 Page 4 of 28 AD12400 AD12400JWS AD12400KWS Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit DR Propagation Delay teor 60 C V 3 88 3 88 ns Data to DR Skew tpp 60 C V 2 68 2 68 ns Pipeline Latency Full IV 40 40 Cycles Aperture Delay t4 60 C V 1 6 1 6 ns Aperture Uncertainty Jitter 60 C V 0 4 0 4 ps rms All ac specifications tested with a single ended 2 0 V p p ENCODE Dynamic performance guaranteed for analog input frequencies of 10 MHz to 180 MHz Not including image spur 4 Image spur will be at fs 2 Aw and the offset spur will be at fs 2 5F1270 MHz F2 73 MHz Parts are tested with 400 MSPS encode Device can be clocked at lower encode rates but specifications are not guaranteed Specifications will be guaranteed by design for encode 400 MSPS x 196 Pipeline latency will be exactly 40 cycles EXPLANATION OF TEST LEVELS 10096 production tested 100
19. AFB from VCorp Technologies AFB is implemented using a state of the art Field Programmable Gate Array FPGA and provides a wide bandwidth wide temperature match for any gain phase and clock timing errors between each ADC channel TIME INTERLEAVING ADCS When two ADCs are time interleaved gain and or phase mismatches between each channel will produce an Image Spur at fs 2 fam and an Offset Spur as shown in Figure 18 These mismatches can be the result of any combination of device tolerance temperature and frequency deviations IMAGE SPUR 40 X OFFSET SPUR dB 1 P 03735 0 017 20 40 6 80 10 120 140 160 180 200 2 Figure 18 Image Spur Due to Mismatches between Two Interleaved ADCs No AFB Digital Post Processing Figure 19 displays the performance of a similar converter with on board AFB post processing implemented The 44 dBFS image spur has been reduced to 77 dBFS and as a result the dynamic range of this time interleaved ADC is no longer limited by the channel matching AD12400 IMAGE SPUR OFFSET SPUR 03735 0 018 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz Figure 19 AD12400 with AFB Digital Post Processing The relationship between image spur and channel mismatches is captured in Table 7 for specific conditions Table 7 Image Spur vs Channel M
20. EADILAG PIN IS RELEASED DRA AND DRB WILL RESUME ON THE NEXT VALID DRA AFTER LEADILAG IS RELEASED 03735 0 002 RESET Low LVTTL High 3 74 kQ Pull Up LEAD LAG Low LVTTL Low 10 60 Figure 3 Timing Diagram Pull Down ENCODE PECL DRIVER 03735 0 004 ENCODE Figure 4 Highlighted Timing Diagram 03735 0 003 Figure 2 Encode Equivalent Circuit Rev 0 Page 7 of 28 AD12400 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 119 TOP VIEW JOHNSON SMA 50 OHM CONNECT NO 142 0711 821 PIN 79 2 56 STUDS 4x END VIEW SAMTEC CONNECTOR BOARD QTE 060 01 L D A K TR PIN 39 BOTTOM VIEW LEFT SIDE VIEW NOTES INTEGRAL GROUND PLANE CONNECTIONS FOR MATING HALF USE SAMTEC INC SECTION A DGND PINS 121 124 PART NO QSE 60 01 L D A K SECTION B DGND PINS 125 128 SECTION C AGND PINS 129 132 PIN 1 Figure 5 Pin Configuration Rev 0 Page 8 of 28 VA PIN 120 VA VA VA AGND AGND DNC DNC DNC DNC DNC DNC AGND AGND AGND AGND AGND AGND AGND AGND DNC PIN 80 LEAD LAG DA1 DA1 DA3 DA3 5 DA5 DA7 DA7 B DA9 DA9 DA11 DA11 DNC DNC 1 40 DB1 DB3 DB3 DB5 DB5 DB7 DB7 DB9 DB9 A DB11 DB11 DNC DNC DNC DNC DNC RESET vc vc PIN 2 03735 0 005 Table 6 Pin Function Descriptions AD12400
21. VSWR can be related to input impedance using the following equations 21 Zg 21 Z vswn El 1 7 2 Actual Load Impedance Z5 Reference Impedance Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step Effective Number of Bits ENOB Calculated from the measured SNR based on the equation SNR MEASURED 1 76 dB 6 02 Encode Pulsewidth Duty Cycle Pulsewidth high is the minimum amount of time the ENCODE pulse should be left in Logic 1 state to achieve rated perform ance pulsewidth low is the minimum time the ENCODE pulse should be left in low state See timing implications of changing tencuin the Application Notes Encode Input section At a specified clock rate of 400 MSPS these specifications define an acceptable ENCODE duty cycle ENOB Full Scale Input Power Expressed in dBm Computed using the following equation 2 FULL SCALErms POWER 1010 FULL SCALE 1 Es 0 001 AD12400 Gain Error The difference between the measured and ideal full scale input voltage range of the ADC Harmonic Distortion Second The ratio of the RMS signal amplitude to the RMS value of the second harmonic component reported in dBFS Harmonic Distortion Third The ratio of the RMS signal amplitude to the RMS value of the third harmonic component reported in dBFS Distortion Image Spur The ratio of the RMS signal amplitude to the RMS signal amplitude of the imag
22. amage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev 0 Page 6 of 28 ED ESD SENSITIVE DEVICE AD12400 Table 4 Output Coding Twos Complement Code AIN V Digital Output 4095 1 6 0111 1111 1111 22 ee ten 1 ENCODE ayy 400MHZ DW lt 40 CLOCK CYCLES 2048 0 0000 0000 0000 2047 0 000781 11111111 1111 pataoura O GENES DRA 3 zn DRA Mee E m 0 16 1000 0000 0000 LEAD LAG Table 5 Option Pin List With Necessar Associated Circuitr y LOST DUE TO ASSERTION OF LEADILAG LATENCY OF 40 ENCODE CLOCK CYCLES BEFORE DATA VALID z NOTES Active Logic Associated 1 IF A SINGLE ENDED SINEWAVE IS USED FOR ENCODE USE THE ZERO CROSSING POINT AC COUPLED AS THE 50 POINT AND APPLY THE SAME TIMING INFORMATION 2 THE LEADILAG PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES THE H Ig hor Level Default Circu itry LEADILAG PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12400 IF APPLIED n ASYNCHRONOUSLY LEADILAG MUST BE HELD HIGH FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION THE Pin Name Low Type Level Within Part FUNCTION WILL SHUT OFF DRA AND DRB UNTIL THE L
23. e spur reported in dBFS The image spur a result of gain and phase errors between two time interleaved conversion channels is located at fs 2 fam Distortion Offset Spur The ratio of the RMS signal amplitude to the RMS signal amplitude of the offset spur reported in dBFS The offset spur a result of offset errors between two time interleaved conversion channels is located at fs 2 Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using best straight line determined by a least square curve fit Minimum Conversion Rate The minimum ENCODE rate at which the image spur calibration will degrade no more than 1 dB when image spur is 70 dB Maximum Conversion Rate The maximum ENCODE rate at which the image spur calibration will degrade no more than 1 dB when image spur is 70 dB Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE or zero crossing of a single ended ENCODE Total Noise Calculated as follows Be SNRpc SIGNAL Z 0 001 10 10 where Z is the input impedance FS is the full scale of the device for the frequency in question SNR is the value of the particular input level and SIGNAL is the signal level within the ADC reported in dB below full scale This value includes both thermal and quantization noise Rev 0 Page 11 of 28 AD12400 Offset Error The DC offs
24. eed be aware of the thermal conditions of the AD12400 at start up If large thermal imbalances are present the AD12400 may require additional time to stabilize before providing specified image spur performance LEAD LAG The LEAD LAG pin is used to synchronize the collection of data into external buffer memories The LEAD LAG pin can be applied synchronously or asynchronously to the AD12400 If applied asynchronously LEAD LAG must be held high for a minimum of 5 ns to ensure correct operation The function will shut off DRA and DRB until the LEAD LAG pin is released DRA and DRB will resume on the next valid DRA after LEAD LAG is released If this feature is not required tie this pin to DGND THERMAL CONSIDERATIONS The module is rated to operate over a case temperature of 0 C to 60 C In order to maintain the tight channel matching and reliability of the AD12400 care must be taken to assure that proper thermal and mechanical considerations have been made and addressed to assure case temperature is kept within this range Each application will require evaluation of the thermal management as applicable to the system design The following provides information that should be used in the evaluation of AD12400 thermal management for each specific use AD12400 In addition to the radiation of heat into its environment the AD12400 module enables flow of heat through the mounting studs and standoffs as they contact the motherboard As d
25. el is lowered or in dBFS always related back to converter full scale Rev 0 Page 12 of 28 AD12400 TYPICAL PERFORMANCE CHARACTERISTICS NOTE X Image spur N Interleaved offset spur SNR 61 648 SFDR 69 0dBc SINAD 60 0dB 4 IMAGE SPUR 70 4dBc SNR 63 3dB 10 SFDR 75dBc SINAD 62 9dB 20 IMAGE SPUR 80 5dBc dB o o CET jal ch Lu Dada alt lo sl lll 0 20 40 60 80 100 120 140 160 180 200 03735 0 009 03735 0 006 0 20 40 60 80 100 120 140 160 180 200 2 FREQUENCY MHz Figure 6 FFT fs 400 MSPS Aw 10 123 MHz 1 0 dBFS Figure 9 FFT fs 400 MSPS 180 123 MHz 1 0 dBFS 0 10 SNR 63 148 SFDR 76 3dBc SFDR 78 7dBc 20 SINAD 62 7dB 20 IMAGE SPUR 78 8dBc En 30 40 40 50 50 m 60 m 60 sts um 70 70 1 Hy n 80 EX 3N 80 n EE asi 90 90 heal 100 1 M 100 i a aoo dz uM A oL ua uu 2 120 8 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY MHz Figure 7 FFT fs 400 MSPS Aw 65 123 MHz 1 0 dBFS Figure 10 Two Tone Intermodulation Distortion 25 1 MHz and 28 1
26. escribed in the Package Integrity Mounting Guidelines section the module should be secured to the motherboard using 2 56 nuts washer use is optional The torque on the nuts should not exceed 32 inch ounces Use of a thermal grease at the standoffs will result in better thermal coupling between the board and module Depending on the ambient conditions air flow may be necessary to ensure the components in the module do not exceed their maximum operating temperature In terms of reliability the most sensitive component has a maximum junction temperature rating of 125 C Figures 21 and 22 provide a basic guideline for two key thermal management decisions the use of thermal interface material between the module bottom cover mother board and airflow Figure 21 characterizes the typical thermal profile of an AD12400 that is not using thermal interface material Figure 22 provides the same information for a configuration that uses gap filling thermal interface material in this case Thermagon T Flex 600 series 0 040 thickness was used One can see from these profiles that the maximum die temperature is reduced by approximately 2 C when thermal interface material is used Figures 21 and 22 also provide a guideline for determining the airflow requirements for given ambient conditions For example a goal of 120 C die temperature in a 40 C ambient environment without the use of thermal interface material would require an air flow of 100 LFM See the
27. et imposed on the input signal by the ADC reported in LSB codes Pipeline Latency The number of clock cycles that the output data will lag the corresponding clock cycle Power Supply Rejection Ratio The ratio of power supply voltage change to the resulting ADC output voltage change Signal to Noise and Distortion SINAD The ratio of the RMS signal amplitude set 1 dB below full scale to the RMS value of the sum of all other spectral components including harmonics but excluding DC and image spur Signal to Noise Ratio SNR The ratio of the RMS signal amplitude set at 1 dB below full scale to the RMS value of the sum of all other spectral components excluding the first five harmonics and DC Spurious Free Dynamic Range SFDR The ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component except the image spur The peak spurious component may or may not be a harmonic May be reported in dBc i e degrades as signal level is lowered or dBFS always related back to converter full scale Two Tone Intermodulation Distortion Rejection The ratio of the RMS value of either input tone to the RMS value of the worst third order intermodulation product reported in dBc Two Tone SFDR The ratio of the RMS value of either input tone to the RMS value of the peak spurious component The peak spurious component may or may not be an IMD product May be reported in dBc i e degrades as signal lev
28. factors will need to be considered open solder mask on the area that contacts the interface material and the thickness of the ground plane While this should be analyzed in each specific system design the use of solder mask may negate any advantage achieved by using the thermal interface material and its use should be carefully considered The ground plane thickness will not have a major impact on the thermal performance but if design margin is slight additional thickness can yield incremental improvements AD12400 PCB INTERFACE Figure 37 provides the mounting hole footprint for assembling the AD12400 to the second level assembly The diagram is referenced to the center of the mating QTE connector Refer to the QTE QSE series connector documentation at www samtec com for the SMT footprint of the mating connector The top view of the second level assembly footprint provides a diagram of the second level assembly locating tab locations for mating the SAMTEC QTE 060 01 L A K TR terminal strip on the AD12400BWS to a QSE 060 01 L A K TR socket on the second level assembly The diagram is referenced to the center of the QTE terminal strip on the AD12400BWS and the mounting holds for the screws which will hold the AD12400BWS to the second level assembly board The relationship of these locating tabs is based on information provided by SAMTEC connector supplier and should be verified with SAMTEC by the customer Mating and unmating forces
29. he RESET switch will pull the data ready and output bits high The RESET switch should remain low for a minimum of 200 ns On the rising edge of the RESET pulse the AD12400 will start loading the configuration into the on module FPGA The reload process requires a maximum of 600 ms to complete Valid signals on the data ready pins indicate that the reset process is complete The AD12400 is not compatible with the HSC ADC EVAL DC SC hardware or software Rev 0 Page 19 of 28 AD12400 Table 9 Evaluation Board Bill of Materials Item No Quantity REF DES Device Package Value 1 2 C5 Capacitor 603 0 1 uF 25V 2 2 C6 Capacitor 805 10 uF 6 3 V 3 1 R9 Resistor 603 4 02 196 4 1 AFB 2 Pin Header Jumper Pin Strip Molex GC Weldon 5 1 P2 80 Pin Dual Connector Assemble Surface Mount Post Header AMP 6 1 SW1 Switch Push Button SPST 6 MM Panasonic 7 3 2 J3 4 Pin Header Power Connecter Pin Strip Wieland 8 1 P1 60 Pin Dual Socket Assembly Surface Mount SAMTEC 9 1 PCB AD12400 Interface Bd GS08054 PCB R8 A 1 1 0 0 E14 _ 55 u SPARE2 S oris R9 ssvo gt 4 02kQ GAIN GAIN 210 Favo 4 02kO NYQ R11 4 02kQ JP2 E12 0 0 JP3 E13 o o DGND P4 SELECT D DIGITAL ANALOG sv gt sv gt SELECTD gt 0 lt 3 3VD I 0 1uF E17
30. ismatch Gain Error Aperture Delay Error Image Spur 96 ps dBc 1 15 40 0 25 2 7 54 0 2 1 1 62 0 025 0 5 70 For a more detailed description of time interleaving in ADCs and a design example using the AD12400 refer to Advanced Digital Post Processing Techniques Enhance Performance in Time Interleaved ADC Systems published in the August 2003 edition of Analog Dialogue This article can be found at http www analog com analogDialogue Rev 0 Page 15 of 28 AD12400 ANALOG INPUT The AD12400 analog input is ac coupled using a proprietary transformer front end circuit that provides 1 dB of gain flatness over the first Nyquist zone and a 3 dB bandwidth of 450 MHz This front end circuit provides a VSWR of 1 5 50 over the first Nyquist zone and the typical full scale input is 3 2 V p p The MiniCircuits HELA 10 amplifier module can be used to drive the input at these power levels CLOCK INPUT The AD12400 requires a 400 MSPS encode that is divided by 2 and distributed to each ADC channel 180 out of phase from each other Internal ac coupling and bias networks provide the framework for flexible clock input requirements that include single ended sine wave single ended PECL and differential PECL While the AD12400 is tested and calibrated using a single ended sine wave properly designed PECL circuits that provide fast slew rates gt 1V ns and minimize ringing will result in comparable
31. it 2 True output bit 37 DB1 Channel B Data Bit 1 Complement output bit 38 Channel B Data Bit 0 Complement output bit DBO is LSB 39 DB1 Channel B Data Bit 1 True output bit 40 DBO Channel B Data Bit 0 True output bit DBO is LSB 41 48 Digital Supply 1 5 V 50 PASS LVTTL Factory use only DNC 53 DA11 Channel A Data Bit 11 Complement output bit 54 DA10 Channel A Data Bit 10 Complement output bit 55 DA11 Channel A Data Bit 11 True output bit 56 DA10 Channel A Data Bit 10 True output bit 57 9 Channel Data Bit 9 Complement output bit 58 DA8 Channel A Data Bit 8 Complement output bit 59 DA9 Channel A Data Bit 9 True output bit 60 DA8 Channel A Data Bit 8 True output bit 61 7 Channel Data Bit 7 Complement output bit 62 DA6 Channel A Data Bit 6 Complement output bit 63 7 Channel A Data Bit 7 True output bit 64 DA6 Channel A Data Bit 6 True output bit 65 DA5 Channel A Data Bit 5 Complement output bit 66 DA4 Channel A Data Bit 4 Complement output bit 67 DA5 Channel A Data Bit 5 True output bit Rev 0 Page 9 of 28 AD12400 Pin Number Mnemonic Function 68 DA4 Channel A Data Bit 4 True output bit 69 DA3 Channel A Data Bit 3 Complement output bit 70 DA2 Channel A Data Bit 2 Complement output bit 71 DA3 Channel A Data Bit 3 True output bit 72 DA2 Channel A Data Bit 2 True
32. mended A low jitter clock source is recommended 0 5 ps to properly evaluate the AD12400 Data Outputs The AD12400KWS digital outputs are available at the 80 pin connector P2 on the evaluation board The AD12400 KIT comes with a Buffer Memory FIFO board connected to P2 that provides the interface to the parallel port of a PC The Dual Analyzer software is compatible with Windows 95 Windows 98 Windows 2000 and Windows NT The Buffer Memory FIFO board can be removed and an external logic analyzer or other data acquisition module can be connected to this connector if required AD12400 Adapter Card The AD12400KWS is attached to an adapter card that interfaces to the evaluation board through a 120 pin connector P1 which is on the top side of the evaluation board Digital Post Processing Control The AD12400 has a two pin jumper labeled AFB that allows the user to enable disable the digital post processing The digital post processing is active when the AFB jumper is applied When the jumper is removed the FPGA is set to a pass through mode which will demonstrate to the user the performance of the AD12400 without the digital post processing RESET The AD12400KWS s FPGA configuration is stored in an EEPROM and loaded into the FPGA when power is applied to the AD12400 The RESET switch SW1 active low allows the user to reload the FPGA in case of a low voltage condition or a power supply glitch Depressing t
33. oot and ringing can affect phase matching and degrade the image spur performance DIGITAL OUTPUTS The AD124005 digital post processing circuit provides two parallel 12 bit 200 MSPS data output buses By providing two output busses that operate at one half the conversion rate the AD12400 eliminates the need for large expensive high power demultiplexing circuits The output data format is twos complement maintaining the standard set by other high speed A D converters such as the AD9430 and AD6645 Data ready signals are provided for facilitating proper timing in the data capture circuit Finally the digital post processing circuit can be configured to provide alternate data output formats Contact the factory for more details POWER SUPPLIES The AD12400 requires three different supply voltages a 1 5 V supply for the digital post processing circuit a 3 3 V supply to facilitate digital I O through the system and a 3 8 V supply for the analog conversion and clock distribution circuits The AD12400 incorporates two key features that result in solid power supply rejection ratio PSRR performance First on board linear regulators are used to provide an extra level of power supply rejection for the analog circuits The linear regulator used to supply the A D converters provides an additional 60 dB of rejection at 100 kHz Second in order to address higher frequency noise where the linear regulators rejection degrades the AD12400 incorp
34. orates high quality ceramic decoupling capacitors Rev 0 Page 16 of 28 While this product has been designed to provide good PSRR performance systems designers need to be aware of the risks associated with switching power supplies and consider using linear regulators in their high speed ADC systems Switching power supplies typically produce both conducted and radiated energy that result in common differential mode EMI currents Any system that requires 12 bit performance has very little room for errors associated with power supply EMI For example a system goal of 74 dB dynamic range performance on the AD12400 will require noise currents that are less than 4 5 uA and noise voltages of less than 225 in the analog input path START UP AND RESET The AD124005 FPGA configuration is stored in the on board EPROM and loaded into the FPGA when power is applied to the device The RESET pin active low allows the user to reload the FPGA in case of alow digital supply voltage condition or a power supply glitch Pulling the RESET pin low will pull the data ready and output bits high until the FPGA has been reloaded The RESET pin should remain low for a minimum of 200 ns On the rising edge of the reset pulse the AD12400 will start loading the configuration into the FPGA The reload process requires a maximum of 600 ms to complete Valid signals on the data ready pins indicate that the reset process is complete Also system designers n
35. production tested at 25 C and sample tested at specified temperatures Il Sample tested only IV Parameter is guaranteed by design and characterization testing V Parameter is a typical value only VI 100 production tested at 25 C guaranteed by design and characterization testing for industrial temperature range 100 production tested at temperature extremes for military devices Rev 0 Page 5 of 28 AD12400 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Value VA to AGND 5V VC to 4V VD to DGND 1 65V Analog Input Voltage 6 V DC Analog Input Power 18 dBm AC Encode Input Voltage 6 V DC Encode Input Power 12 dBm AC Logic Inputs and Outputs to DGND 5V Storage Temperature Range Ambient 65 C to 150 C Operating Temperature 0 C to 60 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent d
36. served Trademarks and ANALOG registered trademarks are the property of their respective owners 0 g La DEVICES Rev 0 Page 28 of 28
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ANALOG DEVICES AD12400 12 Bit 400 MSPS A/D Converter handbook