ANALOG DEVICES AD10465 Dual Channel 14-Bit 65 MSPS A/D Converter with Analog Input Signal Conditioning handbook
Contents
1. should be separate power supplies This is because the fast digital output swings can couple switching current back into the analog sup plies Note that AVcc must be held within 5 of 5 V The AD 10465 is specified for 3 3 V as this is a common supply for digital ASICs Output Loading Care must be taken when designing the data receivers for the AD10465 The digital outputs drive an internal series resistor 2 100 Q followed by a gate like 75LCX574 To minimize capacitive loading there should only be one gate on each output pin An example of this is shown in the evaluation board sche matic shown in Figure 10 The digital outputs of the AD10465 have a constant output slew rate of 1 V ns A typical CMOS gate combined with a PCB trace will have a load of approxi mately 10 pF Therefore as each bit switches 10 mA 10 pF x 1 V 1 ns of dynamic current per bit will flow in or out of the device A full scale transition can cause up to 140 mA 14 bits x 10 mA bit of current flow through the output stages These switching currents are confined between ground and the DVcc pin Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD10465 It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications Digital out put timing is guaranteed with 10 pF loads 9 2V48 AGNDS2. IIR Tm TU itd m dual 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 20 0 22 5 25 0 27 5 30 0 32 5 FREQUENCY MHz SFDR SINAD 4 989 9 989 19 000 32 000 INPUT FREQUENCY MHz TPC 6 SFDR and SINAD vs Frequency REV 0 dB LSB dBFS REV 0 ENCODE 65MSPS Ain 9MHz AND 10MHz 7dBFS SFDR 82 83dBc F2 2F1 Fi 2 2 F2 F2 1 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 20 0 22 5 25 0 27 5 30 0 32 5 FREQUENCY MHz TPC 7 Two Tone 9 10 MHz ODE 65MSPS MAX 0 549 CODES MIN 0 549 CODES 2048 4096 6144 8192 10240 12288 14336 16384 TPC 8 Differential Nonlinearity 42 7 4 10 6 13 8 17 0 20 2 23 4 26 6 29 8 33 0 FREQUENCY MHz TPC 9 Gain Flatness LSB SNRFS AD10465 ENCODE 65MSPS 17MHz AND 18MHz 7dBFS SFDR 77 68dBc 0 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 20 0 22 5 25 0 27 5 30 0 32 5 3 0 2 0 1 0 72 0 71 5 71 0 70 5 70 0 69 5 69 0 68 5 68 0 67 5 FREQUENCY MHz TPC 10 Two Tone 9 17 18 MHz ENCODE 65MSPS INL 41 173 CODES INL MIN 1 332 CODES 2048 4096 6144 8192 10240 1
3. LAYOUT INFORMATION The schematic of the evaluation board Figure 10 represents a typical implementation of the AD10465 The pinout of the AD10465 is very straightforward and facilitates ease of use and the implementation of high frequency high resolution design practices It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device All capacitors can be standard high quality ceramic chip capacitors Care should be taken when placing the digital output runs Because the digital outputs have such a high slew rate the capacitive loading on the digital outputs should be minimized Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate EVALUATION BOARD The AD10465 evaluation board Figure 9 is designed to pro vide optimal performance for evaluation of the AD10465 analog to digital converter The board encompasses everything needed to insure the highest level of performance for evaluating the AD10465 The board requires an analog input signal encode clock and power supply inputs The clock is buffered on board to provide clocks for the latches The digital outputs and clocks are available at the standard 40 pin connectors J1 and J2 Power to the analog supply pin
4. AD10463 DEVICES ANALOG Dual Channel 14 Bit 65 MSPS A D Converter with Analog Input Signal Conditioning AD10465 FEATURES Dual 65 MSPS Minimum Sample Rate Channel to Channel Matching 0 5 Gain Error Channel to Channel Isolation gt 90 dB DC Coupled Signal Conditioning Included Selectable Bipolar Input Voltage Range 0 5 V 1 0 V 2 0 V Gain Flatness up to 25 MHz lt 0 2 dB 80 dB Spurious Free Dynamic Range Two s Complement Output Format 3 3 V or 5 V CMOS Compatible Output Levels 1 75 W per Channel Industrial and Military Grade APPLICATIONS Phased Array Receivers Communications Receivers FLIR Processing Secure Communications GPS Antijamming Receivers Multichannel Multimode Receivers PRODUCT DESCRIPTION The AD10465 is a full channel ADC solution with on module signal conditioning for improved dynamic performance and fully matched channel to channel performance The module includes two wide dynamic range AD6644 ADCs Each AD6644 has dc coupled amplifier front end including an AD8037 low distortion high bandwidth amplifier providing a high input impedance and gain and driving the AD8138 single to differential ampli fier The AD6644s have on chip track and hold circuitry and utilize an innovative multipass architecture to achieve 14 bit 65 MSPS performance The AD10465 uses innovative high density circuit design and laser trimmed thin film resistor networks to achieve exceptional
5. average DNL of the ADC typically 0 50 LSB N Number of bits in the ADC rms rms noise referred to the analog input of the ADC typically 5 LSB For a 14 bit analog to digital converter like the AD10465 aper ture jitter can greatly affect the SNR performance as the analog frequency is increased The chart below shows a family of curves that demonstrates the expected SNR performance of the AD10465 as jitter increases The chart is derived from the above equation For a complete discussion of aperture jitter please consult Analog Devices Application Note AN 501 Aperture Uncer tainty and ADC System Performance 71 70 Ain 5MHz 69 68 Ain 10MHz 67 66 65 SNR dBFS Ap 20MHz 64 63 62 Ap 32MHz 61 60 01 05 09 13 17 21 25 29 33 37 11 15 19 23 27 341 35 39 RMS CLOCK JITTER ps Figure 8 SNR vs Jitter REV 0 AD10465 Power Supplies Care should be taken when selecting a power source Linear supplies are strongly recommended Switching supplies tend to have radiated components that may be received by the AD10465 Each of the power supply pins should be decoupled as closely to the package as possible using 0 1 uF chip capacitors The AD10465 has separate digital and analog power supply pins The analog supplies are denoted and the digital supply pins are denoted
6. 53 AGNDB 18 TOP VIEW 52 ENCODEB D4A 19 Not to Scale 51 ENCODEB 20 50 DVcc D6A 21 19 D13B MSBB 22 48 0128 23 D11B D9A 24 ae 0108 D10A 25 45 098 D13A MSBA amp DOB LSBB REV 0 5 AD10465 Typical Performance Characteristics dB dB 100 110 120 130 120 130 130 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 20 0 22 5 25 0 27 5 30 0 32 5 FREQUENCY MHz TPC 1 Single Tone 5 MHz ENCODE 65MSPS 20MHz 1dBFS 5 5 NR 70 71 FDR 79 73dB illl hae be 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 20 0 22 5 25 0 27 5 30 0 32 5 PTT Lei di FREQUENCY MHz TPC 2 Single Tone 20 MHz 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 20 0 22 5 25 0 27 5 30 0 32 5 FREQUENCY MHz TPC 3 Single Tone 32 MHz dB 100 110 120 fF 130 100 110 120 130 100 dBc a 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 20 0 22 5 25 0 27 5 30 0 32 5 FREQUENCY MHz TPC 4 Single Tone 10 MHz TPC 5 Single Tone 25 MHz T THER
7. 08 G D HD40M 6 L6 L11 47 uH Inductor 47 100 MHz 20 IND2 Fair Rite 2743019447 IND2 2 U7 U9 IC Differential Receiver SOIC 8 Motorola MC10EP16D MCIOEPI6D 6 C22 C50 C52 C53 C59 C62 10 Capacitor 10 UF 20 16 V dc 1812POL Kemet T491C106M016A57280 POLCAP 1812 4 R99 R100 R123 R124 000 Resistor 0 0 0805 6 0 00 52 0805 2 R140 R141 33 000 Q Resistor 33 000 Q 5 0 10 Watt 0805 Panasonic ERJ 6GEY 333V RES2 0805 8 R76 R79 R82 510 Resistor 51 5 0 10 Watt 0805 Panasonic ERJ 6GEYJ510V RES2 0805 RES 0805 R83 R98 R118 R119 R137 36 R89 R94 R95 100 Q Resistor 100 Q 5 0 10 Watt 0805 Panasonic ERJ 6GEYJ101V RES2 0805 RES 0805 R97 R101 R117 R120 R122 R125 R136 8 J2 J6 J8 Connector SMA Female St Johnson Components 142 0701 201 SMA 16 718 J20 J22 REV 0 15 AD10465 00000000000000000000 00000000000000000000 090000000000009000000 00000000000000000000 o 29 06 00 o o 9 a o o o ooo 5 090 9 O0 9900000900000900000000 99000000000000000000 99000000000000000000 690000000000000000000 00000000000000000000 990000900000000000000 o00000000000000006000 oo0000000000000000000 ooo0090000000000000000 9000 0000000000000000 0000000000000000 Figure 10a Top Layer Cop
8. MSB D13B MSB C58 0128 0128 0 1pF 10pF D11B D11B D10B D10B A D9B D9B DGNDB m m m DGNDB Evaluation Board 12 REV 0 C42 OJP11 J6 O1pF ENCODEA R82 C44 AGNDA 510 0 1 C40 C49 J18 0 0 1pF ENCODEA C ENCA R83 AGNDA 510 8 7 Teal MC10EP16D E AGNDA AGNDA NC NO CONNECT AGNDA AGNDA C43 C37 OJP12 J16 0 1pF OPEN ENCODEB R76 C48 AGNDB 7510 ENCB C39 C46 J17 0 0 1pF ENCODEB R79 AGNDB 510 MC10EP16D NC NO CONNECT AGNDB AGNDB AGNDAB AGNDB Figure 9c Evaluation Board REV 0 13 AD10465 AD10465 OUT_3 3VDA OUT_3 3VDA C14 C15 DGNDA BANANA JACKS FOR GNDS AND PWRS LSB DOA R1002 R99 DIA 00 p2A D3A D4A D5A DGNDA D6A D7A D8A D9A ES D10A D11A D12A MSB D13A NWO gt OO NOU RAONS AGNDA DGNDB AGNDB DGNDA OUT_3 3VDA C25 DGNDB E87 E159 19 88 160 ie E89 E72 E162 E161 E139 E140 E163 E167 17 E143 E141 E164 E168 16 E146 E142 E165 E169 15 E148 E144 E166 E170 14 E149 E145 E171 E178 13 E152 E147 E172 E180 12 E153 E150 E177 E182 BUFLATB 11 E184 E151 E179 E183 R135 E188 E154 E181 E191 D7
9. V All specifications guaranteed within 100 ms of initial power up regardless of sequencing Specifications subject to change without notice REV 0 3 AD10465 ABSOLUTE MAXIMUM RATINGS TEST LEVEL Parameter Min Max Units I 100 Production Tested ELECTRICAL 100 Production Tested at 25 C and sample tested at Voltage 0 7 specified temperatures AC testing done on sample basis Ver Voltage 7 0 Sample Tested only Analog Input Voltage Vm IV Parameter is guaranteed by design and characterization Analog Input Current 10 10 mA testing Digital Input Voltage ENCODE 0 IV ENCODE ENCODE Differential Voltage 4 v V Parameter is a typical value only Digital Output Current 10 10 mA VI 100 production tested at temperature at 25 C sample ENVIRONMENTAL tested at temperature extremes Operating Temperature Case 40 85 9 Maximum Junction Temperature 174 9 Lead Temperature Soldering 10 sec 300 C Storage Temperature Range Ambient 65 150 NOTES Absolute maximum ratings are limiting values applied individually and beyond which the serviceability of the circuit may be impaired Functional operability is not necessarily implied Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability Typical thermal impedance for ES package 2 22C W 24 3 C W ORDERING GUIDE Model Te
10. matching and performance while still maintaining excellent isolation and providing for significant board area savings The AD10465 operates with 5 0 V for the analog signal condi tioning with a separate 5 0 V supply for the analog to digital conversion and 3 3 V digital supply for the output stage Each channel is completely independent allowing operation with independent encode and analog inputs The AD10465 also offers the user a choice of analog input signal ranges to fur ther minimize additional external signal conditioning while still remaining general purpose The AD10465 is packaged in 68 lead Ceramic Gull Wing package footprint compatible with the earlier generation AD10242 12 bit 40 MSPS and AD10265 12 bit 65 MSPS Manufac turing is done on Analog Devices Inc Mil 38534 Qualified Manufacturers Line QML and components are available up to Class H 40 C to 85 C The AD6644 internal components are manufactured on Analog Devices Inc high speed comple mentary bipolar process XFCB PRODUCT HIGHLIGHTS 1 Guaranteed sample rate of 65 MSPS 2 Input amplitude options user configurable 3 Input signal conditioning included both channels matched for gain 4 Fully tested characterized performance 5 Footprint compatible family 68 lead LCC FUNCTIONAL BLOCK DIAGRAM 2 1 REF_A D9A pioa 69 69 REV 0 Information furnished Analog Devices is believed
11. 00 00000000000000000000 a 00000000000000000000 000000000000000090000 00000 9000 9009000000000 oe e Figure 10 Fourth Layer Copper 17 REV 0 AD10465 e e ITE a 00000000000000090000 4 999090 Siia TING o Oc 30 36 90 9 D E 0000000000000000000 2909005990099005644589 Figure 10 Fifth Layer Copper p 0000000000 0000000000000 00000000000000000000 990000000000099000000 REV 0 Figure 10f Bottom Layer Copper 18 AD10465 5505741 4 BOTTOM SOLOER MASK 65603741 A BOTTOM SILKSCREEN 2503741 BOTTOM ASSEMBLY Figure 10h Bottom Assembly REV 0 19 AD10465 OUTLINE DIMENSIONS Dimensions shown in inches and mm 68 Lead Ceramic Leaded Chip Carrier ES 68A 1 180 29 97 SQ 0 950 24 13 SQ 0 240 6 096 0 060 01 52 TOP VIEW PINS DOWN 20 REV 0 02356 4 5 1 01 0 PRINTED IN U S A
12. 2288 14336 16384 TPC 11 Integral Nonlinearity 40 C 25 C 85 C 5 10 19 32 Apn MHz TPC 12 SNR vs Frequency AD10465 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency as determined by the FFT analysis is reduced by 3 dB Aperture Delay The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled Aperture Uncertainty Jitter The sample to sample variation in aperture delay Differential Nonlinearity The deviation of any code from an ideal 1 LSB step Encode Pulsewidth Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance pulsewidth low is the minimum time ENCODE pulse should be left in low state At a given clock rate these specs define an acceptable Encode duty cycle Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit Maximum Conversion Rate The e
13. B 1000 19 E189 E185 E186 E192 D8B 9 E190 E194 E187 E193 D9B 8 E195 E196 E207 E208 D10B 7 E197 E198 E209 E210 DB 6 E199 E200 E211 E212 Diog 5 E201 E202 E213 E214 SB sans 4 E203 E204 E215 E216 MSB 4 E205 E206 E217 E218 E224 E223 E219 E220 2 E226 E225 E221 E222 1 E227 E228 E229 E230 DGNDA AGNDA Edo E45 E233 E234 DGNDB AGNDB DGNDB DGNDB Figure 9d Evaluation Board 14 REV 0 AD10465 Bill of Materials List for AD10465 Evaluation Board Reference Manufacturer and Component Qty Designator Value Description Part Number Name 2 U2 U4 IC Low Voltage Quad 2 Input Nand SOIC 14 Toshiba TC74LCX00FN 74LCX00M 2 U21 U22 IC 16 Bit Transparent Latch with Three State Fairchild 74LCX163743MTD 74LCX163743MTD Outputs TSSOP 48 1 UI DUT IC 14 Bit Analog to Digital Converter ADI AD10465AZ ADI AD10465AZ 2 U6 U8 IC Voltage Regulator 3 3 V RT 6 Analog Devices ADP3330ART 3 ADP3330 3 RLT 10 10 Banana Jack Socket Johnson Components 08 0740 001 Banana Hole 22 13 15 0 1 uF Capacitor 0 1 20 12 V dc 0805 Mena GRM40X7R104K025BL CAP 0805 C20 C21 C23 C27 C37 C39 C40 C42 C44 C46 C48 C49 C57 C61 C63 C64 2 C38 C41 0 47 uF Capacitor 0 47 uF 5 12 V dc 1206 Vitramon VJ1206U474MFXMB CAP 1206 2 C43 C45 100 pF Capacitor 100 pF 10 12 V dc 0805 Johansen 500R15N101 V4 CAP 0805 2 J3 J4 Connector 40 pin Header Male St Samtec TSW 120
14. II 5 6 70 78 dBFS Analog Input 32 1 MHz 25 C I 4 62 68 dBFS Full II 5 6 60 66 dBFS TWO TONE IMD REJECTION fw 10 MHz and 11 MHz 25 C I 4 78 87 dBFS f and f are 7 dB II 5 6 78 fw 31 MHz and 32 MHz 25 C I 4 68 70 dBFS f and f Are 7 dB Full II 5 6 60 CHANNEL TO CHANNEL ISOLATION 25 C IV 12 90 dB TRANSIENT RESPONSE 25 C 15 3 ns OVERVOLTAGE RECOVERY TIME VIN 2 0 x fs Full IV 12 40 100 ns VIN 4 0 x fs Full IV 12 150 200 ns DIGITAL OUTPUTS Logic Compatibility CMOS DVcc 3 3 V Logic 1 Voltage Full I 1 2 3 2 5 DVcc 0 2 Logic 0 Voltage Full I 1 2 3 0 2 0 5 DVcc 5V Logic 1 Voltage Full DVcc 0 3 V Logic 0 Voltage Full 0 35 Output Coding Two s Complement POWER SUPPLY AVcc Supply Voltage Full VI 4 85 5 0 5 25 I AVcc Current Full I 270 308 mA Supply Voltage Full VI 5 25 5 0 475 V I AVgg Current Full V 38 49 mA Supply Voltage Full VI 3 135 33 3 465 V I Current Full 30 46 mA Total Supply Current per Channel Full I 1 2 3 338 403 mA Power Dissipation Total Full I 1 2 3 3 5 3 9 W Power Supply Rejection Ratio PSRR Full 0 02 Passband Ripple to 10 MHz 0 1 dB Passband Ripple to 25 MHz 0 2 dB NOTES 1 Gain tests are performed on Ay input voltage range Input Capacitance spec combines AD8037 die capacitance and ceramic package capacitance 3 Full power bandwidth is the freque
15. Voltage nominally 5 0 26 27 DGNDA A Channel Digital Ground 15 25 31 33 DOA D13A Digital Outputs for ADC A DO LSB 28 ENCODEA ENCODE is complement of ENCODE 29 ENCODEA Data conversion initiated on rising edge of ENCODE input 30 DVcc Digital Positive Supply Voltage nominally 5 0 V 3 3 V 43 44 DGNDB B Channel Digital Ground 34 42 45 49 DOB D13B Digital Outputs for ADC B DO LSB 53 54 57 61 65 68 AGNDB B Channel Analog Ground A and B grounds should be connected as close to the device as possible 50 DVcc Digital Positive Supply Voltage nominally 5 0 V 3 3 V 51 ENCODEB Data conversion initiated on rising edge of ENCODE input 52 ENCODEB ENCODE is complement of ENCODE 55 DRBOUT Data Ready B Output 56 B Channel Internal Voltage Reference 62 ApB1 Analog Input for side ADC nominally 0 5 63 2 Analog Input for B side ADC nominally 1 0 V 64 3 Analog Input for side ADC nominally 2 0 V 66 AVcc Analog Positive Supply Voltage nominally 5 0 V 67 Analog Negative Supply Voltage nominally 5 0 V 5 2 V PIN CONFIGURATION 68 Lead Ceramic Leaded Chip Carrier uo AA agana 5112563526026 22265 1 lt 1 lt lt lt 0 lt lt 4 lt lt lt lt lt es 65 64 63 ez 61 AGNDA 10 60 AGNDB AGNDA 11 IDENTIFIER 59 AGNDB DRAOUT 12 58 AGNDB 13 AGNDB AVcc 14 56 REF B DOA LSBA ts 55 DRBOUT D1A 6 54 AGNDB D2A AD10465
16. ck Schottky diodes across the transformer secondary limit clock excursions into the AD10465 to approximately 0 8 V p p differential This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD10465 and limits the noise presented to the ENCODE inputs A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor typically 100 Q is placed in the series with the primary 0 1nF 1 CLOCK SOURCE Figure 6 Crystal Clock Oscillator Differential Encode 1000 T1 4T HSMS2812 DIODES If a low jitter ECL PECL clock is available another option is to ac couple a differential ECL PECL signal to the encode input pins as shown below A device that offers excellent jitter perfor mance is the MC100LVEL16 or same family from Motorola 10 VT ECL PECL AD10465 VT Figure 7 Differential ECL for Encode Jitter Considerations The signal to noise ratio SNR for an ADC can be predicted When normalized to ADC codes Equation 1 accurately predicts the SNR based on three terms These are jitter average DNL error and thermal noise Each of these terms contributes to the noise within the converter l e DN SNR 20 x log 2x n X x ty rms 2 RMS 2 1 2 1 faNaLoG analog input frequency ty RMS rms jitter of the encode rms sum of encode source and internal encode circuitry
17. dwidth Full 100 MHz ENCODE INPUT ENC Differential Input Voltage Full IV 0 4 V p p Differential Input Resistance 25 C 10 Differential Input Capacitance 25 C 2 5 SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 4 5 6 65 MSPS Minimum Conversion Rate Full V 12 20 MSPS Aperture Delay t4 25 C 1 5 ns Aperture Delay Matching 25 C IV 12 250 500 ps Aperture Uncertainty Jitter 25 C 0 3 ps rms ENCODE Pulsewidth High 25 C IV 12 6 2 TU 9 2 ns ENCODE Pulsewidth Low 25 C IV 12 6 2 7 7 9 2 ns Output Delay top Full 6 8 ns Encode Rising to Data Ready Rising Delay pr Full 11 5 ns SNR Analog Input 4 98 MHz 25 C 70 dBFS Analog Input 9 9 MHz 25 C I 4 69 70 dBFS Full II 5 6 68 70 dBFS Analog Input 19 5 MHz 25 C 4 68 70 dBFS Full II 5 6 67 70 dBFS Analog Input 32 1 MHz 25 C I 4 67 69 dBFS Full II 5 6 67 69 dBFS SINAD Analog Input 4 98 MHz 25 C 70 Analog Input 9 9 MHz 25 C I 4 67 5 69 dB Full II 5 6 67 5 69 dB Analog Input 19 5 MHz 25 C 4 65 68 dB Full II 5 6 65 68 dB Analog Input 32 1 MHz 25 C I 4 60 63 dB Full II 5 6 58 61 dB 2 REV 0 AD10465 Test Mil AD10465AZ BZ QML H Parameter Temp Level Subgroup Min Typ Max Unit SPURIOUS FREE DYNAMIC RANGE Analog Input 4 98 MHz 25 C 85 dBFS Analog Input 9 9 MHz 25 C I 4 73 82 dBFS Full II 5 6 70 82 dBFS Analog Input 19 5 MHz 25 C I 4 72 78 dBFS Full
18. e converter to achieve 0 03 accu racy when a one half full scale step function is applied to the analog input Two Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product reported in dBFS N 3 Figure 1 Timing Diagram REV 0 AD10465 2000 2 1000 AD8037 1000 Figure 2 Analog Input Stage Figure 3 ENCODE Inputs THEORY OF OPERATION The AD10465 is a high dynamic range 14 bit 65 MHz pipeline delay three pipelines analog to digital converter The custom analog input section maintains the same input ranges 1 V p p 2 V and 4 and input impedance 100 200 and 400 Q as the AD10242 The AD10465 employs four monolithic ADI components per channel AD8037 AD8138 AD8031 and AD6644 along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 14 bit analog to digital converter The input signal is passed through a precision laser trimmed resistor divider allowing the user to externally select operation with a full scale signal of 0 5 V 1 0 V or 2 0 V by choosing the proper input terminal for the application The AD10465 analog input includes an AD8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifiers inputs and outputs The AD8037 amplifier provides a high in
19. mperature Range Package Description AD10465AZ 259 to 85 C Case 68 Lead Ceramic Leaded Chip Carrier AD10465BZ 40 C to 85 C Case 68 Lead Ceramic Leaded Chip Carrier 5962 9961601 40 C to 85 C Case 68 Lead Ceramic Leaded Chip Carrier AD10465 PCB 25 C Evaluation Board with AD10465AZ CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although WARNING the AD10465 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE 4 REV 0 AD10465 PIN FUNCTION DESCRIPTIONS Pin No Name Function 1 SHIELD Internal Ground Shield between channels 2 4 5 9 11 AGNDA A Channel Analog Ground A and B grounds should be connected as close to the device as possible 3 A Channel Internal Voltage Reference 6 Analog Input for A side ADC nominally 0 5 7 2 Analog Input for side ADC nominally 1 0 V 8 ApA3 Analog Input for A side ADC nominally 2 0 V 12 DRAOUT Data Ready A Output 13 Analog Negative Supply Voltage nominally 5 0 V 5 2 V 14 Analog Positive Supply
20. ncode rate at which parametric testing is performed above which converter performance may degrade Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels Overvoltage Recovery Time The amount of time required for the converter to recover to 0 02 accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage Signal to Noise and Distortion SINAD The ratio of the rms signal amplitude set at 1 dB below full scale to the rms value of the sum of all other spectral compo nents including harmonics but excluding dc May be reported in dB i e relative to signal level or in dBFS always related back to converter full scale Signal to Noise Ratio without Harmonics The ratio of the rms signal amplitude set at 1 dB below full scale to the rms value of the sum of all other spectral compo nents excluding the first five harmonics and dc May be reported in dB i e relative to signal level or in dBFS always related back to converter full scale Spurious Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component The peak spurious compo nent may or may not be a harmonic Transient Response The time required for th
21. ncy at which the spectral power of the fundamental frequency as determined by FFT analysis is reduced by 3 dB 4 ac specifications tested by driving ENCODE and ENCODE differentially gt Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50 5 6 Analog input signal power at 1 dBFS signal to noise ratio SNR is the ratio of signal level to total noise first five harmonics removed Encode 65 MSPS SNR is reported in dBFS related back to converter full power 7 Analog input signal power at 1 dBFS signal to noise and distortion SINAD is the ratio of signal level to total noise harmonics Encode 65 MSPS 8 Analog input signal power swept from 1 dBFS 60 dBFS SFDR is ratio of converter full scale to worst spur 9 Both input tones at 7 dBFS two tone intermodulation distortion IMD rejection is the ratio of either tone to the worst third order intermod product 19 Channel to channel isolation tested with A channel grounded and a full scale signal applied to channel Input driven to 2x and 4x 1 range for gt four clock cycles Output recovers inband in specified time with Encode 65 MSPS 12 Digital output logic levels 3 3 V 10 pF Capacitive loads gt 10 pF will degrade performance 13 Supply voltage recommended operating range may be varied from 4 85 V to 5 25 V However rated ac harmonics performance is valid only over the range AVcc 5 0 V to 5 25
22. open 75 when is shorted to GND 50 Q when 2 is shorted to GND 2 200 when Aj is open Am2 100 when is shorted to GND Am2 75 when 2 to Am3 has an external resistor of 300 with Am3 shorted to GND Am2 50 when 2 to Am3 has an external resistor of 100 with Am3 shorted to GND Am 400 Q Am3 100 when Ap has an external resistor of 133 to GND Am3 75 when has an external resistor of 92 Q to GND Am3 50 when Am3 has an external resistor of 57 Q to GND APPLYING THE AD10465 Encoding the AD10465 The AD10465 encode signal must be a high quality extremely low phase noise source to prevent degradation of performance Maintaining 14 bit accuracy places a premium on encode clock phase noise SNR performance can easily degrade by 3 dB to 4 dB with 32 MHz input signals when using a high jitter clock source See Analog Devices Application Note AN 501 Aper ture Uncertainty and ADC System Performance for complete details For optimum performance the AD10465 must be clocked differentially The encode signal is usually ac coupled into the ENCODE and ENCODE pins via a transformer or capacitors These pins are biased internally and require no additional bias Shown below is one preferred method for clocking the AD10465 The clock source low jitter is converted from single ended to differential using an RF transformer The back to ba
23. per 00000000000900000000 D 900000 00000000090000000000 990990 00000000000000 00000000000000 7 mr o 9 9 9 9 9 99 9 995 oo oo 9 9 o o 0 9 9 00 e 9 oo eo 00000000000000000000 0 0000000000000000000 0 0 0 0 00000000000000 00000000000000000000 joO000000000000000000Q Figure 10b Second Layer Copper REV 0 16 AD10465 20000000000000000000 990000090000000000000 90000000000000000000 9 5 o 930 2 9 amp 90000000000000000000 990000000000000000000 09 0 Figure 10c Third Layer Copper 5 o 00000000000000000000 00000000000000000000 00000000000000000000 60255 2 9 gt oo 99 OO OO s o Q o x 00000000000000000000 oocooocoooogooooocoooooG 900000090000000000000 0 0 0000000000000000 O00000000000000000000 oo00090000000000000
24. put impedance and gain for driving the AD8138 in a single ended to differential amplifier configu ration The AD8138 has 3 dB bandwidth at 300 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier The AD8138 differential outputs help balance the differential inputs to the AD6644 maximizing the performance of the ADC The AD8031 provides the buffer for the internal reference of the AD6644 The internal reference voltage of the AD6644 is designed to track the offsets and drifts of the ADC and is used to ensure matching over an extended temperature range of operation The reference voltage is connected to the output common mode input on the AD8138 The AD6644 reference voltage sets the output common mode on the AD8138 at 2 4 V which is the midsupply level for the AD6644 The AD6644 has complementary analog input pins AIN and AIN Each analog input is centered at 2 4 V and should swing 0 55 V around this reference Since AIN and AIN are 180 degrees out of phase the differential analog input signal is 2 2 V peak to peak Both analog inputs are buffered prior to the first track and hold REV 0 DVcc CURRENT MIRROR a Figure 4 Digital Output Stage DVcc CURRENT MIRROR Figure 5 Digital Output Stage THI The high state of the ENCODE pulse places in hold mode The held value of TH1 is applied to the input of a 5 bit coarse ADCI The digital output of ADCI drive
25. s 14 bits of precision which is achieved through laser trimming The output of is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal TH2 provides an analog pipeline delay to compensate for the digital delay of ADCI The first residue signal is applied to a second conversion stage consisting of a 5 bit ADC2 5 bit DAC2 and pipeline TH4 The second DAC requires 10 bits of precision which is met by the process with no trim The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4 T H5 drives a final 6 bit ADC3 The digital outputs from ADC1 ADC2 and ADC3 are added together and corrected in the digital error correction logic to generate the final output data The result is a 14 bit parallel digital CMOS compatible word coded as two s complement USING THE FLEXIBLE INPUT The AD10465 has been designed with the user s ease of opera tion in mind Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance While the standard inputs are 0 5 V 1 0 V and 2 0 V the user can select the input impedance of the AD10465 AD10465 on any input by using the other inputs as alternate locations for GND or an external resistor The following chart summarizes the impedance options available at each input location Am1 100 when Am2 and Am3 are
26. s is connected via banana jacks The analog supply powers the associated components and the analog section of the AD10465 The digital outputs of the AD10465 are powered via banana jacks with 3 3 V Contact the factory if additional layout or applications assistance is required c 9 CL CL 00000000000009 99000008908996 434 4010465 GR 010265 Eval Test Board 6503468 RevZ2 Figure 9a Evaluation Board Mechanical Layout REV 0 11 AD10465 5 CLKLATCHB2 CLKLATCHB1 mE JP3 DRBOUT DRAOUT 1 Pe CLKLATCHA1 AGNDB j s J7 CLKLATCHA2 o o AGNDA AT i AGNDA AGNDA DRAOUT DRAOUT AGNDA 5 2 45VAA 45VAA DOA DOA LSB 17 DIA DIA D2A D2A C53 470 D3A D3A 10pF 7 100MHz D4A D4A D5A D5A D6A D6A D7A D7A D8B D9A D10A D8B D9A D10A DGNDA 3 3VDA D13A MSB DOB LSB 54 25 44 Srrrmaa DGNDA 98 0004 e a L11 43 3VDA 662 47 C63 10 T 0 1pF DGNDA DGNDA Figure 9b AD10465 LATCHB BUFLATB 74LCX00M 741 74 74LCXOO0M 741 00 741 00 BUFLATA LATCHA 470 100 2 AGNDB AGNDB AGNDB AGNDB REFB DRBOUT AGNDB AGNDB ENCBB ENCB 3 3VDB C61 DRBOUT AGNDB ENCBB ENCB DUT_3 3VDB D13B
27. to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices AD10465 A nB3 2 1 D12A D13A MSB DOB LSB D1B D2B D3B D5B D6B D7B One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2001 AD 1 046 5 SPEC CATI 0 NS AVec 5 V 5 V 3 3 V applies to each ADC unless otherwise noted Test Mil AD10465AZ BZ QML H Parameter Temp Level Subgroup Min Typ Max Unit RESOLUTION 14 Bits DC ACCURACY No Missing Codes Full VI 1 2 3 Guaranteed Offset Error 25 C I 1 2 2 50 02 2 2 FS Full VI 2 3 2 2 1 0 2 2 FS Offset Error Channel Match Full 1 51 0 1 Gain Error 25 C I 1 3 1 0 1 FS Full VI 2 3 5 32 0 5 FS Gain Error Channel Match 25 C I 1 1 5 50 5 1 5 I 2 3 51 0 3 Min I 3 5 5 ANALOG INPUT Input Voltage Range Anl Full 0 5 Am2 Full V 1 0 Am Full V t2 V Input Resistance 1 Full IV 12 99 100 101 Q Am2 Full IV 12 198 200 202 Q Am3 Full IV 12 396 400 404 Q Input Capacitance 25 C IV 12 0 4 0 7 0 pF Analog Input Ban
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ANALOG DEVICES AD10465 Dual Channel 14 Bit 65 MSPS A/D Converter with Analog Input Signal Conditioni