ANALOG DEVICES 10-Bit 65/80/105 MSPS 3 V A/D Converter AD9214 handbook
Contents
1. 4 Adot ano 0007 aro dWVA 2 2 VOST div 22 aan 9 XON 8 xoa 5 7 053 lt 951 AISIN3SSV LV SIHL 4 16 w e xea J NYY dO 100 EME ano ano ed BE Ja incl ano 0022 T G ano 281 151 39143A DLSLATWL gemma le 203 1 2212 m 1 2 2 2 ans 2 5 ano sza JEME ae 5 5 7 Sa 22222 xed one SEd gsw 22222551 6 9 xia ita EE 5 ano 228 7 oe 2 z 85 9r 0022 VeLSLATbZ QNS PLSLATL vn Figure 51 TSSOP Evaluation Board Digital Path Rev A Page 27 of 36 AD9215 050 820 I I I I TYNOILdO VLVd va LYTI 8TH ANY 8 H SHOISIS3H 24 YOLSISSY SAOWSY 3 31LV9 OML 40135 AV I3Q 31V9 T SMOHS DILVW3HOS ONISSVdAd LNA PAR 3 iT00 0 L arro 619 98X9 v4 sn gt SNISSVdA amp SN 31170070 3 0 31170070 153 084 ATOA 669 969 069 MISA aNd 8 2 SNISSVdA8 IDA 953 653 ano 009 02. 009 092 ys 00 xu xu HOVLLV 304 dNLAS 31v9 0ML SMOHS XONA 98XOAVL 0 868 zu ASN 19341A V 4 82H 3SN v uod SLNSWLSNCAY 2012 Avot 92 dWVA SNISSVdA8 SNISSVdA8 TV1I9Iq SNISSVdA8 9O1VNV SNISSVdA8 1 ano Anz WTO 0 rito A or vT 69 9 569 g Ji j Figure 43 LFCSP Evaluation Board Schematic Clock Input Rev A Page 21 of 36 AD9215 9 C O Figure 44 LFCSP Evaluation Board Layout Primary Side Figure 45 LFCSP Evaluation Board Layout Secondary Side Rev A Page 22 of 36 AD9215 02874 A 044 02874 A 045 Figure 46 LFCSP Evaluation Board Layout Ground Plane Figure 47 LFCSP Evaluation Board Layout Power Plane Rev A Page 23 of 36 AD9215 LVO N V 1820 99 K IM XT 83 9 0 7 820 Srz60v Cl 2002 45 08 LC260Y CI 2 300243 5951590 9260 O SOAM o 545409 s z6qv o 54580222 61260 O Quvog 1VA3 33N01S09 NI SOTYNY 300 3SN3S Figure 49 LFCSP Eva
3. 33 5 03 Revision 0 Initial Version Rev A Page 2 of 36 SPECIFICATIONS AD9215 AVDD 3 V DRVDD 2 5 V specified maximum conversion rate 2 V differential input 1 0 V internal reference unless otherwise noted Table 1 DC Specifications Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity DNL Integral Nonlinearity INL TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage 1 V Mode INTERNAL VOLTAGE REFERENCE Output Voltage Error 1 V Mode Load Regulation 1 0 mA Output Voltage Error 0 5 V Mode Load Regulation 0 5 mA INPUT REFERRED NOISE VREF 0 5 V VREF 1 0 V ANALOG INPUT Input Span VREF 0 5 V Input Span VREF 1 0 V Input Capacitance REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current lAVDD lorvop PSRR POWER CONSUMPTION Sine Wave Input lavon Standby Power With a 1 0 V internal reference Test Temp Level Full Full Full Full Full Full Full Full Full 25 C 25 C Full Full Full Full Full Full Full 25 C Full Full 25 C 25 C lt AD9215BRU 65 AD9215BCP 65 AD9215BRU 80 AD9215BCP 80 AD9215BRU 105 AD9215BCP 105 Min Typ Max 10 Guaranteed 0 3 2 0 0 1 5 4 0 0 5 1 0 0 5 1 2 15 30 230 2 35 0 2 1 0 2 0 8 0 4 NIN N 2 7 3 0 3 3 2 25 25
4. Ja 5 E vee NIV Xva sr T HAND 1 2 zz 2 aaraa ve 5 v QNS OAT OL aanv 6 8 1 2 xea xao w L asw THO yeu ar 0 69 41170 SOW 1d 2 d 982 50754 506 1 1 9T T 83 v3 NOILV33dO LNdNI Q3QN3 319NIS 0022 ie ee o i _ sito za 519 1 w w 2 2 2 2 8 1 lt lt 21 gt 5 2 5 2 8 Z 2 88 22 1 r 1 m m QN9 o 2001 o o 127272 7 65866608685 I IV NOILdO M 5 5 13 93 153135 AT 3 3 8 AS 0 TV NHBLNI G 3 338 3 9 AT 9 NO 250921 3 3338 39V L 10A TVNH3LX3 V AAO 56504923 NOILVYNSIANOD 193135 IAOW AD9215 NOILVYNSISANOSD 39N3H3H3H Figure 50 TSSOPP Evaluation Board Schematic Analog Inputs and DUT Rev A Page 26 of 36 AD9215 8 8 092 3 9 ano 8 39143A Ted g Woo Ha any 3 9 tvo
5. 3a02N3 S M ASN 19840 V 458 ASN AGOONA 43 3331 8 v SNISSVdA amp 8 vien 20 T 429 T SNISSVdAS8 LNG aNd aNd QN9 3122 L anot L 422 L 31122 il ss QGAHG X19A Figure 52 TSSOP Evaluation Board Schematic Clock Input Rev A Page 28 of 36 AD9215 02874 051 02874 053 02874 052 02874 054 Figure 54 TSSOP Evaluation Board Layout Secondary Side Figure 56 TSSOP Evaluation Board Layout Power Plane Rev A Page 29 of 36 AD9215 090000000000000000000 e TE E 9 199 zee 11 2 e ma e EN 2 65455 i 90 99 m mug 99 30 i 99 8 am m 4 e e e e e Figure 57 TSSOP Evaluation Board Layout Primary Silkscreen Figure 58 TSSOP Evaluation Board Layout Secondary Silkscreen Rev A Page 30 of 36 02874 A 056 Table 11 TSSOP Evaluation Board Bill of Materials BOM AD9215 Recommended Item Qty Omit Reference Designator Device Package Value Vendor Part No 1 11 C2 to C4 C10 C20 Tantalum Capacitor TAJD 10 uF C25 C27 C29 C47 C50 C52 C47 2 2 C5 C8 Chip Capacitor 0603 10 pF 1 C31 3 1
6. dB dB dB 80 2 p p SFDR dBc 0 5dBFS 75 70 1V p p SFDR dBc 65 60 I 2V p p SNR dB 55 F 1V p p SNR dB 50 5 15 25 35 45 55 65 75 85 ENCODE MSPS Figure 12 AD9215 80 SNR SFDR vs fsamete 10 3 MHz 80 29 SFDR dBc AIN 0 5dBFS 75 70 1V p p SFDR dBc 65 60 p p SNR dB 55 50 5 15 25 35 45 55 65 ENCODE MSPS Figure 13 AD9215 65 SNR SFDR vs fsamete fiw 10 3 MHz 85 2V p p SFDR 80H 75 70 65 60 55 0 20 40 60 80 100 MSPS Figure 14 AD9215 105 SNR SFDR vs fsamete 10 3 MHz 02874 A 012 02874 A 013 02874 A 066 dB dB dB 80 70 60 50 80dB REFERENCE LINE 1V p p SFDR dBc 40 30 2V p p SNR dB 20 1V p p SNR dB 2V dBc 10 0 50 45 40 35 30 25 20 15 ANALOG INPUT LEVEL 10 5 0 Figure 15 AD9215 80 SNR SFDR vs Analog Input Drive Level fsaupie 80 MSPS fin 39 1 MHz 80 70 2 SFDR dBc 60 50 40 70dBFS REFERENCE LINE 30 20 40 30 20 ANALOG INPUT LEVEL dBFS Figure 16 AD9215 105 SNR SFDR vs Analog Input Drive Level fsaupe 105 MSPS fin 50 3 MHz 80 1V p p SFDR dBc 70 60 80dB REFERENCE LINE 50 2V p p SNR dB 40 30 1V p p SNR d
7. dB dB dB dB Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc MHz AD9215 Table 3 Digital Specifications AD9215BRU 65 AD9215BRU 80 AD9215BRU 105 AD9215BCP 65 AD9215BCP 80 AD9215BCP 105 Test Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS CLK PDWN High Level Input Voltage Full IV 2 0 2 0 2 0 V Low Level Input Voltage Full IV 0 8 0 8 0 8 V High Level Input Current Full IV 650 10 650 10 650 10 HA Low Level Input Current Full IV 70 10 70 10 70 10 HA Input Capacitance Full V 2 2 2 pF LOGIC OUTPUTS DRVDD 2 5 V High Level Output Voltage Full IV 2 45 2 45 2 45 V Low Level Output Voltage Full IV 0 05 0 05 0 05 V 1 Output voltage levels measured with a 5 pF load on each output Table 4 Switching Specifications AD9215BRU 65 AD9215BRU 80 AD9215BRU 105 AD9215BCP 65 AD9215BCP 80 AD9215BCP 105 Unit Parameter Min Typ Max Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS Maximum Conversion Rate 65 MSPS Minimum Conversion Rate MSPS CLOCK Period ns DATA OUTPUT PARAMETERS Output Delay top Full VI 2 5 4 8 6 5 2 5 4 8 6 5 2 5 4 8 6 5 ns Pipeline Delay Latency Full V 5 5 5 Cycles Aperture Delay 25 C V 24 24 24 ns Aperture Uncertainty Jitter 25 C V 0 5 0 5 0 5 ps rms Wake Up Time 25C V 7 7 7 ms OUT OF RANGE RECOVERY TIME 25 C V 1 1 1 Cycles ANALOG INPUT
8. fin Nyquist fin 70 MHz fin 100 MHz WORST OTHER Excluding Second or Third fin 2 4 MHz fin Nyquist fin 70 MHz fin 100 MHz TWO TONE SFDR AIN 7 dBFS fin 70 3 MHz 71 3 MHz fini 100 3 MHz fiy 101 3 MHz ANALOG BANDWIDTH Tested at fin 35 MHz for AD9215 65 fin 39 MHz for AD9215 80 and fin 50 MHz for AD9215 105 Temp Full 25 C Full 25 C 25 C 25 C Full 25 C Full 25 C 25 C 25 C Full 25 C Full 25 C 25 C 25 C Full 25 C Full 25 C 25 C 25 C Full 25 C Full 25 C 25 C 25 C 25 C 25 C 25 C Test Level Vi V VI VI Min Typ Max 56 0 58 5 57 0 59 0 56 0 58 0 565 58 5 55 8 58 5 565 59 0 558 58 0 56 3 58 5 9 1 9 5 92 96 9 1 9 4 9 1 9 5 78 64 80 65 77 64 78 65 77 67 78 68 77 67 78 68 300 Rev A Page 4 of 36 Min 56 0 57 0 56 0 56 5 55 7 56 8 55 5 56 3 9 0 9 3 9 0 9 0 Typ 58 5 59 0 58 0 58 5 58 0 57 5 58 5 58 5 58 0 58 5 56 0 55 5 9 5 9 5 9 4 9 5 9 1 9 0 78 80 76 78 70 70 77 77 77 77 80 80 75 74 300 65 63 Min 56 6 56 4 56 5 56 1 9 2 9 1 Typ 57 5 58 5 57 5 58 0 57 8 57 7 57 6 58 2 57 3 57 8 57 7 574 9 3 9 5 9 4 9 4 9 4 9 3 300 Max 70 61 66 63 Unit dB dB dB dB dB dB dB dB
9. 2V p p V 1 V p p V 59 0 Complement 09 1023 1 000 0 500 111111 1111 01 1111 1111 512 0 0 10 0000 0000 00 0000 0000 511 0 00195 0 000978 0111111111 1111111111 0 1 00 0 5000 00 0000 0000 10 0000 0000 High speed high resolution ADCs are sensitive to the quality of the clock input The degradation in SNR at a given full scale input frequency due only to aperture jitter ta can be calculated with the following equation SNR Degradation 20 x logio 2 x x ta In the equation the rms aperture jitter represents the root sum square of all jitter sources which include the clock input analog input signal and ADC aperture jitter specification Undersampling applications are particularly sensitive to jitter The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9215 Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise Low jitter crystal controlled oscillators make the best clock sources If the clock is generated from another type of source by gating dividing or other meth ods it should be retimed by the original clock at the last step Power Dissipation and Standby Mode As shown in Figure 35 the power dissipated by the AD9215 is proportional to its sample rate The digital power dissipation does
10. A Page 18 of 36 AD9215 AAO 5 135440 OL S SOG ANVNIS 135440 6 OL S 6 0 ano SOG LNAW31d NOD SOML Z OLS WT OIT V LV QHVOS NO AAO SOgQILN3W31dNWOO SOML OL S oza gu 318v33G10S IQON QN9 AV 319NIS Eod sinis 3 38 AS 0 IWNUZLNI 3 e 3 33 TVNH3LX3 2 OL 3 935 l d L1nv43q 338 TVN331NI 8 OL 3 Uee O ginoyx ano M3GIAIG 39V L10A 1VNH3LX3 V OL 3 STH 318V33G10S 3SN3S OMT v 19 2 su 1 0 a Ka 103135 14 ZL TVNOLLdO ano Doce XILT l I l 999929209 T1HO 4 2 3 935 TNR mami TE 55552656 ador O AGENT 5 EF 9 NS T 3 2 1MI LLOV Tare v 1937135 30 aN ote Xsq AW ST NIA vy X99 9T T NIA 68 NIA 25 zN anov az sa 22 OT ONT 153 oz 92H 050 sa To 99 i Tr ano AA eae sj Xuo ano arto stot 22
11. CP 32 Dimensions shown in millimeters Rev A Page 33 of 36 AD9215 ORDERING GUIDE Model Temperature Range Package Description Package Option AD9215BRU 65 40 C to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD9215BRU 80 40 C to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD9215BRU 105 40 C to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD9215BRURL7 65 40 C to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD9215BRURL7 80 40 C to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD9215BRURL7 105 40 C to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD9215BRU 65EB AD9215BRU 65 Evaluation Board TSSOP RU 28 AD9215BRU 80EB AD9215BRU 80 Evaluation Board TSSOP RU 28 AD9215BRU 105EB AD9215BRU 105 Evaluation Board TSSOP RU 28 AD9215BCP 65 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP CP 32 AD9215BCP 80 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP CP 32 AD9215BCP 105 40 C 85 C 32 Lead Lead Frame Chip Scale Package LFCSP CP 32 AD9215BCPZ 65 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP CP 32 AD9215BCPZ 80 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP CP 32 AD9215BCPZ 105 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP CP 32 AD9215BCP 65EB AD9215BCP 65 Evaluation Board LFCSP CP 32 AD9215BCP 80EB AD9215BCP 80 Eval
12. Pin Configurations and Function Descriptions 7 Equivalent Circuits 4 treten ee i 8 Definitions of Specifications a 8 Typical Performance Characteristics sss 10 Applying the AD9215 Theory of 14 Clock Input and Considerations sss 15 Evaluation Board tute etu etes 18 Outline Dimensions need 33 Ordering Guide 5 anii teste Rat e 34 REVISION HISTORY 2 04 Data Sheet Changed from a REV 0 to a REV Renumbered Figures and UNIVERSAL Changes to Product Title seen 1 1 Changes to Product Description sse 1 Changes to Product Highlights sse 1 Changes to Specifications sse 2 Changes to Figure yy 4 Changes to Figures 9 to 11 sse 10 Added Figure 14 iced ete eedem pe 10 Added Figures 16 and 18 sse 1 Changes to Figures 21 to 24 and 25 to 26 12 Deleted Figure 25i emet eti ae eret 12 Changes to Figures 28 and 29 sse 13 Chan ges to Figure 3 RR 14 Changes tO Figure RR ORI 16 Changes to Figures 50 through 58 sss 26 Added Table TT 31 Updated Outline Dimensions 32 Changes to Ordering Guide
13. 0 25 0 75 1 25 1 75 2 25 2 75 ANALOG INPUT COMMON MODE VOLTAGE V Figure 31 AD9215 105 SNR SFDR vs Common Mode Voltage For best dynamic performance the source impedances driving VIN and VIN should be matched such that common mode settling errors are symmetrical These errors are reduced by the common mode rejection of the ADC An internal differential reference buffer creates positive and negative reference voltages REFT and REFB respectively that define the span of the ADC core The output common mode of the reference buffer is set to midsupply and the REFT and REFB voltages and span are defined as REFT 1 2 AVDD VREF REFB 1 2 AVDD VREF Span 2 REFT REFB 2 x VREF It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and by definition the input span is twice the value of the VREF voltage The internal voltage reference can be pin strapped to fixed val ues of 0 5 V or 1 0 V or adjusted within the same range as dis cussed in the Internal Reference Connection section Maximum Rev A Page 14 of 36 SNR performance is achieved with the AD9215 set to the largest input span of 2 V p p The relative SNR degradation is 3 dB when changing from 2 V p p mode to 1 V p p mode The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference volt age The minimum and maximum common mode inp
14. 105 Two Tone SFDR vs Ain 70 1 MHz and fw 71 1 MHz fsamece 105 MSPS 02874 068 Figure 24 AD9215 80 Two Tone SFDR vs 100 3 MHz and Rev A Page 12 of 36 dB dB 80dBFS REFERENCE LINE 0 60 55 50 45 40 35 30 25 20 15 10 5 Ain dBFS 101 3 MHz 105 MSPS SFDR DCS ON DCS OFF 20 30 40 50 60 70 80 CLOCK DUTY CYCLE HIGH Figure 25 SINAD SFDR vs Clock Duty Cycle 105 MSPS fin 50 3 MH 40 20 0 20 40 60 80 TEMPERATURE C Figure 26 SINAD SFDR vs Temperature 105 MSPS fin 50 MHz 02874 A 073 02874 A 069 02874 A 070 GAIN ERROR ppm C o N 30 02874 025 40 40 20 0 20 40 60 80 TEMPERATURE C Figure 27 Gain vs Temperature External 1 V Reference 0 5 0 4 0 1 DNL LSB 0 1 02874 A 064 Figure 28 AD9215 105 Typical DNL fsamece 105 MSPS fin 2 3 MHz AD9215 INL LSB 02874 A 074 128 256 384 512 640 768 896 1024 CODE Figure 29 AD9215 105 Typical INL 105 MSPS 2 3 MHz Rev A Page 13 of 36 AD9215 APPLYING THE AD9215 THEORY OF OPERATION The AD9215 architecture consists o
15. 3 6 32 35 7 0 0 1 96 18 1 0 Min Typ Max Guaranteed 0 3 2 0 1 5 4 0 0 5 1 0 0 5 1 2 NIN N 2 7 3 0 3 3 2 25 25 3 6 34 5 39 8 6 0 1 104 20 1 0 2 Measured at fin 2 4 MHz full scale sine wave with approximately 5 pF loading on each output bit 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND Refer to Figure 5 for the equivalent analog input structure Standby power is measured with a dc input the CLK pin inactive i e set to AVDD or AGND Rev A Page 3 of 36 Min Unit Bits Guaranteed 30 3 2 0 FSR 41 5 4 0 FSR 10 0 6 41 2 LSB 0 65 1 2 LSB ppm C ppm C ppm C LSB rms LSB rms 2 7 3 0 3 3 225 2 5 3 6 40 44 AD9215 AVDD 3 V DRVDD 2 5 V specified maximum conversion rate 2 V differential input 1 0 V internal reference AIN 0 5 dBFS MODE AVDD 3 duty cycle stabilizer DCS enabled unless otherwise noted Table 2 AC Specifications AD9215BRU 65 AD9215BCP 65 AD9215BRU 80 AD9215BCP 80 AD9215BRU 105 AD9215BCP 105 Parameter SIGNAL TO NOISE RATIO SNR fin 2 4 MHz fin Nyquist fin 70 MHz fin 100 MHz SIGNAL TO NOISE AND DISTORTION SINAD fin 2 4 MHz fin Nyquist fin 70 MHz fin 100 MHz EFFECTIVE NUMBER OF BITS ENOB fin 2 4 MHz fin Nyquist fin 70 MHz fin 100 MHz WORST HARMONIC Second or Third fin 2 4 MHz
16. 4 A 008 Figure 8 Equivalent Digital Input Circuit DEFINITIONS OF SPECIFICATIONS Aperture Delay Aperture delay is a measure of the sample and hold amplifier SHA performance and is measured from the rising edge of the clock input to when the input signal is held for conversion Aperture Jitter Aperture jitter is the variation in aperture delay for successive samples and can be manifested as frequency dependent noise on the input to the ADC Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated per formance Pulse width low is the minimum time the clock pulse should be left in the low state At a given clock rate these speci fications define an acceptable clock duty cycle Differential Nonlinearity DNL No Missing Codes An ideal ADC exhibits code transitions that are exactly 1 LSB apart DNL is the deviation from this ideal value Guaranteed no missing codes to 10 bit resolution indicate that all 1024 codes respectively must be present over all operating ranges Effective Number of Bits ENOB For a sine wave SINAD can be expressed in terms of the num ber of bits Using the following formula it is possible to obtain a measure of performance expressed as N the effective number of bits N SINAD 1 76 6 02 Thus the effective number of bits for a device for sine wave inputs at a given input frequency can be ca
17. 4 Fairchild 74VCX86M 30 1 U6 High Speed Amplifier SOMB10 Analog Devices Inc AD8351ARM 31 2 J1 93 SMB Connecter SMBP 1 J4 32 2 1 P2 Power Connector PTMICRO4 Weiland 25 531 3425 0 Posts 25 602 5453 0 Top 33 26 E1 E5 E2 E3 E4 E8 Headers Jumper Blocks TSW 120 07 G S E9 E11 E6 E7 E16 E17 SMT 100 BK G E19 E22 E18 E23 E21 20 E35 E51 E36 E50 E43 E53 E44 E52 34 12 E24 E27 E25 E26 E28 E29 Wirehole E13 E14 E30 E12 E32 E45 Rev A Page 32 of 36 AD9215 OUTLINE DIMENSIONS 6 40 BSC II 0 20 1 0 0 60 le COPLANARITY 0 19 SEATING 0 09 0 60 0 10 PLANE 0 45 COMPLIANT TO JEDEC STANDARDS MO 153AE Figure 59 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 Dimensions shown in millimeters 0 60 MAX PIN 1 INDICATOR PIN1 INDICATOR 0 50 t LO TOP ese BS 9 25 VIEW 3 10 SQ 2 95 0 50 1 0 40 30 0 25 ee 3 50 REF 12 MAX 065 e 0 65 TYP 0 05 MAX 1 00 0 02 Nom 0 85 0 30 0 80 0 23 0 20 REF 0 08 SEATING 018 PLANE NoTE COMPLIANT TO JEDEC STANDARDS MO 220 VHHD 2 IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE THERE IS AN INCREASED RELIABILITY OF THE SOLDER JOINTS AND THE MAXIMUM THERMAL CAPABILITY OF THE PACKAGE IS ACHIEVED WITH THE EXPOSED PADDLE SOLDERED TO THE CUSTOMER BOARD Figure 60 32 Lead Lead Frame Chip Scale Package LFCSP
18. 5 C6 C9 C13 Chip Capacitor 0603 0 1 uF C15 to C18 C21 C24 C26 C30 C32 C34 C36 C40 C46 C48 C51 4 3 C12 C14 C23 C28 Chip Capacitor 0603 Select 5 8 C7 C19 C35 C19 Chip Capacitor 0603 0 001 uF C37 to C39 C49 6 6 C1 C33 C41 to C42 BCAP0402 0402 0 1 uF C44 to C5 7 1 C43 BCAP0402 0402 0 001 uF 8 1 C11 BCAP0603 0603 Select 9 11 R2 R8 to R11 R24 BRES603 0603A 1 R26 R29 R39 R41 to R45 2 R48 R49 10 4 R6 R25 R34 R37 BRES603 0603A 00 8 R5 R35 R17 to R18 R27 to R28 R38 R52 11 2 R7 R40 BRES603 0603A 500 1 R14 12 2 R19 R21 BRES603 0603A 330 13 2 R32 R33 50603 0603A 360 14 1 R16 BRES603 0603 Select 15 2 R4 R15 BRES603 0603 10 16 4 R20 R22 to R23 R47 BRES603 0603A Select 17 2 R48 R49 BRES603 0603 1 18 4 R36 R46 R50 to R51 BRES603 0603 250 19 1 R31 BRES603 0603 1000 20 1 R30 BRES603 0603 1 2 21 1 R3 BRES603 0603 5 22 1 R1 Potentiometer RJ24FW 10 23 4 RP1 to RP4 Resister Pack 220 742C163221 Rev A Page 31 of 36 AD9215 Recommended Item Qty Omit Reference Designator Device Package Value Vendor Part No 24 1 L1 Chip Inductor 0603 10 nH Coilcraft 0603CS 10NXGBU 25 1 T1 1 1 RF Transformer CD542 Mini Circuits AWT1 1T 26 1 U1 ADC 28TSSOP Analog Devices Inc AD9215 27 1 U2 Right Angle 40 Pin Header Samtec TSW 120 08 T D RA 28 2 U3 U4 Octal D Type Flip Flop Fairchild 74LVT57MSA 29 1 U5 Quad XOR Gate 501
19. B 20 2N p p SFDR dBc 10 0 50 45 40 35 30 25 20 15 ANALOG INPUT LEVEL 10 5 0 Figure 17 AD9215 65 SNR SFDR vs Analog Input Drive Level fsaupie 65 MSPS fin 30 3 MHz 02874 A 014 02874 A 067 02874 A 015 Rev A Page 11 of 36 dB dB 80 75 70 65 60 55 50 AD9215 o Figure 18 AD9215 105 SNR SFDR vs 100 150 FREQUENCY MHz 200 250 fin Ain 0 5 dBFS 105 MSPS 02874 A 072 2V p p SFDR dBc 2V p p SNR dB 80 Figure 19 AD9215 80 SNR SFDR vs fin Ain 0 5 dBFS FsampLe 80 MSPS fin MHz 02874 A 016 75 2V p p SFDR dBc 70 65 60 2V p p SNR dB 55 50 50 Figure 20 AD9215 65 SNR SFDR vs fin Ain 0 5 dBFS 65 MSPS 100 150 ANALOG INPUT MHz 200 250 02874 A 017 300 AD9215 dB Aina Am2 7dBFS SFDR 744 02874 A 060 0 13 125 26 250 39 375 52 500 FREQUENCY MHz Figure 21 Two Tone 32k FFT with 70 1 MHz and 71 1 MHz fsamere 105 MSPS A1 A2 7dBFS SFDR 744 02874 A 061 0 13 125 26 250 39 375 52 500 FREQUENCY MHz Figure 22 Two Tone 32k FFT with fiw 100 3 MHz and 101 3 MHz fsampte 105 MSPS AIN1 AIN2 dBFS Figure 23 AD9215
20. CLK DATA OUT 02874 A 002 Figure 2 Timing Diagram Output delay is measured from CLK 5096 transition to DATA 5096 transition with 5 pF load on each output 2 Wake up time is dependent on the value of decoupling capacitors typical values shown with 0 1 uF and 10 capacitors and REFB Rev A Page 5 of 36 AD9215 ABSOLUTE MAXIMUM RATINGS ables EXPLANATION OF TEST LEVELS With 1 Mnemonic Respectto Min Unit Test Leve ELECTRICAL I 100 production tested AVDD AGND 03 39 V DRVDD DRGND 03 39 V 100 production tested at 25 C and sample tested at AGND DRGND 03 403 V specified temperatures AVDD DRVDD 39 39 Digital Outputs DRGND 03 DRVDD 03 Vv HI Sample tested only CLK MODE AGND 03 AVDD 0 3 V IV Parameter is guaranteed by design and characterization VIN VIN AGND 03 AVDD 03 v testing VREF AGND 03 AVDD 0 3 V SENSE AGND 03 AVDD 0 3 V V Parameter is a typical value only REFB REFT AGND 03 AVDD 0 3 V VI Acti d d by des 4 PDWN AGND 03 AVDD 03 A pese Me 55 M 7 esign ENVIRONMENTAL characterization testing for industrial temperature range 100 production tested at temperature extremes for mili Operating Temperature 40 85 C tary devices Junction Temperature 150 Lead Temperature 10 sec 300 C Storage Temperature 65 150 C NOTES Absolute maximum ratings are limiting values to be applied individually and
21. ER TES RAR EXEHSRA ARAM MVR ANALOG DEVICES 10 Bit 65 80 105 MSPS 3 V A D Converter FEATURES Single 3 V supply operation 2 7 V to 3 3 V SNR 58 dBc to Nyquist SFDR 77 dBc to Nyquist Low power ADC core 96 mW at 65 MSPS 104 mW 80 MSPS 120 mW at 105 MSPS Differential input with 300 MHz bandwidth On chip reference and sample and hold amplifier DNL 0 25 LSB Flexible analog input 1 V p p to 2 V p p range Offset binary or twos complement data format Clock duty cycle stabilizer APPLICATIONS Ultrasound equipment IF sampling in communications receivers Battery powered instruments Hand held scopemeters Low cost digital oscilloscopes PRODUCT DESCRIPTION The AD9215 is a family of monolithic single 3 V supply 10 bit 65 80 105 MSPS analog to digital converters ADC This family features a high performance sample and hold amplifier SHA and voltage reference The AD9215 uses a multistage differential pipelined architecture with output error correction logic to pro vide 10 bit accuracy at 105 MSPS data rates and to guarantee no missing codes over the full operating temperature range The wide bandwidth truly differential sample and hold ampli fier SHA allows for a variety of user selectable input ranges and offsets including single ended applications It is suitable for multiplexed systems that switch full scale voltage levels in successive channels an
22. N pin high the AD9215 is placed in standby mode In this state the ADC typically dissipates 1 mW if the CLK and analog inputs are static During standby the output drivers are placed in a high impedance state Reasserting the PDWN pin low returns the AD9215 into its normal opera tional mode Rev A Page 16 of 36 In standby mode low power dissipation is achieved by shutting down the reference reference buffer and biasing networks The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation As a result the wake up time is related to the time spent in standby mode and shorter standby cycles result in proportionally shorter wake up times With the recommended 0 1 uF and 10 decoupling capacitors on REFT and REFB it takes approximately one second to fully discharge the reference buffer decoupling capacitors and 7 ms to restore full operation Digital Outputs The AD9215 output drivers can be configured to interface with 2 5 V or 3 3 V logic families by matching DRVDD to the digital supply of the interfaced logic The output drivers are sized to provide sufficient output current to drive a wide variety of logic families However large drive currents tend to cause current glitches on the supplies that may affect converter performance Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or la
23. T1 T1 Mini Circuits 18 1 U1 74LVTH162374 CMOS TSSOP 48 Register 19 1 U4 AD9215BCP ADC DUT CSP 32 Analog Devices Inc 20 1 U5 74VCX86M SOIC 14 Fairchild 21 1 PCB AD9XXBCP PCB PCB Analog Devices Inc 22 1 U3 AD8351 Op Amp MSOP 8 Analog Devices Inc 23 1 T2 MACOM Transformer 1 1 13 1 1TX MACOM ETC1 1 13 24 5 R9 R1 R2 R38 R39 Chip Resistor 0603 Select 25 3 R18 R14 R35 Chip Resistor 0603 250 26 2 R40 R41 Chip Resistor 0603 10kQ 27 1 R34 Chip Resistor 1 2 28 1 R33 Chip Resistor 1100 These items are included in the PCB design but are omitted at assembly Rev A Page 25 of 36 HOLIDVdVO 213 OL 15 3951 20 38 3553 14 SvO V v 820 GOW 63 ano O NOlLVH3dO Q30N3 319NIS EZI 69 ZU NOILV33dO dO 2 T3 72 ano NOLLVHSdO TVILN3H344Id HO 9H T LNdNISOTWNY 225 OT OAT OAT 6zH 50 5 4 851 Use ae 096 XZON 7 gr ador 99 ETT Y 9 ONG ano s xoa 1 I a 7 woo 7 BT 2939 NIV ano 49 31110070 6r OT s 19 509 v
24. VIEW 20 D9 MSB DNC 6 Not to Scale 19 D8 DNC 7 18 D7 DNC 8 17 D6 LSB DO 9 D1 10 D211 D3 12 D413 D5 14 DRGND 15 DRVDD 16 DNC DO NOT CONNECT Figure 4 LFCSP CP 32 02874 A 004 TSSOP Pin No LFCSP Pin No Mnemonic Description 1 21 OR Out of Range Indicator 2 22 MODE Data Format and Clock Duty Cycle Stabilizer DCS Mode Selection 3 23 SENSE Reference Mode Selection 4 24 VREF Voltage Reference Input Output 5 25 REFB Differential Reference Negative 6 26 REFT Differential Reference Positive 7 12 27 32 AVDD Analog Power Supply 8 11 28 31 AGND Analog Ground 9 29 VIN Analog Input Pin 10 30 Analog Input Pin 13 2 CLK Clock Input Pin 14 4 PDWN Power Down Function Selection Active High 15 to 16 1 3 5to8 DNC Do not connect recommend floating this pin 17 to 22 9 to 14 DO LSB to Data Output Bits 25 to 28 17 to 20 D9 MSB 23 15 DRGND Digital Output Ground 24 16 DRVDD Digital Output Driver Supply Must be decoupled to DRGND with a minimum 0 1 uF capacitor Recommended decoupling is 0 1 uF in parallel with 10 pF Rev A Page 7 of 36 AD9215 EQUIVALENT CIRCUITS AVDD MODE 02874 A 005 Figure 5 Equivalent Analog Input Circuit AVDD MODE 20 02874 006 Figure 6 Equivalent MODE Input Circuit DRVDD 9 02874 007 Figure 7 Equivalent Digital Output Circuit AVDD CLK 0287
25. beyond which the serviceability of the circuit may be impaired Functional operability is not necessarily implied Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability Typical thermal impedances 28 lead TSSOP 67 7 C W 32 lead LFCSP 32 7 C W heat sink soldered down to ground plane ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Spr Aat electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance DEVICE degradation or loss of functionality Rev A Page 6 of 36 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 28 D9 MSB MODE 2 D8 SENSE 3 26 D7 VREF 4 25 D AvpD 7 VIEW Not to Scale 22 AGND 8 21 VIN 20 D3 19 D2 AGND 18 D1 12 DO LSB 13 16 DNC 02874 A 003 DNC DO NOT CONNECT Figure 3 TSSOP RU 28 Table 6 Pin Function Descriptions 82 a gt lt lt d oo 30 VIN 29 VIN 28 AGND 27 AVDD 26 REFT 25 REFB AD9215 DNC 1 24 VREF CLK 2 23 SENSE DNC 3 22 MODE PDWN 4 AD9215 210R DNC 5 TOP
26. d for sampling single channel inputs at frequencies well beyond the Nyquist rate Combined with power and cost savings over previously available ADCs the AD9215 is suitable for applications in communications imag ing and medical ultrasound A single ended clock input is used to control all internal conversion cycles A duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent performance The digital output data is presented in straight binary or twos complement for mats An out of range signal indicates an overflow condition which can be used with the MSB to determine low or high overflow Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD gt 6 DC CORE ADC CORE VIN REFT AD9215 REFB CORRECTION LOGIC OUTPUT BUFFERS ET OR 5 D9 MSB VREF O pe CLOCK DUTY CYCLE SENSE STABLIZER i AGND CLK PDWN MODE amp Figure 1 Fabricated on an advanced CMOS proce
27. f a front end SHA followed by a pipelined switched capacitor ADC Each stage provides sufficient overlap to correct for flash errors in the preceding stages The quantized outputs from each stage are combined into a final 10 bit result in the digital correction logic The pipe lined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples Sampling occurs on the rising edge of the clock The input stage contains a differential SHA that can be config ured as ac coupled or dc coupled in differential or single ended modes Each stage of the pipeline excluding the last consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier MDAC The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipe line Redundancy is used in each one of the stages to facilitate digital correction of flash errors The output staging block aligns the data carries out the error correction and passes the data to the output buffers The output buffers are powered from a separate supply allowing adjust ment of the output voltage swing During power down the output buffers go into a high impedance state Analog Input and Reference Overview The analog input to the AD9215 is a differential switched capacitor SHA that has been designed for optimum perform ance while processi
28. lculated directly from its measured SINAD Gain Error The first code transition should occur at an analog value 1 2 LSB above negative full scale The last transition should occur at an analog value 1 1 2 LSB below the positive full scale Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions Integral Nonlinearity INL INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale The point used as negative full scale occurs 1 2 LSB before the first code transition Positive full scale is defined as a level 1 1 2 LSB beyond the last code transition The deviation is measured from the middle of each particular code to the true straight line Maximum Conversion Rate The clock rate at which parametric testing is performed Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit Offset Error The major carry transition should occur for an analog value 1 2 LSB below VIN VIN Zero error is defined as the deviation of the actual transition from that point Out of Range Recovery Time Out of range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10 above positive full scale to 10 above negative full scale or f
29. lement Table 9 Mode Selection MODE Voltage Data Format Duty Cycle Stabilizer AVDD Twos Complement Disabled 2 3 AVDD Twos Complement Enabled 1 3 AVDD Offset Binary Enabled AGND Default Offset Binary Disabled The MODE pin is internally pulled down to AGND by a 20 resistor EVALUATION BOARD The AD9215 evaluation board provides all of the support cir cuitry required to operate the ADC in its various modes and configurations The converter can be driven differentially through an AD8351 driver a transformer or single ended Separate power pins are provided to isolate the DUT from the support circuitry Each input configuration can be selected by proper connection of various jumpers refer to the schematics Figure 40 shows the typical bench characterization setup used to evaluate the ac performance of the AD9215 It is critical that signal sources with very low phase noise 1 ps rms jitter be used to realize the ultimate performance of the converter Proper filtering of the input signal to remove harmonics and lower the integrated noise at the input is also necessary to achieve the specified noise performance Complete schematics and layout plots follow that demonstrate the proper routing and grounding techniques that should be applied at the system level AVDD GND DRVDD GND Vp DATA AD9215 CAPTURE EVALUATION BOARD AND PROCESSING 02874 038 Figure 40 Evaluation Board Connections Rev
30. luation Board Layout Secondary Silkscreen Figure 48 LFCSP Evaluation Board Layout Primary Silkscreen Rev A Page 24 of 36 AD9215 Table 10 LFCSP Evaluation Board Bill of Materials BOM Recommended Vendor Item Qty Omit Reference Designator Device Package Value Part Number 1 18 C1 C5 C7 C8 CO C11 Chip Capacitor 0603 0 1 uF C12 C13 C15 C16 C31 C33 C34 C36 C37 C41 C43 C47 8 C6 C18 C27 C17 C28 C35 C45 C44 2 8 C2 C3 C4 C10 Tantalum Capacitor TAJD 10 uF C20 C22 C25 C29 2 C46 C24 3 8 C14 C30 C32 C38 Chip Capacitor 0603 0 001 C39 C40 C48 C49 uF 4 1 C19 Chip Capacitor 0603 10 pF 2 C21 C23 5 1 C26 Chip Capacitor 0603 10 pF 6 9 E31 E35 E43 E44 Header EHOLE Jumper Blocks E50 E51 E52 E53 2 E1 E45 7 2 11 12 SMA Connector 50 SMA 8 1 L1 Inductor 0603 10 nH Coilcraft 0603CS 10NXGBU 9 1 P2 Terminal Block TB6 Wieland 25 602 2653 0 5 530 0625 0 10 12 Header Dual 20 Pin RT HEADER40 Digi Key S2131 20 ND Angle 11 5 R3 R12 R23 R18 RX Chip Resistor 0603 00 6 R37 R22 R42 R16 R17 R27 12 2 R4 R15 Chip Resistor 0603 330 13 14 R5 R6 R7 R8 R13 R20 R21 R24 Chip Resistor 0603 10 R25 R26 R30 R31 R32 R36 14 2 R10 R11 Chip Resistor 0603 360 15 1 R29 Chip Resistor 0603 500 1 R19 16 2 RP1 RR2 Resistor Pack R_742 2200 Digi Key CTS 742C163220JTR 17 1 ADT1 1WT AW
31. mance of the AD9215 This is especially true in IF undersampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled For these applications differ ential transformer coupling is the recommended input configura tion The value ofthe shunt capacitor is dependant on the input frequency and source impedance and should be reduced or re moved An example of this is shown in Figure 33 AD9215 02874 A 031 Figure 33 Differential Transformer Coupled Configuration The signal characteristics must be considered when selecting a transformer Most RF transformers saturate at frequencies below a few MHz and excessive signal power can also cause core saturation which leads to distortion Single Ended Input Configuration A single ended input may provide adequate performance in cost sensitive applications In this configuration there is a deg radation in SFDR and distortion performance due to the large input common mode swing However if the source impedances on each input are kept matched there should be little effect on SNR performance Figure 34 details a typical single ended input configuration 10 2 p p 49 90 0 1 1kO 02874 A 032 Figure 34 Single Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and as a result may be sensi tive to clock duty cycle Commonly a 596 tolerance is re
32. mperature drift Figure 39 shows the typical drift characteris tics of the internal reference in both 1 V and 0 5 V modes 0 6 0 5 e 96 o 02874 A 037 40 20 0 20 40 60 80 TEMPERATURE C Figure 39 Typical VREF Drift When the SENSE pin is tied to AVDD the internal reference is disabled allowing the use of an external reference An internal reference buffer loads the external reference with an equivalent 7 load The internal buffer still generates the positive and REFIN R AND S SMG 2V p p BAND PASS SIGNAL SYNTHESIZER FILTER 10MHz R AND S SNG 2V p p REFOUT SIGNAL SYNTHESIZER negative full scale references REFT and REFB for the ADC core The input span is always twice the value of the reference voltage therefore the external reference must be limited to a maximum of 1 V Operational Mode Selection As discussed earlier the AD9215 can output data in either offset binary or twos complement format There is also a provision for enabling or disabling the clock duty cycle stabilizer DCS The MODE pin is a multilevel input that controls the data format and DCS state For best ac performance enabling the duty cycle stabilizer is recommended for all applications The input threshold values and corresponding mode selections are out lined in Table 9 As detailed in Table 9 the data format can be selected for either offset binary or twos comp
33. ng a differential input signal The SHA input can support a wide common mode range and maintain excel lent performance as shown in Figure 31 An input common mode voltage of midsupply minimizes signal dependent errors and provides optimum performance VIN VIN 02874 A 028 Figure 30 Switched Capacitor SHA Input The clock signal alternatively switches the SHA between sample mode and hold mode see Figure 30 When the SHA is switched into sample mode the signal source must be capable of charging the sample capacitors and settling within one half of a clock cycle A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source Also a small shunt capacitor can be placed across the inputs to provide dynamic charging currents This passive network creates a low pass filter at the ADC s in put therefore the precise values are dependent upon the appli cation In IF undersampling applications any shunt capacitors should be removed In combination with the driving source impedance they would limit the input bandwidth The analog inputs of the AD9215 are not internally dc biased In ac coupled applications the user must provide this bias ex ternally AVDD 2 is recommended for optimum per formance but the device functions over a wider range with rea sonable performance see Figure 31 dB 02874 A 071
34. not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit The maximum DRVDD current can be calculated as Iprvpp Vorvpp X X where N is the number of output bits 10 in the case of the AD9215 This maximum current is for the condition of every output bit switching on every clock cycle which can only occur for a full scale square wave at the Nyquist frequency 2 In practice the DRVDD current is established by the average num ber of output bits switching which are determined by the encode rate and the characteristics of the analog input signal Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers The data in Figure 35 was taken with a 5 pF load on each output driver 40 15 09215 105 lAvDD 13 e 35 AD9215 65 80 11 lavpp mA IpRvDD 30 E 7 25 5 3 20 1 5 15 25 35 45 55 65 15 85 95 105 MSPS 02874 A 075 1 Figure 35 Supply Current vs for fN 10 3 MHz The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency By asserting the PDW
35. one SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component The peak spurious component may or may not be an IMD product It may be reported in dBc i e degrades as signal levels are lowered or in dBFS always related back to converter full scale Rev A Page 9 of 36 AD9215 TYPICAL PERFORMANCE CHARACTERISTICS AVDD 3 0 V DRVDD 2 5 V with DCS enabled 25 C 2 V differential input Am 0 5 dBFS VREF 1 0 V unless otherwise noted 0 Ain 0 5dBFS SNR 58 0 20 ENOB 9 4 BITS SFDR 75 5dB AMPLITUDE dBFS 1 100 E diis Mida Mau ua 6 56 13 13 19 69 26 25 32 81 39 38 45 94 52 50 FREQUENCY MHz 02874 A 062 Figure 9 Single Tone 32k FFT with 10 3 MHZ 105 MSPS 0 0 5dBFS SNR 57 8 20 ENOB 9 4 BITS SFDR 75 0dB AMPLITUDE dBFS 02874 063 0 0 656 1313 1969 2625 3281 3938 4594 525 FREQUENCY MHz Figure 10 Single Tone 32k FFT with fin 70 3 MHz fsaunie 105 MSPS 0 Ain 0 5dBFS SNR 57 7 20 ENOB 9 3 BITS SFDR 75dB AMPLITUDE dBFS EMEN 100 55 48 41 41 44 0 6 56 13 13 1969 2625 32 81 39 38 45 94 52 50 FREQUENCY MHz 02874 A 065 Figure 11 Single Tone 32k FFT with fiw 100 3 MHz fsamece 105 MSPS Rev A Page 10 of 36
36. quired on the clock duty cycle to maintain dynamic performance char acteristics The AD9215 contains a clock duty cycle stabilizer that retimes the nonsampling edge providing an internal clock signal with a nominal 5096 duty cycle This allows a wide range of dock input duty cycles without affecting the performance of the AD9215 As shown in Figure 25 noise and distortion per formance are nearly flat over a 50 range of duty cycle For best ac performance enabling the duty cycle stabilizer is recom mended for all applications The duty cycle stabilizer uses a delay locked loop DLL to cre ate the nonsampling edge As a result any changes to the sam pling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate Rev A Page 15 of 36 AD9215 Table 7 Reference Configuration Summary External SENSE Internal Op Amp Resulting VREF Resulting Differential Span Selected Mode Connection Configuration V V p p Externally Supplied Reference AVDD N A N A 2 x External Reference Internal 0 5 V Reference VREF Voltage Follower G 1 0 5 1 0 Programmed Variable External Divider Noninverting 1 lt G lt 2 0 5 1 R2 R1 2x VREF Reference Internally Programmed 1 V AGND to 0 2 V Internal Divider 1 0 2 0 Reference Table 8 Digital Output Coding Code VIN Input Span VIN VIN Input Span Digital Output Offset Binary Digital Output Twos
37. rom 10 below negative full scale to 10 below positive full scale Output Propagation Delay The delay between the clock logic threshold and the time when Rev A Page 8 of 36 all bits are within valid logic levels Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit Signal to Noise and Distortion SINAD Ratio SINAD is the ratio of the rms value of the measured input sig nal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for SINAD is expressed in decibels Signal to Noise Ratio SNR SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency excluding the first six harmonics and dc The value for SNR is expressed in decibels AD9215 Spurious Free Dynamic Range SFDR SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal Temperature Drift The temperature drift for zero error and gain error specifies the maximum change from the initial 25 C value to the value at Tum or Tmax Total Harmonic Distortion THD THD is the ratio of the rms sum of the first six harmonic com ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels Two T
38. s shown in Figure 37 the switch is again set to the SENSE pin This puts the reference amplifier in a noninverting mode with the VREF output defined as AD9215 R2 VREF 0 5x 1 RI 10uF AD9215 02874 A 034 Figure 36 Internal Reference Configuration In all reference configurations REFT and REFB drive the ADC conversion core and establish its input span The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference 10uF AD9215 02874 A 035 Figure 37 Programmable Reference Configuration If the internal reference of the AD9215 is used to drive multiple converters to improve gain matching the loading of the refer ence by the other converters must be considered Figure 38 de picts how the internal reference voltage is affected by loading Rev A Page 17 of 36 AD9215 0 10 VREF ERROR 96 0 15 0 20 02874 036 0 0 5 1 0 1 5 2 0 2 5 3 0 lLoAp Figure 38 VREF Accuracy vs Load External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac teristics When multiple ADCs track one another a single refer ence internal or external may be necessary to reduce gain matching errors to an acceptable level A high precision external reference may also be selected to provide lower gain and offset te
39. ss the AD9215 is avail able in both a 28 lead surface mount plastic package and a 32 lead chip scale package and is specified over the industrial temperature range of 40 C to 85 C PRODUCT HIGHLIGHTS 1 The AD9215 operates from a single 3 V power supply and features a separate digital output driver supply to accom modate 2 5 V and 3 3 V logic families 2 Operating at 105 MSPS the AD9215 core ADC consumes alow 120 mW at 80 MSPS the power dissipation is 104 mW and at 65 MSPS the power dissipation is 96 mW 3 The patented SHA input maintains excellent performance for input frequencies up to 200 MHz and can be config ured for single ended or differential operation 4 The AD9215 is part of several pin compatible 10 12 and 14 bit low power ADCs This allows a simplified upgrade from 10 bits to 12 bits for systems up to 80 MSPS 5 The clock duty cycle stabilizer maintains converter per formance over a wide range of clock pulse widths 6 The out of range OR output bit indicates when the signal is beyond the selected input range One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved AD9215 TABLE OF CONTENTS hs 3 Absolute Maximum Ratings eee 6 Explanation of Test Levels sse 6 ESD Caution 6
40. tches Timing The AD9215 provides latched data outputs with a pipeline delay of five clock cycles Data outputs are available one propagation delay top after the rising edge of the clock signal Refer to Figure 2 for a detailed timing diagram The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9215 these transients can detract from the converter s dynamic per formance The lowest typical conversion rate of the AD9215 is 5 MSPS At clock rates below 5 MSPS dynamic performance may degrade Voltage Reference A stable and accurate 0 5 V voltage reference is built into the AD9215 The input range can be adjusted by varying the refer ence voltage applied to the AD9215 using either the internal reference or an externally applied reference voltage The input span of the ADC tracks reference voltage changes linearly Internal Reference Connection A comparator within the AD9215 detects the potential at the SENSE pin and configures the reference into four possible states which are summarized in Table 1 If SENSE is grounded the reference amplifier switch is connected to the internal resis tor divider see Figure 36 setting VREF to 1 V Connecting the SENSE pin to the VREF pin switches the amplifier output to the SENSE pin configuring the internal op amp circuit as a voltage follower and providing a 0 5 V reference output If an external resistor divider is connected a
41. td 6 3 0 0 ano 55 diro 6 m e lt lt lt lt 2 g oe gt lt lt lt i 8 6 868 Sd 9310H 1W Oz q 2 8 vada OX0T 84 64 223 zl ter 9310 93 auo AT 338 3 v VL8z0 Figure 41 LFCSP Evaluation Board Schematic Analog Inputs and DUT Rev A Page 19 of 36 OT en WTO 0 Svo tvo Hano QN9 di VA 6 8 H e Nj oja N aN9 Alo d e d H3QV3H 09215 or 0 0 7 820 009 6TH NI ASN SVG ILV DIETO xoa 851 xed ano ano asw ovd Lvy19 oj N MINI Alo VLEZCOTHLA TPL Figure 42 LFCSP Evaluation Board Digital Path Rev A Page 20 of 36 AD9215 0 820
42. uation Board LFCSP CP 32 AD9215BCP 105EB AD9215BCP 105 Evaluation Board LFCSP CP 32 17 Pb free part Rev A Page 34 of 36 108218 NOTES Rev A Page 35 of 36 AD9215 NOTES 2004 Analog Devices Inc All rights reserved Trademarks and regis ANALOG tered trademarks are the property of their respective owners WWW ana 0 0 com xw bail DEVICES Rev A Page 36 of 36
43. ut levels are defined as VCMum VREF 2 VCMuax AVDD VREF 2 The minimum common mode input level allows the AD9215 to accommodate ground referenced inputs Although optimum performance is achieved with a differential input a single ended source may be driven into VIN or VIN In this configuration one input accepts the signal while the opposite input should be set to midscale by connecting it to an appropriate reference For example a 2 V signal may be applied to VIN while a 1 V reference is applied to VIN The AD9215 then accepts a signal varying between 2 V and 0 V In the single ended configuration distortion performance may degrade significantly as compared to the differential case How ever the effect is less noticeable at lower input frequencies Differential Input Configurations As previously detailed optimum performance is achieved while driving the AD9215 in a differential input configuration For baseband applications the AD8138 differential driver provides excellent performance and a flexible interface to the ADC The output common mode voltage of the AD8138 is easily set to AVDD 2 and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal 02874 A 030 Figure 32 Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above the performance of most amplifiers is not adequate to achieve the true perfor
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