ANALOG DEVICES Complete 10-Bit 20 MSPS 80 mW CMOS A/D Converter AD9200 handbook
Contents
1. re es 9099000900080 111 111 9966000000000 iub Figure 40a Evaluation Board Component Signal Not to Scale 90000000006000609 6 2009909089909990898 909909909909090998 1 6 se Ry ard Solder Signal 20 REV E 109200 9009000090000000000000 06006000090000000000000 444444444444444 44444444444 444 244444444444444 3 44444444 4444 9844444444444444 944444444 444444 444444444444444 RA a e e de dede de Figure 40c Evaluation Board Power Plane Not to Scale B NE p II 6 5 6 06 06 60 99990000 00000000 en 444444444444444 844444444444444 444444444444444 444444444444444 EEE E 84444444444444 4 444444444444444 eco 4 4 444444444444444 Figure 40d Evaluation Board Ground Plane Not to Scale 21 REV 109200 43 58 n J CLOCK IN DRVDD 3 5 ai 20 C B ow 2 moe 53 0 ins ma e PEE 3200850 REV B2. 92008 hy fi ANALOG DEVICES Complete 10 Bit 20 MSPS 80 mW CMOS A D Converter 109200 FEATURES CMOS 10 Bit 20 MSPS Sampling A D Converter Pin Compatible with AD876 Power Dissipation 80 mW 3 V Supply Operation Between 2 7 V and 5 5 V Supply Differential Nonlinearity 0 5 LSB Power Down Sleep Mode Three State Outputs Out of Range Indicator Built In Clamp Function DC Restore Adjustable On Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT DESCRIPTION The AD9200 is a monolithic single supply 10 bit 20 MSPS analog to digital converter with an on chip sample and hold amplifier and voltage reference The AD9200 uses a multistage differential pipeline architecture at 20 MSPS data rates and guarantees no missing codes over the full operating temperature range The input of the AD9200 has been designed to ease the devel opment of both imaging and communications systems The user can select a variety of input ranges and offsets and can drive the input either single ended or differentially The sample and hold SHA amplifier is equally suited for both multiplexed systems that switch full scale voltage levels in suc cessive channels and sampling single channel inputs at frequen cies up to and beyond the Nyquist rate AC coupled input signals can be shifted to a predetermined level with an onboard clamp circuit AD9200ARS AD9200KST The dynamic per formance is excellent The AD9200 has an onboa
3. am 141 TPE US cit Sco Hat T Q ca Son OD Q 0 0 00000060000000000 0000000000000000 20000000000000000 0000000000000000 090000006000000 0000 00000000 00000000 00000000 00000000000000000 o o 00 09 00000000000000000 0000000000000 OOO0O0000000000000Q oc000000000000000 00000000 O Figure 40f Evaluation Board Solder Silk Not to Scale 22 REV E 109200 GROUNDING AND LAYOUT RULES As is the case for any high performance device proper ground ing and layout techniques are essential in achieving optimal performance The analog and digital grounds on the AD9200 have been separated to optimize the management of return currents in a system Grounds should be connected near the ADC It is recommended that a printed circuit board PCB of at least four layers employing a ground plane and power planes be used with the AD9200 The use of ground and power planes offers distinct advantages 1 The minimization of the loop area encompassed by a signal and its return path 2 The minimization of the impedance associated with ground and power paths 3 The inherent distributed capacitor formed by the power plane PCB insulation and ground plane The
4. 75 80 1 00 05 1 00 06 1 00 07 INPUT FREQUENCY Hz 1 00E 08 Figure 7 THD vs Input Frequency 0 LLLI 60 50 B 40 30 20 10 0 100 03 1 06 10 06 100 06 CLOCK FREQUENCY Hz Figure 8 THD vs Clock Frequency 40 20 0 20 40 60 80 100 Figure 9 Voltage Reference Error vs Temperature REV E AD9200 a a o POWER CONSUMPTION mW 77 5 77 0 0 2 4 6 8 10 12 14 16 18 20 CLOCK FREQUENCY MHz Figure 10 Power Consumption vs Clock Frequency MODE AVSS 499856 100k 54160 N 1 N N 1 CODE Figure 11 Grounded Input Histogram 140 0 0 1 6 2 6 6 4 6 5 6 6 6 7 6 8 6 9 6 10 6 SINGLE TONE FREQUENCY DOMAIN Figure 12 Single Tone Frequency Domain 109200 SIGNAL AMPLITUDE dB 1 0E 6 10 0E 6 100 0E 6 1 0E 9 FREQUENCY Hz Figure 13 Full Power Bandwidth REFBS 0 5V REFTS 2 5V CLOCK 20MHz 0 0 5 1 0 15 2 0 2 5 3 0 INPUT VOLTAGE V
5. CLK 20MSPS SINGLE TONE 45 52MHz DUAL TONE F 44 49MHz CLK 20MSPS SINGLE TONE 85 52MHz DUAL F 84 49MHz WORST CASE SPURIOUS dBFS SNR dBc WORST CASE SPURIOUS dBFS SNR dBc Fo 45 52 2 Fo 85 52 2 60 50 40 30 20 10 0 M 50 40 30 20 10 0 INPUT POWER LEVEL dBFS INPUT POWER LEVEL dBFS Figure 35 SNR SFDR for IF 45 MHz Figure 37 SNR SFDR for IF 85 MHz SINGLE TONE SFDR o o n 7 DUAL TONE SFD 5 T DUAL TONE SFDR SINGLE SFDR 5 o 20 al a Oo uz aon o lt lt o 2 5 CLK 21 538MSPS S CLK 20MSPS SINGLE 70 55MHz SINGLE 135 52MHz DUAL TONE F4 69 50MHz DUAL TONE F 134 44 2 Fa 70 55MHz 135 52MHz 0 0 60 50 40 30 20 10 0 60 50 40 30 20 10 0 INPUT POWER LEVEL dBFS INPUT POWER LEVEL dBFS Figure 36 SNR SFDR for IF 70 MHz Figure 38 SNR SFDR for IF 135 MHz REV E 17 109200 10 11 510 150 0 626 R19 O 1pF T 10 10V 1780 J lt Tui TP11 3 5A CLAMP THREE STATE STBY AVDDO O DRVDD 220 C16 C19 6 11 0 1uF 010 48 220 D L 8 Y TN 5 RN1 28 2 m AVDD DRVDD OTR tw J8 U1 WHITE AD
6. Figure 2 Equivalent Circuits CAUTION accumulate on the human body and test equipment and can discharge without detection Although the AD9200 features proprietary ESD protection circuitry permanent damage may Sp occur on devices subjected to high energy electrostatic discharges Therefore proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING 1 mS REV 109200 PIN CONFIGURATIONS 28 Lead Shrink Small Outline SSOP 28 AVDD AIN 26 VREF 25 REFBS 23 MODE REFTS 20 CLAMPIN 19 CLAMP 18 REFSENSE STBY 16 THREE STATE 15 CLK 48 Lead Plastic Thin Quad Flatpack LQFP VREF S NC c c c R AVSS NC R AVDD NC NC 8 AIN AD9200 TOP VIEW Not to Scale 22225 5 PIN FUNCTION DESCRIPTIONS SSOP LQFP Pin No Pin No Name Description 1 44 AVSS Analog Ground 2 45 DRVDD Digital Driver Supply 3 1 DO Bit 0 Least Significant Bit 4 2 D1 Bit 1 5 3 D2 Bit 2 6 4 D3 Bit 3 7 5 D4 Bit 4 8 8 D5 Bit 5 9 9 D6 Bit 6 10 10 D7 Bit 7 11 11 D8 Bit 8 12 12 D9 Bit 9 Most Significant Bit 13 16 OTR Out of Range Indicator 14 17 DRVSS Digital Ground 15 22 CLK Clock Input 16 23 THREE STATE HI High Impedance State LO Normal Operation
7. Cy 1 UF and Ry 20 Q the acquisition time needed to set the input dc level to one volt with 1 mV accuracy is about 140 us assuming a full 1 volt Vc With a 1 UF input coupling capacitor the droop across one horizontal can be calculated Ip as 10 and t 63 5 so dV 0 635 mV which is less than one LSB After the input capacitor is initially charged the clamp pulse width only needs to be wide enough to correct small voltage errors such as the droop The fine scale settling characteristics of the clamp circuitry are shown in Table II Depending on the required accuracy a CLAMP pulsewidth of 1 8 3 should work most applications The OFFSET val ues ignore the contribution of offset from the clamp amplifier they simply compare the output code with a final value mea sured with a much longer CLAMP pulse duration Table II CLAMP OFFSET 10 us lt 1 LSB 5 us 5 LSBs 4 us 7 LSBs 3 us 11 LSBs 2 Us 19 LSBs 1 us 42 LSBs AD9200 CLAMP IN 0 1 AD9200 0 1 5 OR EXTERNAL DC CLAMPIN Figure 24b Video Clamp Circuit 13 109200 DRIVING THE ANALOG INPUT Figure 25 shows the equivalent analog input of the AD9200 a sample and hold amplifier switched capacitor input SHA Bringing CLK to a logic low level closes Switches 1 and 2 and opens Switch 3 The input source connected to AIN must charge capacitor CH during this time When CLK trans
8. Input Input MODE REFSENSE Modes Connect Span Pin Pin REF REFTS REFBS Figure TOP BOTTOM AIN 1V AVDD Short REFSENSE REFTS and VREF Together AGND 18 AIN 2 AVDD AGND Short REFTS and VREF Together AGND 19 CENTER SPAN AIN 1V AVDD 2 Short VREF and REFSENSE Together AVDD 2 AVDD 2 20 AIN 2 AVDD 2 AGND No Connect AVDD 2 AVDD 2 Differential AIN Is Input 1 1 AVDD 2 Short VREF and REFSENSE Together AVDD 2 AVDD 2 29 REFTS and REFBS Are Shorted Together for Input 2 2V AVDD 2 AGND No Connect AVDD 2 AVDD 2 External Ref AIN 2 V max AVDD AVDD No Connect Span REFTS 21 22 REFBS 2 V AGND Short to Short to 23 VREFTF VREFBF AD876 AIN 2 Float or AVDD No Connect Short to Short to 30 AVSS VREFTF VREFBF REV E 109200 SUMMARY OF MODES VOLTAGE REFERENCE 1 V Mode the internal reference may be set to 1 V by connect ing REFSENSE and VREF together 2 V Mode the internal reference my be set 2 V by connecting REFSENSE to analog ground External Divider Mode the internal reference may be set to a point between 1 V and 2 V by adding external resistors See Figure 16f External Reference Mode enables the user to apply an exter nal reference to REFTS REFBS and VREF pins This mode is attained by tying REFSENSE to VDD REFERENCE BUFFER Center Span Mode midscale is set by shorting REFTS and REFBS together and applying the midscale voltage to that point The MODE pin i
9. Kelvin Connected Reference Using the AD9200 STANDBY OPERATION The ADC may be placed into a powered down sleep mode by driving the STBY standby pin to logic high potential and holding the clock at logic low In this mode the typical power drain is approximately 4 mW If there is no connection to the STBY pin an internal pull down circuit will keep the ADC in a wake up mode of operation The ADC will wake up in 400 ns typ after the standby pulse goes low CLAMP OPERATION The AD9200ARS and AD9200KST parts feature an optional clamp circuit for dc restoration of video or ac coupled signals Figure 24 shows the internal clamp circuitry and the external control signals needed for clamp operation To enable the clamp apply a logic high to the CLAMP pin This will close the switch SW1 The clamp amplifier will then servo the volt age at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN pin After the desired clamp level is attained SW1 is opened by taking CLAMP back to a logic low Ignoring the droop caused by the input bias current the input capacitor CIN will hold the dc voltage at AIN constant until the next clamp interval The input resistor RIN has a minimum recom mended value of 10 Q to maintain the closed loop stability of the clamp amplifier The allowable voltage range that can be applied to CLAMPIN depends on the operational limits of the internal clamp ampli fier When operating off of 3 volt
10. VREF V av REFSENSE AVDD AD9200 g Internal Reference Disable Power Reduction REV E 109200 The actual reference voltages used by the internal circuitry of the AD9200 appear REFTF and For proper tion it is necessary to add a capacitor network to decouple these pins The REFTF and REFBF should be decoupled for all internal and external configurations as shown in Figure 17 AD9200 Figure 17 Reference Decoupling Network Note REFTF reference top force REFBF reference bottom force REFTS reference top sense REFBS reference bottom sense INTERNAL REFERENCE OPERATION Figures 18 19 and 20 show example hookups of the AD9200 internal reference in its most common configurations Figures 18 and 19 illustrate top bottom mode while Figure 20 illustrates center span mode Figure 29 shows how to connect the AD9200 for 1 V p p differential operation Shorting the VREF pin directly to the REFSENSE pin places the internal reference amplifier Al in unity gain mode and the resultant reference output is 1 V In Figure 18 REFBS is grounded to give an input range from 0 V to 1 V These modes can be chosen when the supply is either 3 V or 5 V The VREF pin must be bypassed to AVSS analog ground with 1 0 uF tantalum capacitor in parallel with low inductance low ESR 0 1 uF ceramic capacitor AD9200 move VREF O REF we uF SENSE Figure 18 Internal Reference
11. its distortion performance the AD9200 is config ured in the differential mode with a 1 V span using a transformer The center tap of the transformer is biased at midsupply via a resistor divider Preceding the AD9200 is a bandpass filter as well as a 32 dB gain stage A large gain stage may be required to compensate for the high insertion losses of a SAW filter used for image rejection The gain stage will also provide adequate isolation for the SAW filter from the charge kick back currents associated with AD9200 s input stage The gain stage can be realized using one or two cascaded AD8009 op amps amplifiers The AD8009 is a low cost 1 GHz current feedback op amp having a 3rd order intercept character ized up to 250 MHz A passive bandpass filter following the AD8009 attenuates its dominant 2nd order distortion products which would otherwise be aliased back into the AD9200 s baseband region Also it reduces any out of band noise which would also be aliased back due to the AD9200 s noise band width of 220 MHz Note the bandpass filters specifications are application dependent and will affect both the total distor tion and noise performance of this circuit The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC for a narrowband IF sampling application Both single tone and dual tone SFDR vs amplitude are very useful in an assessing an ADC s noise performance
12. maintain the performance outlined in the data sheet specifica tions the resistor should be limited to 20 or less For applica tions with signal bandwidths less than 10 MHz the user may proportionally increase the size of the series resistor Alterna tively adding a shunt capacitance between the AIN pin and analog ground can lower the ac load impedance The value of this capacitance will depend on the source resistance and the required signal bandwidth The input span of the AD9200 is a function of the reference voltages For more information regarding the input range see the Internal and External Reference sections of the data sheet Figure 26 Simple AD9200 Drive Configuration 14 In many cases particularly in single supply operation ac cou pling offers a convenient way of biasing the analog input signal at the proper signal range Figure 25 shows a typical configura tion for ac coupling the analog input signal to the AD9200 Maintaining the specifications outlined in the data sheet requires careful selection of the component values The most important is the f ap high pass corner frequency It is a function of R2 and the parallel combination of C1 and C2 The f 5 point can be approximated by the equation 1 2 x pi x R2 Czo where Cgo is the parallel combination of and C2 Note that C1 is typically a large electrolytic or tantalum capacitor that becomes inductive at high frequencies Adding a s
13. 1 V p p Input Span Top Bottom Mode Figure 19 shows the single ended configuration for 2 V p p operation REFSENSE is connected to GND resulting in a 2 V REFTS reference output O 3 O ners _ A D 4 2 10uF CORE f TOTAL 010 Pu p pe Figure 19 Internal Reference 2 V p p Input Span Top Bottom Mode Figure 20 shows the single ended configuration that gives the good high frequency dynamic performance SINAD SFDR optimize dynamic performance center the common mode voltage of the analog input at approximately 1 5 V Connect the shorted REFTS and REFBS inputs to a low impedance 1 5 V source In this configuration the MODE pin is driven to a volt age at midsupply AVDD 2 Maximum reference drive is 1 mA An external buffer is re quired for heavier loads AD9200 2777 2 A D 4 21 10 TOTAL 0 1uF pe x 1060 Figure 20 Internal Reference 1 V Input Span Center Span Mode 11 109200 EXTERNAL REFERENCE OPERATION Using an external reference may provide more flexibility and improve drift and accuracy Figures 21 through 23 show ex amples of how to use an external reference with the AD9200 To use an external reference the user must disable the internal reference amplifier by connecting the REFSENSE pin to VDD The user then has the option of driving the VREF pin or driv ing the REFTS and REFBS pins The AD9
14. 17 24 STBY HI Power Down Mode LO Normal Operation 18 26 REFSENSE Reference Select 19 27 CLAMP HI Enable Clamp Mode LO No Clamp 20 28 CLAMPIN Clamp Reference Input 21 29 REFTS Top Reference 22 30 REFTF Top Reference Decoupling 23 32 MODE Mode Select 24 34 REFBF Bottom Reference Decoupling 25 35 REFBS Bottom Reference 26 38 VREF Internal Reference Output 27 39 AIN Analog Input 28 42 AVDD Analog Supply 109200 DEFINITIONS SPECIFICATIONS Integral Nonlinearity INL Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale The point used as zero occurs 1 2 LSB before the first code transi tion Full scale is defined as a level 1 1 2 LSB beyond the last code transition The deviation is measured from the center of each particular code to the true straight line Differential Nonlinearity DNL No Missing Codes An ideal ADC exhibits code transitions that are exactly 1 LSB apart DNL is the deviation from this ideal value It is often specified in terms of the resolution for which no missing codes NMC are guaranteed Offset Error The first transition should occur at a level 1 LSB above zero Offset is defined as the deviation of the actual first code transi tion from that point Gain Error The first code transition should occur for an analog value 1 LSB above nominal negative full scale The last transition should occur for an anal
15. 200 contains an internal reference buffer A2 that simplifies the drive requirements of an external reference The external reference must simply be able to drive a 10 kQ load Figure 21 shows an example of the user driving the top and bottom references REFTS is connected to a low impedance 2 V source and REFBS is connected to a low impedance 1 V source REFTS and REFBS may be driven to any voltage within the supply as long as the difference between them is between 1 V and 2 V AD9200 2V O 1V A D 4 2 10 TOTAL 0 1pF AVDD 10 Figure 21 External Reference Mode 1 V Input Span Figure 22 shows an example of an external reference generating 2 5 V at the shorted REFTS and REFBS inputs In this in stance a REF43 2 5 V reference drives REFTS and REFBS A resistive divider generates a 1 V VREF signal that is buffered by A3 A3 must be able to drive a 10 kQ capacitive load Choose this op amp based on noise and accuracy requirements AD9200 0 1 pF AVDD 2 Figure 22 External Reference Mode 1 V Input Span 2 5 Figure 2 shows an example of the external references driving the REFTF and pins that is compatible with the AD876 REFTS is shorted to REFTF and driven by an external 4 V low impedance source REFBS is shorted to REFBF and driven by a 2 V source The MODE pin is connected to GND in this configuration 12 Figure 23b
16. 9200 m 220 2 15 5 48 DUTCLK 15 RN1 THREE STATE lt 16 THREE STATE 228 STBY 5 STBY VCCB VCCA REFSENSE gt REFSENSE 81 CLAMP 5 5 SZU REFTS REFTF 9 22 REFTF CLK MODE 5 22 C WHITE 24 6 11 REFBF 2 31 33 48 REFBS Deva RN2 VREF L 2 571 VREF 220 CLK_OUT 5 Js C33 AVSS RN2 EI 10 10V 2 220 1 4 13 P RN2 DRVDDo 220 C41 3 14 19 48 220 GND 2 15 7 RN2 1 1 16 GND 15 48 220 Figure 39a Evaluation Board Schematic 18 REV E 4 7 47 10V 49 42 43 4 GND 6 GND 0 REFSENSE EXTB REFBF REFTF EXTT CLAMPIN EXTT REFTS REFBS EXTB REFBS TP29 L4 Sea 3 5D C32 C31 0 1pF 10 10V TP20 L1 DRVDD C22 0 1pF 10 10V 21 g L2 AVDD C24 L c25 33 16 22 13 3 5 C26 L c27 d gmo TP23 TP24 TP25 TP26 TP27 TP28 AD9200 JP14 AVDD 5 MODE 10 JP15 JP22 AVDD O O 210 4 99102 ADC_CLK DUTCLK U6 DECOUPLING AVDDCLK Figure 39b Evaluation Board Schematic 19 109200 B 7 oes A gt aus 3 Life I add i PWS ee 2 9090996909998 k 00000000 5 eo 4 44
17. D9200 sustains 20 MSPS operation with DRVDD 3 V In all cases check your logic family data sheets for compatibility with the AD9200 Digital Specification table THREE STATE OUTPUTS The digital outputs of the AD9200 can be placed in a high impedance state by setting the THREE STATE pin to HIGH This feature is provided to facilitate in circuit testing or evaluation 23 109200 OUTLINE DIMENSIONS Dimensions shown in inches and mm 48 Lead Plastic Thin Quad Flatpack LQFP ST 48 0 063 1 60 MAX 0 354 9 00 BSC 0 057 1 45 0 276 7 0 BSC 0 030 0 75 Y 0 053 1 35 n X 0 018 0 45 SEATING 9 9 PLANE VIEW 5 8 PINS DOWN 5 o 0 006 0 15 ps v 0 002 0 05 213 MIN 0 77 olf ot 0 007 0 18 0 18 0 004 0 09 28 Lead Shrink Small Outline Package SSOP RS 28 0 407 10 34 0 397 10 08 28 15 A alg 85 98 s olo 1 14 2 0 078 1 98 PIN 1 0 07 1 79 0 068 1 73 0 066 1 67 0 008 0 203 90256 0 015 0 38 SEATING 0 009 t 528 00020050 065 0 010 0 25 PLANE 9 59 0 005 0 127 0 03 0 762 F alle 0 022 0 558 0 002 0 050 gsc 24 REV E C3033e 0 8 99 PRINTED IN U S A
18. Figure 14 Input Bias Current vs Input Voltage APPLYING THE AD9200 THEORY OF OPERATION The AD9200 implements a pipelined multistage architecture to achieve high sample rate with low power The AD9200 distrib utes the conversion over several smaller A D subblocks refining the conversion with progressively higher accuracy as it passes the results from stage to stage As a consequence of the distrib uted conversion the AD9200 requires a small fraction of the 1023 comparators used in a traditional flash type A D A sample and hold function within each of the stages permits the first stage to operate on a new input sample while the second third and fourth stages operate on the three preceding samples OPERATIONAL MODES The AD9200 is designed to allow optimal performance in a wide variety of imaging communications and instrumentation applications including pin compatibility with the AD876 A D To realize this flexibility internal switches on the AD9200 are used to reconfigure the circuit into different modes These modes are selected by appropriate pin strapping There are three parts of the circuit affected by this modality the voltage reference the reference buffer and the analog input The nature of the appli cation will determine which mode is appropriate the descrip tions in the following sections as well as the Table I should assist in picking the desired mode Table I Mode Selection
19. O O AVSS REV E Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices DRVDD One Technology Way 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1999 9200 AVDD 3 V 08 3 V 20 MHz 50 Duty Cycle MODE AVDD 2 V Input Span from 0 5 V to 2 5 V External Reference Tm to Tmax unless otherwise noted Parameter Symbol Min Max Units Condition RESOLUTION 10 Bits CONVERSION RATE Fs 20 MHz DC ACCURACY Differential Nonlinearity DNL t0 5 1 LSB REFTS 2 5 V REFBS 0 5 V Integral Nonlinearity INL 0 75 2 LSB Offset Error 0 4 1 2 FSR Gain Error Eps 1 4 3 5 FSR REFERENCE VOLTAGES Top Reference Voltage REFTS 1 AVDD Bottom Reference Voltage REFBS GND AVDD 1 V Differential Reference Voltage 2 V p p Reference Input Resistance 10 kQ REFTS REFBS MODE AVDD 4 2 kQ Between REFTF and REFBF MODE AVSS ANALOG INPUT Input Voltage Range AIN REFBS REFTS REFBS Min GND REFTS AVDD Input Capacitance Cw 1 pF Switched Aperture D
20. TS and REFBS together to be used as the second input REV E AD9200 Figure 15 AD9200 Equivalent Functional Input Circuit In single ended operation the input spans the range REFBS AIN REFTS where REFBS can be connected to GND and REFTS con nected to VREF If the user requires a different reference range REFBS and REFTS can be driven to any voltage within the power supply rails so long as the difference between the two is between 1 V and 2 V In differential operation REFTS and REFBS are shorted to gether and the input span is set by VREF REFTS VREF 2 lt AIN REFTS VREF 2 where VREF is determined by the internal reference or brought in externally by the user The best noise performance may be obtained by operating the AD9200 with a 2 V input range The best distortion perfor mance may be obtained by operating the AD9200 with a 1 V input range REFERENCE OPERATION The AD9200 can be configured in a variety of reference topolo gies The simplest configuration is to use the AD9200 s onboard bandgap reference which provides a pin strappable option to generate either a 1 V or 2 V output If the user desires a refer ence voltage other than those two an external resistor divider can be connected between VREF REFSENSE and analog ground to generate a potential anywhere between 1 V and 2 V Another alternative is to use an external reference for designs requiring enhanced accuracy and or drift perfor
21. and noise contribution due to aper ture jitter In any application one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device Figure 34 Simplified AD9200 IF Sampling Circuit 16 REV 109200 Figures 35 38 combine the dual tone SFDR as well as single Although not presented data was also taken with the insertion tone SFDR and SNR performance at IF frequencies of 45 MHz of an AD8009 gain stage of 32 dB in the signal path No 70 MHz 85 MHz and 135 MHz Note the SFDR vs ampli degradation in two tone SFDR vs amplitude was noted at an tude data is referenced to dBFS while the single tone SNR data IF of 45 MHz 70 MHz and 85 MHz However at 135 MHz is referenced to dBc The performance characteristics in these the AD8009 became the limiting factor in the distortion perfor figures are representative of the AD9200 without the AD8009 mance until the two input tones were decreased 15 dBFS The AD9200 was operated in the differential mode via trans from their full scale level of 6 5 dBFS Note the SNR perfor former with a 1 V span at 20 MSPS The analog supply mance in each case degraded by approximately 0 5 dB due to AVDD and the digital supply DRVDD were set to 5 V and the AD8009 s in band noise contribution 3 3 V respectively SINGLE TONE SFDR DUAL TONE SFDR DUAL TONE SFDR
22. differential signal the top leg is driven into AIN In the configuration below the AD9200 is accepting a 1 V p p signal See Figure 29 AD9200 2V Figure 29 Differential Input AD876 MODE OF OPERATION The AD9200 may be dropped into the AD876 socket This will allow AD876 users to take advantage of the reduced power consumption realized when running the AD9200 on a 3 0 V analog supply Figure 30 shows the pin functions of the AD876 and AD9200 The grounded REFSENSE pin and floating MODE pin effec tively put the AD9200 in the external reference mode The external reference input for the AD876 will now be placed on the reference pins of the AD9200 The clamp controls will be grounded by the AD876 socket The AD9200 has a 3 clock cycle delay compared to a 3 5 cycle delay of the AD876 9200 01 10uF O CLAMP O CLAMPIN Figure 30 AD876 Mode CLOCK INPUT The AD9200 clock input is buffered internally with an inverter powered from the AVDD pin This feature allows the AD9200 to accommodate either 5 V or 3 3 V CMOS logic input sig nal swings with the input threshold for the CLK pin nominally at AVDD 2 REV E The pipelined architecture of the AD9200 operates on both rising and falling edges of the input clock To minimize duty cycle variations the recommended logic family to drive the clock input is high speed or advanced CMOS HC HCT AC ACT logic CMOS logic provides both s
23. elay tap 4 ns Aperture Uncertainty Jitter tay 2 ps Input Bandwidth 3 dB BW Full Power 0 dB 300 MHz DC Leakage Current 23 Input FS INTERNAL REFERENCE Output Voltage 1 V Mode VREF 1 REFSENSE VREF Output Voltage Tolerance 1 V Mode 10 25 Output Voltage 2 Mode VREF 2 REFSENSE GND Load Regulation 1 V Mode 0 5 2 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 7 3 5 5 DRVDD 2 7 3 5 5 Supply Current IAVDD 26 6 33 3 mA AVDD 3 V MODE AVSS Power Consumption Pp 80 100 mW AVDD DRVDD 3 V MODE AVSS Power Down 4 mW STBY AVDD MODE and CLOCK AVSS Gain Error Power Supply Rejection PSRR 1 FS DYNAMIC PERFORMANCE AIN 0 5 dBFS Signal to Noise and Distortion SINAD f 3 58 MHz 54 5 57 dB f 10 MHz 54 dB Effective Bits f 3 58 MHz 9 1 Bits f 10 MHz 8 6 Bits Signal to Noise SNR f 3 58 MHz 55 57 dB f 10 MHz 56 dB Total Harmonic Distortion THD f 3 58 MHz 59 66 dB f 10 MHz 58 dB Spurious Free Dynamic Range SFDR f 3 58 MHz 61 69 dB f 10 MHz 61 dB Two Tone Intermodulation Distortion IMD 68 dB f 44 49 MHz and 45 52 MHz Differential Phase DP 0 1 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0 05 REV E 109200 Parameter Symbol Min Typ Max Units Condition DIGITAL INPUTS High Input Voltage Vin 2 4 Low Input Voltage 0 3 DIGITAL OUTPUTS High Z Leakage 10 10 Output GND to VDD Data Valid Delay to
24. ess is often referred to as Direct IF Down Conversion or Undersampling There are several potential ben efits in using the ADC to alias i e mix down a narrowband or wideband IF signal First and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters reducing cost and power dissipation Second is the ability to apply various DSP techniques to perform such functions as filtering channel selection quadrature demodulation data reduction detection etc A detailed discussion on using this technique in digital receivers can be found in Analog Devices Application Notes AN 301 and AN 302 In Direct IF Down Conversion applications one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will down convert an IF signal Similar to the mixer topology an image rejection filter is required to limit other potential interfering signals from also aliasing back into the ADC s baseband region A tradeoff exists between the complexity of this image rejection filter and the sample rate as well as dynamic range of the ADC The AD9200 is well suited for various narrowband IF sampling applications The AD9200 s low distortion input SHA has a full power bandwidth extending to 300 MHz thus encompassing many popular IF frequencies DNL of 0 5 LSB typ com bined with low thermal
25. input referred noise allows the AD9200 in the 2 V span to provide 60 dB of SNR for a baseband input sine wave Also its low aperture jitter of 2 ps rms ensures minimum SNR degradation at higher IF frequencies In fact the AD9200 is capable of still maintaining 56 dB of SNR at an IF of 135 MHz with a 1 V i e 4 dBm input span Note although the AD9200 will typically yield a 3 to 4 dB improvement in SNR when con figured for the 2 V span the 1 V span provides the optimum full scale distortion performance Furthermore the 1 V span reduces the performance requirements of the input driver cir cuitry and thus may be more practical for system implementa tion purposes G4 8 Gp 12dB L C SAW BANDPASS MINICIRCUITS FILTERZ FILTER T4 6T AD9200 OUTPUT 1 4 500 Figure 34 shows a simplified schematic of the AD9200 config ured in an IF sampling application To reduce the complexity of the digital demodulator in many quadrature demodulation ap plications the IF frequency and or sample rate are selected such that the bandlimited IF signal aliases back into the center of the ADC s baseband region 1 Fs 4 For example if an IF sig nal centered at 45 MHz is sampled at 20 MSPS an image of this IF signal will be aliased back to 5 0 MHz which corre sponds to one quarter of the sample rate i e Fs 4 This demodulation technique typically reduces the complexity of the post digital demodulator ASIC which follows the ADC To maximize
26. itions from logic low to logic high Switches 1 and 2 open placing the SHA in hold mode Switch 3 then closes forcing the output of the op amp to equal the voltage stored on CH When CLK transitions from logic high to logic low Switch 3 opens first Switches 1 and 2 close placing the SHA in track mode The structure of the input SHA places certain requirements on the input drive source The combination of the pin capacitance and the hold capacitance CH is typically less than 5 pF The input source must be able to charge or discharge this ca pacitance to 10 bit accuracy in one half of a clock cycle When the SHA goes into track mode the input source must charge or discharge capacitor CH from the voltage already stored on CH to the new voltage In the worst case a full scale voltage step on the input the input source must provide the charging current through the Ron 50 Q of Switch 1 and quickly within 1 2 CLK period settle This situation corresponds to driving a low input impedance On the other hand when the source voltage equals the value previously stored on CH the hold capacitor requires no input current and the equivalent input impedance is ex tremely high Adding series resistance between the output of the source and the AIN pin reduces the drive requirements placed on the source Figure 26 shows this configuration The bandwidth of the particular application limits the size of this resistor To
27. mall ceramic or polystyrene capacitor on the order of 0 01 UF that does not become inductive until negligibly higher frequencies maintains a low impedance over a wide frequency range NOTE AC coupled input signals may also be shifted to a desired level with the AD9200 s internal clamp See Clamp Operation Figure 27 AC Coupled Input There are additional considerations when choosing the resistor values The ac coupling capacitors integrate the switching tran sients present at the input of the AD9200 and cause a net dc bias current Ip to flow into the input The magnitude of the bias current increases as the signal magnitude deviates from midscale and the clock frequency increases 1 minimum bias current flow when AIN V midscale This bias current will result in an offset error of R1 R2 x Ip If it is necessary to compensate this error consider making R2 negligibly small or modifying VBIAS to account for the resultant offset In systems that must use dc coupling use an op amp to level shift a ground referenced signal to comply with the input re quirements of the AD9200 Figure 28 shows an AD8041 config ured in noninverting mode AD9200 MIDSCALE OFFSET VOLTAGE Figure 28 Bipolar Level Shift REV E 109200 DIFFERENTIAL INPUT OPERATION The AD9200 will accept differential input signals This function may be used by shorting REFTS and REFBS and driving them as one leg of the
28. mance A third alternative is to bring in top and bottom references bypassing VREF altogether Figures 16d 16e and 16f illustrate the reference and input ar chitecture of the AD9200 In tailoring a desired arrangement the user can select an input configuration to match drive circuit Then moving to the reference modes at the bottom of the figure select a reference circuit to accommodate the offset and amplitude of a full scale signal Table I outlines pin configurations to match user requirements 109200 FS AIN MODE AVDD F S RANGE OBTAINED FROM VREF PIN OR REFTF EXTERNAL REF F S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF a Top Bottom Mode MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO INTERNAL REF MIDSCALE AD9200 ve AD9200 AVDD 2 REFTF 04 TOTAL INTERNAL REF MIDSCALE OFFSET VOLTAGE IS DERIVED FROM INTERNAL OR EXTERNAL REF b Center Span Mode MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE MODE O AVDD 2 REFTF 0 1HF O TOTAL c Differential Mode 1 0pF 1 REFSENSE AVSS Y AD9200 d 1 V Reference VREF 1 1 0uF 1 y AD9200 INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF AND Rp f Variable Reference Between 1 V and 2 V Figure 16 10 2 V Reference C Q
29. ngs for extended periods may effect device reliability AVDD AVSS 0 8 6 5 V ORDERING GUIDE DRVDD DRVSS 0 3 6 5 V gt 821 Pak AVSS DRVSS 0 3 0 3 V ah uU AVDD DRVDD 6 5 6 5 V ange 729 pions MODE AVSS 0 3 AVDD 0 3 V AD9200JRS 0 C to 70 28 SSOP RS 28 CLK 5 1 05 AVDD 03 V AD9200ARS 40 C to 85 C 28 Lead SSOP RS 28 Digital Outputs DRVSS 0 3 DRVDD 0 3 V AD9200JST 0 C to 70 48 Lead LQFP ST 48 AIN AVSS 0 3 AVDD 0 3 V AD9200KST 0 Cto 70 C 48 Lead LQFP ST 48 VREF AVSS 0 3 AVDD 0 3 V AD9200JRSRL 0 C to 70 28 SSOP Reel RS 28 REFSENSE AVSS 0 3 AVDD 0 3 V AD9200ARSRL 40 C to 85 C 28 Lead SSOP Reel RS 28 REFTF REFTB AVSS 03 AVDD 0 3 V AD9200JSTRL 0 to 70 C 48 Lead LQFP Reel ST 48 REFTS REFBS AVSS 0 3 AVDD 0 3 V AD9200KSTRL 0 C to 70 48 Lead LQFP Reel ST 48 Junction Temperature 150 C AD9200 SSOP EVAL Evaluation Board Storage Temperature 65 150 C AD9200 LQFP EVAL Evaluation Board Lead Temperature ae TT 10 sec 300 C RS Shrink Small Outline ST Thin Quad Flatpack AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS x 55 55 DRVSS AVSS AVSS a DO D9 OTR b Three State Standby Clamp c CLK REFBS 85 REFTF 80 AVDD REFBF 84 REFTS 08 AVSS d AIN e Reference AVDD AVDD AVDD AVDD hs d AVSS AVSS AVSS AVSS CLAMPIN g MODE h REFSENSE VREF
30. og value 1 LSB below the nominal positive full scale Gain error is the deviation of the actual difference be tween first and last code transitions and the ideal difference between the first and last code transitions Pipeline Delay Latency The number of clock cycles between conversion initiation and the associated output data being made available New output data is provided every rising edge 1 AVDD 3 V DRVDD 3 V 20 MHz 50 Duty Cycle MODE AVDD 2 V Input Typical Characterization Curves Span from 0 5 V to 2 5 V External Reference unless otherwise noted 1 0 0 128 256 384 512 640 768 896 1024 CODE OFFSET Figure 3 Typical DNL o 128 256 384 512 640 768 896 1024 CODE OFFSET Figure 4 Typical INL 60 55 50 45 a 9 0 2 35 30 25 20 1 00 05 1 00 06 1 00 07 1 00 08 INPUT FREQUENCY Hz Figure 5 SNR vs Input Frequency 60 0 5 AMPLITUDE 55 50 6 0 AMPLITUDE 45 a 40 a 20 0 AMPLITUDE z 35 30 25 20 1 00 05 1 00E 06 1 00E 07 1 00E 08 INPUT FREQUENCY Hz Figure 6 SINAD vs Input Frequency REV E CLOCK 20MHz 20 0 AMPLITUDE 55 6 0 AMPLITUDE 0 5 AMPLITUDE
31. p 25 ns Cr 20 pF Data Enable Delay tpEN 25 ns Data High Z Delay tpuz 13 ns LOGIC OUTPUT with DRVDD 3 V High Level Output Voltage 50 HA Vou 2 95 High Level Output Voltage 0 5 mA Vou 2 80 Low Level Output Voltage 1 6 mA Vor 0 4 Low Level Output Voltage 50 HA Vor 0 05 LOGIC OUTPUT with DRVDD 5 High Level Output Voltage 50 uA Vou 4 5 High Level Output Voltage 0 5 mA 2 4 Low Level Output Voltage 1 6 mA Vor 0 4 Low Level Output Voltage 50 HA Vor 0 1 CLOCKING Clock Pulsewidth High 22 5 ns Clock Pulsewidth Low 22 5 ns Pipeline Latency 3 Cycles CLAMP Clamp Error Voltage Eoc 20 40 mV CLAMPIN 0 5 V 2 7 Ru 10 Q Clamp Pulsewidth 2 us 1 uF Period 63 5 us NOTES 15 Figures 1 and 1b Available only in AD9200ARS and AD9200KST Specifications subject to change without notice REV E Figure 1a Figure 1b 109200 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the With device at these or any other conditions above those indicated in the operational Respect sections of this specification is not implied Exposure to absolute maximum Parameter to Min Max Units rati
32. rd programmable reference An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application A single clock input is used to control all internal conversion cycles The digital output data is presented in straight binary output format An out of range signal OTR indicates an over flow condition which can be used with the most significant bit to determine low or high overflow The AD9200 can operate with supply range from 2 7 V to 5 5 V ideally suiting it for low power operation in high speed portable applications The AD9200 is specified over the industrial 40 to 85 C and commercial 0 C to 70 C temperature ranges PRODUCT HIGHLIGHTS Low Power The AD9200 consumes 80 mW on a 3 V supply excluding the reference power In sleep mode power is reduced to below 5 mW Very Small Package The AD9200 is available in both a 28 lead SSOP and 48 lead LQFP packages Pin Compatible with AD876 The AD9200 is pin compatible with the AD876 allowing older designs to migrate to lower supply voltages 300 MHz On Board Sample and Hold The versatile SHA input can be configured for either single ended or differential inputs Out of Range Indicator The OTR output bit indicates when the input signal is beyond the AD9200 s input range Built In Clamp Function Allows dc restoration of video signals with AD9200ARS and AD9200KST FUNCTIONAL BLOCK DIAGRAM CLAMP IN CLK AVDD
33. s set to AVDD 2 The analog input will swing about that midscale point ToplBottom Mode sets the input range between two points The two points are between 1 V and 2 V apart The Top Bottom Mode is enabled by tying the MODE pin to AVDD ANALOG INPUT Differential Mode is attained by driving the AIN pin as one differential input and shorting REFTS and REFBS together and driving them as the second differential input The MODE pin is tied to AVDD 2 Preferred mode for optimal distortion performance Single Ended is attained by driving the AIN pin while the REFTS and REFBS pins are held at dc points The MODE pin is tied to AVDD Single EndedlClamped AC Coupled the input may be clamped to some dc level by ac coupling the input This is done by tying the CLAMPIN to some dc point and applying a pulse to the CLAMP pin MODE pin is tied to AVDD SPECIAL AD876 Mode enables users of the AD876 to drop the AD9200 into their socket This mode is attained by floating or grounding the MODE pin INPUT AND REFERENCE OVERVIEW Figure 16 a simplified model of the AD9200 highlights the relationship between the analog input AIN and the reference voltages REFTS REFBS and VREF Like the voltages applied to the resistor ladder in a flash A D converter REFTS and REFBS define the maximum and minimum input voltages to the A D The input stage is normally configured for single ended opera tion but allows for differential operation by shorting REF
34. se characteristics result in both a reduction of electro magnetic interference EMI and an overall improvement in performance It is important to design a layout that prevents noise from cou pling onto the input signal Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry Separate analog and digital grounds should be joined together directly under the AD9200 in a solid ground plane The power and ground return currents must be carefully managed A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry REV E DIGITAL OUTPUTS Each of the on chip buffers for the AD9200 output bits 00 09 is powered from the DRVDD supply pins separate from AVDD The output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated In all cases a fan out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level For DRVDD 5 V the AD9200 output signal swing is compat ible with both high speed CMOS and TTL logic families For TTL the AD9200 on chip output drivers were designed to support several of the high speed TTL families F AS S For applications where the clock rate is below 20 MSPS other TTL families may be appropriate For interfacing with lower voltage CMOS logic the A
35. supplies the recommended clamp range is between 0 5 volts and 2 0 volts REV E 109200 The input capacitor should be sized to allow sufficient acquisi tion time of the clamp voltage at AIN within the CLAMP inter val but also be sized to minimize droop between clamping intervals Specifically the acquisition time when the switch is closed will equal T aco RinCin 3 where is the voltage change required across and Vz is the error voltage is calculated by taking the difference be tween the initial input dc level at the start of the clamp interval and the clamp voltage supplied at CLAMPIN is system dependent parameter and equals the maximum tolerable devia tion from Vc For example if a 2 volt input level needs to be clamped to 1 volt at the AD9200 s input within 10 millivolts then Vc equals 2 1 or 1 volt and Vg equals 10 mV Note that once the proper clamp level is attained at the input only a very small voltage change will be required to correct for droop The voltage droop is calculated with the following equation _ IBIAS dV 2 where time between clamping intervals The bias current of the AD9200 will depend on the sampling rate Fs The switched capacitor input AIN appears resistive over time with an input resistance equal to 1 CsFs Given a sampling rate of 20 MSPS and an input capacitance of 1 pF the input resistance is 50 This input resistance is equivalently termina
36. ted at the midscale voltage of the input range The worst case bias current will thus result when the input signal is at the extremes of the input range that is the furthest distance from the midscale voltage level For a 1 volt input range the maxi mum bias current will be 0 5 volts divided by 50 which is 10 pA If droop is a critical parameter then the minimum value of Cp should be calculated first based on the droop requirement Acquisition time the width of the CLAMP pulse can be adjusted accordingly once the minimum capacitor value is cho sen tradeoff will often need to be made between droop and acquisition time or error voltage Vg Clamp Circuit Example A single supply video amplifier outputs a level shifted video signal between 2 and 3 volts with the following parameters horizontal period 63 56 us horizontal sync interval 10 9 us horizontal sync pulse 4 7 us sync amplitude 0 3 volts video amplitude of 0 7 volts reference black level 2 3 volts The video signal must be dc restored from a 2 to 3 volt range down to a 1 to 2 volt range Configuring the AD9200 for a one volt input span with an input range from 1 to 2 volts see Figure 24 the CLAMPIN voltage can be set to 1 volt with an external voltage or by direct connection to REFBS The CLAMP pulse may be applied during the SYNC pulse or during the REV E back porch to truncate the SYNC below the AD9200 s mini mum input voltage With a
37. ymmetrical voltage threshold levels and sufficient rise and fall times to support 20 MSPS operation The AD9200 is designed to support a conversion rate of 20 MSPS running the part at slightly faster clock rates may be possible although at reduced performance levels Conversely some slight performance improvements might be realized by clocking the AD9200 at slower clock rates 51 52 ANALOG INPUT INPUT CLOCK lt 25ns DATA OUTPUT DATAS Figure 31 Timing Diagram The power dissipated by the output buffers is largely propor tional to the clock frequency running at reduced clock rates provides a reduction in power consumption DIGITAL INPUTS AND OUTPUTS Each of the AD9200 digital control inputs THREE STATE and STBY are reference to analog ground The clock is also referenced to analog ground The format of the digital output is straight binary see Figure 32 A low power mode feature is provided such that for STBY HIGH and the clock disabled the static power of the AD9200 will drop below 5 mW OTR FS41LSB FS FS ILSB Figure 32 Output Data Format THREE STATE tpuz HIGH IMPEDANCE Figure 33 Three State Timing Diagram DATA 00 09 15 109200 APPLICATIONS DIRECT IF DOWN CONVERSION USING THE AD9200 Sampling IF signals above an ADC s baseband region 1 dc to Fs 2 is becoming increasingly popular in communication applications This proc
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ANALOG DEVICES Complete 10 Bit 20 MSPS 80 mW CMOS A/D Converter AD9200 handbook