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SPANSION S29PL-N handbook

1. WE State Control Command PGM Voltage Register G t enero Chip Enable Output Enable CE Logic Data Latch OE gt Y Decoder Vcc Detector Timer 8 fo A A3 o m X Decoder Cell Matrix lt A2 A0 Notes 1 RY BY is an open drain output 2 Amar A23 PL256N A22 PL127N A21 PL129N 3 PL129N has two CE pins CE1 and CE2 8 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un 4 Connection Diagrams Physical Dimensions This section contains the 1 0 designations and package specifications for the S29PL256N 4 1 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth ods The package and or data integrity may be compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time 4 2 VBHO084 8 0 x 11 6 mm 4 2 1 Connection Diagram S29PL256N MCP Compatible Package Reserved for Future Use zo Ti c GEO a H c zm pul c gt m N gt m un gt N o gt e m E o on P d gt o5 gt DEGE wo Uo c re Fx ic i un 1o p a D N ya o m He g
2. 11 7 DC Characteristics 11 7 1 DC Characteristics Vcc 2 7 V to 3 6 V CMOS Compatible Parameter Parameter Description n Symbol Notes Test Conditions Input Load Current Vin Vss to Vec Vcc Vcc max 6 V Vss to Vcc OE V Output Leakage Current OUT SS ce IH j 4 Vcc Vcc max 6 OE V Vcc Active Read Current 1 3 IH 5 MHz cc L 3 Vee Vee max 1 6 Vec Active Write Current 3 OE Viu WE Vy CE 7 RESET Vcc Standby Current WP ACC Vec 10 3 V Vcc Reset Current RESET Vss 0 3 V Automatic Sleep Mode 4 Vin Vcc 0 3 V Vit Vss 0 3 V Vec Active Read While Write _ Current 1 SES Min Ste Vcc Active Program While Erase E Suspended Current 5 OE Vin OE Vip 8 word Vec Active Page Read Current Page Read Input Low Voltage Vcc 2 7 to 3 6 V Input High Voltage Vcc 2 7 to 3 6 V Voltage for ACC Program _ Acceleration Vcc 3 0 V 10 6 Output Low Voltage lo 100 pA Vcc Vec min 6 Output High Voltage lon 100 pA 6 Low Vcc Lock Out Voltage 5 Notes 1 The Icc current listed is typically less than 5 mA MHz with OE at Vip 2 Maximum lec specifications are tested with Vcc Vcc max TA Tamak Typical Icc specifications are with typical Vec 3 0 V Ta 25 C 3 lec is active while Embedded Erase or Embedded Program is in progress 4 Automatic sleep mode enables the low power mode when addresses remain stable for tacc 30 ns Ty
3. essse eee US E Input Waveforms and Measurement Levels sseeeee uwiii 61 Vee Powet Up Diagram uere een deponere E dhahama Read Operation TIMING uen een cun cune nene Ren Ken eeu eene nete eu Ente eu ne EA Page Read Operation Timings ssssssss nnns Reset TIMINGS osi ERE ie aa aa a NIU D IUD UIS UD E E CUPIT Program Operation TIMINGS ses cis ee eh a UR CR UR UR UR UR UR DR UR CR DE UR DR ER aga aaa E REN aa ga aa a aa aaa aa Accelerated Program Timing Diagram ssss nnn Chip Sector Erase Operation Timings Back to back Read Write Cycle Timings Data Polling Timings During Embedded Algorithms eeeeee 69 Toggle Bit Timings During Embedded Algoriths ccccccccccececeeeeeeeeeeeeeeeeeeeeeeees 69 DOZ ipo rm 70 SPANSION un November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family SPANSION Preliminary a Ordering Information The ordering part number is formed by a valid combination of the following S29PL 256 N 65 GA W WO 0 PACKING TYPE 0 Tray 2 7 inch Tape and Reel 3 13 inch Tape and Reel MODEL NUMBER Vcc Range WO 2 7 3 1V 2 7 3 6V TEMPERATURE RANGE Ww Wireless 25 C to 85 C l Industrial 40 C to 85 C PACKAGE TYPE AND MATERIAL FA Fortified BGA Lead Pb free Compliant package FF Fortified BGA Lead Pb free package GA Very Thin Fine Pitch MCP
4. ter wL CE Setup Time twHEH CE Hold Time twi WH Write Pulse Width tWHDL twpH Write Pulse Width High tsryw Latency Between Read and Write Operations twHwH1 twHwH1 Programming Operation twHwH1 twHwH1 Accelerated Programming Operation twHwH2 twHwH2 Sector Erase Operation tVHH Vhp Rise and Fall Times tre Write Recovery Time from RY BY tBusy Program Erase Valid to RY BY Delay twep Noise Pulse Margin on WE tsea Sector Erase Accept Time out tes Erase Suspend Latency test Program Suspend Latency tasp Toggle Time During Sector Protection Notes 1 Not 100 tested tpsp Toggle Time During Programming Within a Protected Sector 2 In program operation timing addresses are latched on the falling edge of WE 3 See Program Erase Operations for more information 4 Does not include the preprogramming time 66 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un Addresses WE Data RY BY Vcc 4 tvcs i Note PA program address PD program data Dour is the true data at the program address Figure 11 9 Program Operation Timings WP ACC Vic or Vip tVHH Figure ILIO Accelerated Program Timing Diagram November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flas
5. 0085h 0095h Program Suspend gogan 0 Not supported 1 Supported Unlock Bypass 00 Not Supported 01 Supported 0007h Secured Silicon Sector Customer OTP Area Size 2 bytes 0001h Hardware Reset Low Time out during an embedded algorithm to read mode Maximum 2 ns 000Eh Hardware Reset Low Time out not during an embedded algorithm to read mode Maximum 2 ns 0005h Erase Suspend Time out Maximum 2 us 0005h Program Suspend Time out Maximum 2 us Bank Organization EAE 00 Data at 4Ah is zero X Number of Banks 0013h PL256N 000Bh PL127N 000Bh PL129N 0030h PL256N 0018h PL127N 0018h PL129N Bank A Region Information X Number of sectors in bank 0030h PL256N Bank 1 Region Information X Number of sectors in bank 0018h PL127N 0018h PL129N 0013h PL256N 000Bh PL127N 000Bh PL129N Bank 2 Region Information X Number of sectors in bank Bank 3 Region Information X Number of sectors in bank November 23 2005 Q9PL N 00 M S29PL N MirrorBit Flash Family 77 Preliminary SPANSION un I3 Commonly Used Terms Term ACC Amax Amin Asynchronous Autoselect Bank Boot sector Boundary Burst Read Byte CFI Clear Configuration Register Continuous Read Erase Erase Suspend Erase Resume BGA Linear Read MCP Memory Array MirrorBit Technology P
6. increment destination pointer WA srctt increment source pointer if wc 0 goto confirm done when word count equals zero WC decrement word count SP goto loop do it again WA confirm UINT16 sector_address 0x0029 write confirm command x poll for completion Example Write Buffer Abort Reset UINT16 addr 0x555 0x00AA write unlock cycle 1 UINT16 addr 0x2AA 0x0055 write unlock cycle 2 UINT16 addr 0x555 OKOOFO write buffer abort reset WA November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 29 SPANSION Preliminary a Write Unlock Cycles Address 555h Data AAh Address 2AAh Data 55h Unlock Cycle 1 Unlock Cycle 2 Issue Write Buffer Load Command Address 555h Data 25h Load Word Count to Program Program Data to Address wc number of words 1 SA wc Confirm command SA lt 29h Wait 4 us Perform Polling Algorithm see Write Operation Status flowchart Write Next Word Write Buffer Decrement wc Abort Desired PA data wc wc 1 Write to a Different Sector Address to Cause Write Buffer Abort Polling Status Done Yes Write Buffer Abort RESET Issue Write Buffer FAIL Issue reset command PASS Device is in Abort Reset Command to return to read array mode read mode Figure 7 2 Write Buffer Programming Operation 7 4 3 Sector Erase The
7. 0x0000 7 4 9 Write Operation Status The device provides several bits to determine the status of a program or erase operation The following subsections describe the function of DQ1 DQ2 DQ3 DQ5 DQ6 and DQ7 DQ7 Data Polling The Data Polling bit DQ7 indicates to the host system whether an Em bedded Program or Erase algorithm is in progress or completed or whether a bank is in Erase Suspend Data Polling is valid after the rising edge of the final WE pulse in the command se quence Note that the Data Polling is valid only for the last word being programmed in the write buffer page during Write Buffer Programming Reading Data Polling status on any word other than the last word to be programmed in the write buffer page returns false status information During the Embedded Program algorithm the device outputs on DQ7 the complement of the datum programmed to DQ7 This DQ7 status also applies to programming during Erase Suspend When the Embedded Program algorithm is complete the device outputs the datum programmed to DQ7 The system must provide the program address to read valid status information on DQ7 If a program address falls within a protected sector Data polling on DQ7 is active for approxi mately tpsp then that bank returns to the read mode During the Embedded Erase Algorithm Data polling produces a 0 on DQ7 When the Embedded Erase algorithm is complete or if the bank enters the Erase Suspend mode Data Poll
8. 64 Ball Fortified Ball Grid Array S29PL N November 23 2005 9PL N 00 M S29PL N MirrorBit Flash Family 15 SPANSION u Preliminary MCP Look Ahead Connection Diagram Physical Dimensions 4 4 1 For All Page Mode MCPs Comprised of Code Flash p SRAM Data Flash it Wu at er KA NC NC NC NC Legend RFU NG NE NG NG Reserved for otis ont PN Future Use e 6 e 6 6 t ene ene ene RFU Ves RFU F2 CE FVcc N pRE N ALE N CLE N Vcc za Code Flash Only o0 009 Oo G ne RFU A7 R LB WP ACC WE A8 A11 NI CE x o 000 aa Only A3 A6 R UB F RST R1 CE2 A19 A12 A15 o Oo O O O O O O Fas bate A2 A5 A18 F RY BY A20 A9 A13 A21 Shared AA Li ooQo0 P0000 A1 A4 A17 R2 CEifor A23 A10 A14 A22 Flash xRAM es Shared we e Q AO Vss DQi R2 Vcc R2 CE2 or DQ6 A24 A16 or N Vcc N RE ji PSRAM Only o o o o Fi CE amp OE DQ9 DQ3 DQ4 DQi3 DQi15 RFU KRAM Shared ka Q Q Q of R1 CE1 DQO DQ10 F Vec Ri Vcc DQ12 DQ7 Vss sX NAND or pSRAM ooo dk Xa Ri Vcc DQ8 DQ2 DQii A25 DQ5 DQi4 N WP Mid NAND O 9 A27 A26 Vss F Vcc N2 CE R Vcco F Vio RFU VN D Nw wo nd NC NC NC NC DA ea D 209 NC NC NC NC i Notes 1 Fl and F2 denote KIP Code Flash while F3 and F4 denote Data Companion Flash 2 In addition to being defined as F2 CE Ball C5 can also be assigned as F1 CE2 for code flash that has two chip enable signals 3 F V
9. Notes 1 Typical program and erase times assume the following conditions 25 C 3 0 V Vcc 10 000 cycles Additionally programming typicals assume checkerboard pattern All values are subject to change 2 Under worst case conditions of 90 C Vcc 2 7 V 100 000 cycles All values are subject to change 3 The typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum program times listed 4 Inthe pre programming step of the Embedded Erase algorithm all bytes are programmed to 00h before erasure 5 System level overhead is the time required to execute the two or four bus cycle sequence for the program command See Table 12 1 and Table 12 2 for further information on command definitions 6 Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions 7 See Application Note Erase Suspend Resume Timing for more details 8 Word programming specification is based upon a single word programming operation not utilizing the write buffer 70 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary 11 8 6 BGA Ball Capacitance Parameter Symbol Parameter Description Input Capacitance Test Setup SPANSION un Output Capacitance Notes Control Pin Capacitance 1 Sampled not 100 tested 2 Test conditions T
10. 25 C f 1 0 MHz November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 71 SPANSION Preliminary a 72 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary I2 Appendix SPANSION un This section contains information relating to software control or interfacing with the Flash device For additional information and assistance regarding software see Additional Resources or ex plore the Web at www amd com and www fujitsu com Table 12 1 Memory Array Commands Manufacturer ID BA 555 BA X00 Device ID 10 BA 555 BA X01 BA XOE BA XOF Indicator Bits BA 555 BA X03 555 PA Write to Buffer 17 SA SA Program Buffer to Flash Write to Buffer Abort Reset 17 555 Chip Erase Unlock Bypass Entry ieee Unlock Bypass Program 12 13 Unloc Unlock Bypass Sector Erase 12 13 Bypass Mode Unlock Bypass Erase 12 13 Unlock Bypass CFI 12 13 Unlock Bypass Reset Secured Silicon Sector Command Definitions Secured Silicon Sector Entry 18 Secured a Secured Silicon Sector Program Silicon Sector Secured Silicon Sector Read Secured Silicon Sector Exit 19 Legend X Don t care RA Read Address RD Read Data PA Address of the memory location to be programmed Addresses latch on the falling edge of the WE or CE pu
11. All values are in hexadecimal Except for the following all bus cycles are write cycle read cycle fourth through sixth cycles of the Autoselect commands and password verify commands and any cycle reading at RD 0 and RD 1 Data bits DQ15 DQ8 are don t care in command sequences except for RD PD WD PWD and PWD3 PWDO Unless otherwise noted these address bits are don t cares PL127 A22 A15 129N A21 A15 PL256N A23 A14 Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state The system must write the reset command to return the device to reading array data No unlock or command cycles required when bank is reading array data The Reset command is required to return to reading array data or to the erase suspend read mode if previously in Erase Suspend when a bank is in the autoselect mode or if DQ5 goes high while the bank is providing status information or performing sector lock unlock The fourth cycle of the autoselect command sequence is a read cycle The system must provide the bank address See Autoselect The data is 0000h for an unlocked sector and 0001h for a locked sector Device IDs PL256N 223Ch PL127N 2220h PL129N 2221h See Autoselect The Unlock Bypass command sequence is required prior to this command sequence The Unlock Bypass Reset command is required to return to reading array data when t
12. 2 Maximum lec specifications are tested with Vcc Vcc max TA Tamak Typical lcc specifications are with typical Vec 2 9 V TA 25 C 3 lcc active while Embedded Erase or Embedded Program is in progress 4 Automatic sleep mode enables the low power mode when addresses remain stable for tacc 30 ns Typical sleep mode current is 1 pA 5 Not 100 tested 6 Data in table is for Vcc range 2 7 V to 3 1 V recommended for MCP applications 7 CE1 and CE2 for the PL129N November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 63 SPANSION Preliminary a 11 8 AC Characteristics 11 8 1 Read Operations Parameter Speed Options Description Notes Test Setup JEDEC Std 65 70 80 Read Cycle Time 1 Address to Output Delay CE OE Vi Chip Enable to Output Delay 5 OE Vy Page Access Time Output Enable to Output Delay Chip Enable to Output High Z 3 Output Enable to Output High Z 1 3 Output Hold Time From Addresses CE or OE Whichever Occurs First 3 Read Output Enable Hold Time 1 Toggle and Data Polling Notes 1 Not 100 tested 2 See Figure 11 3 and Table 11 1 for test specifications 3 Measurements performed by placing a 50 ohm termination on the data pin with a bias of Vcc 2 The time from OE high to the data bus driven to Vcc 2 is taken as tpr 4 For 70pf Output Load Capacitance 2 ns is
13. O o m c 4 7 o z 8 o a M n c 2 e e g GEZE eo 00 60 Jg N wa eo Mg ROO N N RFU a c Vcc Notes 1 Top view balls facing down 2 Recommended for wireless applications Figure 4 1 Connection Diagram 84 ball Fine Pitch Ball Grid Array S29PL256N November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 9 iN SPANSION Preliminary un 4 2 2 Physical Dimensions VBHO84 8 0 x 11 6 mm 0 05 c D IA D1 2x al 1 H 7 1 QwuO QuO OQ CO OO 9 e OOOOOOOoOooOoO0 8 A 15 0000 00000 7 ji ji ji ji ji i 00090 0 0 0 0 6 1 41 H 0000000009 5 0000000000 OO000j0O0000 3 1 00 00 0 O0 0 00 0 2 o Y IM L K J H F E D c B A bw CORNER A1 CORNER B SDA INDEX MARK AN A AN m NX b 60 08 Mc TOP VIEW Pos Wa BOTTOM VIEW A A2 0 10 C i OC U U OU UAU LD ULGOUOXI E A1 WA I Soost SEATING PLANE SIDE VIEW NOTES PACKAGE VBH 08
14. PL256N Sector and Memory Address Map 19 Table 6 2 PL127N Sector and Memory Address Map 20 Table 6 3 PL129N Sector and Memory Address Map 20 Table 7 1 Device Operation ssaa naaa hh 21 Table 7 2 Dual Chip Enable Device Operation 22 Table 7 3 Word SelectionwithinaPage 23 Table 7 4 Autoselect Codes tee 24 Table 7 5 AutoselecEEntry s escuela ee cee PGS NUAGE ERREUR RUE ee AC de eA 24 Table 7 6 Autoselect EkKit ee nem se o RR ex ERROR RO AO RE ROS Rn 24 Table 7 7 Single Word Program iilis hh 27 Table 7 8 Write Buffer Program iilis hh 29 Table 7 0 SectorErases 2 3 2 aia Sie eb aa akan ee anew a EE eA UR NEQUE EUCH RR A NR RUE 31 Table 7 10 Chip Erase suse WAA drat alas AU aaa 33 Tanu Erase Susp nd ss a ian sess IIIA BA a A AA EA aa 34 Table 7 12 Eras R SWMe sr ssi cite re rg iaai ar nue Rd Ro d AAA ma dud 34 Table 1 13 Program Suspendi aa does ba ee eG WA dn aaa BN a BENE bw Rd 35 Table 7 14 Program Resume issue ER eo be ENNENERRNR GA EREBEXCRIGOEUR E EI 35 Table 7 15 Unlock Bypass ENG a nicis ooi doy CREER Een HR dox ER Pe ham d ALEGRE Roe e 36 Table 7 16 Unlock Bypass Program sasaaa aaa 37 Table 7 17 Unlock Bypass Reset lsssiiesee eh hh 37 Table 7 18 Write Operation Status hh 42 T
15. 12 1 that also returns the device to array read mode and must be used for the following conditions 1 To exit Autoselect mode 2 Toreset software when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3 To exit sector lock unlock operation 4 Toreturn to erase suspend read mode if the device was previously in Erase Suspend mode 5 To reset software after any aborted operations Software Functions and Sample Code Table 7 19 Reset LLD Function lld ResetCmd Note Base Base Address The following is a C source code example of using the reset function Refer to the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example Reset software reset of Flash state machine UINT16 base addr 0x000 OKOOFO The following are additional points to consider when using the reset command W This command resets the banks to the read and address bits are ignored W Reset commands are ignored once erasure has begun until the operation is complete W Once programming begins the device ignores reset commands until the operation is com plete W Thereset command may be written between the cycles in a program command sequence be fore programming begins prior to the third cycle This resets the bank to which the system was writing to the read
16. 23 2005 9PL N 00 M S29PL N MirrorBit Flash Family I9 SPANSION un Preliminary Table 6 2 PLI27N Sector and Memory Address Map Sector Size KB Sector Sector Range Address Range 000000h 007FFFh 008000h 00FFFFh 010000h 017FFFh 018000h O1FFFFh Sector Starting Address Sector Ending Address 020000h 03FFFFh OE0000h OFFFFFh Sector Starting Address Sector Ending Address see note 100000h 11FFFFh 3E0000h 3FFFFFh First Sector Sector Starting Address Last Sector Sector Ending Address see note 400000h 41FFFFh 6E0000h 6FFFFFh First Sector Sector Starting Address Last Sector Sector Ending Address see note 700000h 71FFFFh 7C0000h 7DFFFFh 7E0000h 7E7FFFh 7E80000h 7EFFFFh 7F0000h 7F7FFFh 7F8000h 7FFFFFh Sector Starting Address Sector Ending Address see note Sector Starting Address Sector Ending Address Note Ellipses indicate that other addresses in sector range follow the same pattern Table 6 3 PLI29N Sector and Memory Address Map Sector Size KB Sector Sector Address Range Range 000000h 007FFFh 008000h O0FFFFh 010000h 017FFFh 018000h O1FFFFh Sector Starting Address Sector Ending Address 020000h 03FFFFh OE0000h OFFFFFh Sector Starting Address Sector Ending Address see note 100000h 11FFFFh 3E0000h 3FFFFFh First Sector Sector Starting Address
17. 4 Connection Diagram 64 Ball Fine Pitch Ball Grid Array S29PLI29N 12 S29PL N MirrorBit Flash Family S29PL N_00_A4 November 23 2005 Prel iminary iN SPANSION e 4 3 3 Physical Dimensions VBHO64 8 x 11 6 mm S29PL N Mlo 05 c D IX wa Di 2x ele i 4 t ok ok a 000000 9 e 000000004 gt A SE 000000004144 7 ji li f g f ii li E i 4 0000 0000 Lom 0000 l 0000 5 1 000000004 4 4 4000000004 3 00Q0 00084 2 1 Q tle op IM L K J H F E D c B A ca CORNER A1 CORNER B jo SD 7 INDEK MARK AN A 10 05 C BA NXob H TOP VIEW peoe Ole 100 15 cla Be BOTTOM VIEW i A A2 P c OO COE DE Eby l i A1 C ON c SEATING PLANE SIDE VIEW NOTES PACKAGE VBH 064 JEDE NA 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 ALL DIMENSIONS ARE IN MILLIMETERS 11 60 mm x 8 00 mm NOM 3 BALL POSITION DESIGNATION PER JESD 95 1 SPP 010 EXCEPT PACKAGE AS NOTED SYMBOL MIN NOM MAX NOTE 4 e REPRESENTS THE SOLDER
18. 576 S29PL127N 7OFA OOO hy FS S29PL N MirrorBit Flash Family 29PL256N S29PLI27N S29PLI29N 256 128 128 Mb 16 8 8 M x 16 Bit CMOS 3 0 Volt only SPANSION Simultaneous Read Write Page Mode Flash Memory Notice to Readers This document indicates states the current technical specifications regarding the Spansion product s described herein The Preliminary status of this document indicates that a product qualification has been completed and that initial production has begun Due to the phases of the manufacturing process that require maintaining efficiency and quality this document may be revised by subsequent versions or modifications due to changes in technical specifications Publication Number S29PL N_00 Revision A Amendment 4 Issue Date November 23 2005 SPANSION Preliminary a Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle includ ing development qualification initial production and full production In all cases however readers are encouraged to verify that they have the latest information before finalizing their de sign The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions Advance Information The Advance Information designation indicates that Spansion LLC is
19. Address The bank address is required 3 base base address The following is a C source code example of using the autoselect function to read the manufac turer ID See the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines 24 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un Here is an example of Autoselect mode getting manufacturer ID Define UINT16 example typedef unsigned short UINT16 UINT16 manuf_id Auto Select Entry UINT16 bank_addr 0x555 UINT16 bank_addr 0x2AA UINT16 bank_addr 0x555 OKOGAA write unlock cycle 1 0x0055 write unlock cycle 2 0x0090 write autoselect command multiple reads can be performed after entry manuf id UINT16 bank addr 0x000 read manuf id Autoselect exit UINT16 base addr 0x000 Ox00F0 exit autoselect write reset command November 23 2005 Q9PL N 00 M S29PL N MirrorBit Flash Family 25 SPANSION Preliminary a 7 4 Program Erase Operations 7 4 1 These devices are capable of single word or write buffer programming operations which are de scribed in the following sections The write buffer programming is recommended over single word programming as it has clear benefits from greater programming efficienc
20. DQ6 DQ2 Whenever the system initially begins reading toggle bit status it must read DQ7 DQO at least twice in a row to determine whether a toggle bit is toggling Typ ically the system would note and store the value of the toggle bit after the first read After the second read the system would compare the new value of the toggle bit with the first If the toggle bit is not toggling the device has completed the program or erases operation The system can read array data on DQ7 DQO on the following read cycle However if after the initial two read cycles the system determines that the toggle bit is still toggling the system also should note whether the value of DQ5 is high see the section on DQ5 If it is the system should then deter mine again whether the toggle bit is toggling since the toggle bit might have stopped toggling just as DQ5 went high If the toggle bit is no longer toggling the device has successfully com pleted the program or erases operation If it is still toggling the device did not complete the operation successfully and the system must write the reset command to return to reading array data The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high The system may continue to monitor the toggle bit and DQ5 through 40 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un successive read cycles determining
21. Last Sector Sector Ending Address see note 000000h O1FFFFh 2E0000h 2FFFFFh First Sector Sector Starting Address Last Sector Sector Ending Address see note 300000h 31FFFFh 3C0000h 3DFFFFh Sector Starting Address Sector Ending Address see note 3E0000h 3E7FFFH 3E8000h 3EFFFFh 3F0000h 3F7FFFh 3F8000h 3FFFFFh Sector Starting Address Sector Ending Address 20 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un 7 Device Operations This section describes the read program erase simultaneous read write operations and reset features of the Flash devices Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers see Table 12 1 and Table 12 2 The command regis ter itself does not occupy any addressable memory location Instead the command register is composed of latches that store the commands along with the address and data information needed to execute the command The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device Writing incorrect ad dress and data values or writing them in an improper sequence can place the device in an unknown state in which case the system must write the reset command to return the device to the reading array data
22. ProgramCmd Cycle Operation Word Address Data Unlock Cycle 1 Base 555h 00AAh Unlock Cycle 2 Base 2AAh 0055h Program Setup Base 555h 00A0h Program Word Address Data Word Note Base Base Address The following is a C source code example of using the single word program function See the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example Program Command x UINT16 base addr 0x555 0x00AA write unlock cycle 1 y UINT16 base addr 0x2AA 0x0055 write unlock cycle 2 id UINT16 base addr 0x555 0x00A0 write program setup command WA UINT16 pa data write data to be programmed ud Poll for program completion November 23 2005 Q9PL N 00 M S29PL N MirrorBit Flash Family 27 SPANSION Preliminary a 7 4 2 Write Buffer Programming Write Buffer Programming allows the system to write a maximum of 32 words in one program ming operation This results in a faster effective word programming time than the standard word programming algorithms The Write Buffer Programming command sequence is initiated by first writing two unlock cycles This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs At this point the system writes the number of word locations
23. SPANSION Preliminary a See Table 12 1 for command sequence details Table 7 4 Autoselect Codes Description DQI5 to DQO Manufacturer ID 0001h Read Cycle 1 227Eh ur 223Ch PL256N Cyde 2 2220h PL127N 2221h PL129N n 2200h PL256N Cyele 3 2200h PL127N 2200h PL129N 0000h Unprotected Sector Neither DYB nor PPB Locked Protection 0001h Verification Device ID Protected Either DYB or PPB Locked DQ15 DQ8 0 DQ7 Factory Lock Bit 1 Locked 0 Not Locked DQ6 Customer Lock Bit 1 Locked 0 Not Locked DA Handshake Bit Reserved Indicator Bit 0 Standard Handshake DQ4 amp DQ3 WP Protection Boot Code 00 WP Protects both Top Boot and Bottom Boot Sectors 11 No WP Protection DQ2 DQ0 0 Legend L Logic Low Vip H Logic High Vjy BA Bank Address SA Sector Address X Don t care Note For the PL129N Either CE1 or CE2 must be low to access Autoselect Codes Software Functions and Sample Code Table 7 5 Autoselect Entry LLD Function lld AutoselectEntryCmd Cycle Operation Word Address Data Unlock Cycle 1 BAx555h 0x00AAh Unlock Cycle 2 BAx2AAh 0x0055h Autoselect Command BAx555h 0x0090h Table 7 6 Autoselect Exit LLD Function Illd AutoselectExitCmd Cycle Operation Word Address Data Notes 1 Any offset within the device works 2 BA Bank
24. Two CE inputs control selection of each half of the memory space m Single Power Supply Operation Full Voltage range of 2 7 3 6 V read erase and program operations for battery powered applications Voltage range of 2 7 3 1 V valid for PL N MCP products m Simultaneous Read Write Operation Data can be continuously read from one bank while executing erase program functions in another bank Zero latency switching from write to read operations m 4 Bank Sector Architecture with Top and Bottom Boot Blocks m 256 Word Secured Silicon Sector Region Up to 128 factory locked words Up to 128 customer lockable words Manufactured on 0 11 um Process Technology Data Retention of 20 years Typical Cycling Endurance of 100 000 Cycles per Sector Typical Performance Characteristics Read Access Times 30 pF Industrial Temp Random Access Time ns tacc Page Access Time ns tpAcc Max CE Access Time ns tcg Max OE Access Time ns tog Current Consumption typical values 8 Word Page Read Simultaneous Read Write Program Erase Standby Hardware Features m WP ACC Write Protect Acceleration Input At Vj hardware level protection for the first and last two 32 Kword sectors At Vip allows the use of DYB PPB sector protection At Vyp provides accelerated programming in a factory setting m Dual Boot and No Boot Options m Low Vcc Write Inhibit Security Fea
25. added to the above tacc tce tpacc tog values for all speed grades 5 CE1 and CE2 for the PL129N 11 8 2 Read Operation Timing Diagrams Addresses CE OE WE pata RI v D RESET RY BY Figure 11 6 Read Operation Timings 64 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un A22 to A3 Same page Addresses la p de a pt pe cL gt a CE me OE emm Em ws Se cone e _HEHEDEDE DEDEDE 0 Figure II 7 Page Read Operation Timings 11 8 3 Hardware Reset RESET Parameter All Speed Options Description JEDEC RESET Pulse Width Reset High Time Before Read See Note Note Not 100 tested CE OE tay RESET N n he trp gt Figure 11 8 Reset Timings November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 65 SPANSION un Preliminary 11 8 4 Erase Program Timing Parameter JEDEC Description Notes Write Cycle Time 1 Speed Options 65 70 80 Address Setup Time Address Setup Time to OE low during toggle bit polling Address Hold Time Address Hold Time From CE or OE high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling tauwL Read Recovery Time Before Write OE High to WE Low
26. array data The system can read CFI in formation at the addresses given in Tables 12 3 12 6 within that bank All reads outside of the CFI address range within the bank return non valid data Reads from other banks are allowed writes are not To terminate reading CFI data the system must write the reset command The following is a C source code example of using the CFI Entry and Exit functions Refer to the Spansion Low Level Driver User s Guide available at www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example CFI Entry command UINT16 bank addr 0x555 0x0098 write CFI entry command ay Example CFI Exit command UINT16 bank addr 0x000 Ox00F0 write cfi exit command yr November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 75 SPANSION Preliminary a For further information please see the CFI Specification see JEDEC publications JEP137 A and JESD68 01and CFI Publication 100 Please contact your sales office for copies of these documents Table 12 3 CFI Query Identification String Addresses Description Query Unique ASCII string QRY Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set 00h none exists Address for Alternate OEM Extended Table 00h none exists Table 12 4 System Interface String Addresses Description 1Bh Vcc Min writ
27. compatible BGA Lead Pb free Compliant Package GF Very Thin Fine Pitch MCP compatible BGA Lead Pb free Package SPEED OPTI ON 65 65ns 70 70ns 80 80ns PROCESS TECHNOLOGY N 110 nm MirrorBit Technology FLASH DENSITY 256 256Mb 129 128 Mb Dual CE 127 128 Mb Single CE Ld DEVICE FAMILY S29PL 3 0 Volt only Simultaneous Read Write Page Mode Flash Memory Valid Combinations Package Type Base Ordering Speed Package Type Material Model Packing Vio Range Note 2 Part Number Option amp Temperature Range Number Type VBHO84 8 0 x 11 6 mm S29PL256N 84 ball MCP Compatible FBGA S29PL127N VBHO64 8 0 x 11 6 mm S29PL129N 64 ball MCP Compatible FBGA S29PL256N LAA064 11x13 mm S29PL127N 64 Ball Fortified BGA Notes 1 Type 0 is standard Specify other options as required Valid Combinations 2 BGA package marking omits leading S29 and packing Valid Combinations list configurations planned to be type designator from ordering part number supported in volume for this device Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations 6 S29PL N MirrorBit Flash Family S29PL N_00_A4 November 23 2005 Preliminary SPANSION un 2 Input Output Descriptions and Logic Symbols Table 2 1 identifies the input and output package connections provided on the devic
28. developing one or more spe cific products but has not committed any design to production Information presented in a document with this designation is likely to change and in some cases development on the prod uct may discontinue Spansion LLC therefore places the following conditions upon Advance Information content This document contains information on one or more products under development at Spansion LLC The information is intended to help you evaluate this product Do not design in this product without con tacting the factory Spansion LLC reserves the right to change or discontinue work on this proposed product without notice Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place This designation covers several aspects of the product life cycle including product qualification initial production and the subsequent phases in the manufacturing process that occur before full production is achieved Changes to the technical specifications presented in a Preliminary document should be expected while keeping these as pects of production under consideration Spansion places the following conditions upon Preliminary content This document states the current technical specifications regarding the Spansion product s described herein The Preliminary status of this document indicates that product qualification has been completed and that
29. each additional cycle is written e The host system may monitor DQ3 or wait tee to ensure acceptance of erase commands e No limit on number of sectors e Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data Status may be obtained by reading DQ7 DQ6 and or DQ2 Error condition Exceeded Timing Limits Figure 7 3 Sector Erase Operation Sequence Chip erase is a six bus cycle operation as indicated by Table 12 1 These commands invoke the Embedded Erase algorithm which does not require the system to preprogram prior to erase The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase The system is not required to provide any controls or timings during these operations The Command Definition tables Table 12 1 and Table 12 2 show the address and data requirements for the chip erase command sequence 32 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un When the Embedded Erase algorithm is complete that bank returns to the read mode and ad dresses are no longer latched The system can determine the status of the erase operation by using DQ7 or DQ6 DQ2 See Write Operation Status for information on these status bits Any commands written during the chip erase operation are ignored However note that a hard ware reset immediat
30. mode m f the program command sequence is written to a bank that is in the Erase Suspend mode writing the reset command returns that bank to the erase suspend read mode W The reset command may be also written during an Autoselect command sequence 46 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un W fa bank has entered the Autoselect mode while in the Erase Suspend mode writing the reset command returns that bank to the erase suspend read mode m If DQ1 goes high during a Write Buffer Programming operation the system must write the Write to Buffer Abort Reset command sequence to RESET the device to reading array data The standard RESET command does not work during this condition W To exit the unlock bypass mode the system must issue a two cycle unlock bypass reset com mand sequence see command tables for detail November 23 2005 9PL N 00 M S29PL N MirrorBit Flash Family 47 SPANSION Preliminary a 8 Advanced Sector Protection Unprotection The Advanced Sector Protection Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and or hardware meth ods which are independent of each other This section describes the various methods of protecting data stored in the memory array An overview of these methods in shown in Figure 8 1 Hardware Methods Software Methods Lock Register
31. program operation using the DQ7 or DQ6 status bits just as in the standard program operation See Write Operation Status for more information The system must write the Program Resume command address bits are don t cares to exit the Program Suspend mode and continue the programming operation Further writes of the Program Resume command are ignored Another Program Suspend command can be written after the de vice has resumed programming Software Functions and Sample Code Table 7 13 Program Suspend LLD Function lld ProgramSuspendCmd Cycle Operation Word Address Data The following is a C source code example of using the program suspend function Refer to the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example Program suspend command UINT16 base_addr 0x000 0x00B0 write suspend command WA Table 7 14 Program Resume LLD Function lld ProgramResumeCmd Cycle Operation Word Address Data The following is a C source code example of using the program resume function Refer to the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example Program resume command UINT16 base_addr 0x000 0x0030 write resume command WA 7 4 7 Accelerated Pro
32. sector erase function erases one or more sectors in the memory array See Table 12 1 and Figure 7 3 The device does not require the system to preprogram prior to erase The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pat tern prior to electrical erase The system is not required to provide any controls or timings during these operations After the command sequence is written a sector erase time out of no less than tse occurs Dur ing the time out period additional sector addresses and sector erase commands can be written Loading the sector erase buffer can be done in any sequence and the number of sectors can be from one sector to all sectors The time between these additional cycles must be less than tsga Any sector erase address and command following the exceeded time out tggA may or may not 30 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un be accepted Any command other than Sector Erase or Erase Suspend during the time out period resets that bank to the read mode The system can monitor DQ3 to determine if the sector erase timer has timed out see DQ3 Sector Erase Timeout State Indicator The time out begins from the rising edge of the final WE pulse in the command sequence When the Embedded Erase algorithm is complete the bank returns to reading array data and ad dresses are no longer latched Note that while the Emb
33. that support Write Buffer Programming See Table 12 1 for the re quired bus cycles and Figure 7 1 for the flowchart When the Embedded Program algorithm is complete the device then returns to the read mode and addresses are no longer latched The system can determine the status of the program oper ation by using DQ7 or DQ6 See Write Operation Status for information on these status bits Single word programming is supported for backward compatibility with existing Flash driver soft ware and use of write buffer programming is strongly recommended for general programming The effective word programming time using write buffer programming is approximately four times faster than the single word programming time 26 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un Write Unlock Cycles Address 555h Data AAh Address 2AAh Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Program Command Setup Command Address 555h Data AOh Program Address PA Program Data to Address Program Data PD PA PD Perform Polling Algorithm see Write Operation Status flowchart Polling Status Busy Polling Status Done Error condition Exceeded Timing Limits PASS Device is in FAIL Issue reset command read mode to return to read array mode Figure 7 1 Single Word Program Operation Software Functions and Sample Code Table 7 7 Single Word Program LLD Function lld
34. the device draws CMOS standby current Icc4 If RESET is held at Vi but not within Vss 0 2 V the standby current is greater RESET may be tied to the system reset circuitry and thus a system reset would also reset the Flash memory enabling the system to read the boot up firmware from the Flash memory 9 4 Output Disable OE When the OE input is at Vip output from the device is disabled The outputs are placed in the high impedance state November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 55 SPANSION Preliminary a IO Secured Silicon Sector Flash Memory Region 10 1 The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number ESN The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words for customer secured areas All Secured Silicon reads outside of the 256 word address range returns invalid data The Factory Indicator Bit DQ7 at Autoselect address 03h is used to indicate whether or not the Factory Se cured Silicon Sector is locked when shipped from the factory The Customer Indicator Bit DQ6 is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped from the factory Note the following general conditions m While the Secured Silicon Sector access is enabled simultaneous operations are allowed ex cept for Bank A W On powe
35. the required state of each control pin for any particular operation November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 21 SPANSION Preliminary a Table 7 2 Dual Chip Enable Device Operation Addresses Operation RESET WPZ ACC A21 A0 DQI5 DQO Write Standby Output Disable Reset Temporary Sector Unprotect High Voltage Legend L Logic Low Vip H Logic High Vi VID 11 5 12 5 V Vy 8 5 9 5 V X Don t Care SA Sector Address An Address In D y Data In Dour Data Out Notes 1 The sector and sector unprotect functions may also be implemented by programming equipment 2 WP ACC must be high when writing to the upper two and lower two sectors 7 2 Asynchronous Read The internal state machine is set for reading array data upon device power up or after a hardware reset This ensures that no spurious alteration of the memory content occurs during the power transition No command is necessary in this mode to obtain array data Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs Each bank remains enabled for read access until the command register con tents are altered 7 2 1 Non Page Random Read Address access time tacc is equal to the delay from stable addresses to valid output data The chip enable access time tce is the delay fr
36. the status as described in the previous paragraph Alterna tively it can choose to perform other system tasks In this case the system must start at the beginning of the algorithm when it returns to determine the status of the operation Refer to Figure 7 4 Write Operation Status Flowchart for more details DQ5 Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit Under these conditions DQ5 produces a 1 indicating that the program or erase cycle was not successfully completed The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0 Only an erase operation can change a 0 back to a 1 Under this condition the device halts the operation and when the timing limit has been exceeded DQ5 produces a 1 Under both these conditions the system must write the reset command to return to the read mode or to the erase suspend read mode if a bank was previously in the erase suspend program mode DQ3 Sector Erase Timeout State I ndicator After writing a sector erase command sequence the system may read DQ3 to determine whether or not erasure has begun The sector erase timer does not apply to the chip erase command If additional sectors are selected for erasure the entire time out also applies after each additional sector erase command When the time out period is complete DQ3 switches from a 0 to a 1 If the time betwe
37. to Switching Waveforms ssssssssesseee 60 I 5 Switching Waveforms aee eaaa IH Hm 6l I6 Vee Power Up iijar rana e Ever er rerai a BA ag a Na Bg BI TEE E A NR uev Y 6l I7 IDC Characteristics sci seid cheer er Ru eI ER ERIT RET BAE RA UO REA ERR 62 II 7 1 DC Characteristics Vcc 27 V to 36 V 62 1 7 2 DC Characteristics Vcc 2 7 V to 31 V 63 UB AC Characteristics eei chs eere tem t hr rr rechter ee e mere e dee 64 ILS Read Operations 5 ceo cae eee erem eR Rr he ex n ERR Ree 64 11 8 2 Read Operation Timing Diagrams 64 1 8 3 Hardware Reset RESET 65 11 84 Erase Program Timing 66 11 8 5 Erase and Programming Performance 70 11 8 6 BGA Ball Capacitance 71 I2 Appendix re ehm e a EN ere ace TAN E ET E aS 73 12 1 Common Flash Memory Interface 75 I3 Commonly Used Terms 78 Id Revisions II Ka aana E ia Ga a a Ta aa TE Ta a Ba ENG aaa aa 82 November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 3 SPANSION Preliminary a Tables Table 2 1 Input Output Descriptions 7 Table 6 1
38. 2 43 BULOSCIECE conce ag A a DAGAN Ka A eR aa nie aa S dene ee 23 74 Program Erase Operations saenake 26 74 1 Single Word Programming 26 742 Write Buffer Programming eee eee eea e 28 TAS Sector Erase apana ag ra vos Bg od A deg naa a a Wea na bodie PERRO E wb 30 744 Chip Erase Command Seguence 32 7 45 Erase Suspend Erase Resume Commands 33 74 6 Program Suspend Program Resume Commands 34 744 Accelerated Program cece cece eee eee men 35 7 48 Unlock Bi IIIA 36 74 9 Write Operation Status 37 75 Simultaneous Read Write awnnensnnnnon 43 7 6 Writing Commands Command Seguences 45 TI Hardware Ri tp esee e aga Ta ah ecri RS TO GA AN E BR BAB REY AK a AR mane 46 7 8 Software Reset NBK AG dud AYE AS e A hd TET aaa ANAN a a DN Bag ERU ag aa a 46 8 Advanced Sector Protection Unprotection 48 8 1 Lock Register once anaa a E tad EA TEN EUER ens PEE e ERN ERR HU RR 49 8 2 Persistent Protection Bits cece eee teen eene hee 49 83 Dynamic Protection BA Ia aa 50 8 4 Persistent Protection Bit Lock Bit 50 8 5 Password Protection Method cece cece eee 5 8 6 Adv
39. 4 PI ja SUED NA DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 ALL DIMENSIONS ARE IN MILLIMETERS 11 60 mm x 8 00 mm NOM BALL POSITION DESIGNATION PER JESD 95 1 SPP 010 EXCEPT PACKAGE AS NOTED SYMBOL MIN NOM MAX NOTE REPRESENTS THE SOLDER BALL GRID PITCH A E E 1 00 OVERALL THICKNESS SYMBOL MD IS THE BALL ROW MATRIX SIZE IN THE A1 0 18 BALL HEIGHT D DIRECTION A2 0 62 ds 0 76 BODY THICKNESS SYMBOL ME IS THE BALL COLUMN MATRIX SIZE IN THE E DIRECTION D 11 60 BSC BODY SIZE E 500 BSC BUNTE N IS THE TOTAL NUMBER OF SOLDER BALLS ZA DIMENSION b IS MEASURED AT THE MAXIMUM BALL D1 8 80 BSC BALL FOOTPRINT DIAMETER IN A PLANE PARALLEL TO DATUM C E1 7 20 BSC BALL FOOTPRINT YA SD AND SE ARE MEASURED WITH RESPECT TO DATUMS MD 12 ROW MATRIX SIZE D DIRECTION A AND B AND DEFINE THE POSITION OF THE CENTER ME 10 ROW MATRIX SIZE E DIRECTION PALPER ACEITE AMER BAN WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN N 84 TOTAL BALL COUNT THE OUTER ROW PARALLEL TO THE D OR E DIMENSION ob 0 33 m 0 43 BALL DIAMETER RESPECTIVELY SD OR SE 0 000 e 0 80 BSC BALL PITCH WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN SD SE 0 40 BSC SOLDER BALL PLACEMENT THE OUTER ROW SD OR SE eer 8 NOT USED A2 A9 B10 L10 DEPOPULATED SOLDER BALLS M2 M9 B1 L1 9 INDICATES THE THEORETICAL CENTER OF DEPOPULATED Note Recommended for wireless applications BALLS Ad A1 CORNER TO BE IDENTIFIED BY CHAMFER LASER OR INK MARK M
40. 4 cycle Program command are not required reducing all Program commands to two bus cycles while in this mode Two contiguous bytes 16 bits located at an even byte boundary A double word is two contiguous words located on a two word boundary A quad word is four contiguous words located on a four word boundary November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 79 Preliminary SPANSION un Term Definition Special burst read mode where the read address wraps or returns back to the lowest Wraparound Write Write Buffer Write Buffer Programming Write Operation Status address boundary in the selected range of words after reading the last Byte or Word in the range e g for a 4 word range of 0 to 3 a read beginning at word 2 would read words in the sequence 2 3 0 1 Interchangeable term for a program erase operation where the content of a register and or memory location is being altered The term write is often associated with writing command cycles to enter or exit a particular mode of operation Multi word area in which multiple words may be programmed as a single operation A Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively Method of writing multiple words up to the maximum size of the Write Buffer in one operation Using Write Buffer Programming results in greater than eight times faster programming time than by using single word at a tim
41. 9PL N MirrorBit Flash Family S29PL N_00_A4 November 23 2005 Preliminary SPANSION un Table 12 6 Primary Vendor Specific Extended Query Addresses Description Query unique ASCII string PRI Major version number ASCII reflects modifications to the silicon Minor version number ASCII reflects modifications to the CFI table Address Sensitive Unlock Bits 1 0 0 Required 1 Not Required Silicon Technology Bits 5 2 0100 0 11 um Erase Suspend 0 Not Supported 1 To Read Only 2 To Read amp Write Sector Protect 0 Not Supported X Number of sectors in per group Sector Temporary Unprotect 00 Not Supported 01 Supported Sector Protect Unprotect scheme 01 29F040 mode 02 29F016 mode 03 29F400 mode 04 29LV800 mode 07 New Sector Protect mode 08 Advanced Sector Protection 0008h PL N 0073h PL256N 003Bh PL127N Simultaneous Operation 003Bh PL129N 00 Not Supported X Number of Sectors except Bank A Burst Mode Type 0000h 00 Not Supported 01 Supported E Page Mode Type 0002h PL N 00 Not Supported 01 4 Word Page 02 8 Word Page ACC Acceleration Supply Minimum 00h Not Supported D7 D4 Volt D3 D0 100 mV ACC Acceleration Supply Maximum 00h Not Supported D7 D4 Volt D3 D0 100 mV Top Bottom Boot Sector Flag 0001h 00h No Boot 01h Dual Boot Device 02h Bottom Boot Device 03h Top Boot Device
42. AA write unlock cycle 1 WA UINT16 base addr 0x2AA 0x0055 write unlock cycle 2 WA UINT16 base_addr 0x555 00090 write SecSi Sector Exit cycle 3 UINT16 base addr 0x000 0x0000 write SecSi Sector Exit cycle 4 58 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un Il Electrical Specifications ILI Absolute Maximum Ratings Storage Temperature Plastic Packages ch dawns hh E E E ds ee hula woes eek Paw RR wok Paes A 65 C to 150 C Ambient Temperature withPowerApplied 65 C to 125 C Voltage with Respect to Ground All Inputs and I Os except as noted below Note 1l 0 5 V to Vio 0 5 V Vee Nte reaa ai a a a a ak ee AA Dae n dus a a wa ade md dd 0 5 V to 4 0 V Vio CORRES 2 MP T 0 5 V to 4 0V ACC NOES 2 rr 0 5 V to 10 5 V Output Short Circuit Current Note 3 200 mA Notes 1 Minimum DC voltage on input or I Os is 0 5 V During voltage transitions inputs or I Os may undershoot Vss to 2 0 V for periods of up to 20 ns See Figure 11 1 Maximum DC voltage on input or I Os is Vcc 0 5 V During voltage transitions outputs may overshoot to Vcc 2 0 V for periods up to 20 ns See Figure 11 2 2 Minimum DC input voltage on pin WP ACC is 0 5 V During voltage transitions WP ACC may overshoot Vss to 2 0 V for perio
43. BALL GRID PITCH A ad 1 00 OVERALL THICKNESS SYMBOL MD IS THE BALL ROW MATRIX SIZE IN THE A1 0 18 BALL HEIGHT D DIRECTION A2 0 62 0 76 BODY THICKNESS SYMBOL ME IS THE BALL COLUMN MATRIX SIZE IN THE E DIRECTION D 11 60 BSC BODY SIZE 560 Bsc BOOY size NIS THE TOTAL NUMBER OF SOLDER BALLS f ZA DIMENSION b IS MEASURED AT THE MAXIMUM BALL D1 8 80 BSC BALL FOOTPRINT DIAMETER IN A PLANE PARALLEL TO DATUM C E1 7 20 BSC BALL FOOTPRINT 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS MD 12 ROW MATRIX SIZE D DIRECTION A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW ME 10 ROW MATRIX SIZE E DIRECTION WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN N 64 TOTAL BALL COUNT THE OUTER ROW PARALLEL TO THE D OR E DIMENSION b 0 33 m 0 43 BALL DIAMETER RESPECTIVELY SD OR SE 0 000 e 0 80 BSC BALL PITCH WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE e 2 SD SE 0 40 BSC SOLDER BALL PLACEMENT S 8 NOT USED A2 9 B1 4 B7 10 C1 K1 DEPOPULATED SOLDER BALLS M2 9 C10 K10 L1 4 L7 10 9 INDICATES THE THEORETICAL CENTER OF DEPOPULATED G5 6 F5 6 BALLS Note Recommended for wireless applications Ad A1 CORNER TO BE IDENTIFIED BY CHAMFER LASER OR INK MARK METALLIZED MARK INDENTATION OR OTHER MEANS 3330 16 038 25b Figure 4 5 Physical Dimensions 64 Ball Fine Pitch Ball Grid Array S29PL N November 23 2005 9PL N 00 M S29PL N MirrorBi
44. Command S UINT16 bank_addr 0x555 0x00AA write unlock cycle 1 y UINT16 bank addr 0x2AA 0x0055 write unlock cycle 2 WA se bank addr 0x555 0x0020 write unlock bypass command 7 At this point programming only takes two write cycles WA 7 Once you enter Unlock Bypass Mode do a series of like WA operations programming or sector erase and then exit Unlock Bypass Mode before beginning a different type of operations 36 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un Table 7 16 Unlock Bypass Program LLD Function lld UnlockBypassProgramCmd Cycle Description Operation Word Address Data Program Setup Command Base xxxh 00A0h Program Command Program Address Program Data Example Unlock Bypass Program Command po while in Unlock Bypass Entry Mode Wa UINT16 bank addr 0x555 0x00A0 write program setup command y UINT16 pa data write data to be programmed Poll until done or error af If done and more to program do above two cycles again WA Table 7 17 Unlock Bypass Reset LLD Function lld UnlockBypassResetCmd Cycle Description Operation Word Address Data Reset Cycle 1 Base xxxh Reset Cycle 2 Base xxxh Example Unlock Bypass Exit Command UINT16 base addr 0x000 0x0090 UINT16 base addr 0x000
45. ETALLIZED MARK INDENTATION OR OTHER MEANS 3339 16 038 25b Figure 4 2 Physical Dimensions 84 ball Fine Pitch Ball Grid Array S29PL256N 10 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un 4 3 VBH064 8 x II 6 mm 4 3 1 Connection Diagram S29PL127N MCP Compatible Package Reserved for Future Use No Connection 4 m amp 9 gt jan o gt a RY BY fs A o oe a 8 0 20 A3 A2 2 A1 AO n CE1 o m o D o w g OQ eo o o iw O 00 o N g o a Notes 1 Top view balls facing down 2 Recommended for wireless applications Figure 4 3 Connection Diagram 64 Ball Fine Pitch Ball Grid Array S29PLI27N November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family II SPANSION Preliminary a 4 3 2 Connection Diagram S29PL129N MCP Compatible Package Reserved for Future Use No Connection M 4 Q A 021 C x jak gt 5 amp co gt un wo un RY BY gt gt o m N 8 0 20 2 09 Za di v 7 o n 8 A3 A2 2 Al AO n CE1 3k o 6 o ka Ww o EA par g e oo o N g o a Notes 1 Top view balls facing down 2 Recommended for wireless applications Figure 4
46. GA Package 9 42 VBH084 8 0 x IL6 mm cece ene emet 9 42 Connection Diagram S29PL256N MCP Compatible Package 9 42 2 Physical Dimensions VBH084 8 0 x I 6mm 10 43 VBH064 8 x ILGIMMs a ae eaaa aga AA 4 3 1 Connection Diagram S29PLI27N MCP Compatible Package 4 3 2 Connection Diagram S29PLI29N MCP Compatible Package 2 43 3 Physical Dimensions VBH064 8 x Il 6mm S29PL N 13 434 Connection Diagram S29PL N Fortified Ball Grid Array Package 14 43 5 Physical Dimensions LAA064 Il x I3 mm S29PL N aee I5 44 MCP Look Ahead Connection Diagram Physical Dimensions l6 44 For All Page Mode MCPs Comprised of Code Flash p SRAM Data Flash l6 5 Additional Resources 18 6 Product Overview 19 6L Memory aa Sa trea hth de Bate ia 19 7 Device Operations 21 7 Device Operation Table 2l 7 1 1 Dual Chip Enable Device Description and Operation PLI29N Only 2l 7 2 Asynchronous Read sa aan geg ee rh ett Ree ne a eee due eae 22 72 1 Non Page RandomRead 22 7 22 Page Mode Read sis ang ana a neinean Wa 2
47. IGHT 0 40 STANDOFF 0 60 BODY THICKNESS 13 00 BSC BODY SIZE 11 00 BSC BODY SIZE 7 00 BSC MATRIX FOOTPRINT 7 00 BSC MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION 64 BALL COUNT 0 50 0 60 0 70 BALL DIAMETER 1 00 BSC BALL PITCH D DIRECTION 1 00 BSC BALL PITCH E DIRECTION 0 50 BSC SOLDER BALL PLACEMENT A1 AB8 K1 K8 amp DEPOPULATED SOLDER BALLS Note Recommended for automotive applications 9 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14 5M 1994 ALL DIMENSIONS ARE IN MILLIMETERS BALL POSITION DESIGNATION PER JESD 95 1 SPP 010 EXCEPT AS NOTED e REPRESENTS THE SOLDER BALL GRID PITCH SYMBOL MD IS THE BALL MATRIX SIZE IN THE D DIRECTION SYMBOL ME IS THE BALL COLUMN MATRIX SIZE IN THE E DIRECTION N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME DIMENSION b IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE 0 000 WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE e 2 X IN THE PACKAGE VARIATIONS DENOTES PART IS UNDER QUALIFICATION INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS Figure 4 7 Physical Dimensions
48. One Time Programmable Password Method Persistent Method DQ2 DQ1 WP Vi All boot sectors locked 64 bit Password One Time Protect PPB Lock Bit Notes 1 2 3 0 PPBs Locked 1 PPBs Unlocked Persistent Protection Bit PPD Notes 5 6 Dynamic Protection Bit DYB Memory Array Notes 7 8 9 Sector N 2 Sector N 1 Sector N Note 4 Notes 1 Bit is volatile and defaults to 1 on reset 6 PPBs programmed individually but cleared collectively 2 Programming to 0 locks all PPBs to their current state 7 0 Sector Protected 3 Once programmed to 0 requires hardware reset to unlock 1 Sector Unprotected 4 N Highest Address Sector 8 Protect effective only if PPB Lock Bit is unlocked and 5 0 Sector Protected corresponding PPB is 1 unprotected 1 Sector Unprotected 9 Volatile Bits defaults to user choice upon power up see ordering options Figure 8 1 Advanced Sector Protection Unprotection 48 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un 8 Lock Register As shipped from the factory all devices default to the persistent mode when power is applied and all sectors are unprotected unless otherwise chosen through the DYB ordering option see Or dering Information The device programmer or host system must then choose which sector protection method to use Programming setting to 0 any on
49. Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming op eration or a Write to Buffer programming operation so that data can read from any non suspended sector When the Program Suspend command is written during a programming pro cess the device halts the programming operation within tps program suspend latency and updates the status bits After the programming operation has been suspended the system can read array data from any non suspended sector The Program Suspend command can also be issued during a programming operation while an erase is suspended In this case data can be read from any addresses not in Erase Suspend or Program Suspend If a read is needed from the Secured Silicon Sector area then user must use the proper command sequences to enter and exit this region 34 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un The system can also write the Autoselect command sequence when the device is in Program Sus pend mode The device allows reading Autoselect codes in the suspended sectors since the codes are not stored in the memory array When the device exits the Autoselect mode the device re verts to Program Suspend mode and is ready for another valid operation See Autoselect for more information After the Program Resume command is written the device reverts to programming The system can determine the status of the
50. Sector Erase Command UINT16 base addr 0x555 0x00AA write unlock cycle 1 WA UINT16 base addr Ox2AA 0x0055 write unlock cycle 2 WA UINT16 base_addr 0x555 0x0080 write setup command WA UINT16 base_addr 0x555 UINT16 base_addr 0x2AA UINT16 sector_address 0x00AA write additional unlock cycle 1 0x0055 write additional unlock cycle 2 0x0030 write sector erase command J November 23 2005 Q9PL N 00 M S29PL N MirrorBit Flash Family 3l Preliminary SPANSION AN Write Unlo Address 555 ck Cycles h Data AAh Address 2AAh Data 55h Write Sector Erase Cycles Address 555 Address 555 h Data 80h h Data AAh Address 2AAh Data 55h Sector Addre Se Write Ad Additional Sectors Sector Addresses ss Data 30h ect Yes ditional oY Last Sector Selected Wait Perform Write Operation Status A PASS Device returns to reading array Notes gorithm No FAIL Write reset command to return to reading array 1 See Table 12 1 for erase command sequence 2 See the section on DQ3 for information on the sector erase timeout 7 4 4 Chip Erase Command Unlock Cycle 1 Unlock Cycle 2 Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure e Each additional cycle must be written within tec timeout e Timeout resets after
51. Vcc 0 2 V The device requires standard ac cess time tcg for read access before it is ready to read data If the device is deselected during erasure or programming the device draws active current until the operation is completed cc in DC Characteristics represents the standby current specification 9 2 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode the device automatically enables this mode when addresses remain stable for tacc 20 ns The automatic sleep mode is independent of the CE WE and OE control signals Standard address access timings provide new data when addresses are changed While in sleep mode out put data is latched and always available to the system lccg in DC Characteristics represents the automatic sleep mode current specification 9 3 Hardware RESET Input Operation The RESET input provides a hardware method of resetting the device to reading array data When RESETZ is driven low for at least a period of tgp the device immediately terminates any operation in progress tristates all outputs resets the configuration register and ignores all read write commands for the duration of the RESET pulse The device also resets the internal state machine to reading array data The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity When RESET is held at Vss 0 2 V
52. able 7 19 Reset ius ose a goto een SURG PIG hed ke NE eed Pema qud dE ie gu 46 Table 8 1 Kock Register uas fecic STREP Pah Pw SR ee One s SOR RC eg RR a Dra obs 49 Table 8 2 Sector ProtectionSchemes 53 Table 10 1 Secured Silicon Sector Addresses 56 Table 10 2 Secured Silicon Sector Entry siis 58 Table 10 3 Secured Silicon Sector Program 58 Table 10 4 Secured Silicon Sector Ekit 58 Table 11 1 Test Specifications cce Rx nece ee XS RRROR cx xe EAR S Ra nate DR RS 60 Table 12 1 Memory Array Commands hh 73 Table 12 2 Sector Protection Commands ise n 74 Table 12 3 CFI Query Identification String 76 Table 12 4 System Interface String 76 Table 12 5 Device Geometry Definition 76 Table 12 6 Primary Vendor Specific Extended Ouery 77 4 S29PL N MirrorBit Flash Family S29PL N_00_A4 November 23 2005 Preliminary Figures gure 2 1 gure 4 1 gure 4 2 gure 4 3 gure 4 4 gure 4 5 gure 4 6 gure 4 7 gure 4 8 gure 7 1 gure 7 2 gure 7 3 gure 7 4 gure 7 5 gure 7 6 gure 8 1 gure 8 2 gure 11 1 gure 11 2 gure 11 3 gure 11 4 gure 11 5 gure 11 6 gure 11 7 gure 11 8 gure 11 9 gu
53. acteristics Updated Ici cc4 cce 82 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un Revision A3 November 14 2005 Ordering I nformation Updated table Valid Combinations Table Updated table Revision A4 November 23 2005 Logic Symbols Removed Vio from the illustrations Block Diagram Removed Vio from the illustration Connection Diagrams Modified Fortified BGA Pinout LAA064 PL129N Sector and Memory Address Map Updated Address Ranges for Banks 2A and 2B Colophon The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated I for any use that includes fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for any use where chance of failure is intolerable i e submersible repeater and artificial satellite Please note that Spansion will not be liable to you and or any third party for any claims or damages arisi
54. age Definition ACCelerate A special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above Vcc In some devices ACC may protect all sectors when at a low voltage Most significant bit of the address input A23 for 256 Mbit A22 for 128 Mbit A21 for 64 Mbit Least significant bit of the address input signals AO for all devices in this document Operation where signal relationships are based only on propagation delays and are unrelated to synchronous control clock signal Read mode for obtaining manufacturer and device information as well as sector protection status Section of the memory array consisting of multiple consecutive sectors A read operation in one bank can be independent of a program or erase operation in a different bank for devices that offer simultaneous read and write feature Smaller size sectors located at the top and or bottom of Flash device address space The smaller sector size allows for finer granularity control of erase and protection for code or parameters used to initiate system operation after power on or reset Location at the beginning or end of series of memory locations See synchronous read 8 bits Common Flash Interface A Flash memory industry standard specification J EDEC 137 A and J ESD68 01 designed to allow a system to interrogate the Flash to determine its size type and other performance parameters Zero Logic Low Leve
55. anced Sector Protection Software Ekamples 53 8 7 Hardware Data Protection Methods 53 8 7 WP Method iii eb ERE ben ER Oe oT ERN D DIE se URS 53 872 Low Vcc Write Inhibit 53 87 3 Write Pulse Glitch Protection 54 8 74 Power Up Write Inhibit 54 9 Power Conservation Modes 55 2 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un Pili Standby Ya aya UU anan ia riot rete od pix WA UA 55 92 Automatic Sleep Mode 55 9 3 Hardware RESET Input Operation 55 JA Output Disable OE sienten erre E her yere 55 10 Secured Silicon Sector Flash Memory Region 56 10 1 Factory Secured Silicon Sector 56 10 2 Customer Secured Silicon Sector 57 10 3 Secured Silicon Sector Entry and Exit Command Seguences 57 Il Electrical Specifications 59 Il Absolute Maximum Ratings ns 59 l2 Operating Ranges IA AA Ii 60 I3 Test Conditions IAA aaa 60 Il4 Key
56. any of the following conditions W Load a value that is greater than the page buffer size during the Number of Locations to Pro gram step W Write to an address in a sector different than the one specified during the Write Buffer Load command W Write an Address Data pair to a different write buffer page than the one selected by the Starting Address during the write buffer data loading stage of the operation W Write data other than the Confirm Command after the specified number of data load cycles 28 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un Use of the write buffer is strongly recommended for programming when multiple words are to be programmed Write buffer programming is approximately four times faster than programming one word at a time Note that the Secured Silicon the CFI functions and the Autoselect Codes are not available for read when a write buffer programming operation is in progress Software Functions and Sample Code Table 7 8 Write Buffer Program LLD Functions Used lld_WriteToBufferCmd lld ProgramBufferToFlashCmd Description Operation Word Address Unlock Base 555h Unlock Base 2AAh Write Buffer Load Command Write Program Address 0025h Write Word Count Write Program Address Word Count N 1 h Number of words N loaded into the write buffer can be from 1 to 32 words Load Buffer Word N Write Program Address Word N Word N Write B
57. as in the standard program operation In the erase suspend read mode the system can also issue the Autoselect command sequence See Write Buffer Programming and Autoselect for details To resume the sector erase operation the system must write the Erase Resume command The bank address of the erase suspended bank is required when writing this command Further writes of the Resume command are ignored Another Erase Suspend command can be written after the chip has resumed erasing Software Functions and Sample Code Table 7 11 Erase Suspend LLD Function lld EraseSuspendCmd The following is a C source code example of using the erase suspend function Refer to the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example Erase suspend command UINT16 bank addr 0x000 0x00B0 write suspend command WA Table 7 12 Erase Resume LLD Function lld EraseResumeCmd The following is a C source code example of using the erase resume function Refer to the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example Erase resume command UINT16 bank addr 0x000 0x0030 write resume command WA The flash needs adequate time in the resume state Program Suspend
58. boot sectors in addition to 128 Kword sectors A bank address is the set of address bits required to uniquely select a bank Similarly a sector address is the address bits required to uniquely select a sector Icc2 in DC Characteristics represents the active current specification for the write mode see AC Characteristics contains timing specification tables and timing diagrams for write operations November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 45 SPANSION Preliminary a 7 7 Hardware Reset The RESET input provides a hardware method of resetting the device to reading array data When RESET is driven low for at least a period of tap the device immediately terminates any operation in progress tristates all outputs and ignores all read write commands for the duration of the RESET pulse The device also resets the internal state machine to reading array data To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence When RESET is held at Vss the device draws CMOS standby current Iccq If RESET is held at Vig but not at Vss the standby current is greater RESET may be tied to the system reset circuitry which enables the system to read the boot up firmware from the Flash memory upon a system reset See Figure 11 5 and Figure 11 8 for timing diagrams 7 8 Software Reset Software reset is part of the command set see Table
59. dard Embedded Program Algorithm DQ7 Toggle 0 N A No toggle 0 Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle N A Reading within Broaram INVALID INVALID INVALID INVALID INVALID INVALID Program Suspended P d Not Not Not Not Not Not Suspend Allowed Allowed Allowed Allowed Allowed Allowed Mode Note 3 Reading within Non Program Suspended Sector Data Data Data Data Data Data Erase Suspended Sector 1 No Toggle 0 N A Toggle N A Erase Erase Suspend Read Suspend Non Erase Mode Suspended Sector Data Data Data Data Data Data Erase Suspend Program DQ7 Toggle 0 N A N A N A Erase Suspended Sector 1 No toggle 0 N A Toggle N A Erase oes Suspend Non Erase Mode Suspended Sector Data Data Data Data Data Data Erase Suspend Program DQ7 Toggle 0 N A N A N A BUSY State DQ7 Toggle 0 N A N A 0 Write to Buffer Exceeded Timing Limits DQ7 Toggle 1 N A N A 0 Note 5 ABORT State DQ7 Toggle 0 N A N A 1 Notes 1 DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits Refer to the section on DQ5 for more information DQ7 a valid address when reading status information Refer to the appropriate subsection for further details Data are invalid for addresses in a Program Suspended sector DOT indicates the Write to Buffer ABORT status during Write Buffer Programming operations The data bar polling algorithm should be used for Write Buffer Programming operations No
60. ded Algorithms November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 69 Preliminary SPANSION un ae Erase Enter Erase Erase Erasing Suspend Suspend Program Resume WE Erase Erase Suspend Erase Erase Suspend Erase Erase Read Suspend Read Complete Program Note DQ2 toggles only when read at an address within an erase suspended sector The system may use OE or CE to toggle DQ2 and DQ6 Figure II 15 DQ2 vs DQ6 Parameter Notes 128 Kword Sector Erase Time 32 Kword Device Condition 11 8 5 Erase and Programming Performance Typ Note I Max Note 2 0 3 0 3 Chip Erase Time 202 PL256N 100 PL127N 100 PL129N 900 PL256N 450 PL127N 450 PL129N 130 PL256N 65 PL127N 65 PL129N 512 PL256N 256 PL127N 256 PL129N Comments Notes Excludes 00h programming prior to erasure 4 Word Programming Time 40 400 24 240 Excludes system level overhead 5 Effective Word Programming Time utilizing Program Write Buffer 94 60 Total 32 Word Buffer Programming Time 3000 1920 Chip Programming Time using 32 Word Buffer 3 Erase Suspend Erase Resume 157 3 PL256N 78 6 PL127N 78 6 PL129N 315 PL256N 158 PL127N 158 PL129N 100 PL256N 50 PL127N 50 PL129N 200 PL256N 100 PL127N 100 PL129N Excludes system level overhead 5 Program Suspend Program Resume
61. ds of up to 20 ns See Figure 11 1 Maximum DC voltage on pin WP ACC is 9 5 V which may overshoot to 10 5 V for periods up to 20 ns 3 No more than one output may be shorted to ground at a time Duration of the short circuit should not be greater than one second 4 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability 20 ns 20 ns lt gt 20 ns Figure Il Maximum Negative Overshoot Waveform 20 ns Ec kem 20 ns 20 ns Figure 11 2 Maximum Positive Overshoot Waveform November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 59 SPANSION Preliminary a II 2 Operating Ranges Wireless W Devices Ambient Temperature Ta 25 C to 85 C Industrial 1 Devices Ambient Temperature Ta a ee 40 C to 85 C Supply Voltages Vcc Supply Voltages lt a aaa eoi sor aoa dod eui i onii e a oa aLe h a ao a Ea dad a a ai ia aa doaa a E 2 7 V to 3 1 V or KA Batok aa a Side ga a AI e de at eat res Kana kai T 2 7 V to 3 6 V Note 3 Notes 1 Operating ranges define those limits between which the functional
62. e Table 2 1 Input Output Descriptions Description Amax A0 Input Address bus DQ15 DQO 1 0 16 bit data inputs outputs float Input Chip Enable input OE Input Output Enable input Input Write Enable Supply Device ground Not connected Pin Not Connected Internally Ready Busy output and open drain RY BY Output When RY BY Vy the device is ready to accept read operations and commands When RY BY Vo the device is either executing an embedded algorithm or the device is executing a hardware reset operation Vec Supply Device Power Supply RESET Input Hardware reset pin CE1 CE2 Input Chip Enable inputs for S29PL129 device max 1 22 Amax A0 16 16 CE DQ15 DQO i CE1 DQ15 DQO lt r gt OE gt CE2 gt WEF gt OEZ WP ACC WE RESET RY BY WP ACC gt VCC RESET VCC Notes 1 Amax 23 for the PL256N and 22 for the PL127N Logic Symbol PL256N and PLI27N Logic Symbol PLI29N Figure 2 1 Logic Symbols PL256N PLI29N and PLI27N November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 7 SPANSION Preliminary a 3 Block Diagram DQ15 DQO RY BY See Note Vcc Vss Sector Switches RESET e Erase Voltage Generator Input Output Buffers
63. e erase D7 D4 volt D3 DO 100 millivolt Vcc Max write erase D7 D4 volt D3 DO 100 millivolt Vpp Min voltage 00h no Vpp pin present Vpp Max voltage 00h no Vpp pin present Typical timeout per single byte word write 2 us Typical timeout for Min size buffer write 2 us 00h not supported Typical timeout per individual block erase 2 ms Typical timeout for full chip erase 2 ms 00h not supported Max timeout for byte word write 2 times typical Max timeout for buffer write 2 times typical Max timeout per individual block erase 2 times typical Max timeout for full chip erase 2 times typical 00h not supported Table 12 5 Device Geometry Definition Addresses Description 0019h PL256N 0018h PL127N Device Size 2 byte 0018h PL129N OCDE Flash Device Interface description see CFI publication 100 0006h Max number of byte in multi byte write 2 0000h 00h not supported 0003h Number of Erase Block Regions within device 0003h 0000h Erase Block Region 1 Information 0000h see the CFI specification or CFI publication 100 0001h 007Dh PL256N 003Dh PL127N 003Dh PL129N Erase Block Region 2 Information 0000h see the CFI specification or CFI publication 100 0000h 0004h 0003h 0000h Erase Block Region 3 Information 0000h see the CFI specification or CFI publication 100 0001h 76 S2
64. e of the following two one time pro grammable non volatile bits locks the part permanently in that mode W Lock Register Persistent Protection Mode Lock Bit DQ1 W Lock Register Password Protection Mode Lock Bit DQ2 Table 8 1 Lock Register Device DYB Lock Boot Bit ppp One Time 0 sectors Programmable Bit power up 0 All PPB erase command disabled 1 All PPB Erase command enabled Password Persistent Secured Protection Protection Silicon Sector Mode Lock Bit Mode Lock Bit Protection Bit S29PL256N Undefined protected 1 sectors power up unprotected For programming lock register bits see Table 12 2 Notes 1 Ifthe password mode is chosen the password must be programmed before setting the cor responding lock register bit 2 After the Lock Register Bits Command Set Entry command sequence is written reads and writes for Bank A are disabled while reads from other banks are allowed until exiting this mode 3 If both lock bits are selected to be programmed to zeros at the same time the operation aborts 4 Once the Password Mode Lock Bit is programmed the Persistent Mode Lock Bit is perma nently disabled and no changes to the protection scheme are allowed Similarly if the Persistent Mode Lock Bit is programmed the Password Mode is permanently disabled After selecting a sector protection method each sector can operate in any of the following three states 1 Constan
65. e power up No commands are required to retrieve data Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm All addresses are latched on the falling edge of WE or CE whichever happens later All data is latched on the rising edge of WE or CE whichever happens first Reads from the memory array may be performed in conjunction with the Erase Suspend and Pro gram Suspend features After the device accepts an Erase Suspend command the corresponding bank enters the erase suspend read mode after which the system can read data from any non erase suspended sector within the same bank The system can read array data using the standard read timing except that if it reads at an address within erase suspended sectors the device out puts status data After completing a programming operation in the Erase Suspend mode the system may once again read array data with the same exception After the device accepts a Pro gram Suspend command the corresponding bank enters the program suspend read mode after which the system can read data from any non program suspended sector within the same bank Table 7 3 Word Selection within a Page ejej o o y yjryjyrtlo o Autoselect The Autoselect mode allows the host system to access manufacturer and device identification and verify sector protection through identifier codes output from the internal register separate from the memor
66. e programming commands Allows the host system to determine the status of a program or erase operation by reading several special purpose register bits 80 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 8l SPANSION Preliminary a I4 Revisions Revision AO February 28 2005 Initial Release Revision Al August 8 2005 Performance Characteristics Updated Package Options MCP Look Ahead Connection Diagram Corrected Pinout Memory Map Added Sector and Memory Address Map for S29PL127N Device Operation Table Added Dual Chip Enable Device Operation Table Vcc Power Up Updated tycs Added Vcc ramp rate restriction DC Characteristics Updated typical and maximum values Revision A2 October 25 2005 Ordering Information Updated table Connection Diagram and Package Dimensions S29PL N Fortified BGA Added pinout and package dimensions Global Changed data sheet status from Advance Information to Preliminary Removed Byte Address Information Distinctive and Performance Characteristics Removed Enhanced Versatilel O updated read access times and Package options Logic Symbol and Block Diagram Removed Vio from Logic Symbol and Block Diagram Erase and Programming Performance Updated table Write Buffer Programming Updated Write Buffer Abort Description Operating Ranges Updated Vj go supply voltages DC char
67. ector is locked and verified the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the mem ory array at sector 0 10 3 Secured Silicon Sector Entry and Exit Command Sequences The system can access the Secured Silicon Sector region by issuing the three cycle Enter Secured Silicon Sector command sequence The device continues to access the Secured Silicon Sector re gion until the system issues the four cycle Exit Secured Silicon Sector command sequence See the Command Definition Tables Table 12 1 Memory Array Commands Table 12 2 Sector Protection Commands for address and data requirements for both command sequences The Secured Silicon Sector Entry Command allows the following commands to be executed W Read customer and factory Secured Silicon areas W Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence it may read the Secured Silicon Sector by using the addresses normally occupied by sector SAO within the memory array This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence or until power is removed from the device Software Functions and Sample Code The following are C functions and source code examples of using the Secured Silicon Sector Entry Program and exit commands Refer to the Spansion Low Level Driver User Guide available soon on www amd com and www fu
68. edded Erase operation is in progress the system can read data from the non erasing banks The system can determine the status of the erase operation by reading DQ7 or DQ6 DQ2 in the erasing bank See Write Operation Status for information on these status bits Once the sector erase operation has begun only the Erase Suspend command is valid All other commands are ignored However note that a hardware reset immediately terminates the erase operation If that occurs the sector erase command sequence should be reinitiated once that bank has returned to reading array data to ensure data integrity Figure 7 3 illustrates the algorithm for the erase operation See AC Characteristics for the Erase Program Operations parameters and timing diagrams Software Functions and Sample Code Table 7 9 Sector Erase LLD Function lld_SectorEraseCmd Description Operation Word Address Unlock Base 555h Unlock Base 2AAh Setup Command Base 555h Unlock Write Base 555h 00AAh Unlock Write Base 2AAh 0055h Sector Erase Command Write Sector Address 0030h Unlimited additional sectors can be selected for erase command s must be written within tcc The following is a C source code example of using the sector erase function Refer to the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example
69. eems the products to have been in sufficient production volume such that sub sequent versions of this document are not expected to change However typographical or specification corrections or modifications to the valid combinations offered may occur Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 S29PL N MirrorBit Flash Family S29PL256N S29PLI27N S29PLI29N 256 128 128 Mb 16 8 8 M x 16 Bit CMOS 3 0 Volt only Simultaneous Read Write Page Mode Flash Memory Data Sheet iN SPANSION PRELIMINARY General Description The Spansion S29PL N is the latest generation 3 0 Volt page mode read family fabricated using the 110 nm Mirrorbit Flash process technology These 8 word page mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks These devices offer fast page access times of 25 to 30 ns with corresponding random access times of 65 ns 70 ns and 80 ns respectively allowing high speed microprocessors to op erate without wait states The S29PL129N device offers the additional feature of dual chip enable inputs CE1 and CE2 that allow each half of the memory space to be controlled separately Distinctive Characteristics Architectural Advantages m 32 Word Write Buffer Dual Chip Enable Inputs only for S29PL129N
70. ely terminates the erase operation If that occurs the chip erase command sequence should be reinitiated once that bank has returned to reading array data to ensure data integrity Software Functions and Sample Code Table 7 10 Chip Erase LLD Function lld ChipEraseCmd Cycle Description Operation Word Address Data Unlock Base 555h Unlock Base 2AAh Setup Command Unlock Base 555h Unlock Base 2AAh Base 555h Chip Erase Command Base 555h The following is a C source code example of using the chip erase function Refer to the Span sion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example Chip Erase Command Note Cannot be suspended UINT16 base addr 0x555 0x00AA write unlock cycle 1 WA UINT16 base_addr Ox2AA 0x0055 write unlock cycle 2 x UINT16 base addr 0x555 0x0080 write setup command Wa OKOOAA write additional unlock cycle 1 0x0055 write additional unlock cycle 2 0x0010 write chip erase command x UINT16 base_addr 0x555 UINT16 base_addr 0x2AA UINT16 base_addr 0x000 7 4 5 Erase Suspend Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from or program data to any sector not selected for
71. en additional sector erase commands from the system can be assumed to be less than tsga the system need not monitor DQ3 See Sector Erase Command Sequence for more details After the sector erase command is written the system should read the status of DQ7 Data Poll ing or DQ6 Toggle Bit to ensure that the device has accepted the command sequence and then read DQ3 If DQ3 is 1 the Embedded Erase algorithm has begun all further commands ex cept Erase Suspend are ignored until the erase operation is complete If DQ3 is 0 the device accepts additional sector erase commands To ensure the command has been accepted the sys tem software should check the status of DQ3 prior to and following each sub sequent sector erase command If DQ3 is high on the second status check the last command might not have been accepted Table 7 18 shows the status of DQ3 relative to the other status bits DQ1 Write to Buffer Abort DQ1 indicates whether a Write to Buffer operation was aborted Under these conditions DQ1 produces a 1 The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data See Write Buffer Programming Operation for more details November 23 2005 9PL N 00 M S29PL N MirrorBit Flash Family 4l SPANSION Preliminary a Table 7 18 Write Operation Status DQ7 DO5 DQ2 DQI Status Note2 P26 Noten P23 Note 2 Note 4 Stan
72. erasure The bank address is re quired when writing this command This command is valid only during the sector erase operation including the minimum tse time out period during the sector erase command sequence The Erase Suspend command is ignored if written during the chip erase operation When the Erase Suspend command is written during the sector erase operation the device re quires a maximum of tes erase suspend latency to suspend the erase operation However when the Erase Suspend command is written during the sector erase time out the device imme diately terminates the time out period and suspends the erase operation After the erase operation has been suspended the bank enters the erase suspend read mode The system can read data from or program data to any sector not selected for erasure The de vice erase suspends all sectors selected for erasure Reading at any address within erase suspended sectors produces status information on DQ7 DQO The system can use DQ7 or DQ6 and DQ2 together to determine if a sector is actively erasing or is erase suspended Refer to Table 7 18 for information on these status bits November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 33 SPANSION Preliminary a 7 4 6 After an erase suspended program operation is complete the bank returns to the erase suspend read mode The system can determine the status of the program operation using the DQ7 or DQ6 status bits just
73. et programmed to 0 only after all PPBs are configured to the desired settings 8 5 Password Protection Method The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit In addition to this password requirement after power up and reset the PPB Lock Bit is set 0 to maintain the password mode of operation Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit allowing for sector PPBs modifications Notes 1 Dou cs There is no special addressing order required for programming the password Once the Password is written and verified the Password Mode Locking Bit must be set to prevent ac cess The Password Program Command is only capable of programming Os Programming a 1 after a cell is programmed as a 0 results in a time out with the cell as a O The password is all 1s when shipped from the factory All 64 bit password combinations are valid as a password There is no means to verify what the password is after it is set The Password Mode Lock Bit once set prevents reading the 64 bit password on the data bus and further password programming The Password Mode Lock Bit is not erasable The lower two address bits A1 AO are valid during the Password Read Password Pro gram and Password Unlock The exact password must be entered in order for the un
74. ges to the PPBs are allowed The PPB Lock Bit can only be unlocked reset to 1 through a hardware reset or power cycle See also Figure 8 1 for an overview of the Advanced Sector Protection feature 8 7 Hardware Data Protection Methods 8 7 1 8 7 2 The device offers data protection at the sector level via hardware control m When WP ACC is at Vi the four outermost sectors are locked device specific There are additional methods by which intended or accidental erasure of any sectors can be pre vented via hardware means The following subsections describes these methods WP Method The Write Protect feature provides a hardware method of protecting the four outermost sectors This function is provided by the WP ACC pin and overrides the previously discussed Sector Pro tection Unprotection method If the system asserts Vi on the WP ACC pin the device disables program and erase functions in the outermost boot sectors The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual boot configured device If the system asserts Vj on the WP ACC pin the device reverts to whether the boot sectors were last set to be protected or unprotected That is sector protection or unprotection for these sectors depends on whether they were last protected or unprotected Note that the WP ACC pin must not be left floating or unconnected as inconsistent behavior of the device may result The WP ACC pi
75. gram Accelerated single word programming write buffer programming sector erase and chip erase operations are enabled through the ACC function This method is faster than the standard chip program and erase command sequences The accelerated chip program and erase functions must not be used more than 10 times per sector n addition accelerated chip program and erase should be performed at room temperature 25 C 10 C This function is primarily intended to allow faster manufacturing throughput at the factory If the system asserts Vy on this input the device automatically enters the aforementioned Unlock By pass mode and uses the higher voltage on the input to reduce the time required for program and erase operations The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode Note that if a Write to Buffer Abort Reset is required while in Unlock November 23 2005 9PL N 00 M S29PL N MirrorBit Flash Family 35 SPANSION Preliminary a 7 4 8 Bypass mode the full 3 cycle RESET command sequence must be used to reset the device Re moving Vyy from the ACC input upon completion of the embedded program or erase operation returns the device to normal operation W Sectors must be unlocked prior to raising WP ACC to Vy m The WP ACC must not be at Vyp for operations other than accelerated programming and accelerated chip erase or device damage can result W Setthe ACC pin at Vcc whe
76. h Family 67 SPANSION Preliminary a Read Status Data Erase Command Sequence last two cycles KANA VA Addresses KXAXXA YA t CE OE WE Data i 10 for Chip Erase tpusy lt latip RY BY gt tvcs m Voc Note SA sector address for Sector Erase VA Valid Address for reading status data see Write Operation Status Figure II I Chip Sector Erase Operation Timings Addresses WE Controlled Write Cycle Read Cycle CE Controlled Write Cycles Figure 11 12 Back to back Read Write Cycle Timings 68 S29PL N MirrorBit Flash Family S29PL N_00_A4 November 23 2005 Preliminary SPANSION un CE NG A OE WE High Z Do7 L ornen PH KEA Tow AS High Z Da6 boo Suus bats Sas bata XR M vasa gt Busy RY BY Note VA Valid address Illustration shows first status cycle after command sequence last status read cycle and array data read cycle Figure 11 13 Data Polling Timings During Embedded Algorithms Addresses CE WE OE Valid Data DQ6 DQ2 To Valid Data first read second read stops toggling RY BY Note VA Valid address not required for DQ6 Illustration shows first two status cycle after command sequence last status read cycle and array data read cycle Figure 11 14 Toggle Bit Timings During Embed
77. he bank is in the unlock bypass mode The system may read and program in non erasing sectors or enter the autoselect mode when in the Erase Suspend mode The Erase Suspend command is valid only during a sector erase operation and requires the bank address Common Flash Memory Interface 15 16 17 18 19 20 21 22 23 24 25 26 27 SPANSION un The Erase Resume command is valid only during the Erase Suspend mode and requires the bank address Command is valid when device is ready to read array data or when device is in autoselect mode The total number of cycles in the command sequence is determined by the number of words written to the write buffer The maximum number of cycles in the command sequence is 37 The entire four bus cycle sequence must be entered for which portion of the password The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode The system may read and program in non erasing sectors or enter the autoselect mode when in the Erase Suspend mode The Erase Suspend command is valid only during a sector erase operation and requires the bank address The Erase Resume command is valid only during the Erase Suspend mode and requires the bank address Command is valid when device is ready to read array data or when device is in autoselect mode The total number of cycles in the command sequence is determined by the nu
78. i o is RFU on the PL N product family Figure 4 8 MCP Look Ahead Diagram 16 S29PL N MirrorBit Flash Family S29PL N_00_A4 November 23 2005 Preliminary SPANSION un To provide customers with a migration path to higher densities as well as the option to stack more die in a package Spansion has prepared a standard pinout that supports m NOR Flash and SRAM densities up to 4 Gb m NOR Flash and PSRAM densities up to 4 Gb m NOR Flash and PSRAM and Data Storage densities up to 4 Gb The signal locations of the resultant MCP device are shown above Note that for different densi ties the actual package outline can vary However any pinout in any MCP is a subset of the pinout shown above In some cases there may be outrigger balls in locations outside the grid shown above In such cases the user is advised to treat these as RFUs and not connect them to any other signal In case of any further inquiries about the above look ahead pinout please see the application note Design in Scalable Wireless Solutions with Spansion Products or contact a Spansion sales office November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 17 SPANSION Preliminary a 5 Additional Resources Visit www amd com and www fujitsu com to obtain the following related documents Application Notes Using the Operation Status Bits in AMD Devices Simultaneous Read Write vs Erase Suspend Resume MirrorBit Flash Memory Write Buffer Programmi
79. ic PPB and no specific sector address is required for this operation Exit command must be issued after the execution which resets the device to read mode and re enables reads and writes for Bank A The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart below 8 3 Dynamic Protection Bits Dynamic Protection Bits are volatile and unique for each sector and can be individually modified DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared erased to 1 By issuing the DYB Set or Clear command sequences the DYBs are set pro grammed to 0 or cleared erased to 1 thus placing each sector in the protected or unprotected state respectively This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed Notes 1 The DYBs can be set programmed to 0 or cleared erased to 1 as often as needed When the parts are first shipped the PPBs are cleared erased to 1 and upon power up or re set the DYBs can be set or cleared depending upon the ordering option chosen If the option to clear the DYBs after power up is chosen erased to 1 then the sectorsmay be modified depending upon the PPB state of that sector The sectors would be in the protected state If the option to set the DYBs after power up is chosen program
80. imings During Embedded Algorithms shows the Data Polling timing diagram 38 S29PL N MirrorBit Flash Family S29PL N_00_A4 November 23 2005 Preliminary SPANSION un START Note 6 YES Erase Operation Complete DQ7 valid data Read 2 NO Read 3 Read 2 Programming Operation Program Operation Failed Write Buffer Programming Device BUSY Re Poll Note 3 Note 1 Note 5 DEVICE ERROR Note 4 Note 2 Device BUSY Re Poll Device BUSY Re Poll Erase Operation Complete Device in Erase Suspend Mode Notes 1 DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6 2 DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2 3 May be due to an attempt to program a 0 to 1 Use the RESET command to exit operation 4 Write buffer error if DQ1 of last read 1 5 Invalid state use RESET command to exit operation 6 Valid data is the data that is intended to be programmed or all 1 s for an erase operation 7 Data polling algorithm valid for all operations except advanced sector protection Write Buffer Operation Failed AND DQ7 Valid Data Device BUSY Re Poll Figure 7 4 Write Operation Status Flowchart November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 39 SPANSION Preliminary a DQ6 Toggle Bit I Toggle Bit on DQ6 indicates whether an Embedded P
81. ing pro duces a 1 on DQ7 The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7 After an erase command sequence is written if all sectors selected for erasing are protected Data Polling on DQ7 is active for approximately tasp then the bank returns to the read mode If not all selected sectors are protected the Embedded Erase algorithm erases the unprotected sectors and ignores the selected sectors that are protected However if the system reads DQ7 at an address within a protected sector the status may not be valid Just prior to the completion of an Embedded Program or Erase operation DQ7 can change asyn chronously with DQ6 DQO while Output Enable OE is asserted low That is the device may change from providing status information to valid data on DQ7 Depending on when the system November 23 2005 Q9PL N 00 M S29PL N MirrorBit Flash Family 37 SPANSION u Preliminary samples the DQ7 output it may read the status or valid data Even if the device has completed the program or erase operation and DQ7 has valid data the data outputs on DQ6 DQO may be still invalid Valid data on DQ7 DQO appears on successive read cycles See the following for more information Table 7 18 Write Operation Status shows the outputs for Data Polling on DQ7 Figure 7 4 Write Operation Status Flowchart shows the Data Polling algorithm Figure 11 13 Data Polling T
82. initial production has begun Due to the phases of the manufacturing process that require maintaining efficiency and quality this document may be revised by subsequent versions or modifica tions due to changes in technical specifications Combination Some data sheets will contain a combination of products with different designations Advance In formation Preliminary or Full Production This type of document will distinguish these products and their designations wherever necessary typically on the first page the ordering information page and pages with DC Characteristics table and AC Erase and Program table in the table notes The disclaimer on the first page refers the reader to the notice on this page Full Production No Designation on Document When a product has been in production for a period of time such that no changes or only nominal changes are expected the Preliminary designation is removed from the data sheet Nominal changes may include those affecting the number of ordering part numbers available such as the addition or deletion of a speed option temperature range package type or Vio range Changes may also include those needed to clarify a description or to correct a typographical error or incor rect specification Spansion LLC applies the following conditions to documents in this category This document states the current technical specifications regarding the Spansion product s described herein Spansion LLC d
83. ister Command Address 555h Data 40h XXXh Address don t care Program Lock Register Data Address XXXh Data AOh Not on future devices Address 77h Data PD Program Data PD See text for Lock Register definitions Caution Lock data may only be progammed once Wait 4 us Perform Polling Algorithm see Write Operation Status flowchart Error condition Exceeded Timing Limits PASS Write Lock Register FAIL Write rest command Exit Command Address XXXh Data 90h Address XXXh Data 00h Device returns to reading array to return to reading array Figure 8 2 Lock Register Program Algorithm 52 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un 8 6 Advanced Sector Protection Software Examples Table 8 2 Sector Protection Schemes Sector PPB Sector DYB Unique Device PPB Lock Bit 0 protected 0 protected 0 locked unlocked unprotected unprotected Sector Protection Status Any Sector Protected through PPB Any Sector Protected through PPB Any Sector Unprotected Any Sector Protected through DYB Any Sector Protected through PPB Any Sector Protected through PPB Any Sector Protected through DYB Any Sector Unprotected Table 8 2 contains all possible combinations of the DYB PPB and PPB Lock Bit relating to the sta tus of the sector In summary if the PPB Lock Bit is locked set to 0 no chan
84. ity of the device is guaranteed 2 For all AC and DC specifications Vig Vcc 3 Voltage range of 2 7 3 1 V valid for PL N MCP products 11 3 Test Conditions Figure 11 3 Test Setup Table Il Test Specifications Test Condition All Speeds Output Load Capacitance C including jig capacitance Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 11 4 Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Steady AWA Changing from H to L SLE Changing from L to H XXXXXYX Don t Care Any Change Permitted Changing State Unknown Center Line is High Impedance State 60 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un 11 5 Switching Waveforms Vio All Inputs and Outputs l Input Vcc 2 Vcc 2 Output 0 0 V Figure II 4 Input Waveforms and Measurement Levels 11 6 Vcc Power Up Min 250 us Vcc Setup Time Time between RESET high and CE low Notes 1 Vcc ramp rate must exceed 1 V 400 us 2 Vig is internally connected to Vcc tvcs Vcc Vcc min OOO Vin RESET PRR CE NIK KKK KKK KIKI KIKI KIO PRRR ELL RRR ORR RIOR 0 4 4 5 Figure II 5 Vcc Power Up Diagram November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 61 Preliminary SPANSION AN
85. jitsu com for general information on Spansion Flash memory software development guidelines November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 57 Preliminary SPANSION un Table 10 2 Secured Silicon Sector Entry LLD Function lld SecSiSectorEntryCmd Cycle Unlock Cycle 1 Operation Word Address Base 555h Data Unlock Cycle 2 Entry Cycle Base 2AAh Base 555h Note Base Base Address Example SecSi Sector Entry Command UINT16 base addr 0x555 0x00AA write unlock cycle 1 WA UINT16 base addr 0x2AA 0x0055 write unlock cycle 2 WA UINT16 base_addr 0x555 00088 write Secsi Sector Entry Cmd WA Table 10 3 Secured Silicon Sector Program LLD Function Id_ProgramCmd Cycle Unlock Cycle 1 Operation Word Address Base 555h Data Unlock Cycle 2 Program Setup Base 2AAh Base 555h 00A0h Program Note Base Base Address Once in the SecSi Sector mode you program words using the programming algorithm x Word Address Table 10 4 Secured Silicon Sector Exit LLD Function lld SecSiSectorExitCmd Data Word Cycle Unlock Cycle 1 Operation Word Address Base 555h Data Unlock Cycle 2 Base 2AAh Base 555h Exit Cycle Note Base Base Address Example SecSi Sector Exit Command UINT16 base_addr 0x555 0x00
86. l Special purpose register which must be programmed to enable synchronous read mode Synchronous method of burst read whereby the device reads continuously until it is stopped by the host or it has reached the highest address of the memory array after which the read address wraps around to the lowest memory array address Returns bits of a Flash memory array to their default state of a logical One High Level Halts an erase operation to allow reading or programming in any sector that is not selected for erasure Ball Grid Array package Spansion LLC offers two variations Fortified Ball Grid Array and Fine pitch Ball Grid Array See the specific package drawing or connection diagram for further details Synchronous burst read operation in which 8 16 or 32 words of sequential data with or without wraparound before requiring a new initial address Multi Chip Product A method of combining integrated circuits in a single package by stacking multiple die of the same or different devices The programmable area of the product available for data storage Spansion trademarked technology for storing multiple bits of data in the same transistor Group of words that may be accessed more rapidly as a group than if the words were accessed individually 78 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary Term Page Read Password Protection Persistent Protection Program Program Suspe
87. locking function to occur The Password Unlock command cannot be issued any faster than 1 us at a time to prevent a hacker from running through all the 64 bit combinations in an attempt to correctly match a password Approximately 1 us is required for unlocking the device after the valid 64 bit password is given to the device Password verification is only allowed during the password programming operation All further commands to the password region are disabled and all operations are ignored If the password is lost after setting the Password Mode Lock Bit there is no way to clear the PPB Lock Bit Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank A Reads and writes for other banks excluding Bank A are allowed If the user attempts to program or erase a protected sector the device ignores the com mand and returns to read mode A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector The programming of the DYB PPB and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status PPB Status and PPB Lock Status to the device November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 5l SPANSION Preliminary a Write Unlock Cycles Address 555h Data AAh Wis ied Address 2AAh Data 55h y Write Enter Lock Reg
88. lse whichever happens later PD Program Data Data latches on the rising edge of WE or CE pulse whichever occurs first Notes 1 See Table 7 1 for description of bus operations 2 All values are in hexadecimal 3 Except for the following all bus cycles are write cycle read cycle fourth through sixth cycles of the Autoselect commands fourth cycle of the password verify command and any cycle reading at RD 0 and RD 1 4 Data bits DQ15 DQ8 are don t care in command sequences except for RD PD WD PWD and PWD3 PWDO 5 Unless otherwise noted these address bits are don t cares PL127 A22 A15 129N A21 A15 PL256N A23 A14 6 Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state The system must write the reset command to return the device to reading array data 7 No unlock or command cycles required when bank is reading array data 8 The Reset command is required to return to reading array data or to the erase suspend read mode if previously in Erase Suspend when a bank is in the autoselect mode or if DQ5 goes high while the bank is providing status information or performing sector lock unlock SA Sector Address PL127 129N A22 A15 PL256N A23 A15 BA Bank Address PL256N A23 A21 PL127N A22 A20 PL127N A21 A20 WBL Write Buffer Location Address must be within the same
89. mber of words written to the write buffer The maximum number of cycles in the command sequence is 37 The entire four bus cycle sequence must be entered for which portion of the password The ALL PPB ERASE command pre programs all PPBs before erasure to prevent over erasure of PPBs WP ACC must be at VHH during the entire operation of this command Command sequence resets device for next command after write to buffer operation Entry commands are needed to enter a specific mode to enable instructions only available within that mode If both the Persistent Protection Mode Locking Bit and the password Protection Mode Locking Bit are set a the same time the command operation aborts and returns the device to the default Persistent Sector Protection Mode The Exit command must be issued to reset the device into read mode Otherwise the device hangs The Common Flash Interface CFI specification outlines device and host system software inter rogation handshake which allows specific vendor specified soft ware algorithms to be used for entire families of devices Software support can then be device independent J EDEC D indepen dent and forward and back ward compatible for the specified flash device families Flash vendors can standardize their existing interfaces for long term compatibility This device enters the CFI Query mode when the system writes the CFI Query command 98h to address BA 555h any time the device is ready to read
90. med to 0 It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively However if there is a need to change the status of the per sistently locked sectors a few more steps are required First the PPB Lock Bit must be cleared by either putting the device through a power cycle or hardware reset The PPBs can then be changed to reflect the desired settings Setting the PPB Lock Bit once again locks the PPBs and the device operates normally again To achieve the best protection it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP Vj Note that the PPB and DYB bits have the same function when WP ACC Vyy as they do when WP ACC Vig 8 4 Persistent Protection Bit Lock Bit The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors When set programmed to 0 this bit locks all PPB and when cleared programmed to 1 unlocks each sector There is only one PPB Lock Bit per device 50 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminary SPANSION un Notes 1 No software command sequence unlocks this bit unless the device is in the password pro tection mode only a hardware reset or a power up clears this bit The PPB Lock Bit must be s
91. mer s code with or without the random ESN The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked Contact your local representative for details on using Spansion programming services 56 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un 10 2 Customer Secured Silicon Sector The Customer Secured Silicon Sector is typically shipped unprotected DQ6 set to 0 allowing customers to utilize that sector in any manner they choose If the security feature is not required the Customer Secured Silicon Sector can be treated as an additional Flash memory space Please note the following W Once the Customer Secured Silicon Sector area is protected the Customer Indicator Bit is permanently set to 1 W The Customer Secured Silicon Sector can be read any number of times but can be pro grammed and locked only once The Customer Secured Silicon Sector lock must be used with caution as once locked there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way W The accelerated programming ACC and unlock bypass functions are not available when pro gramming the Customer Secured Silicon Sector but are available when reading in Banks B through D W Once the Customer Secured Silicon S
92. minus 1 that is loaded into the page buffer at the Sector Ad dress in which programming occurs This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash confirm command The number of locations to program cannot exceed the size of the write buffer or the operation aborts Number loaded the number of locations to program minus 1 For example if the sys tem programs 6 address locations then 05h should be written to the device The system then writes the starting address data combination This starting address is the first address data pair to be programmed and selects the write buffer page address All subsequent address data pairs must fall within the elected write buffer page The write buffer page is selected by using the addresses Ama A5 The write buffer page addresses must be the same for all address data pairs loaded into the write buffer This means Write Buffer Programming cannot be performed across multiple write buffer page This also means that Write Buffer Programming cannot be performed across multiple sec tors If the system attempts to load programming data outside of the selected write buffer page the operation ABORTS After writing the Starting Address Data pair the system then writes the remaining address data pairs into the write buffer Note that if a Write Buffer address location is loaded multiple times the address data pair c
93. mode 7 1 Device Operation Table 7 1 1 The device must be setup appropriately for each operation Table 7 1 describes the required state of each control pin for any particular operation Table 7 1 Device Operation Addresses Operation RESET WP IACC Amar 7 A0 DQI5 DQO Read X X See Note Write Standby Output Disable Legend L Logic Low Vj H Logic High Vip Vhp 8 5 9 5 V X Don t Care SA Sector Address An Address In Diy Data In Doyr Data Out Note WP ACC must be high when writing to upper two and lower two sectors PL256N 0 1 132 and 133 PL127 129N 0 1 68 and 69 Dual Chip Enable Device Description and Operation PL129N Only The dual CE product PL129N offers a reduced number of address pins to accommodate pro cessors with a limited addressable range This product operates as two separate devices in a single package and requires the processor to address half of the memory space with one chip en able and the remaining memory space with a second chip enable For more details on the addressing features of the Dual CE device refer to Table 6 3 on page 20 for the PL129N Sector and Memory Address Map Dual chip enable products must be setup appropriately for each operation To place the device into the active state either CE1 or CE2 must be set to Vj To place the device in standby mode both CE1 and CE2 must be set to Vi Table 7 2 describes
94. n accelerated programming not in use Unlock Bypass The device features an Unlock Bypass mode to facilitate faster word programming Once the de vice enters the Unlock Bypass mode only two write cycles are required to program data instead of the normal four cycles This mode dispenses with the initial two unlock cycles required in the standard program command sequence resulting in faster total programming time Table 12 1 Memory Array Commands shows the requirements for the unlock bypass command sequences During the unlock bypass mode only the Read Unlock Bypass Program and Unlock Bypass Reset commands are valid To exit the unlock bypass mode the system must issue the two cycle unlock bypass reset command sequence The first cycle must contain the bank address and the data 90h The second cycle need only contain the data 00h The bank then returns to the read mode Software Functions and Sample Code The following are C source code examples of using the unlock bypass entry program and exit functions Refer to the Spansion Low Level Driver User s Guide available soon on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Table 7 15 Unlock Bypass Entry LLD Function Ild_UnlockBypassEntryCmd Cycle Description Operation Word Address Data Unlock i Base 555h Unlock i Base 2AAh Entry Command i Base 555h Example Unlock Bypass Entry
95. n must be held stable during a command sequence execution Low Vcc Write Inhibit When Vcc is less than Vi o the device does not accept any write cycles This protects data during Vcc power up and power down The command register and all internal program erase circuits are disabled and the device resets to reading array data Subsequent writes are ignored until Vcc is greater than Viko The system must provide the proper signals to the control inputs to prevent unintentional writes when Vcc is greater than Viko November 23 2005 Q9PL N 00 M S29PL N MirrorBit Flash Family 53 SPANSION Preliminary a 8 7 3 Write Pulse Glitch Protection Noise pulses of less than 3 ns typical on OE CE or WE do not initiate a write cycle 8 7 4 Power Up Write Inhibit If WE CE RESET Vi and OE V p during power up the device does not accept com mands on the rising edge of WE The internal state machine is automatically reset to the read mode on powerup 54 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un 9 Power Conservation Modes 9 1 Standby Mode When the system is not reading or writing to the device it can place the device in the standby mode In this mode current consumption is greatly reduced and the outputs are placed in the high impedance state independent of the OE input The device enters the CMOS standby mode when the CE and RESET inputs are both held at
96. nality while requiring low power consumption These products also offer 32 word buffer for programming with program and erase suspend resume functionality Ad ditional features include W Advanced Sector Protection methods for protecting an individual or group of sectors as re quired 256 word of secured silicon area for storing customer and factory secured information Simultaneous Read Write operation 6 1 Memory Map The S29PL N devices consist of 4 banks organized as shown in Tables 6 1 6 2 and 6 3 Table 6 1 PL256N Sector and Memory Address Map Sector Size Sector KB Sector Range Address Range 000000h 007FFFh 008000h O0FFFFh Sector Starting Address 010000h 017FFFh Sector Ending Address 018000h O1FFFFh 020000h 03FFFFh Sector Starting Address Sector Ending Address see note 1E0000h 1FFFFFh 200000h 21FFFFh First Sector Sector Starting Address Last Sector Sector Ending Address see note 7E0000h 7FFFFFh 8000000 8L1EFEER First Sector Sector Starting Address H Last Sector Sector Ending Address see note DE0000h DFFFFFh E00000h E1FFFFh Sector Starting Address Sector Ending Address see note FC0000h FDFFFFh FE0000h FE7FFFh FE8000h FEFFFFh Sector Starting Address FF0000h FF7FFFh Sector Ending Address FF8000h FFFFFFh Note Ellipses indicate that other addresses in sector range follow the same pattern November
97. nd Program Resume Read Registers Secured Silicon Sector Protection Sector Simultaneous Operation Synchronous Operation VersatilelO Vio Unlock Bypass Word SPANSION un Definition Asynchronous read operation of several words in which the first word of the group takes a longer initial access time and subsequent words in the group take less page access time to be read Different words in the group are accessed by changing only the least significant address lines Sector protection method which uses a programmable password in addition to the Persistent Protection method for protection of sectors in the Flash memory device Sector protection method that uses commands and only the standard core voltage supply to control protection of sectors in the Flash memory device This method replaces a prior technique of requiring a 12V supply to control the protection method Stores data into a Flash memory by selectively clearing bits of the memory array to leave a data pattern of ones and zeros Halts a programming operation to read data from any location that is not selected for programming or erase Host bus cycle that causes the Flash to output data onto the data bus Dynamic storage bits for holding device control information or tracking the status of an operation An area consisting of 256 bytes in which any word may be programmed once and the entire area may be protected once from any future programming I
98. nd Set Definitions Global Volatile Sector Protection Freeze 3 2AA Command Set Entry 25 PPB Lock PPB Lock Bit Set 2 XX I 2 Bit PPB Lock Bit Status Read Global Volatile Sector Protection Freeze Command Set Exit 27 Volatile Sector Protection Command Set Definitions Volatile Sector Protection Command Set Entry 25 2AA BA 555 DYB Set BA SA DYB Clear BA SA DYB Status Read Volatile Sector Protection XX Command Set Exit 27 Legend X Don t care BA Bank Address PL256N A23 A21 PL127N A22 A20 RA Read Address PL127N A21 A20 RD Read Data WBL Write Buffer Location Address must be within the same write PA Address of the memory location to be programmed Addresses buffer page as PA latch on the falling edge of the WE or CE pulse whichever WC Word Count Number of write buffer locations to load minus 1 happens later PWD3 PWDO Password Data PD3 PDO present four 16 bit PD Program Data Data latches on the rising edge of WE or CE combinations that represent the 64 bit Password pulse whichever occurs first RD 0 DQO protection indicator bit If protected DQO 0 if SA Sector Address PL127 129N A22 A15 PL256N A23 unprotected DQO 1 A15 74 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary Notes 1 2 3 12 1 See Table 7 1 for description of bus operations
99. nformation in this area may be programmed at the factory or by the user Once programmed and protected there is no way to change the secured information This area is often used to store a software readable identification such as a serial number Use of one or more control bits per sector to indicate whether each sector may be programmed or erased If the Protection bit for a sector is set the embedded algorithms for program or erase ignore the program or erase commands related to that sector An Area of the memory array in which all bits must be erased together by an erase operation Mode of operation in which a host system may issue a program or erase command to one bank that embedded algorithm operation may then proceed while the host immediately follows the embedded algorithm command with reading from another bank Reading may continue concurrently in any bank other than the one executing the embedded algorithm operation Operation that progresses only when a timing signal known as a clock transitions between logic levels that is at a clock edge Separate power supply or voltage reference signal that allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs Mode that facilitates faster program times by reducing the number of command bus cycles required to issue a write operation command In this mode the initial two Unlock write cycles of the usual
100. ng and Page Buffer Read Design In Scalable Wireless Solutions with Spansion Products Common Flash Interface Version 1 4 Vendor Specific Extensions Specification Bulletins Contact your local sales office for details Drivers and Software Support W Spansion Low Level Drivers W Enhanced Flash Drivers W Flash File System CAD Modeling Support W VHDL and Verilog m IBIS m ORCAD Technical Support Contact your local sales office or contact Spansion LLC directly for additional technical support Email US and Canada HW support amd com Asia Pacific asia support amd com Europe Middle East and Africa Japan http edevice fujitsu com jp support tech b7 Frequently Asked Questions FAQ http ask amd com http edevice fujitsu com jp support tech b7 Phone US 408 749 5703 Japan 03 5322 3324 Spansion LLC Locations 915 DeGuigne Drive P O Box 3453 Sunnyvale CA 94088 3453 USA Telephone 408 962 2500 or 1 866 SPANSION Spansion J apan Limited 4 33 4 Nishi Shinjuku Shinjuku ku Tokyo 160 0023 Telephone 81 3 5302 2200 Facsimile 81 3 5302 2674 http www spansion com 18 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un 6 Product Overview The S29PLxxxN family consists of 256 and 128 Mb 3 0 volts only simultaneous read write page mode read Flash devices that are optimized for wireless designs of today that demand large storage array and rich functio
101. ng in connection with above mentioned uses of the products Any semiconductor device has an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on ex port under the Foreign Exchange and Foreign Trade Law of Japan the US Export Administration Regulations or the applicable laws of any other country the prior authorization by the respective government entity will be required for export of those products Trademarks and Notice The contents of this document are subject to change without notice This document may contain information on a Spansion LLC product under development by Spansion LLC Spansion LLC reserves the right to change or discontinue work on any product without notice The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy completeness operability fitness for particular purpose merchantability non infringement of third party rights or any other warranty express implied or statutory Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document Copyright 2005 Spansion LLC All rights rese
102. om the stable addresses and stable CE to valid data at the output inputs The output enable access time is the delay from the falling edge of the OE to valid data at the output assuming the addresses have been stable for at least tacc tog time 7 2 2 Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation This mode provides faster read access speed for random locations within a page The random or initial page access is tacc or tcg and subsequent page read accesses as long as the locations specified by the microprocessor falls within that page is equivalent to tpacc When CE is deasserted Vp the reassertion of CE for subsequent access has access time of tacc or tce Here again CE selects the device and OE is the output control and should be used to gate data to the output inputs if the device is selected Fast page mode accesses are obtained by keeping Amax A3 constant and changing A2 AO to select the specific word within that page Address bits Amar A3 select an 8 word page and address bits A2 AO select a specific word within that page This is an asynchronous operation with the microprocessor supplying the specific word location See Table 7 3 for details on selecting specific words 22 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 7 3 Preliminary SPANSION un The device is automatically set to reading array data after devic
103. only available within that mode 22 Requires Entry command sequence prior to execution Secured 19 The Exit command must be issued to reset the device into read Silicon Sector Exit Reset command is required to exit this mode mode Otherwise the device hangs device may otherwise be placed in an unknown state 20 The following mode cannot be performed at the same time Autoselect CFI Unlock Bypass Secured Silicon Command sequence resets device for next command after write to buffer operation Table 12 2 Sector Protection Commands Bus Cycles Notes 6 Command Sequence Second Third Fourth Fifth Seventh Notes Addr Data Addr Data Addr Data Addr Data Addr Data Lock Register Command Set Definitions Lock Register Command Set Entry 25 Lock Lock Register Bits Program 26 Register Lock Register Bits Read Lock Register Command Set Exit 27 Password Protection Command Set Definitions Password Protection Command Set Entry 25 55 PWDO PWD1 Password Program PWD2 Password PWD3 Password Read PWD1 Password Unlock 03 Password Protection Command Set Exit 27 ile Sector Protection Command Set Definiti Non Volatile Sector Protection Command Set Entry 25 2AA BA 555 PPB Program BA SA All PPB Erase 22 PPB Status Read BA SA RD 0 Non Volatile Sector Protection XX 90 Command Set Exit 27 Global Non Volatile Sector Protection Freeze Comma
104. ounter decrements for every data load operation Also the last data loaded at a location before the Pro gram Buffer to Flash confirm command is programmed into the device The software takes care of the ramifications of loading a write buffer location more than once The counter decrements for each data load operation Nor for each unique write buffer address location Once the speci fied number of write buffer locations have been loaded the system must then write the Program Buffer to Flash command at the Sector Address Any other address data write combinations abort the Write Buffer Programming operation The device then goes busy The Data Bar polling tech niques should be used while monitoring the last address location loaded into the write buffer This eliminates the need to store an address in memory because the system can load the last address location issue the program confirm command at the last loaded address location and then data bar poll at that same address The write buffer embedded programming operation can be suspended using the standard sus pend resume commands Upon successful completion of the Write Buffer Programming operation the device returns to READ mode If the write buffer command sequence is entered incorrectly the device enters write buffer abort When an abort occurs the write to buffer abort reset command must be issued to return the de vice to read mode The Write Buffer Programming Sequence is ABORTED under
105. pical sleep mode current is 1 pA 5 Not 100 tested 6 The data in the table is for Vcc range 2 7 V to 3 6 V recommended for standalone applications 7 CE1 and CE2 for the PL129N 62 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un 11 7 2 DC Characteristics Vcc 2 7 V to 3 1 V CMOS Compatible Parameter Parameter Description Symbol Notes Test Conditions Input Load Current Vin Vss to Vcc Vcc Vec max 6 Vout Vss to Vcc OE Vin Vcc Vcc max 6 OE Vin Vcc Vcc max 1 6 Vec Active Write Current 2 3 OE Viu WE Vi CE 7 RESET WP ACC Vec 0 3 V Vcc Reset Current 2 RESET Vss 0 3 V Automatic Sleep Mode 2 4 Vin Vec 0 3 V Vit Vss 0 1 V Vcc Active Read While Write Current 1 2 Vcc Active Program While Erase Suspended Current 2 5 Output Leakage Current Vcc Active Read Current 1 2 5 MHz Vcc Standby Current 2 OE Viy 5 MHz OE Viu OE Vin 8 word Page Read Input Low Voltage Vcc 2 7 to 3 6 V Input High Voltage Vcc 2 7 to 3 6 V Voltage for ACC Program Acceleration Vcc 3 0 V 10 6 Vcc Active Page Read Current 2 Output Low Voltage lo 100 pA Vcc Vec min 6 Output High Voltage log 100 pA 6 Low Vcc Lock Out Voltage 5 Notes 1 The Icc current listed is typically less than 5 mA MHz with OE at Vip
106. r up or following a hardware reset the device reverts to sending commands to the normal address space Reads outside of sector 0 return memory array data Sector 0 is remapped from the memory array to the Secured Silicon Sector array Once the Secured Silicon Sector Entry Command is issued the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode W The Secured Silicon Sector is not accessible when the device is executing an Embedded Pro gram or Embedded Erase algorithm Table 10 1 Secured Silicon Sector Addresses Sexo Semwsue AddemRage Customer 128 words 000080h 0000FFh Factory 128 words 000000h 00007Fh Factory Secured Silicon Sector The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit DQ7 permanently set to a 1 This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field These devices are available pre programmed with one of the following W Arandom 8 word secure ESN only within the Factory Secured Silicon Sector W Customer code within the Customer Secured Silicon Sector through the Spansion program ming service W Both a random secure ESN and customer code through the Spansion programming service Customers may opt to have their code programmed through the Spansion programming services Spansion programs the custo
107. re 11 10 gure 11 11 gure 11 12 gure 11 13 gure 11 14 gure 11 15 Logic Symbols PL256N PL129N and PL127N sec sud Connection Diagram 84 ball Fine Pitch Ball Grid Array S29PL256N ar O Physical Dimensions 84 ball Fine Pitch Ball Grid Array S29PL256N sae 10 Connection Diagram 64 Ball Fine Pitch Ball Grid Array S29PL127N oo 11 Connection Diagram 64 Ball Fine Pitch Ball Grid Array S29PL129N 12 Physical Dimensions 64 Ball Fine Pitch Ball Grid Array S29PL N eee 13 Connection Diagram 64 Ball Fine Pitch Ball Grid Array S29PL127N S29PL256N 14 Physical Dimensions 64 Ball Fortified Ball Grid Array S29PL N seene 15 MCP EooksAhead Diagratm oi dun o etd ue nek Ux ux a stan araa a a tas ma naa ara CURE 16 Single Word Program Operations cos c eun o ERR XS RENE aaa URN UR ARMY N UR VERO 27 Write Buffer Programming Operation nenen wanan HH 30 Sector Erase Operation Aa 32 Write Operation Status Flowchart ssm www 2 39 Simultaneous Operation Block Diagram for S29PL256N and S29PL127N 43 Simultaneous Operation Block Diagram for S29PL129N sssss 44 Advanced Sector Protection Unprotection ssssssss nnn 48 Lock Register Program Algorithm sssssssse n Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform
108. rogram or Erase algo rithm is in progress or complete or whether the device has entered the Erase Suspend mode Toggle Bit can be read at any address in the same bank and is valid after the rising edge of the final WE pulse in the command sequence prior to the program or erase operation and during the sector erase time out During an Embedded Program or Erase algorithm operation successive read cycles to any ad dress cause DQ6 to toggle When the operation is complete DQ6 stops toggling After an erase command sequence is written if all sectors selected for erasing are protected DQ6 toggles for approximately t4sp all sectors protected toggle time then returns to reading array data If not all selected sectors are protected the Embedded Erase algorithm erases the unpro tected sectors and ignores the selected sectors that are protected The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase suspended When the device is actively erasing that is the Embedded Erase algorithm is in progress DQ6 toggles When the device enters the Erase Suspend mode DQ6 stops tog gling However the system must also use DQ2 to determine which sectors are erasing or erase suspended Alternatively the system can use DQ7 see DQ7 Data Polling If a program address falls within a protected sector DQ6 toggles for approximately tpyp after the program command sequence is written then returns to reading a
109. rorBit Flash Family 43 SPANSION AN Preliminary Vec gt CE1 L Ves CE2 H ux Bank 1A lt A21 AO Bank 1A Address K Decoder e o7 ay 1 ank 1B Address Bank 1B lt 3 8 a a X Decoder in OE A21 A0 o a RESET State RY BY WE p Status Control gt DQ15 DQO CE14 and CE2 WM Command Control WP ACC Register mux z E a a et ee et ie LA Ya e CE1 H e CE24 L a DQO DQ15 X Decoder Y H TA 8 Bank 2A Address Bank 2A E 8 2 5 in gt 3 K Decoder a A21 AO Bank 2B Address Bank 2B J Figure 7 6 Simultaneous Operation Block Diagram for S29PLI29N 44 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary SPANSION un 7 6 Writing Commands Command Sequences During a write operation the system must drive CE and WE to Vi and OE to Viy when pro viding an address command and data Addresses are latched on the last falling edge of WE or CE while data is latched on the 1st rising edge of WE or CE An erase operation can erase one sector multiple sectors or the entire device Table 6 1 and Table 6 2 indicate the address space that each sector occupies The device address space is divided into four banks Banks B and C contain only 128 Kword sectors while Banks A and D contain both 32 Kword
110. rray data DQ6 also toggles during the erase suspend program mode and stops toggling once the Embed ded Program Algorithm is complete See the following for additional information Figure 7 4 Write Operation Status Flowchart Figure 11 14 Toggle Bit Timings During Embedded Algorithms Table 7 18 Write Operation Status and Figure 11 15 DQ2 vs DQ6 Toggle Bit on DQ6 requires either OE or CE to be de asserted and reasserted to show the change in state DQ2 Toggle Bit II The Toggle Bit II on DQ2 when used with DQ6 indicates whether a partic ular sector is actively erasing that is the Embedded Erase algorithm is in progress or whether that sector is erase suspended Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure But DQ2 cannot distinguish whether the sector is actively erasing or is erase suspended DQ6 by comparison indicates whether the device is actively eras ing or is in Erase Suspend but cannot distinguish which sectors are selected for erasure Thus both status bits are required for sector and mode information Refer to Table 7 18 Write Opera tion Status to compare outputs for DQ2 and DQ6 See the following for additional information Figure 7 4 Write Operation Status Flowchart and Figure 11 14 Toggle Bit Timings During Em bedded Algorithms Reading Toggle Bits
111. rved Spansion the Spansion logo and MirrorBit are trademarks of Spansion LLC Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 83
112. t Flash Family 13 SPANSION Preliminary a 4 3 4 Connection Diagram S29PL N Fortified Ball Grid Array Package 2 o gt N N oo 9 89 N w gt gt 8 amp 8 O 9 amp 9 rn gt I Ui m c o ul an o m Hn 3 EQ A m up N HG H No o Q e iw R gt H co gt N o U O N Oo o U O Ww 0 8 N amp 8 Ui g o o e 9 amp 9 20 1O gt t c Notes 1l Top view balls facing down 2 A23 is NC on PL127N Figure 4 6 Connection Diagram 64 Ball Fine Pitch Ball Grid Array S29PLI27N S29PL256N 14 S29PL N MirrorBit Flash Family S29PL N 00 M November 23 2005 Preliminar y iN SPANSION bes 4 3 5 Physical Dimensions LAAO64 11 x 13 mm S29PL N Inl 0 200 D gt TA 2X p E gt o di A1 CORNER ID S INK OR LASER 8 7 Bl A L NX Al 1 00 0 5 TOP VIEW p 20 NXo6b A CORNER AL 2X ACEN CORNER 90 10 c BOTTOM VIEW A o 25 c j O CTIA SSS s MN AZ il SEATING PLANE M Any SIDE VIEW N A mue TT vw wm wow Duc nore ANAA NOTES PROFILE HE
113. te that DQ7 during Write Buffer Programming indicates the data bar for DQ7 data for the LAST LOADED WRI TE BUFFER ADDRESS location KA S 42 S29PL N MirrorBit Flash Family 29PL N 00 M November 23 2005 Preliminary DQ15 DQO DQ15 DQO SPANSION un OE lt a Mux 7 5 Simultaneous Read Write The simultaneous read write feature allows the host system to read data from one bank of mem ory while programming or erasing another bank of memory An erase operation may also be suspended to read from or program another location within the same bank except the sector being erased Figure 11 12 Back to back Read Write Cycle Timings shows how read and write cycles may be initiated for simultaneous operation with zero latency See the table DC Charac teristics for read while program and read while erase current specifications Vcc gt Vs Mux Amar AO S Bank A Address X Decoder o NN lt x Bank B Address lt X Decoder Amax A0 RESET Siate e RY BY Stat WEE gt Control CE uu and WP ACC Command C ontrol Register DQO DQ15 X Decoder o lt m Bank C Address 4 X Decoder Amar AO O9 Bank D Address Mux Note Amax A23 PL256N A22 PL127N DQ15 DQO DQ15 DQO Figure 7 5 Simultaneous Operation Block Diagram for S29PL256N and S29PLI27N November 23 2005 9PL N 00 M S29PL N Mir
114. tly locked The selected sectors are protected and cannot be reprogrammed unless PPB lock bit is cleared via a password hardware reset or power cycle 2 Dynamically locked The selected sectors are protected and can be altered via software commands 3 Unlocked The sectors are unprotected and can be erased and or programmed These states are controlled by the bit types described in Sections 8 2 8 6 8 2 Persistent Protection Bits The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en durances as the Flash memory Preprogramming and verification prior to erasure are handled by the device and therefore do not require system monitoring November 23 2005 S29PL N_00_A4 S29PL N MirrorBit Flash Family 49 Preliminary SPANSION un Notes Ov ur m wo m o 10 Each PPB is individually programmed and all are erased in parallel Entry command disables reads and writes for the bank selected Reads within that bank return the PPB status for that sector Reads from other banks are allowed while writes are not allowed All Reads must be performed using the Asynchronous mode The specific sector addresses A23 A14 PL256N and A22 A14 PL127N PL129N are writ ten at the same time as the program command If the PPB Lock Bit is set the PPB Program or erase command does not execute and times out without programming or erasing the PPB There are no means for individually erasing a specif
115. tures m Persistent Sector Protection A command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector Sectors can be locked and unlocked in system at Vcc level m Password Sector Protection A sophisticated sector protection method locks combinations of individual sectors to prevent program or erase operations within that sector using a user defined 64 bit password Typical Program amp Erase Times typical values See Note Typical Word Typical Effective Word 32 words in buffer Accelerated Write Buffer Program Typical Sector Erase Time 32 Kword Sector Typical Sector Erase Time 128 Kword Sector Note Typical program and erase times assume the following conditions 25 C 3 0 V Vcc 10 000 cycles checkerboard data pattern Package Options VBH064 VBH084 8 0 x 11 6 mm 8 0 x 11 6 mm 11 x 13 mm 64 ball 64 ball 84 ball Fortified BGA 256 E g 129 m 127 m LAA064 S29PL N Publication Number 3S29PL N 00 Revision A Amendment 4 Issue Date November 23 2005 SPANSION un Preliminary Contents Orderinginformation 6 2 Input Output Descriptions and Logic Symbols 7 3 Block Diagram ccc ccc ccc ccc reece eee nnn hh nnn 8 4 Connection Diagrams Physical Dimensions 9 4 1 Special Handling Instructions for FB
116. uffer to Flash Write Sector Address 0029h Notes 1 Base Base Address 2 Last Last cycle of write buffer program operation depending on number of words written the total number of cycles can be from 6 to 37 3 For maximum efficiency it is recommended that the write buffer be loaded with the highest number of words N words possible The following is a C source code example of using the write buffer program function See the Spansion Low Level Driver User s Guide available on www amd com and www fujitsu com for general information on Spansion Flash memory software development guidelines Example Write Buffer Programming Command ya NOTES Write buffer programming limited to 16 words Ya All addresses to be written to the flash in i d gE one operation must be within the same flash S gs page A flash page begins at addresses nl evenly divisible by 0x20 UINT16 src source of data address of source data x UINT16 dst destination of data flash destination address UINT16 wc words to program 1 word count minus 1 UINT16 base_addr 0x555 0x00AA write unlock cycle 1 i UINT16 base addr 0x2AA 0x0055 write unlock cycle 2 WA UINT16 sector address 0x0025 write write buffer load command UINT16 sector address wc write word count minus 1 Wa loop dst src ALL dst MUST BE SAME PAGE write source data to destination dst
117. write buffer page as PA WC Word Count Number of write buffer locations to load minus 1 9 The fourth cycle of the autoselect command sequence is a read cycle The system must provide the bank address See Autoselect 10 Device IDs PL256N 223Ch PL127N 2220h PL129N 2221h 11 See Autoselect 12 The Unlock Bypass command sequence is required prior to this command sequence 13 The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode 14 The system may read and program in non erasing sectors or enter the autoselect mode when in the Erase Suspend mode The Erase Suspend command is valid only during a sector erase operation and requires the bank address 15 The Erase Resume command is valid only during the Erase Suspend mode and requires the bank address 16 The total number of cycles in the command sequence is determined by the number of words written to the write buffer The maximum number of cycles in the command sequence is 37 November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 73 SPANSION Preliminary a 17 Command sequence resets device for next command after write 21 Command is valid when device is ready to read array data or to buffer operation when device is in autoselect mode Address equals 55h on all 18 Entry commands are needed to enter a specific mode to enable future devices but 555h for PL256N instructions
118. y See Table 7 1 on page 21 for the correct device settings required before initiation of a write command sequence Note the following details regarding the program erase operations m When the Embedded Program algorithm is complete the device then returns to the read mode W The system can determine the status of the program operation by using DQ7 or DQ6 See Write Operation Status for information on these status bits W A Ocannot be programmed back to a 1 Attempting to do so causes the device to set DQ5 1 halting any further operation and requiring a reset command A succeeding read shows that the data is still O Only erase operations can convert a 0 to a 1 W Ahardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity W Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command W Secured Silicon Sector Autoselect and CFI functions are unavailable when a program oper ation is in progress W Programming is allowed in any sequence and across sector boundaries for single word pro gramming operation Single Word Programming In single word programming mode four Flash command write cycles are used to program an in dividual Flash address While this method is supported by all Spansion devices in general it is not recommended for devices
119. y array on DQ15 DQO This mode is primarily intended to allow equipment to automatically match a device to be programmed with its corresponding programming algorithm When verifying sector protection the sector address must appear on the appropriate highest order address bits see Table 7 5 The remaining address bits are don t care When all necessary bits have been set as required the programming equipment can then read the corresponding identifier code on DQ15 DQO The Autoselect codes can also be accessed in system through the command register Note that if a Bank Address BA on the four uppermost address bits is asserted during the third write cycle of the Autoselect command the host system can read Autoselect data from that bank and then immediately read array data from the other bank without exiting the Autoselect mode W To access the Autoselect codes the host system must issue the Autoselect command W The Autoselect command sequence can be written to an address within a bank that is either in the read or erase suspend read mode W The Autoselect command cannot be written while the device is actively programming or eras ing in the other bank W Autoselect does not support simultaneous operations or page modes W The system must write the reset command to return to the read mode or erase suspend read mode if the bank was previously in Erase Suspend November 23 2005 29PL N 00 M S29PL N MirrorBit Flash Family 23

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