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ANALOG DEVICES AD9059 handbook

1. AD9059 AD9059 EVALUATION BOARD 48472 6 inel EE E E EE EEE Figure 9 Evaluation Board Layout Bottom REV A 11 AD9059 OUTLINE DIMENSIONS 28 Lead Shrink Small Outline Package SSOP RS 28 Dimensions shown in millimeters 1 85 1 75 0 10 2 00 MAX 1 6 COPLANARITY a 0 25 0 09 3 Y 0 65 0 38 A 44 g 0 95 do 88e 08 mra L O75 elle PLANE 0 55 COMPLIANT TO JEDEC STANDARDS MO 150AH ww BDTI C com Revision History Location Page 4 03 Data Sheet changed from REV 0 to REV A Renumbered Figures and TRES w C u ass ERR EROR VA ad Car e ES da ae Universal Changes SPECIFICATIONS BEd ERI RR RA eR E kaa oa a ie le BE oe Cr 3 Updated OUTLINE DIMENSIONS uyana ba ee ee 12 12 REV A C00563 0 4 03 A
2. C I 6 2 5 6 Yo FS Full VI 8 8 Yo FS Gain Temperature Coefficient Full V 70 ppm C ANALOG INPUT Input Voltage Range Centered at 2 5 V 25 C V 1 0 V p p Input Offset Voltage 25 C I 15 0 15 mV Full VI 25 25 mV Input Resistance 25 C V 150 KO Input Capacitance 25 C V 2 pF Input Bias Current 25 C I 6 16 LA Analog Bandwidth 25 C V 120 MHz CHANNEL MATCHING to B Gain Delta 25 C V zl FS Input Offset Voltage Delta 25 C V 4 mV BAND GAP REFERENCE Output Voltage VI 2 4 5 2 V Temperatur i ll V 10 ppm C SWITCHING C Maximum Conversion Rate ull I MSPS Minimum Conversion Rate Full IV 5 MSPS Aperture Delay ta 25 C V 2 7 ns Aperture Uncertainty Jitter 25 V 5 ps rms Output Valid Time ty Full IV 4 0 6 6 ns Output Propagation Delay tpp Full IV 9 5 14 2 ns DYNAMIC PERFORMANCE Transient Response 25 C V 9 ns Overvoltage Recovery Time 25 9 ns Signal to Noise Ratio SINAD with Harmonics fiw 10 3 MHz 25 C I 40 44 5 dB fw 76 MHz 25 C V 43 5 dB Effective Number of Bits ENOB fw 10 3 MHz 25 C I 6 35 7 1 Bits fw 76 MHz 25 C V 6 9 Bits Signal to Noise Ratio SNR Without Harmonics fiw 10 3 MHz 25 C I 42 46 dB fw 76 MHz 25 C V 45 dB Second Harmonic Distortion fw 10 3 MHz 25 1 50 62 dBc fw 76 MHz 25 C V 54 dBc Third Harmonic Distortion fiw 10 3 MHz 25 C I 46 60 dBc fw 76 MHz 25 C V 54 dBc Two Tone Intermodulation Distortion IMD 25 C V 52 dBc Channel Cr
3. ANALOG DEVICES Dual 8 Bit 60 MSPS A D Converter AD9059 FEATURES Dual 8 Bit ADCs on a Single Chip Low Power 400 mW Typical On Chip 2 5 V Reference and Track and Hold 1 V p p Analog Input Range Single 5 V Supply Operation 5 V or 3 V Logic Interface 120 MHz Analog Bandwidth Power Down Mode 12 mW APPLICATIONS Digital Communications QAM Demodulators RGB and YC Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation PRODUCT DESCRIPTION The AD9059 is a dual 8 bit monolithic analog to digital converter With a 60 MS bandwidth lef applicationsueq g performance To minimize system cost and power dissipation the AD9059 includes an internal 2 5 V reference and dual track and hold circuits The ADC requires only a 5 V power supply and an encode clock No external reference or driver components are required for many applications The AD9059 s single encode input is TTL CMOS compatible and simultaneously controls both internal ADC channels The parallel 8 bit digital outputs can be operated from 5 V or 3 V supplies A power down function may be exercised to bring total consumption to 12 mW when ADC data is not required for lengthy periods of time In power down mode the digital outputs are driven to a high impedance state Fabricated on an advanced BiCMOS process the AD9059 is available in a space saving 28 lead shrink small outline package 28 lead SSOP and is
4. D2B D1A 13 16 D1B DOA LSB 14 15 DOB LSB 4 REV A Typical Performance Characteristics AD9059 _ ENCODE 60MSPS ANALOG IN 10 3MHz 0 5dBFS _ SINAD 43 9dB 7 0 BITS L SNR 45 1dB reo yp TAPI 1 FREQUENCY MHz TPC 1 FFT Spectral Plot 60 MSPS 10 3 MHz ENCODE 60MSPS ANALOG IN 76MHz 0 5dBF SINAD 43 0dB ENOB 6 85 BITS SNR 44 1dB FREQUENCY MHz TPC 2 Spectral Plot 60 MSPS 76 MHz ENCODE 60MSP AIN 0 5dBFS 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY MHz TPC 3 SINAD SNR vs AIN Frequency REV A 5 ENCODE 60MSP AIN 0 5dBFS SECOND HARMONIC THIRD HARMONIC 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY MHz TPC 4 Harmonic Distortion vs AIN Frequency ENCODE 60MSPS F1 IN 9 5MHz 7 0dBFS F2 IN 9 9MHz 7 0dBFS 2F1 F2 52 0dBc 2F2 F1 53 0dBc FREQUENCY MHz TPC 5 Two Tone IMD 5 10 20 30 40 50 60 70 80 90 ENCODE RATE MSPS TPC 6 SINAD SNR vs Encode Rate AD9059 600 MHz 0 5dBFS 550 POWER mW 5 10 20 30 40 50 60 70 80 90 ENCODE RATE MSPS TPC 7 Power Dissipation vs
5. E11 to El am ne E io i P MEE ad 4 The encode signal source should be TTL CMOS compatible P u Sen i and capable of driving a 50 Q termination The digital outputs Pe MEE of the AD9059 are buffered through latches on the evaluation For ac coupled analog input applications amplifiers U3 and U4 board U5 and U6 and are available for the user at connector are removed from the analog signal paths The analog signals Pins 30 37 and Pins 22 29 Latch timing is derived from the are coupled through Capacitors C11 and C12 each terminated ADC ENCODE clock and a digital clocking signal is provided to the VREF voltage through separate 1 kQ resistors providing for the board user at connector Pins 2 and 21 bias current for the AD9059 analog inputs AINA and AINB REV A 9 AD9059 ANALOG IN A U4 C12 9 pos AD8041Q 0 1pF E7 1 8 2 7 R5 TF y FT o 5V 100 AD9059RS T lt R1i E9 w 6 13 500 1KO E15 O R15 1KO R8 tL c17 C10 10kQ 10ur To iuf R9 J1 REF 10kQ ANALOG IN B BNC Ja E4 R12 2500 U7 ml 74AC00 J10 c6 ENcopE 6 A par wT 0 T s 5V f i 500 DECOUPLING CAPS 74AC00 J12 GNDO _ Mis gt Figure 7 AD9059 Dual Evaluation Board Schematic 10 U5 74ACQ574 9 t 7 sa D4B 5 D5B D6B B D7B 2 9 D7A 8D D6A 70 7 D5A ry 6D D4A s 5D D3A 21 4 D2A J 3D D1A ry 2D DOA 1D P2 C37DRPF REV A
6. Encode Rate 45 5 45 0 44 5 44 0 8 43 5 GAIN ERROR ENCODE 60MSPS AIN 10 3MHz 0 5dBFS TEMPERATURE C TPC 8 SINAD SNR vs Temperature 7 45 0 25 70 90 TEMPERATURE C TPC 9 ADC Gain vs Temperature With External 2 5 V Reference 12 11 10 9 5 9 0 8 5 8 0 75 Vpp 5V tpp ns 7 0 6 5 6 0 45 0 25 70 90 TPC 10 tgp vs Temperature Supply 3 V 5 V ENCODE 60M 10 3MHz 9 2 10 ENCODE HIGH PULSEWIDTH ns TPC 11 SINAD SNR vs Encode Pulsewidth L ADC GAIN dB 1 2 5 10 20 50 100 200 500 ANALOG FREQUENCY MHz TPC 12 ADC Frequency Response 6 REV A AD9059 THEORY OF OPERATION The AD9059 combines Analog Devices proprietary MagAmp gray code conversion circuitry with flash converter technology to provide dual high performance 8 bit ADCs in a single low cost monolithic device The design architecture ensures low power high speed and 8 bit accuracy The AD9059 provides two linked ADC channels that are clocked from a single ENCODE input see Functional Block Diagram The two ADC channels simultaneously sample the analog inputs AINA and AINB and provide noninterleaved parallel digital outp
7. ave a 1 mA minimum sink source current capability to ensure complete overdrive of the internal voltage reference AD9059 Digital Logic 5 V 3 V Systems The digital inputs and outputs of the AD9059 can easily be configured to interface directly with 3 V or 5 V logic systems The encode and power down PWRDN inputs are CMOS stages with TTL thresholds of 1 5 V making the inputs compat ible with TT L 5 V CMOS and 3 V CMOS logic families As with all high speed data converters the encode signal should be clean and jitter free to prevent degradation of ADC dynamic performance The AD9059 s digital outputs will also interface directly with 5 V or 3 V CMOS logic systems The voltage supply pins Vpp for these CMOS stages are isolated from the analog Vp voltage supply By varying the voltage on these supply pins the digital output high levels will change for 5 V or 3 V systems The Vpp pins are internally connected on the AD9059 die Care should be taken to isolate the Vpp supply voltages from the 5 V analog supply to minimize noise coupling into the ADCs The AD9059 provides high impedance digital output operation when the ADC is driven into power down mode PWRDN logic high A 200 ns minimum power down time should be provided before a high impedance characteristic is required A 200 ns power up period should be provided to ensure accurate ADC output data after reactivation valid output data is avail able three clock cycles after th
8. e 200 ns delay Timing The AD9059 is guaranteed to operate with conversion rates to operate with an is insensitive to to 10 allowing t c 1 maximum high low specifications will cause no degradation in ADC performance see Figure 1 Due to the linked ENCODE architecture of the ADCs the AD9059 cannot be operated in a 2 channel ping pong mode Power Dissipation The power dissipation of the AD9059 is specified to reflect a typical application setup under the following conditions encode is 60 MSPS analog input is 0 5 dBFS at 10 3 MHz Vp is 5 V Vpp is 3 V and digital outputs are loaded with 7 pF typical 10 pF maximum The actual dissipation will vary as these conditions are modified in user applications TPC 7 shows typi cal power consumption for the AD9059 versus ADC encode frequency and Vpp supply voltage A power down function allows users to reduce power dissipation when ADC data is not required A TTL CMOS high signal PWRDN shuts down portions of the dual ADC and brings total power dissipation to less than 10 mW The internal band gap voltage reference remains active during power down mode to minimize ADC reactivation time If the power down function is not desired Pin 3 should be tied to ground Both ADC channels are controlled simultaneously by the PWRDN pin they cannot be shut down or turned on independently C C Applications The wide analog bandwidth of the AD9059 makes it attractive for a variety of h
9. iety of high E15 C12 to R15 termination resistor for Channel A E4 to E6 speed digitization evaluations On board components include the analog input B to C11 feedthrough capacitor and E10 to E12 AD9059 in the 28 lead SSOP package optional analog input C11 to R14 termination resistor for Channel B using the buffer amplifiers digital output latches board timing drivers and board jumper connectors configurable jumpers for ac coupling dc coupling and power The on board reference voltage may be used to drive the ADC or down function testing The board is configured at shipment for an external reference may be applied The standard configuration dc coupling using the AD9059 s internal reference employs the internal voltage reference without any external For dc coupled analog input applications amplifiers U3 and U4 connection requirements An external voltage reference may be are configured to operate as unity gain inverters with adjustable applied at board connector input REF to overdrive the limited offset for the analog input signals For full scale ADC drive current output of the AD9059 s voltage reference The each analog sy signal should be 1 an be exercised Co E2 to E1 5 V to to ground Sef its a 2 5 V typi t age For dc coupl d cofilect E power dowB mode operation ra normal operation R11 E14 to E13 amplifier output to spele input A of connect E3 to El ground to PWRDN AD9059 E4 to E5 1 B to R10
10. igh performance receiver and encoder applications Figure 4 shows the dual ADC in a typical low cost I and Q demodulator implementation for cable satellite or wireless LAN modem receivers The excellent dynamic performance of the ADC at higher analog input frequencies and encode rates empowers users to employ direct IF sampling techniques see TPC 2 IF sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power AD9059 Figure 4 and O Digital Receiver The high sampling rate and analog bandwidth of the AD9059 are ideal for computer RGB video digitizer applications With a full power analog bandwidth of 2x the maximum sampling rate the ADC provides sufficient pixel to pixel transient settling time to ensure accurate 60 MSPS video digitization Figure 5 shows a typical RGB video digitizer implementation for the AD9059 AD9059 Figure 5 RGB Video Encoder REV A AD9059 Vpp Vp Vp 3V TO 5V ENCODE PWRDN 00 07 VOLTAGE REFERENCE DIGITAL INPUTS DIGITAL OUTPUTS ANALOG INPUTS Figure 6 Equivalent Circuits Evaluation Board Analog input signals to the board should be 1 V p p into 50 Q The AD9059 PCB evaluation board provides an easy to use for full scale ADC drive For ac coupled operation connect E7 analog digital interface for the dual 8 bit 60 MSPS ADC The to E8 analog input A ta C12 feedthrough capacitor E13 to board includes typical hardware configurations for a var
11. n tested Analog Inputs sie anto a ass 0 5 V to Vp 0 5 V o Digital Inputs secet reme er 0 5 V to Vp 0 5 V MS 0 5 V to Vp 0 5 V specified temperatures Digital Output 20 mA III Sample tested only Operating Temperature 55 C to 125 C IV Parameter is guaranteed by design and characterization Storage Temperature 65 C to 150 C testing Stresses above those listed under Absolute Maximum Ratings may cause permanent V Parameter is a typical value only damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of VI 100 production tested at 25 C guaranteed by design this specification is not implied Exposure to absolute maximum ratings for extended and characterization testing for industrial temperature range periods may affect device reliability ORDERING GUIDE Model Temperature Range Package Option AD9059BRS 40 C to 85 C RS 28 AD9059 PCB 25 C Evaluation Board CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD9059 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore pro
12. osstalk Rejection 25 C V 50 dBc Differential Phase 25 C V 0 8 Degrees Differential Gain 25 C V 1 0 2 REV A SPECIFICATIONS o AD9059 AD9059BRS Parameter Temp Test Level Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage Full VI 2 0 V Logic 0 Voltage Full VI 0 8 V Logic 1 Current Full VI uA Logic 0 Current Full VI ti LA Input Capacitance 25 C V 4 5 pF Encode Pulsewidth High ten 25 C IV 6 7 166 ns Encode Pulsewidth Low tg 25 C IV 6 7 166 ns DIGITAL OUTPUTS Logic 1 Voltage Vpp 3 V Full VI 2 95 V Logic 1 Voltage Vpp 5 V Full IV 4 95 V Logic 0 Voltage Vpp 3 V or 5 V Full VI 0 05 V Output Coding Offset Binary Code POWER SUPPLY Vp Supply Current Vp 5 V Full VI 72 92 mA Vpp Supply Current Vpp 3 V Full VI 13 15 mA Power Dissipation 6 Full VI 400 505 mW Power Down Dissipation Full VI 6 12 mW Power Supply Rejection Ratio PSRR 25 C I 3 mV V NOTES Gain error and gain temperature coefficient are based on the ADC only with a fixed 2 5 V external reference ty and tpp are measured from the 1 5 V level of the ENCODE to the 1096 9096 levels of the digital output swing The digital output load during test is not to exceed Typical thermal impedance for the Specifications subject to change without notice EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS Test Level Vp Vpp ER EE EE LES ET EO OE ont QR eU I 100 productio
13. per ESD precautions are recommended to avoid performance degradation or loss of functionality REV A WARNING ESD SENSITIVE DEVICE AD9059 PIN FUNCTION DESCRIPTIONS N Na Nea Pin No Mnemonic Function AIN 1 1 28 AINA AINB Analog Inputs for ADC A and N 2 d 4 2 VREF Internal Voltage Reference 2 5 V tty Typical Bypass with 0 1 UF to elt Ground or Overdrive with External ENCODE m Man Voltage Reference de lt ty 3 PWRDN Power Down Function Select Logic DIGITAL HIGH for Power Down Mode OUTPUTS Ned 2 n NEN Ne Digital Outputs Go to High E Impedance State gt 4 25 Vp Analog 5 V Power Supply 5 24 27 GND Gro ti A APERTURE DELAY PULSEWIDTH HIGH 6 7ns 6 23 Vpp Digital Output Power Supply PULSEWIDTH LOW 6 7ns Nominally 3 Vto5 V OUTPUT VALID TIME 4 ons 6 6n e OUTPUT PROP DELAY 9 5ns 7 14 D7A DOA Digital Outputs of ADC A Figure 1 Timing Diagram 22 15 D7B DOB Digital Outputs of ADC B 26 ENCODE Encode Clock for ADCs A and B PIN CONFIGURATION ADCs Sample Simultaneously on the Rising Edge of ENCODE 28 AINB F Table Digital Coding VREE 2 5 26 ENCODE log Input V Voltage kevel Digital Output Fi 3 0 i 111111 1a Y vie 2 5 i D 000 0000 D7A MSB 22 D7B MSB i 0111 1111 D6A 8 21 Des 2 0 Negative Full Scale 0000 0000 5 9 20 D5B paa 10 19 Da 11 18 Das D2A 12
14. specified over the industrial temperature range 40 C to 85 Customers desiring single channel digitization may consider the AD9057 a single 8 bit 60 MSPS monolithic based on the AD9059 ADC core The AD9057 is available in a 20 lead shrink small outline package 20 lead SSOP and is specified over the industrial temperature range REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM Vp PWRDN Vpp DOA LSB 14 15 DOB LSB One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD9059 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Vp 5 V Von 3 V external reference ENCODE 60 MSPS unless otherwise noted AD9059BRS Parameter Temp Test Level Min Typ Max Unit RESOLUTION 8 Bits DC ACCURACY Differential Nonlinearity 25 1 0 75 2 0 LSB Full VI 2 5 LSB Integral Nonlinearity 25 C I 0 75 2 0 LSB Full VI 2 5 LSB No Missing Codes Full VI Guaranteed Gain Error 25
15. uld be approximately 1 kQ VINA 1V p p AD9059 EXTERNAL VREFO OPTIONAL OUE Y VINB 1V p p O 1pF Figure 2 Capacity Coupled AD9059 REV A edance VINgO 0 5V TO 0 5V Figure 3 DC Coupled AD9059 VIN Inverted Voltage Reference A stable and accurate 2 5 V voltage reference is built into the AD9059 VREF The reference output is used to set the ADC gain offset and can provide dc bias for the analog input signals The internal reference is tied to the ADC circuitry through an 800 Q internal impedance and is capable of providing 300 pA external drive current for dc biasing the analog input or other user circuitry Somefapplia require A e a y improved mp tature p anGey gam adjustment that cannot be obtained using the internal reference An external voltage may be applied to the VREF pin to overdrive the internal voltage reference for gain adjustment of up to 10 the VREF pin is internally tied directly to the ADC circuitry ADC gain and offset will vary simultaneously with external reference adjust ment with a 1 1 ratio a 2 or 50 mV adjustment to the 2 5 V reference varies ADC gain by 2 and ADC offset by 50 mV Theoretical input voltage range versus reference input voltage may be calculated using the following equations Vrance P p VREF 2 5 VwumscaLE VREF Vrop op rancE VREF VrancE 2 V BOTTOM OF RANGE VREF VRANGE 2 The external reference should h
16. uts DOA DTA and DOB D7B The voltage reference VREF is internally connected to both ADCs so channel gains and offsets will track if external reference control is desired Figure 3 shows typical connections for high performance dc biasing using the ADC s internal voltage reference All compo nents may be powered from a single 5 V supply analog input signals are referenced to ground The analog input signal is buffered at the input of each ADC channel and applied to a high speed track and hold The track and hold circuit holds the analog input value during the conversion process beginning with the rising edge of the ENCODE command The track and hold s output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input level Decode logic combines the multistage data and aligns the 8 bit word for strobed outputs on the rising edge of the ENCODE command The MagAmp Flash architecture of the AD9059 results in three pipeline delays for the output data USING THE AD9059 Analog Inputs ADC s internal voltage reference Figure 2 shows a low cost dc bias implementation that allows the user to capacitively couple ac signals directly into the ADC without additional active cir cuitry For best dynamic performance the VREF pin should be decoupled to ground with a 0 1 uF capacitor to minimize modulation of the reference voltage and the bias resistor sho

ANALOG DEVICES AD9059 handbook

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