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ANALOG DEVICES AD9048 Monolithic 8-Bit Video A/D Converter handbook

1. D90486t hy Fi ANALOG DEVICES Monolithic 8 Bit Video A D Converter AD9048 FEATURES 35 MSPS Encode Rate 16 pF Input Capacitance 550 mW Power Dissipation Industry Standard Pinouts MIL STD 883 Compliant Versions Available APPLICATIONS Professional Video Systems Special Effects Generators Electro Optics Digital Radio Electronic Warfare ECM ECCM ESM GENERAL DESCRIPTION The AD9048 is an 8 bit 35 MSPS flash converter made on a high speed bipolar process which is an alternate source for the TDC1048 unit offers enhancements over its predecessor Lower power dissipation makes the AD9048 attractive for a variety of system designs Because of its wide bandwidth it is an ideal choice for real time conversion of video signals Input bandwidth is flat with no missing codes Clocked latching comparators encoding logic and output buffer registers operating at minimum rates of 35 MSPS preclude a need for a sample and hold S H or track and hold T H in most system designs using the AD9048 All digital control in puts and outputs are TTL compatible Devices operating over two ambient temperature ranges and with two grades of linearity are available Linearities of either 0 5 LSB or 0 75 LSB can be ordered for a commercial range of 0 C to 70 C or extended case temperatures of 55 C to 125 C REV Information furnished by Analog Devices is believed to be accurate and reliable However no respons
2. 2 grounds should be connected together and to NMINV Not Most Significant Bit Invert In normal low impedance ground plane near the AD9048 this pin floats high logic LOW at E NMINV inverts most significant bit of digital Positive supply terminals nominally 5 0 output word D1 MSB Vre Negative supply terminals nominally 5 2 V NLINV Not Least Significant Bit Invert In normal CONVERT Input for conversion signal sample of analog operation this pin floats high logic LOW at input signal taken on rising edge of this pulse NLINV inverts the seven least significant bits of the digital output word 52V 50V 0 AD AD CONVERT AD3048 2 0 DIGITAL ANALOG 1k GROUND GROUND MESE ALE RESISTORS 576 OPTION 1 STATIC AD1 2 0V AD2 2 4 ALL CAPACITORS 20 Vi AL SUPPI VOLTAGES gute OPTION 2 DYNAMIC SEE WAVEFORMS a ee LA i 20 640 s e U LT LT LI LI LIT LI LI 5 e jsus ih IL Burn In Diagram REV C _5 AD9048 THEORY OF OPERATION Refer to the Functional Block Diagram of the AD9048 The AD9048 comprises three functional sections a comparator array encoding logic and output latches Within the array the analog input signal to be digitized is com pared with 255 reference voltages The outputs of all compara tors whose references are below the input signal level will be high outputs whose references are above that level will be low Th
3. 0 152 0 015 REV C C1212a 0 1 99 PRINTED IN U S A
4. 00000000 01111111 10000000 OUTLINE DIMENSIONS Dimensions shown in inches and mm 28 Lead Ceramic Side Brazed DIP 28 Terminal Leadless Chip Carrier 0 100 2 54 0 055 1 40 0 064 1 63 0 045 1 14 0 075 1 91 REF 0 610 15 24 0 500 14 43 PIN 0 028 0 71 d 0 12 3 05 oa 1 418 36 02 1 38 35 06 0 225 5 72 0 175 4 45 0 125 3 18 0 065 1 66 0 038 0 965 0 095 2 42 LEAD NO 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE GOLD PLATED 50 MICROINCHES MIN KOVAR OR ALLOY 42 0 022 0 003 0 559 0 076 0 06 1 53 d 0 015 0 305 0 008 0 203 gt 4 0 023 0 508 0 105 2 67 SEATING 0 014 0 381 0 620 15 4 0 590 14 74 0 458 11 63 0 442 11 23 sa ME NOTES 0 050 20005 14 1 27 0 13 0 040 1 02 45 REF 3 PLCS BOTTOM 4 0 022 0 56 No 1 PIN INDEX 0 020 0 51 x 45 REF 1 PLC 1 THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS APPLIES TO ALL FOUR SIDES ALL TERMINALS ARE GOLD PLATED 28 Lead J Lead Package 0 450 40 006 TOP VIEW PINS DOWN 4 1143 10 254 11 0 488 40 010 sa 0 171 4 34 MAX gt 0 102 0 010 1 448 0 254 0 039 0 005 0 991 0 127 Y 0 028 0 002 0 711 0 051 0 420 0 010 10 668 0 254 0 019 0 002 F 0 483 0 051 0 006 0 0006
5. 125 C Mito Vis ox voten exce dex a 2 2 V dc to 42 2 Vdc Maximum Junction Temperature Plastic 150 C CONV NMINV or NLINV to DGND 0 5 V dc to 45 5 V dc Maximum Junction Temperature Hermetic 175 C Applied Output Voltage to DGND 0 5 V dc to 5 5 Vdc Lead Temperature Soldering 10 sec 300 C Applied Output Current Externally Forced Storage Temperature Range Blah Re tert teen 1 0 mA to 6 0 mA ELECTRICAL CHARACTERISTI CS Vec 5 0 V Vg 5 2 V Differential Reference Voltage 2 0 V unless otherwise noted Test AD9048JJ JQ AD9048KJ KQ AD9048SE SQ AD9048TE TQ Parameter Conditions Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 8 8 8 8 Bits DC ACCURACY Differential Nonlinearity 25 C I 0 4 0 75 0 3 0 5 0 4 0 75 0 3 0 5 LSB Full VI 1 0 0 75 1 0 0 75 LSB Integral Nonlinearity 25 C I 0 6 0 75 0 4 0 5 0 6 0 75 0 4 0 5 LSB Full VI 1 0 0 75 1 0 0 75 LSB No Missing Codes Full VI GUARANTEED GUARANTEED GUARANTEED GUARANTEED INITIAL OFFSET ERROR Top of Reference Ladder 25 C I 5 12 5 12 5 12 5 12 mV Full VI 12 12 12 12 mV Bottom of Reference Ladder 25 C I 4 8 4 8 4 8 4 8 mV Full VI 8 8 8 8 mV Offset Drift Coefficient Full V 20 20 20 20 ANALOG INPUT Input Voltage Range Full V 2 15 2 1 2 1 2 1 0 1 0 1 0 1 0 1 V Input Bias Current 25 36 60 36 60 36 60 36 60 uA Full VI 100 100 100 100
6. uA Logic 0 Current Full VI 500 500 500 500 uA Input Capacitance 25 C IV 4 6 4 6 4 6 4 6 pF Convert Pulsewidth LOW 25 C I 18 18 18 18 ns Convert Pulsewidth HIGH 25 C I 10 10 10 10 ns 2 REV C AD9048 Test AD9048JJ JQ AD9048KJ KQ AD9048SE SQ AD9048TE TQ Parameter Conditions Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units AC LINEARITY In Band Harmonics dc to 2 438 MHz 25 C I 47 50 49 55 47 50 49 55 dBc dc to 9 35 MHz 25 C V 48 48 48 48 dBc Signal to Noise Ratio SNR 1 248 MHz Input Frequency 25 C I 43 5 44 45 46 43 5 44 45 46 dB 2 438 MHz Input Frequency 25 C I 43 44 44 46 43 44 44 46 dB 1 248 MHz Input Frequency 25 C I 52 5 53 54 55 52 5 53 54 55 dB 2 438 MHz Input Frequency 25 C I 52 53 53 55 52 53 53 55 dB Signal to Noise Ratio SNR 1 248 MHz Input Frequency 25 C I 43 5 44 45 46 43 5 44 45 46 dB 9 35 MHz Input Frequency 25 C V 40 5 40 5 40 5 40 5 dB Noise Power Ratio 25 C IV 36 5 39 36 5 39 36 5 39 36 5 39 dB Differential Phase 20 25 C IV 1 1 1 1 Degree Differential Gain 25 C IV 2 DIGITAL OUTPUTS Logic 1 Voltage Full VI 2 4 2 4 2 4 2 4 V Logic 0 Voltage Full VI 0 5 0 5 0 5 0 5 V Short Circuit Current Full VI 30 30 30 30 mA POWER SUPPLY Positive Supply Current 25 C I 34 56 34 56 34 56 34 56 mA Full VI 58 58 58 58 mA Negative Supply Current 25 C I 90 110 90 110 90 110 90 110 mA Full VI 120 120 120 120 mA N
7. W RTOP 285858t amp kc RMID 8 2 o NMINV CONV MSB D8 J Leaded Ceramic J Package D2 D7 D3 D6 D4 D5 Rg Rr Ry CONVERT NMINV AD9048 D8 LSB DGND DGND MSB D1 TOP VIEW D7 D2 Not to Scale D6 D3 D5 Vec Vee Vee Vee Vcc Vcc DGND D4 NLINV Bonding Diagram NC NO CONNECT CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment can discharge without detection WARNING S Although the AD9048 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality 4 REV C AD9048 PIN FUNCTION DESCRIPTIONS Pin Description Pin Description D1 D8 Eight digital outputs D1 MSB is the most Rg Most negative reference voltage for internal significant bit of the digital output word reference ladder D8 LSB is the least significant bit Ru Midpoint tap on internal reference ladder AGND One of two analog ground returns Both Rr Most positive reference voltage for internal grounds should be connected together and to reference ladder low impedance ground plane near the AD9048 S IN Analog input signal pin DGND One of two digital ground returns Both
8. e n 0f 255 code that results from this comparison is applied to the encoding logic where it is converted into binary coding When it is inverted with dc signals applied to the NLINV and or NMINV pins it becomes twos complement After encoding the signal is applied to the output latch circuits where it is held constant between updates controlled by the application of CONVERT pulses The AD9048 uses strobed latching comparators in which com parator outputs are either high or low as dictated by the analog input level Data appearing at the output pins have a pipeline delay of one encode cycle Input signal levels between the references applied to Pin 18 and Rg Pin 26 will appear at the output as binary numbers between 0 and 255 inclusive Signals outside that range will show up as either full scale positive or full scale negative out puts No damage will occur to the AD9048 as long as the input is within the voltage range of Vgg to 0 5 V The significantly reduced input capacitance of the AD9048 lowers the drive requirements of the input buffer amplifier and also induces much smaller phase shift in the analog input signal Applications that depend on controlled phase shift at the con verter input can benefit from using the AD9048 because of its inherently lower phase shift The CONVERT analog input and digital output circuits are shown in Figure 1 Nit ANALOG N INPUT APERTURE DELAY CONVERT fa eS Syst
9. ed as closely as possible to the supply pins of the AD9048 For decoupling low frequency signals use 10 uF tantalum capacitors also con nected as closely as practical to voltage supply pins Within the AD9048 reference currents may vary because of coupling between the clock and input signals As a result it is important that the ends of the reference ladder Pin 18 and Rg Pin 28 be connected to low impedances as measured from ground If the AD9048 is being used in a circuit in which the reference is not varied a bypass capacitor to ground is strongly recom mended In applications that use varying references they must be driven from a low impedance source ANALOG INPUT iov TO 2V D1iMSB ADg048 CONVERT 0 1pF 0 1 F 52V 45 0V Figure 5 Typical Connections AD9048 Table I Truth Table Offset Twos Binary Complement Step Range True Inverted True Inverted 2 000 V FS 2 0480 V FS NMINV 1 0 0 1 7 8431 mV Step 8 000 mV Step NLINV 1 0 1 0 000 0 0000 V 0 0000 V 00000000 11111111 10000000 01111111 001 0 0078 V 0 0080 V 00000001 11111110 10000001 01111110 127 0 9961 V 1 0160 V 01111111 10000000 11111111 00000000 128 1 0039 V 1 0240 V 10000000 01111111 00000000 11111111 129 1 0118 V 1 0320 V 10000001 01111110 00000001 11111110 254 1 9921 V 2 0320 V 11111110 00000001 01111110 10000001 255 2 0000 V 2 0400 V 11111111
10. em timing which provides details on delays through the AD9048 as well as the relationships of various timing events is shown in Figure 2 Dynamic performance of the AD9048 i e typical signal to noise ratio is illustrated in Figures 3 and 4 45 04 5 0 Tiki CONVERT DIGITAL OUTPUTS ANALOG INPUT COMPARATOR CELLS Figure 1 Input Output Circuits N 2 OUTPUT DATA nn tro v ns DATA DATA CHANGING CHANGING Figure 2 Timing Diagram REV C AD9048 SIGNAL TO NOISE RATIO dB 1D0kHz MHz TOMIHz ANALOG INPUT FREQUENCY 1dB BELOW FULL SCALE Figure 3 Dynamic Performance 20 MHz Encode Rate SIGNAL TO NOISE RATIO dB 1MHz 10MHz ANALOG INPUT FREQUENCY 118 BELOW FULL SCALE Figure 4 Dynamic Performance 35 MHz Encode Rate LAYOUT SUGGESTIONS Designs that use the AD9048 or any other high speed device must follow some basic layout rules to ensure optimum performance The first requirement is to have a large low impedance ground plane under and around the converter If the system uses sepa rate analog and digital grounds both should be solidly con nected together and to the ground plane as closely to the AD9048 as practical to avoid ground loop currents REV C Ceramic 0 1 uF decoupling capacitors should be plac
11. ibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM E N c 1 N G L G 1 c T T T Vec VEE DGND AGND Commercial versions are packaged in 28 lead DIPs extended temperature versions are available in ceramic DIP and ceramic LCC packages Both commercial units and MIL STD 883 units are standard products The AD9048 A D converter is available in versions compliant with MIL STD 883 Refer to the Analog Devices Military Prod ucts Databook or current AD9048 883B data sheet for detailed specifications One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1999 AD 9048 SPEC CATI 0 NS typical with nominal supplies unless otherwise noted ABSOLUTE MAXIMUM RATINGS Vecto 0 5 V dc to 7 0 V dc Output Short Circuit Duration 1 0 sec AGND to DGND 0 5 V dc to 0 5 Vdc Operating Temperature Range Ambient Vg to AGND 0 5 V dc to 7 0 V dc AD9048 KJQ KQ 0 C to 70 C Vins Vat or to 0 5 V to Veg AD9048SE SQ TE TQ 55 C to
12. l Linearity Temperature Option MSB D1 1 e 28 NMINV AD9048 J 0 75 LSB 0 C to 70 C J 28A p2 2 Ru AD9048K 0 5 LSB 0 C to 70 C J 28A ps 26 Re AD9048JQ 0 75 LSB 0 C to 70 C Q 28 D4 4 25 AGND AD9048KQ 0 5 LSB 0 C to 70 C Q 28 5 a Nc AD9048SE 0 7515 55 C to 125 C E 28A top view 3 Ym AD9048TE 0 5 LSB 55 C to 125 C E 28A Vee 7 Motto Seale 22 AD9048SQ 0 75 LSB 55 C to 125 C Q 28 Vee 8 NC AD9048TQ 0 5 LSB 55 C to 125 C Q 28 Vee 9 Nc NOTES Vcc 10 19 AGND 1 Leadless Ceramic Chip Carrier J J Leaded Ceramic Q Cerdip DGND 18 For temperature designation only MIL STD 883 and Standard Military NLINV 12 CONVERT Drawing available D5 13 16 D8 LSB D6 14 D7 MECHANICAL INFORMATION Ne NAST Die Dimensions 140 x 137 x 21 2 mils LCC E Package Pad Dimensions 000 e rania aa 4 x 4 mils 9 z MetaliZation pa epe e aeaa a E Set Gold tears qgqgqoazce Backing iere RIDERE PR AC None 4 3 2 1 28 27 26 Substrate Potential VEE m Rep DGND 5 LI 25 AGND Passivation iui gelation E SA RC ROT IRA a i Nitride Vec i Die Attach cce RIS Gold Eutectic f 2 V Vee 7 AD9048 IN Bond Wire 1 mil Gold Gold Ball Bonding Vee 8 TOPVIEW 22 NC Vee 9 Not to Scale 21 NC Vec 10 20 NC AGND AIN AGND DGND 11 19 AGND 12 13 14 15 16 17 18 RLO
13. ominal Power Dissipation 25 C V 550 550 550 550 mW Reference Ladder Dissipation 25 C V 45 45 45 45 mW NOTES Maximum ratings are limiting values to be applied individually and beyond which the serviceability of the device may be impaired Functional operation under any of these conditions is not necessarily implied Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability Applied voltage must be current limited to specified range Forcing voltage must be limited to specified range Current is specified as negative when flowing into the device 5Output High one pin to ground one second duration Typical thermal impedances no air flow are as follows Ceramic DIP 0j 49 C W3 15 C W LCC 65 69 C W 21 C W JLCC 044 59 C W3 19 C W To calculate junction temperature use power dissipation PD and thermal impedance PD 054 PD jc Tcasz Measured with 0 V and CONVERT low sampling mode 5Determined by beat frequency testing for no missing codes Ver gt Vgg under all circumstances Outputs terminated with 40 pF and eight 10 Q pull up resistors Interval from 50 point of leading edge CONVERT pulse to change in output data 1 For full scale step input 8 bit accuracy attained in specified time PRecovers to 8 bit accuracy in specified time after 3 V input overvoltage Ou
14. tput time skew includes high to low and low to high transitions as well as bit to bit time skew differences P Measured at 20 MHz encode rate with analog input 1 dB below full scale l Measured at 35 MHz encode rate with analog input 1 dB below full scale 17RMS signal to rms noise 18Peak signal to rms noise IDC to 8 MHz noise bandwidth with 1 248 MHz slot four sigma loading 20 MHz encode Clock frequency 4 x NTSC 14 32 MHz Measured with 40 IRE modulated ramp Specifications subject to change without notice EXPLANATION OF TEST LEVELS Test Level V Test Level VI Parameter is a typical value only All devices are 100 production tested at 25 C 100 production tested at tempera ture extremes for military temperature de vices sample tested at temperature extremes for commercial industrial devices Test Level I 100 production tested Test Level II 100 production tested at 25 C and sample tested at specific temperatures Test Level III Sample tested only Test Level IV Parameter is guaranteed by design and characterization testing REV C 3 AD9048 ORDERING GUIDE PIN DESIGNATIONS Package DIP Q Package Mode
15. uA Input Resistance 25 C JI 200 300 200 300 200 300 200 300 kQ Full VI 40 40 40 40 kQ Input Capacitance 25 C IV 16 20 16 20 16 20 16 20 pF Full Power Bandwidth 25 C IV 10 15 10 15 10 15 10 15 MHz REFERENCE INPUT Positive Reference Voltage Full V 0 0 0 0 0 0 0 0 V Negative Reference Voltage Full V 2 0 2 0 2 0 2 0 V Differential Reference Voltage Full V 2 0 2 0 2 0 2 0 V Reference Ladder Resistance Full VI 30 60 125 30 60 125 30 60 125 30 60 125 Q Ladder Temperature Coefficient Full V 0 22 0 22 0 22 0 22 QC Reference Ladder Current Full VI 23 40 23 40 23 40 23 40 mA Reference Input Bandwidth 25 C V 10 10 10 10 MHz DYNAMIC PERFORMANCE Conversion Rate 25 C I 35 38 35 38 35 38 35 38 MHz Aperture Delay 25 C IV 2 4 5 2 4 5 2 4 5 2 4 5 ns Aperture Uncertainty Jitter 25 C IV 25 50 25 50 25 50 25 50 ps Output Delay tpp 25 C I 13 15 9 15 9 15 9 15 ns Output Hold Time toy 25 5 8 5 8 5 8 5 8 ns Transient Response 25 C IV 6 20 6 20 6 20 6 20 ns Overvoltage Recovery Time 25 C V 8 8 8 8 ns Rise Time 25 C I 9 9 9 ns Fall Time 25 C I 14 14 14 14 ns Output Time Skew 25 1 45 7 45 1 4 5 45 7 ns NMINV and NLINV INPUTS 0 4 V Input Current Full VI 200 200 200 200 uA 2 4 V Input Current Full VI 150 150 150 150 uA 5 5 V Input Current Full VI 150 150 150 150 uA CONVERT INPUT Logic 1 Voltage Full VI 2 0 2 0 2 0 2 0 V Logic 0 Voltage Full VI 0 8 0 8 0 8 0 8 V Logic 1 Current Full VI 150 150 150 150

ANALOG DEVICES AD9048 Monolithic 8-Bit Video A/D Converter handbook

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