ANALOG DEVICES 10-Bit 40 MSPS A/D Converter AD9040A handbook
Contents
1. Vs Transistor Count 5 070 Keone wise Secs Meas Oxynitride Die Attach Epoxy Bond Wire IN IR Gold mE REV B AD9040A DEFINITIONS OF SPECIFICATIONS Analog Bandwidth analog input frequency at which the spectral power of the fundamental frequency as determined by FFT analysis is reduced by 3 dB Aperture Delay delay between the rising edge of the ENCODE command and the instant at which the analog input is sampled Aperture Uncertainty Jitter sample to sample variation in aperture delay Differential Gain percentage of amplitude change of a small high frequency sine wave 3 58 MHZ superimposed on a low frequency signal 15 734 kHz Differential Nonlinearity deviation of any code from an ideal 1 LSB step Differential Phase The phase change of a small high frequency sine wave 3 58 MHz superimposed on a low frequency signal 15 734 kHz Harmonic Distortion rms value of the fundamental divided by the rms value of the harmonic Integral Nonlinearity deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line de termined by a least square curve fit Minimum Conversion Rate encode rate at which the SNR of the lowest analog signal freq2. 8 5V 5 zg GND H4 H5 He 1 M j c5 1 zy GND w wa 1 09 gg GND D8 gg GND T T J9 GND D7 7 34 GND p 1 06 5z GND 5V D5 zz GND c14 c15 cie c17 10 GNP 0 1pF 0 1pF 0 1pF 0 1pF 0 1pF D3 30 GND 02 gg GND 13 ope l 14 7 cnp 5V i GND est ee ess Messer cie 5 286 GND C9 C10 c11 C12 C18 16 5 GND O1pF 17 27 OND 1 D1 18 x GND B DO 21 GND 9 GND Figure 10 PCB Schematic 10 REV B eo o o DISSIPATION Watts 0 4 4 6 10 20 CLOCK RATE MSPS 40 60 Figure 11 Power Dissipation vs Clock Rate a LEAST SIGNIFICANT BITS LSBs 10 20 30 CLOCK MSPS 40 Figure 14 Differential Nonlinearity vs Clock Rate SIGNAL TO NOISE RATIO dB 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C Figure 17 SNR vs Temperature ENCODE 40 5 MSPS f1 IN 2 25 MHz 7 dBFS 12 IN 2 35 MHz 7 dBFS 2f1 12 69 4 dBFS 212 f1 69 2 dBFS a AAA ey pas 0 2 5 FREQUENCY MHz Figure 20 REV B HARMONIC D
3. D 904045 hy f ANALOG DEVICES 10 Bit 40 MSPS A D Converter AD9040A FEATURES Low Power 940 mW 53 dB SNR 10 MHz Ay On Chip T H Reference CMOS Compatible 2 V p p Analog Input Fully Characterized Dynamic Performance APPLICATIONS Ultrasound Medical Imaging Digital Oscilloscopes Professional Video Digital Communications Advanced Television MUSE Decoders Instrumentation GENERAL DESCRIPTION The AD9040A is a complete 10 bit monolithic sampling analog to digital converter ADC with on board track and hold and reference The unit is designed for low cost high performance applications and requires only an encode signal to achieve 40 MSPS sample rates with 10 bit resolution Digital inputs and outputs are CMOS compatible the analog input requires a signal of 2 V p p amplitude The two step architecture used the AD9040A is optimized to provide the best dynamic performance available while maintaining low power requirements of only 940 mW typically maximum dissi pation is 1 1 watt at 40 MSPS signal to noise ratio SNR including harmonics is 53 dB or 8 5 ENOB when sampling an analog input of 10 3 MHz at 40 MSPS Competitive devices perform at less than 7 5 ENOB and require external references and larger input signals AD9040A A D converter is available as either a 28 lead plastic DIP or a 28 lead SOIC The two models operate over a commercial temperature range of 0 C to 70 C
4. AD9040A SPECIFICATIONS ELECTRICAL CHARACTERISTICS Vs Vy 5 V Vs 5 V internal reference ENCODE 40 5 MSPS unless otherwise noted Test AD9040AJNITR Parameter Conditions Temp Level Min Typ Max Units RESOLUTION 10 Bits DC ACCURACY Differential Nonlinearity 25 C I 1 0 2 0 LSB Full VI 2 5 LSB Integral Nonlinearity 25 C I 1 0 2 0 LSB Full VI 2 5 LSB No Missing Codes Full VI Guaranteed Gain Error 25 C I 0 5 15 FS Full VI 2 FS Gain Tempco Full V 70 ppm C ANALOG INPUT Input Voltage Range 25 C V 2 V p p Input Offset Voltage 25 C I 2 25 mV Full VI 30 mV Input Bias Current 25 C I 7 15 25 uA Input Resistance 25 C I 200 350 kQ Input Capacitance 25 C V 5 pF Analog Bandwidth 25 C V 48 MHz BANDGAP REFERENCE Output Voltage Full VI 2 4 2 6 V Temperature Coefficient Full V t40 ppm C SWITCHING PERFORMANCE Maximum Conversion Rate 25 C I 40 MSPS Minimum Conversion Rate 25 C IV 2 10 MSPS Aperture Delay t4 25 C V 1 9 ns Aperture Uncertainty Jitter 259 V 7 ps rms Output Propagation Delay tpp 25 C I 7 5 10 12 ns Full IV 6 14 ns DYNAMIC PERFORMANCE Transient Response 25 C V 25 ns Overvoltage Recovery Time 259 V 40 ns Signal to Noise Ratio fw 2 3 MHz 25 C I 51 54 dB fm 10 3 MHz 25 C I 50 53 dB Signal to Noise Ratio Without Harmonics fw 2 3 MHz 25 C I 52 55 dB fin 10 3 MHz 25 C I 51 54 dB Signal to Noise Ra
5. 2 CLK a 9 450 5 500 Figure 8 Top View Figure 9 PCB Bottom View DAC Reconstruction me AD9040A evaluation board provides an onboard AD9721 Table II Digital Coding reconstruction DAC for observing the digitized analog input signal The AD9721 is terminated into 51 ohms to provide a Digital Output 1 V p p signal at the output RC OUTPUT EVE MIBA THAM Output Data MSB LSB The output data bits are latched with a CMOS 74AC574 which 1 002 V Positive Full Scale 1 LSB 1 1111111111 drives a 40 pin connector AMP p n 102153 9 The data and 1 V Positive Full Scale 0 1111111111 clock signals are available on the connector per the pin assign Full Scale 1 LSB 0 1111111110 ments shown on the schematic of the evaluation board Output E data are available on the falling edge of the clock 1 2 V E 1109900090 1 2 Scale 1 LSB 0 1011111111 0 10000000000 Bipolar Zero 0 01111111111 12 1 2 Scale 1 LSB 0 0100000000 Negative 1 2 Scale 0 0011111111 LV Full Scale 1 LSB 0 0000000001 Y Negative Full Scale 0 0000000000 1 002 V Negative Full Scale 1 LSB 1 0000000000 REV B 9 AD9040A 04 74 574 U2 05 AD9721BR GND U1 74HC86 9 CLK 74HC86 R13 1000 R12 1000 6 OUTPUT 74HC86 4 U1 74HC86 7 5V J L c3 H40DMC J3 1 cub 2 39
6. Contact the factory regarding availability of ceramic military temperature range devices REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM ENCODE ERROR CORRECTION DECODE DECODE AD9040A PRODUCT HIGHLIGHTS 1 CMOS compatible logic for direct interface to ASICs 2 On board T H provides excellent high frequency perfor mance on analog inputs critical for communications and medical imaging applications 3 High input impedance and 2 volt p p input range reduce need for external amplifiers 4 Easy to use no cumbersome external voltage references required allowing denser packing of ADCs for multichannel applications 5 Available in 28 lead plastic DIP and SOIC packages 6 Evaluation board includes AD9040AJR reconstruction and latches Space is available near the analog input and digital outputs of the converter for additional circuits Order as part number AD9040A PCB schematic shown in data sheet One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1999
7. reus dU RIO eva 7 V Output propagation delay tpp is measured from the 50 point of the falling edge of the encode command to the min max voltage levels of the digital VD 7 V outputs with 10 pF maximum loads ANALOG TIN ecc ane EE EEE Vs to 3RMS signal to rms noise with analog input signal 1 dB below full scale at 5 to Vs 222 2 Vat put 0 V to Vs 53rd order intermodulation measured with analog input frequencies of 2 3 MHz Digital Output Current 20 mA and 2 4 MHz at 7 dB below full scale Operating Temperature For rated performance at 40 MSPS duty cycle of encode command should be AD9040AJN TR 09 to 70 C 2809 10 Storage Temperature 65 C to 150 C Measured as the ratio of the change in offset voltage for a 5 change Maximum Junction Temperature JN JR Suffixes 150 C Lead Soldering Temp 10 sec 300 C Specifications subject to change without notice EXPLANATION OF TEST LEVELS Test Level 100 Production Tested II 100 production tested at 25 C and sample tested at specified temperatures AC testing done on sample basis III Sample Tested Only IV Parameter is guaranteed by design and characterization testing V Paramet
8. ENCODE 40 5 MSPS ANALOG IN 2 3 MHz ENCODE 40 5 MSPS SNR 55 20 dB ANALOG IN 10 3 MHz SNR w o har 55 90 dB SNR 53 38 dB 2nd HARMONIC 75 1 dB SNR w o har 54 31 dB 3rd HARMONIC 73 2 dB 2nd HARMONIC 64 7 dB 65 3rd HARMONIC 73 7 dB i 0 10 1 20 2 0 10 1 20 2 FREQUENCY MHz FREQUENCY MHz Figure 21 Figure 22 zT1 AD9040A OUTLINE DIMENSIONS Dimensions shown in inches and mm 28 Lead Plastic DIP N 28 1 565 39 70 1 380 35 10 28 15 0 550 13 97 0 530 13 46 R 14 PING 0 015 0 38 0 250 7 MIN 6 35 i MAX X S ALB PUB IHBUB IB UA BUS HUS 0 140 t 3 55 NC MIN 4 gt HF 0 022 0 558 0 100 0 070 SEATING 0 014 0 356 ped 1 77 PLANE MAX 0 625 15 87 05 15 24 0 015 0 381 0 008 0 204 12 28 Lead SOIC Package R 28 j 0 300 7 60 0 292 7 40 0 419 10 64 0 393 9 98 14 1 g 0 712 18 08 1 0 700 17 78 L Ear nem 0 093 2 36 F gt je gt e 0 012 0 30 0 050 0 019 0 48 0 004 0 10 52 0 014 0 36 0 013 0 33 Y 0009 023 alg on 2 1835 0 5 99 PRINTED U S A
9. ISTORTION dBc AD9040A 73 ENCODE 40 5 MSPS 66 m i 5 68 HARMONIC 4 4 DISTORTION E 63 o 48 6 SNR 2 2 190 6 9 3 lt lt z 53 5 5 420 o 4 8 1 2 4 6 10 20 4060 100 4 12 20 28 36 Figure 12 Harmonic Distortion FREQUENCY MHz CLOCK RATE MSPS Figure 13 SNR vs Clock Rate and SNR vs Analog Input 1024 1024 A 896 992 9 768 5 960 n n 640 5 928 l 512 4 Y 535 9 384 g 96 4 3 256 s 64 5 128 32 00 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 Figure 15 Transient Response TIME ns TIME ns Figure 16 Transient Response Expanded View ENCODE 32 2 MSPS ANALOG IN 2 3 MHz SNR 56 79 dB SNR w o har 57 58 dB 2nd HARMONIC 68 5 dB 3rd HARMONIC 80 7 dB ENCODE 32 2 MSPS ANALOG IN 10 3 MHZ SNR 55 37 dB SNR w o har 56 77 dB 2nd HARMONIC 63 3 dB 3rd HARMONIC 75 4 dB mm lii 0 8 0 16 1 0 8 0 16 1 FREQUENCY MHz FREQUENCY MHz Figure 18 Figure 19 0
10. Supply 5 Vout Internal Bandgap Voltage Reference Nominally 2 5 V 6 VREF Noninverting Input to Reference Amplifier Voltage reference for ADC is connected here 7 BP rer External Connection for 0 1 Reference Bypass Capacitor 8 NC No Connection Internally 9 ENCODE Encode Clock Input to ADC Internal T H placed in hold mode ADC is encoding on rising edge 13 Aw Noninverting Input to T H Amplifier 15 OR Out of Range Condition Output Active high when analog input exceeds input range of ADC by 1 LSB lt 5 1 LSB or gt FS 1 LSB 16 D9 MSB Most Significant Bit of ADC Output TTL CMOS Compatible 17 20 D8 D5 Digital Output Bits of ADC TTL CMOS Compatible 23 Vp Digital 5 V Power Supply 24 27 D4 D1 Digital Output Bits of ADC TTL CMOSL Compatible 28 DO LSB Least Significant Bit of ADC Output TTL CMOS Compatible vs 1 e 25 DO LSB GND 2 D1 Vs 26 D2 GND 4 25 D3 relel ango4oa BPrer 7 view 22 GND ENCODE 9 20 D5 Vs 19 D6 GND 11 18 D7 Vs D8 An 13 16 D9 MSB GND 14 15 OR NC NO CONNECT PDIP and SOIC Pinouts Vs ENCODE NC BPrer VREF Vout GND DIE LAYOUT AND MECHANICAL INFORMATION Die Dimensions 204 x 185 x 21 1 mils Pad Dimensions 4 x 4 mils Metalization ose eV ATH d Sce ea iet Aluminum Backing dee RR RI ERES Meg cha EIE SUUS None Substrate Potential
11. board The two sided board includes a recon struction DAC and digital output interface and uses the layout and applications suggestions outlined above It is available from Analog Devices at nominal cost Generous space is provided near the analog input and digital outputs to support additional signal processing components the user may wish to add This prototyping area includes through holes with 100 mil centers to support a variety of component additions Input Output Supply Information Power supply analog input clock connections and recon structed output RC OUTPUT are identified by labels on the evaluation board Operation of the evaluation board should conform to the following characteristics Table I Evaluation Board Characteristics Parameter Typical Units Supply Current T5V 250 mA 5 2 V 300 mA Aw Impedance 51 Q Voltage Range 1 0 V CLOCK Impedance 51 Q Frequency 40 MSPS RC OUTPUT Impedance 51 Q Voltage Range 0Vto 1V V Analog Input Analog input signals can be fed directly into the Device Under Test input Am The input is terminated at the device with a 51 Q resistor 8 REV B AD9040A 5 500 29 0 34904 A a ITITPPPTIIIID LEALES J AD9040A EVALUATION BOARD J X i 1 i ap
12. ept short and run lengths should be matched to avoid propagation delay mismatch The AD9040A digital outputs should be buffered or latched close to the device lt 2 cm This prevents load transients which may feedback into the device In high speed circuits layout of the ground is critical A single low impedance ground plane on the component side of the board is recommended Power supplies should be capacitively coupled to the ground plane with high quality chip capacitors to reduce noise in the circuit Multilayer boards allow designers to lay out signal traces without interrupting the ground plane and provide low impedance ground planes In systems with dedi cated analog and digital grounds all grounds of the AD9040A should be connected to the analog ground plane power supplies of the AD9040A should be isolated from the supplies used for external devices this reduces the amount of noise coupled into the ADC The digital 5 volt connection of the device Vp Pin 23 powers the digital outputs and should be connected to the same supply as Vs Pins 3 and 10 Con necting Vy to a system digital supply may couple noise into the device Sockets limit dynamic performance and are not recom mended for use with the AD9040A EVALUATION BOARD The evaluation board for the AD9040A AD9040A PCB pro vides an easy and flexible method for evaluating the ADC s performance without or prior to developing a user specific printed circuit
13. er is a typical value only VI devices 100 production tested at 25 C 100 production tested at temperature extremes for military temperature devices guaranteed by design and character ization testing for industrial devices NOTES Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired Functional operability is not necessarily implied Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability Typical thermal impedances parts soldered to board N Package Plastic DIP 6j4 42 C W 10 C W R Package SOIC 47 C W 10 C W ORDERING GUIDE Model Temperature Range Package Description Package Option AD9040AJN 0 C to 70 C 28 Lead Plastic DIP N 28 AD9040AJR 0 C to 70 C 28 Lead SOIC Package R 28 AD9040A PWB Printed Circuit Board Only of Evaluation Circuit AD9040A PCB Complete Evaluation Board Assembled and Tested Including AD9040AJR REV AD9040A t etin A 2 3 ENCODE ten ter 1 troe 11 DIGITAL OUTPUTS TYP tA APERTURE DELAY 1 9 ten PULSEWIDTH HIGH 10 100 teL PULSEWIDTH LOW 10 100 tipp OUTPUT PROP DELAY 7 5 10ns 12 Figure 1 Timing Diagram PIN FUNCTION DESCRIPTIONS Pin No Name Function 1 12 21 Vs 5 V Power Supply 2 4 11 14 22 GND Ground 3 10 Vs Analog 5 V Power
14. in burst mode The 50 duty cycle must be main tained even for sample rates down to 10 MSPS The AD9040A provides latched data outputs with 2 1 2 pipe line delays Data outputs are available one propagation delay tpp after the falling edge of the encode command refer to AD9040A Timing Diagram The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9040A these transients detract from the converter s dynamic performance Voltage Reference stable voltage reference is required to establish the 2 V p p range of the AD9040A There are two options for creating this reference The easiest and least expensive way to implement it is to use the 2 5 V bandgap voltage reference which is internal to the ADC Figure 3 illustrates the connections for using the internal reference The internal reference has 500 of extra drive current which can be used for other circuits AD9040A BANDGAP REFERENCE Figure 3 Using Internal Reference Some applications may require greater accuracy improved temperature performance or adjustment of the gain input range of the AD9040A which cannot be obtained by using the internal reference For these applications an external 42 5 V reference can be used as shown in Figure 4 The Vggg input requires 5 of drive current AD9040A BANDGAP REFERENCE REFERENCE REFERENCE Vs Figure 4 Using Exter
15. nal Reference 6 REV B AD9040A In applications using multiple AD9040As slaving the reference inputs to a single reference output will improve gain tracking among the ADCs as shown in Figure 5 AD9040A Figure 5 Slaving Multiple AD9040As to a Single Internal Reference In the specifications table the Gain Tempco parameter under DC ACCURACY applies to the ADC when the internal refer ence is being used If an external reference is used its tempera ture coefficient must be taken into account to determine overall temperature performance The input range can be varied by adjusting the reference voltage applied to the AD9040A By decreasing the reference voltage the gain can be reduced approximately 10 with no degrada tion in performance Increasing the reference voltage increases the gain but for proper operation the reference voltage should not exceed 2 6 V REV B Time Gain Control ADC Ultrasound and sonar systems require an increase in gain versus time This allows the system to correct for attenuation of return pulses Figure 6 shows the AD600 AD602 amplifier and the AD9040A ADC configured as a time gain control analog to digital converter The control voltage ramps from 625 mV to 625 mV permitting 40 dB of gain control range The voltage used for gain control can be either a linear ramp or the output of a voltage output DAC such as the AD7242 GAIN CONTROL VOLTAGE AD9040A Figure 6 Ultrasound So
16. nar Time Gain Control ADC Using X AMPs Transient Response Figure 7 illustrates the method for evaluating ADC transient performance Two synthesizers are locked in synchronization but tuned to frequencies which are slightly offset from a 2 to 1 submultiple One synthesizer clocks a flat pulse network at a frequency of 19 9609375 MHz to provide the analog input signal the other synthesizer output is shaped to provide a CMOS 40 MHz sam pling clock At the output of the AD9040A output data reflects an interleaved alias of the input pulse The repetitive sampling allows the measurement of ADC transient response as shown in performance graphs elsewhere in this data sheet MARCONI 2030 SYNTHESIZER FLAT PULSE NETWORK REF 19 9609375 MHz ANALOG IN AD9040A OUTPUT ENCODE MARCONI 2030 SYNTHESIZER REF 40 MHz Figure 7 Transient Response Test X AMP is a trademark of Analog Devices Inc AD9040A Layout Information Preserving the accuracy and dynamic performance of the AD9040A requires that designers pay special attention to the layout of the printed circuit board Analog paths should be kept as short as possible and be properly terminated to avoid reflections The analog input and reference voltage connections should be kept away from digital signal paths this reduces the amount of digital switching noise which is capacitively coupled into the analog section Digital signal paths should also be k
17. one bit of error correction for the 5 bit main range converter Decode logic aligns the data from the two converters and pre sents the result as a 10 bit parallel digital word The output stage of the AD9040A is CMOS Output data are strobed on the trailing edge of the ENCODE command Full scale range of the AD9040A is determined by the reference voltage applied to the Pin 6 input This voltage sets the internal flash and residue ladder voltage drops these establish the value of the LSB Because of headroom restraints the full scale range cannot be increased by applying a higher than specified reference voltage Conversely a lower reference volt age will reduce the full scale range of the converter but will also decrease its performance An internal bandgap reference voltage of 2 5 V is provided to assure optimum performance over the operating temperature range USING THE AD9040A Timing The duty cycle of the encode clock for the AD9040A is critical for obtaining rated performance of the ADC Internal pulse widths within the track and hold are established by the encode command pulse width to ensure rated performance the duty cycle should be held at 50 Duty cycle variations of less than 10 will cause no degradation in performance Operation at encode rates less than 10 MSPS is not recom mended The internal track and hold saturates causing errone ous conversions This T H saturation precludes clocking the AD9040A
18. the strongest third order IMD signal BANDGAP OUTPUT CMOS OUTPUT Figure 2 Equivalent Circuits REV B AD9040A THEORY OF OPERATION Refer to the block diagram The AD9040A employs subranging architecture and digital error correction This combination of design techniques insures true 10 bit accuracy at the digital outputs of the converter At the input the analog signal is applied to a track and hold T H that holds the analog value which is present when the unit is strobed with an ENCODE command The conversion process begins on the rising edge of this pulse which should have 50 10 duty cycle Minimum encode rate of the AD9040A is 10 MSPS because of the use of three internal T H devices held analog value of the first track and hold is applied to a 5 bit flash converter and a pair of internal T Hs shown in the block diagram as a single unit The T Hs pipeline the analog signal to the amplifier array through a residue ladder and switch ing circuit while the 5 bit flash converter resolves the most significant bits MSBs of the held analog voltage When the 5 bit flash converter has completed its cycle its out put activates 1 of 32 ladder switches these in turn cause the correct residue signal to be applied to the error amplifier array output of the error amplifier is applied to a 6 bit flash con verter whose output supplies the five least significant bits LSBs of the digital output along with
19. tio fw 2 3 MHz 25 C I 52 56 dB fw 10 3 MHz 25 C I 51 55 dB Signal to Noise Ratio 4 Without Harmonics fw 2 3 MHz 259 53 57 fw 10 3 MHz 25 C I 53 56 dB 2nd Harmonic Distortion fw 2 3 MHz 25 C I 56 67 dBc fin 10 3 MHz 25 C I 56 65 dBc 3rd Harmonic Distortion fw 2 3 MHz 25 C I 58 73 dBc fin 10 3 MHz 25 C I 58 70 dBc Two Tone Intermodulation 25 C V 62 dBc Distortion Rejections Differential Phase 25 C III 0 15 0 5 Degrees Differential Gain 25 C III 0 25 1 0 2 REV B AD9040A Test AD9040AJNIJR Parameter Conditions Temp Level Min Typ Max Units ENCODE INPUT Logic 1 Voltage Full VI 4 0 V Logic 0 Voltage Full VI 1 0 V Logic 1 Current Full VI 1 uA Logic 0 Current Full VI 1 uA Input Capacitance 25 C V 14 pF Encode Pulsewidth High 25 C IV 10 100 ns Encode Pulsewidth Low tg 25 C IV 10 100 ns DIGITAL OUTPUTS Logic 1 Voltage Full VI 4 95 V Logic 0 Voltage Full VI 0 05 V Output Coding Offset Binary POWER SUPPLY Vp Supply Current Full VI 13 20 mA Vs Supply Current Full VI 89 110 mA Vs Supply Current Full VI 87 105 mA Power Dissipation Full VI 0 94 1 2 W Power Supply Rejection Ratio PSRR 259 15 mV V NOTES 1 Tempco is for converter using internal reference Temperature ABSOLUTE MAXIMUM RATINGS Coefficient is for bandgap reference only EV Gs m DAR
20. uency tested drops by no more than 3 dB below the guaran teed limit ANALOG INPUT REFERENCE CIRCUIT Vss Maximum Conversion Rate encode rate at which parametric testing is performed Output Propagation Delay delay between the 50 point of the falling edge of the ENCODE command and the 1 V 4 V points of output data Overvoltage Recovery Time amount of time required for the converter to recover to 10 bit accuracy after an analog input signal 150 of full scale is reduced to the full scale range of the converter Power Supply Rejection Ratio PSRR ratio of a change in input offset voltage to a change power supply voltage Signal to Noise Ratio SNR ratio of the rms signal amplitude to the rms value of noise which is defined as the sum of all other spectral com ponents including harmonics but excluding dc with an analog input signal 1 dB below full scale Signal to Noise Ratio Without Harmonics ratio of the rms signal amplitude to the rms value of noise which is defined as the sum of all other spectral com ponents excluding the first eight harmonics and dc with an analog input signal 1 dB below full scale Transient Response The time required for the converter to achieve 10 bit accuracy when a step function is applied to the analog input Two Tone Intermodulation Distortion IMD Rejection ratio of the power of either of two input signals to the power of
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ANALOG DEVICES 10 Bit 40 MSPS A/D Converter AD9040A handbook