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ANALOG DEVICES AD9020 handbook

1. 0000000000 Vsense VA REF 3 4 pee Vsense Effect of Reference Taps on Linearity Resistance between the reference connections and the taps of the first and last comparators causes offset errors T hese errors called top and bottom of the ladder offsets can be nulled by using the voltage sense lines Vsense and Vsense to adjust the reference voltages C urrent through the sense lines should be limited to less than 100 pA Excessive current drawn through the voltage sense lines will affect the accuracy of the sense line voltage T he next page shows a reference circuit which nulls out the off set errors using two op amps and provides appropriate voltage references to the quarter point taps F eedback from the sense lines causes the op amps to compensate for the offset errors T hetwo transistors limit the amount of current drawn directly from the op amps resistors at the base connections stabilize their operation T he 10 KQ resistors R 1 R4 between the volt age sense lines form an external resistor ladder the quarter point voltages are taken off this external ladder and buffered by an op amp T he actual values of resistors R1 R4 are not critical but they should match well and be large enough 210 kQ to limit the amount of current drawn from the voltage sense lines T he select resistors Rs shown in the schematic each pair can be a potentiometer are chosen to adjust the quarter point volt age references but ar
2. A ENCODE RATE 40MSPS a eo e eo e N EFFECTIVE NUMBER OF BITS ENOB N o 20 1 2 4 6 810 20 40 60 100 200 INPUT FREQUENCY MHz AD9020 SNR and ENOB vs Input Frequency 30 35 40 125 C 45 50 HARMONICS dBc 55 60 65 70 1 2 4 6 810 20 40 60 100 INPUT FREQUENCY MHz AD9020 Harmonics vs Input Frequency SIGNAL TO NOISE SNR dB INPUT CAPACITANCE pF NALOG INPUT 2 3MHz EFFECTIVE NUMBER OF BITS ENOB 1 2 4 6 810 20 40 60 100 CONVERSION RATE MSPS AD9020 SNR and ENOB vs Conversion Rate 60 RESISTANCE 80 g I ul 47 40 9 CAPACITANCE lt to 46 30 d tc E 2 45 20 44 10 1 8 1 2 06 0 406 H2 8 ANALOG INPUT A Volts Input Capacitance Resistance vs Input Voltage AD 9020 Truth Table Offset Binary Twos Complement Step Range True Inverted True Inverted 0 1L75V MSB INV 0 MSB INV 1 MSB INV 1 MSB INV 0 FS L75V LSBsINV 0 LSBsINV 1 LSBsINV 0 LSBsINV 1 1024 gt 1 7500 1 1111111111 1 0000000000 1 0111111111 1 1000000000 1023 1 7466 1111111111 0000000000 0111111111 1000000000 1022 1 7432 1111111110 0000000001 0111111110 1000000001 51
3. he analog input volt age and the voltage references should be kept away from digital signal paths this reduces the amount of digital switching noise that is capacitively coupled into the analog section of the circuit D igital signal paths should also be kept short and run lengths should be matched to avoid propagation delay mismatch In high speed circuits layout of the ground circuit is a critical factor A single low impedance ground plane on the compo nent side of the board will reduce noise on the circuit ground Power supplies should be capacitively coupled to the ground plane to reduce noise in the circuit M ultilayer boards allow designers to lay out signal traces without interrupting the ground plane and provide low impedance power planes It is especially important to maintain the continuity of the ground plane under and around the AD 9020 In systems with dedicated digital and analog grounds all grounds of the AD 9020 should be connected to the analog ground plane T he power supplies Vs and Vs of the AD 9020 should be iso lated from the supplies used for external devices this further re duces the amount of noise coupled into the A D converter Sockets limit the dynamic performance and should be used only for prototypes or evaluation PCK Elastomerics Part C CS 68 55 is recommended for the LCC package T el 215 672 0787 An evaluation board is available to aid designers and provide a suggested layout REV
4. mA Full VI 0 4 V POWER SUPPLY Vs Supply Current 25 C 440 530 440 530 mA Full VI 542 542 mA Vs Supply Current 25 C 140 170 140 170 mA F ull VI 177 177 mA Power Dissipation 25 C 2 8 3 3 2 8 3 3 W F ull VI 3 4 3 4 W Power Supply Rejection Ratio PSRR Full VI 6 10 6 10 mV V NOTES Absolute maximum ratings are limiting values to be applied individually and beyond which the service ability of the circuit may be impaired Functional operability is not necessarily implied Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability 27 ypical thermal impedances part soldered onto board 68 pin leaded ceramic chip carrier 6jc 1 C W 6 17 C W no air flow 6j4 15 C W air flow 500 LFM 68 pin ceramic LCC 9c 2 6 C W 6j 15 C W no air flow 0j 13 C W air flow 500 LFM 33 4rer 1 Zrer and 1 4gep reference ladder taps are driven from dc sources at 0 875 V 0 V and 0 875 V respectively Accuracy of the overflow comparator is not tested and not included in linearity specifications 4M easured with ANALOG IN V sense Output delay measured as worst case time from 50 point of the rising edge of ENCODE to 50 point of the slowest rising or falling edge of D D y Output skew measured as worst case difference in output delay among D o D s RM S signal to rms noise with analog input signal 1 dB below full scale at specified frequency 7In
5. will raise the noise floor of the converter F ast clean edges will reduce the jitter in the signal and allow optimum ac performance L ocking the system clock to a crystal oscillator also helps reduce jitter T he AD 9020 is designed to operate with a 5096 duty cycle small 1096 variations in duty cycle should not degrade performance Data Format T he format of the output data D o D 9 is controlled by the M SB INVERT and LSBs INVERT pins T hese inputs are dc control inputs and should be connected to GROUND or Vs The AD 9020 T ruth T able gives information to choose from among Binary Inverted Binary Twos Complement and In verted T wos Complement coding The OVERFLOW output is an indication that the analog input signal has exceeded the voltage at Vseyse T he accuracy of the overflow transition voltage and output delay are not tested or in cluded in the data sheet limits Performance of the overflow in dicator is dependent on circuit layout and slew rate of the encode signal T he operation of this function does not affect the other data bits D D 9 It is not recommended for applications requiring a critical measure of the analog input voltage 10 Layout and Power Supplies Proper layout of high speed circuits is always critical but is par ticularly important when both analog and digital signals are involved Analog signal paths should be kept as short as possible and be properly terminated to avoid reflections T
6. 12 steps each representing two quantization levels T aps along the resistor ladder 1 4gef 1 2rer and 3 4ger are provided to optimize linearity Rated per formance is achieved by driving these points at 1 4 1 2 and 3 4 respectively of the voltage reference range The A D conversion for the nine most significant bits M SBs is performed by 512 comparators T he value of the least signifi cant bit LSB is determined by a unique interpolation scheme between adjacent comparators T he decoding logic processes the comparator outputs and provides a 10 bit code to the output stage of the converter Flash architecture has an advantage over other A D architec tures because conversion occurs in one step T his means the performance of the converter is primarily limited by the speed and matching of the individual comparators In the AD 9020 an innovative interpolation scheme takes advantage of flash archi tecture but minimizes the input capacitance power and device count usually associated with that method of conversion T hese advantages occur by using only half the normal number of input comparator cells to accomplish the conversion In addi tion a proprietary decoding scheme minimizes error codes In put control pins allow the user to select from among Binary Inverted Binary T wos Complement and Inverted T wos Complement coding see AD 9020 T ruth T able APPLICATIONS M any of the specifications used to describe analog digital co
7. 2 0 0034 1000000000 0111111111 0000000000 1111111111 511 0 000 0111111111 1000000000 1111111111 0000000000 510 0 0034 0111111110 1000000001 1111111110 0000000001 02 1 7432 0000000010 1111111101 1000000010 0111111101 01 1 7466 0000000001 1111111110 1000000001 0111111110 00 lt 1 7466 0000000000 1111111111 1000000000 0111111111 T he overflow bit is always 0 except where noted in parentheses M SB INVERT and LSBsINVERT are considered dc controls REV A 11 AD9020 AD 9020 PCB EVALUATION BOARD The AD 9020 PC B Evaluation Board is available from the fac tory and is shown here in block diagram form T he board in cludes a reference circuit that allows the user to adjust both references and the quarter point voltages T he AD 9617 is in cluded as the drive amplifier and the user can configure the gain from 1 to 15 O n board reconstruction of the digital data is provided through the AD 9713 a 12 bit monolithic D AC T he analog and recon structed waveforms can be summed on the board to allow the user to observe the linearity of the AD 9020 and the effects of the quarterpoint voltages T he digital data and an adjustable D ata Ready signal are available through a 37 pin edge connector DAC OUT 5V 5V O O TO ERROR WAVEFORM DUT Vs Vs GND MSB INVERT CIRCUIT BUFFERED ANALOG LSBs INVERT INPUT US AD9617 OUTPUT DATA CONNECTOR TO ERROR AD9020 D TIL WAVEFORM DUT B CALCE CIR
8. A i8JA D 9020 H hy fS ANALOG DEVICES 10 Bit 60 MSPS ND Converter AD9020 FEATURES Monolithic 10 Bit 60 MSPS Converter TTL Outputs Bipolar 1 75 V Analog Input 56 dB SNR 2 3 MHz Input Low 45 pF Input Capacitance MIL STD 883 Compliant Versions Available APPLICATIONS Digital Oscilloscopes Medical Imaging Professional Video Radar Warning Guidance Systems Infrared Systems GENERAL DESCRIPTION TheAD9020 A D converter is a 10 bit monolithic converter capable of word rates of 60 M SPS and above Innovative archi tecture using 512 input comparators instead of the traditional 1024 required by other flash converters reduces input capaci tance and improves linearity Encode and outputs are T T L compatible making the AD 9020 an ideal candidate for use in low power systems An overflow bit is provided to indicate analog input signals greater than V SENSE Voltage sense lines are provided to insure accurate driving of the tVrer voltages applied to the units Quarter point taps on the resistor ladder help optimize the integral linearity of the unit Either 68 pin ceramic leaded gull wing packages or ceramic LCCs are available and are specifically designed for low thermal impedances T wo performance grades for temperatures of both 0 C to 70 C and 55 C to 125 C ranges are offered to allow the user to select the linearity best suited for each application Dynamic performance is fully characterized and prod
9. CUIT VREF lp VSENSE bb iii h T REFERENCE 12 overLow jp CIRCUIT REF 1 4REF VsENsE V CN TIMING FER 9 CIRCUIT V AD9020 PCB Evaluation Board Block Diagram OUTLINE DIMENSIONS Dimensions shown in inches and mm 68 Leaded Ceramic Chip Carrier 68 Terminal Z 68 Leadless Chip Carrier LCC E 68A 0 950 0 010 SQ 241320254 gw 4 0 950 0 010 SQ i FASE 24 13 0 254 mE PIN 1 g oh H 9 61 1 016 MIN 0 025 pay T 60 0 625 EN EE 4 0 050 TYP 1 27 1 210 0 010 Iro TOP VIEW i TOP VIEW DI 30 73 0 254 nee LL LI i Tl mmi 0 036 0 003 o JL 0 965 0 076 R g d 0 050 TYP 1 27 aa ar st ri 26 I 44 J f Cinna nnnnnnnn 0 018 0 002 27 0 700 0 005 SQ R 0 025 STOPS 1 0 080 0 782 TYE 17 78 0 127 0 625 MIN 105 0 01 0 700 0 005 SQ 0 075 x 0 008 0 850 0 009 0 050 0 008 f 2667 20 230 17 78 0 127 1 905 0 203 21 59 0 229 127x076 a 0 850 0 009 fe_ 0 105 0 013 e 0 130 3 301 TYP 21 59 0 229 12 2 667 0 330 REV A C1348b 0 6 97 PRINTED IN U S A
10. M odern studios rely on digitized video to create state of the art special effects Video instrumentation also re quires high resolution AD Cs for studio quality measurement and frame storage The AD 9020 provides sufficient resolution for these demanding applications Conversion speed dynamic performance and ana log bandwidth are suitable for digitizing both composite and RGB video sources AD9020 USING THE AD 9020 Voltage References The AD 9020 requires that the user provide two voltage refer ences Vgep and Vger T hese two voltages are applied across an internal resistor ladder nominally 37 Q and set the analog input voltage range of the converter T he voltage references should be driven from a stable low impedance source In addi tion to these two references three evenly spaced taps on the re sistor ladder 1 4per 1 2rer 3 4ger are available Providing a reference to these quarter points on the resistor ladder will im prove the integral linearity of the converter and improve ac per formance AC and dc specifications are tested while driving the quarter points at the indicated levels T he figure below is not intended to show the transfer function of the ADC but illus trates how the linearity of the device is affected by reference voltages applied to the ladder 1111111111 NOT TO SCALE 1100000000 TAPS FLOATING 1000000000 OUTPUT CODE IDEAL 0100000000 LINEARITY
11. UND All ground pins should be connected together and to low impedance ground 36 38 39 43 53 66 67 plane 7 3 4rEF T hree quarter point of internal reference ladder 8 9 ANALOG IN Analog input nominally between 1 75 V 11 tV SENSE Voltage sense line to most positive point on internal resistor ladder Normally 1 75 V 12 V REF Voltage force connection for top of internal reference ladder N ormally driven to provide 1 75 V at Vcense 14 ENCODE TTL compatible convert command used to begin digitizing process 19 23 46 50 Do Ds TTL compatible digital output data 51 OVERFLOW TTL compatible output indicating ANALOG IN gt Vsense 56 V REF Voltage force connection for bottom of internal reference ladder N ormally driven to provide 1 75 V at V sense 57 V SENSE Voltage sense line to most negative point on internal resistor ladder N ormally 1 75 V 59 LSBs INVERT N ormally grounded When connected to Vs lower order bits Do D g are inverted 61 M SB INVERT N ormally grounded When connected to Vs most significant bit M SB D is inverted 63 l 4ngr One quarter point of internal reference ladder REV A 5 AD9020 THEORY OF OPERATION Refer to the AD 9020 block diagram As shown the AD 9020 uses a modified flash or parallel A D architecture T he ana log input range is determined by an external voltage reference Vger and Vrer nominally 1 75 V An internal resistor lad der divides this reference into 5
12. ce of 45 pF T he input capacitance is nearly constant over the analog input voltage range as shown in the graph which illustrates that characteristic T he analog input signal should be driven from a low distortion low noise amplifier A good choice is the AD 9617 a wide band width monolithic operational amplifier with excellent ac and dc performance T he input capacitance should be isolated by a small series resistor 24 Q for the AD 9617 to improve the ac performance of the amplifier see AD 9020 PCB Evaluation Board Block D iagram REV A AD9020 1 75V 3560 20kQ REV A 40 875V ov 1 2 AD708 0 875V 1 2 AD708 i l AD9020 Reference Circuit ANALOG INPUT TO COMPARATORS Vs AM WIRING RESISTANCE lt 50 AD9020 Vsense S Aggr 1 2REF 1 4per V SENSE AD9020 Equivalent Analog Input DIGITAL BITS AND OVERFLOW AD9020 Equivalent Digital Outputs ENCODE 5 0V 13k AD9020 Equivalent Encode Circuit AD9020 ANALOG INPUT ENCODE E D DATA FOR N 1 OUTPUT DATA FORN ta Aperture Delay top Output Delay AD9020 Timing Diagram Timing In the AD 9020 the rising edge of the ENCODE signal triggers the A D conversion by latching the comparators See the AD 9020 Timing Diagram The ENCODE isTTL CM OS compatible and should be driven from a low jitter phase noise source Jitter on the EN CODE signal
13. ching between devices A perture U ncertainty or jitter is the sample to sample variation in aperture delay T his is especially important when sampling high slew rate signals in wide bandwidth systems Aperture un certainty is one of the factors that degrade dynamic performance as the analog input frequency is increased REV A AD9020 Digitizing Oscilloscopes Oscilloscopes provide amplitude information about an observed waveform with respect to time Digitizing oscilloscopes must ac curately sample this signal without distorting the information to be displayed One figure of merit for the ADC in these applications is E ffective N umber of Bits ENOBs ENOB is calculated with a sine wave curve fit and equals ENOB N LOG Error measured E rror ideal N is the resolution number of bits of the ADC T he measured error isthe actual rms error calculated from the converter out puts with a pure sine wave input The Analog Bandwidth of the converter is the analog input fre quency at which the spectral power of the fundamental signal is reduced 3 dB from its low frequency value T he analog band width is a good indicator of a converter s stewing capabilities TheM aximum Conversion Rate is defined as the encode rate at which the SN R for the lowest analog signal test frequency tested drops by no more than 3 dB below the guaranteed limit Imaging Visible and infrared imaging systems both require similar char acterist
14. e not necessary if R1 R4 match within 0 0596 An alternative approach for defining the quarter point refer ences of the resistor ladder is to evaluate the integral linearity error of an individual device and adjust the voltage at the quarter points to minimize this error T his may improve the low frequency ac performance of the converter Performance of the AD 9020 has been optimized with an analog input voltage of 1 75 V as measured at V seysc If the ana log input range is reduced below these values relatively larger differential nonlinearity errors may result because of comparator mismatches As shown in the figure below performance of the converter is a function of V sense 62 10 0 56 9 0 50 8 0 44 7 0 SIGNAL TO NOISE SNR dB EFFECTIVE NUMBER OF BITS ENOB 38 6 0 32 0 4 5 0 0 6 0 8 1 0 12 1 4 Vsense Volts 1 6 18 2 0 AD9020 SNR and ENOB vs Reference Voltage Applying a voltage greater than 4 V across the internal resistor ladder will cause current densities to exceed rated values and may cause permanent damage to the AD 9020 T he design of the reference circuit should limit the voltage available to the references Analog Input Signal T he signal applied to ANALOG IN drives the inputs of 512 parallel comparator cells see Equivalent Analog Input figure T his connection typically has an input resistance of 7 kQ and input capacitan
15. easured with an FFT and is speci fied as the ratio of the fundamental component of the signal rms amplitude to the rms value of the worst case harmonic usually the 2nd or 3rd Two Tone Intermodulation Distortion IM D is a frequently cited specification in receiver design In narrow band receivers third order IM D products result in spurious signals in the pass band of the receiver Like mixers and amplifiers the AD C is charac terized with two equal amplitude pure input frequencies T he IMD equals the ratio of the power of either of the two input sig nals to the power of the strongest third order IM D signal U n like mixers and amplifiers the IM D does not always behave as it does in linear devices reduced input levels do not result in pre dictable reductions in IM D Performance graphs provide typical harmonic and SNR data for the AD 9020 for increasing analog input frequencies In choos ing an A D converter always look at the dynamic range for the analog input frequency of interest T he AD 9020 specifications provide guaranteed minimum limits at three analog test frequencies Aperture D elay is the delay between the rising edge of the EN CODE command and the instant at which the analog input is sampled M any systems require simultaneous sampling of more than one analog input signal with multiple AD Cs In these situ ations timing is critical and the absolute value of the aperture delay is not as critical as the mat
16. g ce z zz o oc a 1a 2 ORDERING GUIDE Temperature Package Device Range Description Option AD 9020JZ 0 C to 70 C 68 Pin Leaded Ceramic Z 68 AD 9020JE 0 C to 70 C 68 T erminal Ceramic LCC E 68A AD 9020K Z 0 C to 70 C 68 Pin Leaded Ceramic Z 68 AD9020KE 0 C to 70 C 68 T erminal C eramic LCC E 68A AD 9020SZ 883 55 C to 125 C 68 Pin Leaded Ceramic Z 68 AD 9020SE 883 55 C to 125 C 68 T erminal Ceramic LCC E 68A AD 9020T Z 883 55 C to 125 C 68 Pin Leaded Ceramic Z 68 AD 9020T E 883 55 C to 125 C 68 T erminal Ceramic LCC E 68A AD9020 PCB__ 0 C to 70 C Evaluation Board E Ceramic L eadless Chip Carrier Z Ceramic Leaded Chip Carrier 5 0V 3 6 15 18 25 30 33 34 37 40 45 52 55 65 68 27 31 32 36 38 39 43 53 66 67 GROUND S 2 16 28 29 35 41 42 54 64 STATIC AD1 2V AD2 2 4V DYNAMIC AD1 2V TRIANGLE WAVE 2d AD2 TTL PULSE TRAIN 5 2N AD9020 Burn In Circuit REV A NC F 10 Vsense 3 o AD9020 TOP VIEW Not to Scale 99 0 NC NO CONNECT 66 11 6 AD9020 PIN FUNCTION DESCRIPTIONS Pin No Name Function 1 1 2rEF M idpoint of internal reference ladder 2 16 28 29 35 41 42 Vs N egative supply voltage nominally 5 0 V 5 54 64 3 6 15 18 25 30 33 34 TVs Positive supply voltage nominally 5 V 5 37 40 45 52 55 65 68 4 5 13 17 27 31 32 GRO
17. ics from AD Cs T he signal input from a CCD camera or multiplexer is a time division multiplexed signal consisting of a series of pulses whose amplitude varies in direct proportion to the intensity of the radiation detected at the sensor T hese vary ing levels are then digitized by applying encode commands at the correct times as shown below FS An AD9020 FS ENCODE Ji JL TL Imaging Application Using AD9020 REV A T he actual resolution of the converter is limited by the thermal and quantization noise of the ADC T he low frequency test for SNR or ENOB is a good measure of the noise of the AD 9020 At this frequency the static errors in the ADC determine the useful dynamic range of the ADC Although the signal being sampled does not have a significant slew rate this does not imply dynamic performance is not im portant T he Transient Response and O vervoltage Recovery Time specifications insure that the ADC can track full scale changes in the analog input sufficiently fast to capture a valid sample Transient Response is the time required for the AD 9020 to achieve full accuracy when a step function is applied O vervolt age Recovery Timeis the time required for the AD 9020 to re cover to full accuracy after an analog input signal 15096 of full scale is reduced to the full scale range of the converter Professional Video Digital Signal Processing D SP is now common in television production
18. n verters have evolved from system performance requirements in these applications D ifferent systems emphasize particular speci fications depending on how the part is used T he following ap plications highlight some of the specifications and features that make the AD 9020 attractive in these systems Wideband Receivers Radar and communication receivers baseband and direct IF digitization ultrasound medical imaging signal intelligence and spectral analysis all place stringent ac performance require ments on analog to digital converters AD C s Frequency do main characterization of the AD 9020 provides signal to noise ratio SNR and harmonic distortion data to simplify selection ofthe ADC Receiver sensitivity is limited by the Signal to N oise Ratio of the system T he SNR for an ADC is measured in the frequency do main and calculated with a Fast Fourier T ransform FFT The SNR equals the ratio of the fundamental component of the sig nal rms amplitude to the rms value of the noise T he noise is the sum of all other spectral components including harmonic distortion but excluding dc Good receiver design minimizes the level of spurious signals in the system Spurious signals developed in the AD C are the re sult of imperfections in the device transfer function non linearities delay mismatch varying input impedance etc In the ADC these spurious signals appear as H armonic Distortion H armonic D istortion is also m
19. rating T emperature ANALOG IN inline ont 2 V to 2 V AD9020JE KE ZIKZ LL 0 C to 70 C TVner Vger 3 4rer L 2rer lage 2 V to 2 V Storage Temperature 0c cece 65 C to 150 C AV pee TO VREF diea eee nni patas 4 0V Maximum Junction Temperature 175 C DIGITAL INPUTS exces gerd Ir ee 0 5 V to Vs Lead Soldering Temp 10 sec 300 C ELECTRICAL CHARACTERI STICS Vs 5V Vseyse 1 75 V ENCODE 40 MSPS unless otherwise noted Test AD9020JE JZ AD 9020KE KZ Parameter Conditions Temp Level Min Typ Max Min Typ Max Units RESOLUTION 10 10 Bits DC ACCURACY Differential N onlinearity 25 C 1 0 1 25 0 75 1 0 LSB Full VI 1 5 1 25 LSB Integral N onlinearity 25 C 1 25 2 0 1 0 1 5 LSB Full VI 2 5 2 0 LSB No Missing C odes Full VI G uaranteed ANALOG INPUT Input Bias Current 25 C 0 4 1 0 0 4 1 0 mA Full VI 2 0 2 0 mA Input Resistance 25 C 2 0 7 0 2 0 7 0 kQ Input Capacitance 25 C V 45 45 pF Analog Bandwidth 25 C V 175 175 MHz REFERENCE INPUT Reference L adder Resistance 25 C 22 37 56 22 37 56 Q Full VI 14 66 14 66 Q Ladder T empco Full V 0 1 0 1 Q C Reference L adder O ffset Top of Ladder 25 C 45 90 45 90 mV Full VI 90 90 mV Bottom of Ladder 25 C 45 90 45 90 mV Full VI 90 90 mV O ffset D rift C oefficient Full V 50 50 uV C SWITCHING PERFORMANCE Conversion Rate 25 C 60 60 M SPS Aperture D elay t4 25 C V 1 1 ns Aperture U ncertainty Ji
20. termodulation measured with analog input frequencies of 2 3 M Hz and 3 0 M Hz at 7 dB below full scale 8M easured as the ratio of the worst case change in transition voltage of a single comparator for a 5 change in V s or Vs Specifications subject to change without notice REV A 3 AD9020 EXPLANATION OF TEST LEVELS T est L evel 100 production tested 100 production tested at 25 C and sample tested at specified temperatures Sample tested only IV Parameter is guaranteed by design and characterization testing V Parameter is a typical value only VI All devices are 100 production tested at 25 C 100 production tested at temperature extremes for extended temperature devices sample tested at temperature ex tremes for commercial industrial devices DIE LAYOUT AND MECHANICAL INFORMATION Die Dimensions 206 x 140 x 15 2 mils Pad DIMENSIONS 4 x 4 mils M etalization s u sre a ana Gold Backing ze espe OC EUER lode toa EN None Substrate Potential Vs Passivationi Light lei CE e E es Nitride a ao a on z zz z zz 3 3 3 93 tc DD LO e oO QU ca Yee uU otitoo oxs 37601003 Ws srg Vs de ali TANI di Di Mai Ds D sii D Di gti Ds Do LSB s D MSB Ws S5 OVERFLOW GROUND LI 4 Vs Mo wa GROUND Vs Vs ENCODE Vs GROUND wii Vnre VREF Vsense Vsense ss d LSBs INVERT Zzywao wy u 0AA VALLOH oot t Sgt 4 z z5727 amp OOo oo oo Tr 2 22 iva
21. tter 25 C V 5 5 ps rms Output Delay top 25 C 6 10 13 6 10 13 ns Output Time Skew 25 C 3 5 3 5 ns DYNAMIC PERFORMANCE T ransient Response 25 C V 10 10 ns Overvoltage Recovery T ime 25 C V 10 10 ns Effective N umber of Bits ENOB fu 2 2 3MHz 25 C 8 6 9 0 8 6 9 0 Bits fu 210 3MHz 25 C IV 8 0 8 4 8 0 8 4 Bits fu 15 3MHz 25 C IV 7 5 8 0 7 5 8 0 Bits Signal to N oise Ratio fu 2 3 MHz 25 C 54 56 54 56 dB fu 10 3MHz 25 C 50 53 50 53 dB fu 15 3MHz 25 C 47 50 47 50 dB Signal to N oise Ratio Without H armonics fu 2 3 MHz 25 C 54 56 54 56 dB fy 10 3MHz 25 C 51 54 51 54 dB fu 15 3MHz 25 C 48 52 48 52 dB 2 REV A Test AD9020JE JZ AD 9020KE KZ Parameter C onditions Temp Level Min Typ Max Min Typ Max Units DYNAMIC PERFORMANCE continued H armonic Distortion fin 22 3MHz 25 C 61 67 61 67 dBc fin 10 3 MHz 25 C 55 59 55 59 dBc fiy 15 3 MHz 25 C 49 53 49 53 dBc T wo T one Intermodulation Distortion Rejection 25 C V 70 70 dBc Differential Phase 25 C V 0 5 0 5 D egree Differential Gain 25 C V 1 1 ENCODE INPUT Logic 1 Voltage Full VI 2 0 2 0 V Logic 0 Voltage Full VI 0 8 0 8 V Logic 1 Current Full VI 20 20 uA Logic 0 Current Full VI 800 800 uA Input Capacitance 25 C V 5 5 pF Pulse Width High 25 C 6 6 ns Pulse Width Low 25 C 6 6 ns DIGITAL OUTPUTS Logic 1 Voltage lop 2 MA Full VI 2 4 2 4 V Logic 0 Voltage lo 6
22. uction tested at 25 C MIL ST D 883 units are available TheAD 9020 A D Converter is available in versions compliant with M IL ST D 883 Refer to the Analog D evices M ilitary Prod ucts D atabook or current AD 9020 883B data sheet for detailed specifications REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM INVERT INVERT ANALOG IN ner Vsense 11 OVERFLOW M G1 OVERFLOW OVERFLOW OVERFLOW Ds 12per 1 2 04 2 7 z Oo o 7 7 3 D 1024 10 tane G5 O m rod r ENCODE 14 GROUND One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 World Wide Web Site http www analog com Fax 617 326 8703 Analog Devices Inc 1997 AD9020 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS 3 4rer 1 2ree W4rep Current 0 00 c eee 10 mA IV seo bac cea WORD RC RN ae Lalla 6 V Digital Output Current 20 mA Me sr nice ey nine LORENA eR RR d dde wastes 6V Ope

ANALOG DEVICES AD9020 handbook

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