CIRRUS LOGIC CY7C43644AV CY7C43664AV CY7C43684AV handbook
Contents
1. lt 0 5V to 0 5 Electrical Characteristics Over the Operating Range CY7C43644 64 84AV Parameter Description Test Conditions Min Max Unit Output HIGH Voltage Voc 3 0V 2 4 V lou lt 2 0 VoL Output LOW Voltage Vec 3 0 0 5 V loL 8 0 mA Input HIGH Voltage 2 0 Voc V Vit Input LOW Voltage lt 0 5 0 8 V lix Input Leakage Current Voc Max lt 10 10 loz Output OFF High Z Current Vss lt Vo Vec lt 10 10 lozH Ic Active Power Supply Current Commercial 60 mA Industrial 60 mA mL Average Standby Current Commercial 10 mA Industrial 10 mA Capacitancel Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHz Voc 3 3V 4 pF Cour Output Capacitance 8 pF Note 12 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation ofthe device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 13 The input and output voltage ratings may be exceeded provided the input and output current ratings are observed 14 The Voltage on any input or I O pin cannot exceed the power pin during power up 15 Operating Voc Range for 7 speed is 3 3V 5 16 Input signals switch from OV2. 4 Pointer Pointer MRS2 PRS2 x 1K 4K 16K ES o 5 b x 36 25 Dual Ported ap od Memory Ec FIFO 2 Mail2 Register MBF2 4 Cypress Semiconductor Corporation 3901 North First Street SanJose 95134 408 943 2600 Document 38 06025 Rev C Revised December 26 2002 CY7C43644AV ER CY7C43664AV CYPRESS CY7C43684AV Table 1 Pin Configuration TQFP Top View lt a F T a PEE TIE amies 218 2 o BEEE Sees 8 00 arra IANEURANNARLL TL 222385838338 W RA 1 102 CLKB ENA 2 PRS2 CLKA 3 GND 4 Bas Ass 5 Baq 4 6 7 Bao A32 8 GND 9 NC Asi 0 Bai 1 GND 2 Bog Aog 3 Bog Aog 4 Boz A27 5 B 6 CY7C43644AV RTI A25 7 Bos 8 CY7C43664AV Bog _ Aes 9 BE FWFT 20 CY7C43684AV anp GND lt gt m m nm on PRB A21 24 B20 A20 25 Bio Aig 26 Big Ais 27 GND GND 28 B47 A17 29 Big A16 30 SIZE 5 31 Ara 32 Bis E Bra RT2 34 Bis A12 35 B42 GND 36 GND Au 37 Ayo 38 Bio 39 39 3 33 238333582335 OOUUUUUUUU UU OOUUUUUUUU LLLI EELE 6844 9 Sansa fo o7 5 G gt Note 1 Pin compatible to IDT7236X4 family Document 38 06025 Rev C Page 2 of 37 Wn e 7 CYPRESS Functional Description The CY7C436X4AV is a monolithic high speed low power CMOS Bidirectional Synchronous
3. CY7C43644AV oL CY7C43664AV CY7C43684AV P CYPRESS 3 3V 1K 4K 16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching Features Fully asynchronous and simultaneous Read and Write operation permitted 3 3V high speed low power bidirectional First In Mailbox bypass register for each FIFO First Out FIFO memories w bus matching capabilities Parallel and Serial Programmable Almost Full and 1K x 36 x 2 CY7C43644AV Almost Empty flags AK x 36 x 2 CY7C43664AV Retransmit function 16K x 36 2 CY7C43684AV Standard or FWFT user selectable mode 0 25 micron CMOS for optimum speed power Partial Reset High speed 133 MHz operation 7 5 ns Read Write Big or Little Endian format for word or byte bus sizes cycle times 128 pin TQFP packaging Low power lec 60 mA Easily expandable in width and depth gt var gt Mail Register Port A Control CLKB 7 1K 4K 16K CSB 5 x 36 ag 2 Dual Ported a 2 Control ENB 55 D MBB 20 Memory 5 Logic 2 Ox RTI FIFO 1 E SIZE FFA IRA gt EFB ORB AFA gt AEB SPM Programmable y Bo 35 FSO SD Flag Offset BE FWFT FS1 SEN 36 Registers Aoas De EFA ORA 4 Status gt FFB RB AEA 4 Flag Logic gt AB Write Read 4
4. Document 38 06025 Rev C Page 19 of 37 CY7C43644AV CY7C43664AV CY7C43684AV Wn W CYPRESS Switching Waveforms continued Port A Write Cycle Timing for FIFO1 CY Standard and FWFT Modes fc kL yl ICLKH S CLKA lt FFA IRA HIGH XXXXXXXXKKX Port B Long Word Write Cycle Timing for FIFO2 CY Standard and FWFT Modes lt tiki CLKB FFB IRB HIGH CSB 34 wire MBB ENB Bo 35 Notes 30 Itis not necessary to program offset register bits on consecutive clock cycles Attempts to write FIFO memory are ignored until FFA IRA is set HIGH 31 Programmable offsets are written serially to the SD input in the order AFA offset Y1 AEB offset X1 AFB offset Y2 and AEA offset X2 32 If W RA switches from Read to Write before the assertion of CSA tens to s tens 33 Written to FIFO1 Page 20 of 37 Document 38 06025 Rev C
5. 1 Skew Time between CLKAT and CLKBT for EFA 5 5 7 5 ns ORA EFB ORB FFA IRA and FFB IRB tekgw2l Skew Time between CLKAT and CLKBT for AEA 7 8 12 ns AEB AFA AFB ta Access Time CLKAT to Ao 35 and CLKBT to Bp 35 1 6 1 8 3 10 ns twer pipe on Delay Time CLKAT to FFA IRA and 1 6 1 8 2 10 ns CLKBT to FFB IRB tREF Cropagation Dx Delay Time CLKAT to EFA ORA and 1 6 1 8 2 10 ns CLKBT to EFB ORB tPAE Delay Time CLKAT to AEA 1 6 1 8 1 10 ns CLKBT to AEB trar Propagation Delay Time CLKAT to AFA and CLKBT 1 6 1 8 1 10 ns to AFB Propagation Delay Time CLKAT to MBF1 LOW 0 6 0 8 0 12 ns MBF2 HIGH and CLKBT to MBF2 LOW HIGH e Delay Time CLKAT to Bg 351221 and 1 7 2 11 3 12 ns CLKB to 352 Propagation Delay Time to Ag 55 Valid and 1 6 2 9 3 11 ns MBB to By 55 Valid irse Propagation Delay Time MRS1 or PRS1 LOW to 1 6 1 10 1 15 ns AEB LOW AFA HIGH FFA IRA LOW EFB ORB LOW and MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW AFB HIGH FFB IRB LOW EFA ORA LOW and MBF2 HIGH ten Enable Time CSA or W RA LOW to Ap 35 Active 1 6 2 8 2 10 ns and CSB LOW and W RB HIGH to By 35 Active tpit Disable Time CSA or W RA HIGH to Aj 35 at High 1 5 1 6 1 8 ns Impedance and CSB HIGH or W RB LOW to 35 at High Impedance Retransmit Recovery Time 90 90 90 ns Notes 21 Skew time is
6. A LOW to HIGH transition on CLKA writes Ap 35 data to the Mail1 Register when a Port A Write is selected by CSA LOW W RA HIGH ENA HIGH and MBA HIGH If the selected Port bus size is also 36 bits then the usable width of the 1 Register employs data lines Ap 35 If the selected Port bus size is 18 bits then the usable width of the Maill Register Page 9 of 37 Y CYPRESS employs data lines Ag 47 In this case Ayg 35 are Don t Care inputs If the selected Port A bus size is 9 bits then the usable width of the Mail1 Register employs data lines In this case 35 are Don t Care inputs A LOW to HIGH transition CLKB writes Bo lt 35 data to the Mail2 Register when a Port B Write is selected by CSB LOW W RB LOW ENB HIGH and MBB HIGH If the selected Port B bus size is also 36 bits then the usable width of the Mail2 Register employs data lines Bo 35 If the selected Port B bus size is 18 bits then the usable width of the Mail2 Register employs data lines Bo 17 In this case 8 35 are Don t Care inputs If the selected Port B bus size is 9 bits then the usable width of the Mail2 Register employs data lines Bo g In this case Bg 35 are Don t Care inputs Writing data to a mail register sets its corresponding flag MBF1 or MBF2 LOW Any Attempt to write to a mail register are ignored while the mail flag is LOW When data outputs of a port are active the data on th
7. FFA IRA is synchronized to the LOW to HIGH transition of CLKA FFB IRB PortBFull Input This is a dual function pin In the CY Standard mode the FFB function is selected Ready Flag FFB indicates whether or not the FIFO2 memory is full In the FWFT mode the IRB function is selected IRB indicates whether or not there is space available for writing to the FIFO2 memory FFB IRB is synchronized to the LOW to HIGH transition of CLKB FS1 SEN Flag Offset FS1 SEN and FSO SD are dual purpose inputs used for flag offset register Select 1 Serial programming During Master Reset FS1 SEN and FSO SD together with SPM select Enable the flag offset programming method Three offset register programming methods are FSO SD Flag Offset available automatically load one of three preset values 8 16 or 64 parallel load from Select 0 Serial Port A and serial load When serial load is selected for flag offset register programming Data FS1 SEN is used as an enable synchronous to the LOW to HIGH transition of CLKA When FS1 SEN is LOW a rising edge on CLKA loads the bit present on FSO SD into the X and Y registers The number of bit Writes required to program the offset registers is 40 for the CY7C43644AV 48 for the CY7C43664AV and 56 for the CY7C43684AV The first bit Write stores the Y register MSB and the last bit Write stores the X register LSB MBA Port A Mailbox A HIGH level on MBA chooses a mailbox register for a Port A Read or Write Select ope
8. MRS1 and MRS2 Partial Reset also sets the Read and Write pointers to the first location of the memory Unlike Master Reset any settings existing prior to Partial Reset i e programming method and partial flag default offsets are retained Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings Each FIFO has its own independent Partial Reset pin PRS1 and PRS2 The CY7C436X4AV have two modes of operation In the CY Standard mode the first word written to an empty FIFO is deposited into the memory array A Read operation is required to access that word along with all other words residing in Selection Guide CY7C43644AV CY7C43664AV CY7C43684AV memory In the First Word Fall Through mode FWFT the first long word 36 bit wide written to an empty FIFO appears automatically on the outputs no Read operation required nevertheless accessing subsequent words does necessitate a formal Read request The state of the BE FWFT pin during FIFO operation determines the mode in use Each FIFO has a combined Empty Output Ready flag EFA ORA and EFB ORB and a combined Full Input Ready flag FFA IRA and FFB IRB The EF and FF functions are selected in the CY Standard mode EF indicates whether the memory is empty and FF indicates whether the FIFO memory is full The IR and OR functions are selected in the First Word Fall Through mode IR indicates whether or not
9. RT2 Retransmit FIFO2 SIZE Bus Size Select SPM Serial Programming W RA Port A Write Read Select W RB Port B Write Read Select A LOW selects a Write operation and a HIGH selects a Read operation on Port B for a LOW to HIGH transition of CLKB The Bo 35 outputs are in the high impedance state when W RB is LOW Document 38 06025 Rev C Page 6 of 37 Wn 1 CYPRESS Description Master Reset MRS1 MRS2 Each of the two FIFO memories of the CY7C436X4AV undergoes a complete reset by taking its associated Master Reset MRS1 MRS2 input LOW for at least four Port A clock CLKA and four Port B clock CLKB LOW to HIGH transi tions The Master Reset inputs can switch asynchronously to the clocks A Master Reset initializes the internal Read and Write pointers and forces the Full Input Ready flag FFA IRA FFB IRB LOW the Empty Output Ready flag EFA ORA EFB ORB LOW the Almost Empty flag AEA AEB LOW and the Almost Full flag AFA AFB HIGH A Master Reset also forces the Mailbox flag MBF1 MBF2 of the parallel mailbox register HIGH After a Master Reset the FIFO s Full Input Ready flag is set HIGH after two clock cycles to begin normal operation A Master Reset must be performed on the FIFO after power up before data is written to its memory A LOW to HIGH transition on a FIFO Master Reset MRS1 MRS2 input latches the value of the Big Endian BE input or determining the order
10. Almost Full Flag and Almost Empty Flag Offset Values after Reset CY Standard and FWFT Modes 28 uibs MRS1 MRS2 SPM FS1 SEN FS1 SEN WFF FFA IRA COO OO M5 tens ENH an OO 85 LXXX XXX XXX XX IKK AFA Offset Y1 AEB Offset X1 AFB Offset Y2 AEA Offset X2 First Word to FIFO1 FFB IRB Serial Programming of the Almost Full Flag and Almost Empty Flag Offset Values CY Standard and 0 31 S UA Ne eee MRS1 MRS2 uo eee tes t Pi UZ TZ ALLL see 7777777777777 twe FFA IRA lt y less isPH Iseng A SENH isenst wem ZI ARA oe RIZAL ZZ FSs trs 50 lspH tsp SDH AFA Offset Y1 MSB AEA Offset X2 LS e EU a TZ gt lwrE FFB IRB 74 26 Partial Reset is performed in the same manner for FIFO2 27 MRS1 must be HIGH during Partial Reset 28 W RA HIGH MBA LOW It is not necessary to program offset register on consecutive clock cycles FIFO can only be programmed in parallel when FFA IRA is HIGH NND 29 tskewi is the minimum time between the rising CLKA edge and a rising CLKB for FFB IRB to transition HIGH in the next cycle If the time between the rising edge of CLKA and rising edge CLKB is less than tskew1 then FFB IRB may transition HIGH one cycle later than shown
11. FIFO memory which supports clock frequencies up to 133 MHz and has Read access times as fast as 6 ns Two independent 1K 4K 16K x 36 dual port SRAM FIFOs on board each chip buffer data in opposite directions FIFO data on Port B can be input and output in 36 bit 18 bit or 9 bit formats with a choice of Big or Little Endian configurations The CY7C436X4AV is a synchronous clocked FIFO meaning each port employs a synchronous interface All data transfers through a port are gated to the LOW to HIGH transition of a port clock by enable signals The clocks for each port are independent of one another and can be asynchronous or coincident The enables for each port are arranged to provide a simple bidirectional interface between micropro cessors and or buses with synchronous control Communication between each port may bypass the FIFOs via two mailbox registers The mailbox registers width matches the selected Port B bus width Each mailbox register has a flag MBF1 and MBF2 to signal when new mail has been stored Two kinds of reset are available on the CY7C436X4AV Master Reset and Partial Reset Master Reset initializes the Read and Write pointers to the first location of the memory array configures the FIFO for Big or Little Endian byte arrangement and selects serial flag programming parallel programming or one of the three possible default flag offset settings 8 16 or 64 Each FIFO has its own independent Master Reset pin
12. IRA 0 0 0 L L H H 1 to X1 1 to X1 1 to X1 H L H H X1 1 to 1024 X1 1 to 4096 X1 1 to 16384 H H H H Y1 1 Y1 1 Y1 1 1024 Y1 to 1023 4096 Y1 to 4095 16384 Y1 to H H L H 16383 1024 4096 16384 H H L L Table 7 FIFO2 Flag Operation CY Standard and FWFT modes Number of Words in FIFO Memory 7 9 10 Synchronized to CLKA Synchronized to CLKB CY7C43644AV CY7C43664AV CY7C43684AV EFA ORA AEA AFB FFB IRB 0 0 0 L L H H 1 to X2 1 to X2 1 to X2 H L H H X2 1 to 1024 X2 1 to 4096 X2 1 to 16384 H H H H Y2 1 Y2 1 Y2 1 1024 Y2 1023 4096 Y2 to 4095 16384 Y2 to H H L H 16383 1024 4096 16384 H H L L Table 8 Data Size for Long Word Writes to FIFO2 Size Model Data Written to FIFO2 Data Read From FIFO2 BM SIZE BE Bo7 35 18 26 9 17 Bo 8 A27 35 26 Ag 17 Ao 8 L X X A B C D A B C D Table 9 Data Size for Word Writes to FIFO2 Size Model Write No Data Written to FIFO2 Data Read From FIFO2 BM SIZE BE 17 Bo 8 A735 A18 26 Ag 17 Ao 8 H L H 1 A B A B C D 2 C D H L L 1 C D A B C D 2 A B Notes 5 Xiisthe almost empty offset for FIFO1 used by AEB Y1 is the almost full offset for FIFO1 used by AFA Both X1 and Y1 are selected during a FIFO1 reset or port A programming 6 When a word loaded to an empty FIFO is shifted to the output register its previous FIFO memory location is free 7 Data in the ou
13. MRS1 and MRS2 5 7 7 5 ns HIGH tees Set Up Time BE FWFT before MRS1 and MRS2 5 7 7 5 ns HIGH tspms Set Up Time SPM before MRS1 and MRS2 HIGH 5 7 7 5 ns tsps Set Up Time FS0 SD before CLKAT 3 4 5 ns tsens Set Up Time FS1 SEN before CLKAT 3 4 5 ns tews Set Up Time BE FWFT before CLKAT 0 0 0 ns toy Hold Time Ag 35 after CLKAT and By 35 after 0 0 0 ns CLKBT tENH Hold Time CSA W RA ENA and MBA after 0 0 0 ns CLKAT CSB W RB ENB and MBB after CLKBT Notes 19 C 5 pF for tp s 20 Requirement to count the clock edge as one of at least four needed to reset a FIFO Document 38 06025 Rev C Page 16 of 37 CY7C43644AV CY7C43664AV Sars CYPRESS M 917643684 Switching Characteristics Overthe Operating Range continued CY7C43644 CY7C43644 CY7C43644 64 84AV 64 84AV 64 84AV 7 10 15 Description Min Max Min Max Min Max Unit tRSTH Hold Time MRS1 MRS2 PRS1 PRS2 RT1 or RT2 1 2 2 ns LOW after CLKAT or trsH Hold Time FSO and FS1 after MRS1 and MRS2 1 1 2 ns HIGH Hold Time BE FWFT after MRS1 and 2 HIGH 1 1 2 ns tspmy Hold Time SPM after MRS1 and MRS2 HIGH 1 1 2 ns Hold Time FS0 SD after CLKAT 0 0 0 ns teENH Hold Time FS1 SEN after CLKAT 0 0 0 ns tsp Hold Time FS1 SEN HIGH after MRS1 and MRS2 1 1 2 ns HIGH
14. MRS2 inputs go from LOW to HIGH will select a Little Endian arrangement When data is moving in the direction from Port A to Port B the least significant byte word of the long word written to Port A will be transferred to Port B first the most significant byte word of the long word written to Port A will be transferred to Port B last When data is moving in the direction from Port B to Port A the byte word written to Port B first will be transferred to port A as the least significant byte word of the long word the byte word written to Port B last will be transferred to Port A as the most significant byte word of the long word After Master Reset the FWFT select function is active permitting a choice between two possible timing modes CY Standard mode or First Word Fall Through FWFT mode Once the Master Reset MRS1 MRS2 input is HIGH a HIGH on the BE FWFT input at the second LOW to HIGH transition of CLKA for FIFO1 and CLKB for FIFO2 will select CY Standard mode This mode uses the Empty Flag function EFA EFB to indicate whether or not there are any words present in the FIFO memory It uses the Full Flag function FFA FFB to indicate whether or not the FIFO memory has any free space for writing In CY Standard mode every word read from the FIFO including the first must be requested using a formal Read operation Once the Master Reset MRS1 MRS2 input is HIGH a LOW on the BE FWFT input at the second LOW to HI
15. When a byte size bus is selected then mailbox data can be transmitted only between Ag g and Bus Matching FIFO1 Reads Data is read from the FIFO1 RAM in 36 bit long word incre ments If a long word bus size is implemented the entire long word immediately shifts to the FIFO1 output register If byte or word size is implemented on Port B only the first one or two bytes appear on the selected portion of the FIFO1 output register with the rest of the long word stored in auxiliary registers In this case subsequent FIFO1 reads output the rest of the long word to the FIFO1 output register When reading data from FIFO1 in the byte or word format the unused Bj 55 outputs are indeterminate Bus Matching FIFO2 Writes Data is written to the FIFO2 RAM in 36 bit long word incre ments Data written to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary registers The CLKB rising edge that writes the fourth byte or the second word of long word to FIFO2 also stores the entire long word in FIFO2 RAM Reading from FIFO2 on Port A can only be in 36 bit format Retransmit RT1 RT2 The retransmit feature is beneficial when transferring packets of data It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary The retransmit function applies to CY Standard mode only The number of 36 18 9 bit words written into the FIFO should be less than full depth minus 2 4 8
16. by which bytes are transferred through Port B A LOW to HIGH transition on a FIFO reset MRS1 MRS2 input latches the values of the Flag select FSO FS1 and Serial Programming Mode SPM inputs for choosing the Almost Full and Almost Empty offset programming method see Almost Empty and Almost Full flag offset programming below Partial Reset PRS1 PRS2 Each of the two FIFO memories of the CY7C436X4AV undergoes a limited reset by taking its associated Partial Reset PRS1 PRS2 input LOW for at least four Port A clock CLKA and four Port B clock CLKB LOW to HIGH transi tions The Partial Reset inputs can switch asynchronously to the clocks A Partial Reset initializes the internal Read and Write pointers and forces the Full Input Ready flag FFA IRA FFB IRB LOW the Empty Output Ready flag EFA ORA EFB ORB LOW the Almost Empty flag AEA AEB LOW and the Almost Full flag AFA AFB HIGH A Partial Reset also forces the Mailbox flag MBF1 MBF2 of the parallel mailbox register HIGH After a Partial Reset the FIFO s Full Input Ready flag is set HIGH after two clock cycles to begin normal operation Whatever flag offsets programming method parallel or serial and timing mode FWFT or CY Standard mode are currently selected at the time a Partial Reset is initiated those settings will remain unchanged upon completion of the reset operation A Partial Reset may be useful in the case where reprogramming a FIFO following
17. not timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle 22 Writing data to the Mail1 register when the 35 outputs are active and MBB is HIGH 23 Writing data to the Mail2 register when the Ag 35 outputs are active and MBA is HIGH Document 38 06025 Rev C Page 17 of 37 CY7C43644AV Fa CY7C43664AV gt CYPRESS CY7C43684AV Switching Waveforms FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight 124 251 lt gt insrs tRsTH MRS1 165652522000 1 t trws BES a gt lSPMS gt ER 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 TEE SEE HERE trss trsH KK KKK KKK KKK KKK KKK KKK gt WEF _ RSF EFB ORB I RSF AFA RSF mE 4 MBF1 N N N SS FIFO1 Partial Reset CY Standard and Modes 27 CLKA CLKB tRSTH a trsTs PRS1 iRsF wre gt FFA IRA N N N N N Ny RSF EFB ORB N N N N N N RSF AEB 2 E N XS RSF AFA x N N N N SY e _p MBF1 NNNNNNNY Notes 24 Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value 25 PRS1 must be HIGH during Master Reset Document 38 06025 Rev C Page 18 of 37 CY7C43644AV CY7C43664AV CY7C43684AV CYPRESS Mi Switching Waveforms continued Parallel Programming of the
18. the FIFO has available memory locations OR shows whether the FIFO has data available for reading or not It marks the presence of valid data on the outputs Each FIFO has a programmable Almost Empty flag AEA and AEB and_a programmable Almost Full flag AFA and AFB AEA and AEB are asserted when a selected number of words written to FIFO memory achieve a predetermined almost empty state AFA and AFB are asserted when a selected number of words written to the memory achieve a predeter mined almost full state IRA IRB AFA and AFB are synchronized to the port clock that writes data into its array ORA ORB AEA and AEB are synchronized to the port clock that reads data from its array Programmable offset for AEA AEB AFA and AFB are loaded in parallel using Port A or in serial via the SD input Three default offset settings are also provided The AEA and AEB threshold can be set at 8 16 or 64 locations from the empty boundary and AFA and AFB threshold can be set at 8 16 or 64 locations from the full boundary All these choices are made using the FSO and FS1 inputs during Master Reset Two or more devices may be used in parallel to create wider data paths A Retransmit feature is available on these devices The CY7C436X4AV FIFOs are characterized for operation from 0 C to 70 C commercial and from 40 C to 85 C indus trial Input ESD protection is greater than 2001V and latch up is prevented by the use of guard ri
19. to 3V with a rise fall time of less than 3 ns clocks and clock enables switch at 20 MHz while data inputs switch at 10 MHz Outputs are unloaded 17 All inputs Voc 0 2V except RCLK and WCLK which are at frequency 0 MHz All outputs are unloaded 18 Tested initially and after any design or process changes that may affect these parameters Document 38 06025 Rev C Page 15 of 37 CY7C43644AV CY7C43664AV CY7C43684AV i N Table 14 AC Test Loads and Waveforms 10 and 15 R1 3300 ALL INPUT PULSES R2 6800 4 et INCLUDING JIG AND 7 SCOPE AC Test Loads and Waveforms 7 Vcc 2 ALL INPUT PULSES i 3 0V 500 GND Switching Characteristics Over the Operating Range CY7C43644 CY7C43644 CY7C43644 64 84AV 64 84AV 64 84AV 7 10 15 Parameter Description Min Max Min Max Min Max Unit fs Clock Frequency CLKA or CLKB 133 100 67 MHz Clock Cycle Time CLKA CLKB 7 5 10 15 ns tci KH Pulse Duration CLKA or CLKB HIGH 3 5 4 6 ns tek Pulse Duration CLKA or CLKB LOW 3 5 4 6 ns tps Set Up Time Ag 35 before CLKAT and 35 before 3 4 5 ns CLKBT tens Set Up Time CSA W RA ENA and MBA before 3 4 5 ns CLKAT CSB W RB ENB and MBB before CLKBT trsts Set Up Time MRS1 MRS2 PRS1 PRS2 RT1 25 4 5 ns RT2 LOW before CLKAT or CLKBT 70 tess Set Up Time FSO and FS1 before
20. words between the reset of the FIFO master or partial and Retransmit setup A LOW pulse on RT1 RT2 resets the internal Read pointer to the first physical location of the FIFO CLKA and CLKB may be free running but ENB ENA must be disabled during and tprp after the retransmit pulse With every valid Read cycle after retrans mit previously accessed data is read and the Read pointer is incremented until it is equal to the Write pointer Flags are governed by the relative locations of the Read and Write point ers and are updated during a retransmit cycle Data written to the FIFO after activation of RT1 RT2 are transmitted also The full depth of the FIFO can be repeatedly retransmitted Page 10 of 37 4 C 59 E UN Ey z o A27 35 A1g 26 Ag_17 BYTE ORDER ON PORT A A B C D B27 35 B18 26 B9 17 Bos BE BM SIZE A E X L X a LONG WORD SIZE Bo7_35 Big 26 _17 Bos BE BM SIZE A B H H L B27 35 Bi8 26 Bo 17 Bo 8 D b WORD SIZE BIG ENDIAN Bo7_35 B18 26 _17 SIZE C D L H L B27 35 18 26 _17 Bos A B WORD SIZE LITTLE ENDI
21. A The Ag 35 lines are in the high impedance state when either CSA or W RA is HIGH The Ag 35 lines are active outputs when both CSA and W RA are LOW Data is loaded into FIFO1 from the Ao 55 inputs on LOW to HIGH transition of CLKA when CSA is LOW W RA is HIGH ENA is HIGH MBA is LOW and FFA IRA is HIGH Data is read from FIFO2 to the Ag 35 outputs by a LOW to HIGH transition of CLKA when CSA is LOW W RA is LOW ENA is HIGH MBA is LOW and EFA ORA is HIGH see Table 4 FIFO Reads and Document 38 06025 Rev C CY7C43644AV CY7C43664AV CY7C43684AV Writes on Port A are independent of any concurrent Port B operation The Port B control signals are identical to those of Port A with the exception that the Port B Write Read select W RB is the inverse of the Port A Write Read select W RA The state of the Port B data 35 lines is controlled by the B Chip Select CSB and Port B Write Read select W RB The 35 lines are in the high impedance state when either CSB is HIGH or W RB is LOW The By ss lines are active outputs when CSB is LOW and W RB is HIGH Data is loaded into FIFO2 from the Bo 55 inputs on a LOW to HIGH transition of CLKB when CSB is LOW W RB is LOW ENB is HIGH MBB is LOW and FFB IRB is HIGH Data is read from FIFO1 to the 35 outputs by LOW to HIGH transition of CLKB when CSB is LOW W RB is HIGH ENB is HIGH MBB is LOW and EFB ORB is HIGH see Table 5 FIFO Reads and Wri
22. AN 27 35 18 26 Bg 17 Bos BE BM SIZE A H H H B27 35 Bi8 26 Bg 47 27 35 B18 26 Bo 17 B27 35 B18 26 17 Bos D d BYTE SIZE BIG ENDIAN Bo7 35 B18 26 _17 SIZE D L H H B27 35 B18 26 Bg_17 Bos C Bo7_35 Big_26 17 B27 35 B18 26 17 Document 38 06025 Rev C e BYTE SIZE LITTLE ENDIAN CY7C43644AV CY7C43664AV CY7C43684AV Write to FIFO Read from FIFO 1st Read from FIFO 2nd Read from FIFO 1st Read from FIFO 2nd Read from FIFO 1st Read from FIFO 2nd Read from FIFO 3rd Read from FIFO 4th Read from FIFO 1st Read from FIFO 2nd Read from FIFO 3rd Read from FIFO 4th Read from FIFO Page 11 of 37 CY7C43644AV CY7C43664AV E 74 CYPRESS CY7C43684AV Table 3 Flag Programming a ES1 SPM SEN 0 0 MRS1 MRS2 X1 and Y1 Registers X2 andY2 Registers H H H T X 64 X H H H X T X 64 H H L T X 16 X H H L X X 16 H L H T X 8 X H L H X T X 8 H L L T T Parallel programming via Port A Parallel programming via Port A L H L T T Serial programming via SD Serial programming via SD L H H T T Reserved Reserved L L H T T Reserved Reserved L L L T T Reserved Reserved Table 4 Port A Enable Function CSA W RA ENA MBA CLKA Ap 35 Port Fu
23. GH transition of CLKA for FIFO1 and CLKB for FIFO2 will select FWFT mode This mode uses the Output Ready function ORA ORB to indicate whether or not there is valid data at the data outputs Ao 35 or Bo 35 It also uses the Input Ready function IRA IRB to indicate whether or not the FIFO memory has any free space for writing In the FWFT mode the first word written to an empty FIFO goes directly to data outputs no Read request necessary Subsequent words must be accessed by performing a formal Read operation Following Master Reset the level applied to the BE FWFT input to choose the desired timing mode must remain static throughout the FIFO operation Programming the Almost Empty and Almost Full Flags Four registers in the CY7C436X4AV are used to hold the offset values for the Almost Empty and Almost Full flags The Port B Almost Empty flag AEB offset register is labeled X1 and the Port A Almost Empty flag AEA offset register is labeled X2 The Port A Almost Full flag AFA offset register is labeled Y1 and the Port B Almost Full flag AFB offset register is labeled Y2 The index of each register name corresponds with preset values during the reset of a FIFO programmed in parallel using the FIFO s Port A data inputs or programmed in serial using the Serial Data SD input see Table 3 To load a FIFO s Page 7 of 37 Wn e 7 CYPRESS Almost Empty flag and Almost Full flag offset registers w
24. IFO1 Data Read From FIFO1 BM SIZE BE A27 35 26 A917 Bo7 35 P1826 17 Bo 8 L X X A B C A B C D Table 12 Data Size for Word Reads from FIFO1 Size Model Data Written to FIFO1 Read No Data Read From FIFO1 BM SIZE BE Ao a5 26 9 17 17 Bo 8 H L H A B C 1 A B 2 C D H L L A B C 1 C D 2 A B Table 13 Data Size for Byte Reads from FIFO1 Size Model Data Written to FIFO1 Read No Data Read From FIFO1 BM SIZE BE A27 35 A18 26 Ag 17 Ao 8 Bo 8 H H H A B C D 1 A 2 B 3 C 4 D H H L A B C D 1 D 2 C 3 B 4 A Document 38 06025 Rev C Page 14 of 37 CY7C43644AV CY7C43664AV CYPRESS CY7C43684AV Maximum Ratings 14 Output Current into Outputs 20 mA Above which the useful life may be impaired For user guide DORMI es MOORE DLE an lines not tested Be TS Blorade Temperat Bic sues lt 65 C to 150 C atch Up Current sse gt m Ambient Temperature with Operating Range Power Applied eee lt 55 C to 125 C Ambient Supply Voltage to Ground Potential 0 5V to 7 0V Range Temperature cel DC Voltage Applied to Outputs Commercial 0 C to 70 C 3 3V 10 in lt 0 5V to Voc 0 5V 13 Industrial lt 40 C to 85 C 3 3V 10 DC Input Voltage
25. KB Table 6 and Table 7 show the relationship of each port flag to FIFO1 and FIFO2 Empty Output Ready Flags EFA ORA EFB ORB These are dual purpose flags In the FWFT mode the Output Ready ORA ORB function is selected When the Output Ready flag is HIGH new data is present in the FIFO output register When the Output Ready flag is LOW the previous data word remains in the FIFO output register and any FIFO reads are ignored In the CY Standard mode the Empty Flag EFA EFB function is selected When the Empty Flag is HIGH data is available in the FIFO s RAM memory for reading to the output register When Empty Flag is LOW the previous data word remains in the FIFO output register and any FIFO reads are ignored The Empty Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array For both the FWFT Page 8 of 37 Wn m 7 CYPRESS and CY Standard modes the FIFO Read pointer is incre mented each time a new word is clocked to its output register The state machine that controls an Output Ready flag monitors a Write pointer and Read pointer comparator that indicates when the FIFO SRAM status is empty empty 1 or empty 2 In FWFT Mode from the time a word is written to a FIFO it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock Therefore an Output Ready flag is LOW if a word in memory is the next data to be sen
26. a Master Reset would be inconvenient Big Endian First Word Fall Through BE FWFT This is a dual purpose pin At the time of Master Reset the BE select function is active permitting a choice of Big or Little Endian byte arrangement for data written to or read from Port B This selection determines the order by which bytes or words of data are transferred through this port For the following illustrations assume that a byte or word bus size has been selected for Port B Note that when Port B is configured for a long word size the Big Endian function has no application and the BE input is a Don t Care Document 38 06025 Rev C CY7C43644AV CY7C43664AV CY7C43684AV A HIGH on the BE FWFT input when the Master Reset MRS1 and MRS2 inputs go from LOW to HIGH will select a Big Endian arrangement When data is moving in the direction from Port A to Port B the most significant byte word of the long word written to Port A will be transferred to Port B first the least significant byte word of the long word written to Port A will be transferred to Port B last When data is moving in the direction from Port B to Port A the byte word written to Port B first will be transferred to Port A as the most significant byte word of the long word the byte word written to Port B last will be transferred to Port A as the least significant byte word of the long word A LOW on the BE FWFT input when the Master Reset MRS1 and
27. artial Reset of FIFO2 MRS1 FIFO1 Master A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location Reset of memory and sets the Port B output register to all zeroes A LOW pulse on MRS1 selects the programming method serial or parallel and one of three programmable flag default offsets for FIFO1 It also configures Port B for bus size and endian arrangement Four LOW to HIGH transitions of CLKA and four LOW to HIGH transi tions of CLKB must occur while MRS1 is LOW Document 38 06025 Rev C Page 5 of 37 Wn 1 7 CYPRESS Pin Definitions continued CY7C43644AV CY7C43664AV CY7C43684AV y o Function A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location of memory and sets the Port A output register to all zeroes A LOW pulse on MRS2 selects one of three programmable flag default offsets for FIFO2 Four LOW to HIGH transitions of CLKA and four LOW to HIGH transitions of CLKB must occur while MRS2 is LOW ALOWonthis pin initializes the FIFO1 Read and Write pointers to the first location of memory and sets the Port B output register to all zeroes During Partial Reset the currently selected bus size endian arrangement programming method serial or parallel and programmable flag settings are all retained ALOWonthis pin initializes the FIFO2 Read and Write pointers to the first location of memory and sets the Port A output register to al
28. e bus comes from the FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH The Maill Register Flag MBF1 is set HIGH by a LOW to HIGH transition on CLKB when a Port B Read is selected by CSB LOW W RB HIGH ENB HIGH AND MBB HIGH For a 36 bit bus size 36 bits of mailbox data are placed on 55 For an 18 bit bus size 18 bits of mailbox data are placed on Bo 47 In this case B4 35 are indeterminate For a 9 bit bus Size 9 bits of mailbox data are placed on By g In this case Bg 35 are indeterminate The Mail2 register Flag MBF2 is set HIGH by a LOW to HIGH transition on CLKA when a Port A Read is selected by CSA LOW W RA LOW ENA HIGH MBA HIGH For a 36 bit bus size 36 bits of mailbox data are placed on Ao 35 For an 18 bit bus size 18 bits of mailbox data are placed on Ag 47 In this case A4g 35 are indeterminate For a 9 bit bus size 9 bits of mailbox data are placed on Ay In this case Ag 35 are indeterminate The data in a mail register remains intact after it is read and changes only when new data is written to the register The Endian Select feature has no effect on the mailbox data Bus Sizing The Port B bus can be configured in a 36 bit long word 18 bit word or 9 bit byte format for data read from FIFO1 or written to FIFO2 The levels applied to the Port B Bus Size Select SIZE and the Bus Match Select BM determ
29. egister X2 AEB Port B Almost O Programmable Almost Empty flag synchronized to CLKB It is LOW when the Empty Flag number of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register X1 AFA Port A Almost O Programmable Almost Full flag synchronized to CLKA MHz It is LOW when the Full Flag number of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset register Y 1 12 AFB Port B Almost O Programmable Almost Full flag synchronized to CLKB Itis LOW when the number Full Flag of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset register Y2 2 Bo_35 Port B Data 36 bit bidirectional data port for side B BE FWFT Big Endian Thisis a dual purpose pin During Master Reset a HIGH on BE will select Big Endian First Word Fall operation In this case depending on the bus size the most significant byte or word Through Select on Port A is transferred to Port B first for A to B data flow For data flowing from port B to Port A the first word byte written to Port B will come out as the most significant word byte on port A On the other hand a LOW on BE will select Little Endian operation In this case the least significant byte or word on Port A is transferred to Port B first for A to B data flow Similarly the first word byte written into port B will come out as the least significant word byte on Port A for B to A data flow Afte
30. gram the X1 X2 Y1 and Y2 registers serially initiate a Master Reset with SPM LOW FS0 SD LOW and FS1 SEN HIGH during the LOW to HIGH transition of MRS1 and MRS2 After this reset is complete the X and Y register values are loaded bit wise through the FSO SD input on each LOW to HIGH transition of CLKA that the FS1 SEN input is LOW Forty forty eight or fifty six bit Writes are needed to complete the programming for the CY7C436X4AV respectively The four registers are written in the order Y1 X1 Y2 and finally X2 The first bit Write stores the most significant bit of the Y1 register and the last bit Write stores the least significant bit of the X2 register When the option to program the offset registers serially is chosen the Port A Full Input Ready FFA IRA flag remains LOW until all register bits are written FFA IRA is set HIGH by the LOW to HIGH transition of CLKA after the last bit is loaded to allow normal FIFO1 operation The Port B Full Input ready FFB IRB flag also remains LOW throughout the serial programming process until all register bits are written FFB IRB is set HIGH by the LOW to HIGH transition of CLKB after the last bit is loaded to allow normal FIFO2 operation SPM FSO SD and FS1 SEN function the same way in both CY Standard and FWFT modes FIFO Write Read Operation The state of the Port A data Ag 35 lines is controlled by Port A Chip Select CSA and Port A Write Read Select W R
31. ine the Port B bus size These levels should be static throughout FIFO operation Both bus size selections are implemented at the completion of Master Reset by the time the Full Input Ready flag is set HIGH Two different methods for sequencing data transfer are available for Port B when the bus size selection is either byte or word size They are referred to as Big Endian most signif icant byte first and Little Endian least significant byte first The level applied to the Big Endian Select BE input during the LOW to HIGH transition of MRS1 and MRS2 selects the Document 38 06025 Rev C CY7C43644AV CY7C43664AV CY7C43684AV endian method that will be active during FIFO operation BE is a Don t Care input when the bus size selected for Port B is long word The endian method is implemented at the completion of Master Reset by the time the Full Input Ready flag is set HIGH Bus Matching operations are not available when transferring data via mailbox registers Furthermore both the word and byte size bus selections limit the width of the data bus that can be used for mail register operations In this case only those byte lanes belonging to the selected word or byte size bus can carry mailbox data The remaining data outputs will be indeterminate The remaining data inputs will be don t care inputs For example when a word size bus is selected then mailbox data can be transmitted only between Aj and _17
32. ith one of the three preset values listed in Table 3 the Serial Program Mode SPM and at least one of the flag select inputs must be HIGH during the LOW to HIGH transition of its Master Reset input MRS1 and MRS2 For example to load the preset value of 64 into X1 and Y1 SPM FSO and FS1 must be HIGH when FIFO1 reset MRS1 returns HIGH Flag offset registers associated with FIFO2 are loaded with one of the preset values in the same way with Master Reset MRS2 When using one of the preset values for the flag offsets the FIFOs can be reset simultaneously or at different times To program the X1 X2 Y1 and Y2 registers in parallel from Port A perform a Master Reset on both FIFOs simultaneously with SPM HIGH and FSO and FS1 LOW during the LOW to HIGH transition of MRS1 and MRS2 After this reset is complete the first four Writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1 X1 Y2 X2 The Port A data inputs used by the offset registers are Ao Ap_11 or Ag 13 for the CY7C436X4AV respectively The highest numbered input is used as the most significant bit of the binary number in each case Valid programming values for the registers range from 0 to 1023 for the CY7C43644AV 0 to 4095 for the CY7C43664AV 0 to 16383 for the CY7C43684AV After all the offset registers are programmed from Port A the Port B Full Input Ready FFB IRB is set HIGH and both FIFOs begin normal operation To pro
33. l zeroes During Partial Reset the currently selected bus size endian arrangement programming method serial or parallel and programmable flag settings are all retained A LOW strobe on this pin will retransmit the data on FIFO1 This is achieved by bringing the Read pointer back to location zero The user will still need to perform Read operations to retransmit the data Retransmit function applies to CY standard mode only A LOW strobe on this pin will retransmit the data on FIFO2 This is achieved by bringing the Read pointer back to location zero The user will still need to perform Read operations to retransmit the data Retransmit function applies to CY standard mode only A HIGH on this pin when BM is HIGH selects byte bus 9 bit size on Port B A LOW on this pin when BM is HIGH selects word 18 bit bus size SIZE works with BM and BE to select the bus size and endian arrangement for Port B The level of SIZE must be static throughout device operation A LOW on this pin selects serial programming of partial flag offsets A HIGH on this pin selects parallel programming or default offsets 8 16 or 64 A HIGH selects a Write operation and a LOW selects a Read operation on Port A for a LOW to HIGH transition of CLKA The Ag 55 outputs are in the high impedance state when W RA is HIGH Signal Name Description MRS2 FIFO2 Master Reset PRS1 FIFO1 Partial Reset PRS2 FIFO2 Partial Reset RT1 Retransmit FIFO1
34. nction H X X X In high impedance state None L H L X In high impedance state None L H H L In high impedance state FIFO1 Write L H H H In high impedance state Mail1 Write L L L L Active FIFO2 output register None L L H L Active FIFO2 output register FIFO2 Read L L L H Active Mail2 register None L L H H Active Mail2 register Mail2 Read set MBF2 HIGH Table 5 Port B Enable Function CSB W RB ENB MBB CLKB Bo_35 Port Function H X X X In high impedance state None L L L X In high impedance state None L L H L In high impedance state FIFO2 Write L L H H In high impedance state Mail2 Write L H L L X Active FIFO1 output register None L H H L Active FIFO1 output register FIFO1 Read L H L H X Active Mail1 register None L H H H T Active Mail1 register 1 Read set MBF1 HIGH Notes TERM E 3 X1 register holds the offset for AEB Y1 register holds the offset for AFA 4 X2 register holds the offset for AEA Y2 register holds the offset for AFB Document 38 06025 Rev C Page 12 of 37 CY7C43644AV CY7C43664AV CYPRESS CY7C43684AV Table 6 FIFO1 Flag Operation CY Standard and FWFT modes Number of Words in FIFO Memory 5 6 7 8 Synchronized to CLKB Synchronized to CLKA CY7C43644AV CY7C43664AV CY7C43684AV EFB ORB AEB AFA FFA
35. ngs CY7C43644 64 84AV CY7C43644 64 84AV CY7C43644 64 84AV 7 10 15 Unit Maximum Frequency 133 100 66 7 MHz Maximum Access Time 6 8 10 ns Minimum Cycle Time 7 5 10 15 ns Minimum Data or Enable Set Up 3 4 5 ns Minimum Data or Enable Hold 0 0 0 ns Maximum Flag Delay 6 8 10 ns Active Power Supply Commercial 60 60 60 mA Current Industrial 60 Note 2 When FIFO is operated at the almost empty full boundary there may be an uncertainty of up to two clock cycles for flag deassertion but the flag will always be asserted exactly when the FIFO content reaches the programmed value Use the assertion edge for trigger if flag accuracy is required Refer to Cypress s application note entitled Designing with CY7C436xx Synchronous FIFOs for more details on flag uncertainties Document 38 06025 Rev C Page 3 of 37 CY7C43644AV gt CY7C43664AV CYPRESS CY7C43684AV CY7C43644AV CY7C43664AV CY7C43684AV Density 1K x 36 x 2 4K x 36 x 2 16K x 36 x 2 Package 128 TQFP 128 TQFP 128 TQFP Pin Definitions Signal Name Description I O Function Ao 35 Port A Data 36 bit bidirectional data port for side A AEA Port A Almost O Programmable Almost Empty flag synchronized to CLKA It is LOW when the Empty Flag number of words in FIFO2 is less than or equal to the value in the Almost Empty A offset r
36. nts of register Y1 for AFA and register Y2 for AFB These registers are loaded with preset values during a FIFO reset programmed from Port A or programmed serially see Almost Empty flag and Almost Full flag offset programming above An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to 1024 Y 4096 Y or 16384 Y for the CY7C436X4AV respectively An Almost Full flag is HIGH when the number of words in its FIFO is less than or equal to 1024 Y 2 4096 Y 2 16384 Y 2 for the CY7C436X4AV a The Almost Full flag is set HIGH by the first LOW to HIGH transition of its synchronizing clock after two FIFO reads that reduces the number of words in memory to 1024 4096 16384 Y 2 A LOW to HIGH transition of an Almost Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tgxewe or greater after the Read that reduces the number of words in memory to 1024 4096 16384 Y 2 Otherwise the subsequent synchronizing clock cycle will be the first synchronization cycle Mailbox Registers Each FIFO has a 36 bit bypass register to pass command and control information between Port A and Port B without putting it in queue The Mailbox Select MBA MBB inputs choose between a mail register and a FIFO for a port data transfer operation The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port
37. on is selected Output Ready EFA indicates whether or notthe FIFO2 memory is empty In the FWFT mode the ORA Flag function is selected ORA indicates the presence of valid data on Ag 35 outputs available for reading EFA ORA is synchronized to the LOW to HIGH transition of CLKA Document 38 06025 Rev C Page 4 of 37 Wn N 7 CYPRESS Pin Definitions continued CY7C43644AV CY7C43664AV CY7C43684AV Signal Name Description I O Function EFB ORB Port B Empty O This is a dual function pin In the CY Standard mode the EFB function is selected Output Ready EFB indicates whether or not the FIFO1 memory is empty Inthe FWFT mode the ORB Flag function is selected ORB indicates the presence of valid data on 35 outputs available for reading EFB ORB is synchronized to the LOW to HIGH transition of CLKB ENA Port A Enable ENA must be HIGH to enable a LOW to HIGH transition of CLKA to Read or Write data on Port A ENB Port B Enable ENB must be HIGH to enable a LOW to HIGH transition of CLKB to Read or Write data on Port B FFA IRA Port AFull Input This is a dual function pin In the CY Standard mode the FFA function is selected Ready Flag FFA indicates whether or not the FIFO1 memory is full In the FWFT mode the IRA function is selected IRA indicates whether or not there is space available for writing to the FIFO1 memory
38. r Master Reset this pin selects the timing mode A HIGH on BE FWFT selects CY Standard mode a LOW selects First Word Fall Through mode Once the timing mode has been selected the level on this pin must be static throughout device operation BM Bus Match A HIGH on this pin enables either byte or word bus width on Port B depending Select Port A on the state of SIZE A LOW selects long word operation BM works with SIZE and BE to select the bus size and endian arrangement for Port B The level of BM must be static throughout device operation CLKA Port A Clock CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB FFA IRA EFA ORA AFA and AEA are all synchronized to the LOW to HIGH transition of CLKA CLKB Port B Clock CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA FFB IRB EFB ORB AFB and AEB are all synchronized to the LOW to HIGH transition of CLKB CSA Port A Chip CSA must be LOW to enable a LOW to HIGH transition of CLKA to Read or Write Select on Port A The Ag 35 are in the high impedance state when CSA is HIGH CSB Port B Chip CSB must be LOW to enable a LOW to HIGH transition of CLKB to Read or Write Select on Port B The Bg 35 are in the high impedance state when CSB is HIGH EFA ORA Port A Empty O This is a dual function pin In the CY Standard mode the EFA functi
39. ration When a Read operation is performed on Port A a HIGH level on MBA selects data from the Mail2 register for output and a LOW level selects FIFO2 output register data for output When a Write operation is performed on port A a HIGH level on MBA will write the data into Mail1 register while a LOW level will write the data into FIFO1 MBB Port B Mailbox A HIGH level MBB chooses a mailbox register for a Port B Read or Write Select operation When a Read operation is performed on Port B a HIGH level on MBB selects data from the Mail1 register for output and a LOW level selects FIFO1 output register data for output When a Write operation is performed on port B a HIGH level on MBB will write the data into Mail2 register while a LOW level will write the data into FIFO2 MBF1 Mail1 Register O MBF1 is set LOW by a LOW to HIGH transition of CLKA that writes data to the Flag Mail1 register Writes to the Mail1 register are inhibited while MBF1 is LOW MBF1 is set HIGH by a LOW to HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH MBF1 is set HIGH following either a Master or Partial Reset of FIFO1 MBF2 Mail2 Register MBF2is set LOW a LOW to HIGH transition of CLKB that writes data to the Mail2 Flag register Writes to the Mail2 register are inhibited while MBF2 is LOW MBF2 is set HIGH by a LOW to HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH MBF2 is set HIGH following either a Master or P
40. reads data from its array The state machine that controls an Almost Empty flag monitors a Write pointer and Read pointer comparator that indicates when the FIFO SRAM status is almost empty almost empty 1 or almost empty 2 The Almost Empty state is defined by the contents of register X1 for AEB and register X2 for AEA These registers are loaded with preset values during a FIFO reset programmed from Port A or programmed serially see Almost Empty flag and Almost Full flag offset programming above An Almost Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains X 2 or more words l The Almost Empty flag is set HIGH by the first LOW to HIGH transition of its synchronizing clock after two FIFO Writes that fills memory to the X 2 level A LOW to HIGH transition of an Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tskeyo or greater after the Write that fills the FIFO to X 2 words Otherwise the subsequent synchronizing clock cycle will be the first synchro nization cycle Almost Full Flags AFA AFB The Almost Full flag of a FIFO is synchronized to the port clock that writes data to its array The state machine that controls an Almost Full flag monitors a Write pointer and Read pointer comparator that indicates when the FIFO SRAM status is almost full almost full 1 or almost full 2 The Almost Full state is defined by the conte
41. t to the FIFO output register and three cycles have not elapsed since the time the word was written The Output Reagy flag of the FIFO remains LOW until the third LOW to HIGH transition of the synchronizing clock occurs simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register In the CY Standard mode from the time a word is written to a FIFO the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock Therefore an Empty Flag is LOW if a word in memory is the next data to be sentto the FIFO output register and two cycles have not elapsed since the time the word was written The Empty Flag of the FIFO remains LOW until the second LOW to HIGH transition of the synchronizing clock occurs forcing the Empty Flag HIGH only then will data be read A LOW to HIGH transition on an Empty Output Ready flag synchronizing clock begins the first synchronization cycle of a Write if the clock transition occurs at time tskgw or greater after the Write Otherwise the subsequent clock cycle can be the first synchronization cycle Full Input Ready Flags FFA IRA FFB IRB This is a dual purpose flag In FWFT mode the Input Ready IRA and IRB function is selected In CY Standard mode the Full Flag FFA and FFB function is selected For both timing modes when the Full Input Ready flag is HIGH a memory location is free in the SRAM
42. tes on Port B are independent of any concurrent Port A operation The set up and hold time constraints to the port clocks for the port Chip Selects and Write Read selects are only for enabling Write and Read operations and are not related to high impedance control of the data outputs If a port enable is LOW during a clock cycle the port s Chip Select and Write Read select may change states during the set up and hold time window of the cycle When operating the FIFO in FWFT mode and the Output Ready flag is LOW the next word written is automatically sent to the FIFO s output register by the LOW to HIGH transition of the port clock that sets the Output Ready flag HIGH data residing in the FIFO s memory array is clocked to the output register only when a Read is selected using the port s Chip Select Write Read select Enable and Mailbox select When operating the FIFO in CY Standard mode data residing in the FIFO s memory array is clocked to the output register only when a Read is selected using the port s Chip Select Write Read select Enable and Mailbox select Synchronized FIFO Flags Each FIFO is synchronized to its port clock through at least two flip flop stages This is done to improve flag signal reliability by reducing the probability of the metastable events when CLKA and CLKB operate asynchronously to one another EFA ORA AEA FFA IRA and AFA are synchronized to CLKA EFB ORB AEB FFB IRB and AFB are synchronized to CL
43. to receive new data No memory locations are free when the Full Input Ready flag is LOW and any Writes to the FIFO are ignored The Full Input Ready flag of a FIFO is synchronized to the port clock that writes data to its array For both FWFT and CY Standard modes each time a word is written to a FIFO its Write pointer is incremented The state machine that controls a Full Input Ready flag monitors a Write pointer and read pointer comparator that indicates when the FIFO SRAM status is full full 1 or full 2 From the time a word is read from a FIFO its previous memory location is ready to be written to in a minimum of two cycles of the Full Input Ready flag synchro nizing clock Therefore a Full Input Ready flag is LOW if less than two cycles of the Full Input Ready flag synchronizing clock have elapsed since the next memory Write location has been read The second LOW to HIGH transition on the Full Input Ready flag synchronizing clock after the Read sets the Full Input Ready flag HIGH A LOW to HIGH transition on a Full Input Ready flag synchro nizing clock begins the first synchronization cycle of a Read if the clock transition occurs at time tskeywy or greater after the Read Otherwise the subsequent clock cycle will be the first synchronization cycle Document 38 06025 Rev C CY7C43644AV CY7C43664AV CY7C43684AV Almost Empty Flags AEA AEB The Almost Empty flag of a FIFO is synchronized to the port clock that
44. tput register does not count as a word in FIFO memory Since FWFT mode the first word written to an empty FIFO goes unrequested to the output register no Read operation necessary it is not included in the FIFO memory count 8 The ORB and IRA functions are active during FWFT mode the EFB and FFA functions are active in CY Standard mode 9 X2isthe almost empty offset for FIFO2 used by AEA Y2 is the almost full offset for FIFO2 used by AFB Both X2 and Y2 are selected during a FIFO2 reset or port A programming 10 The ORA and IRB functions are active during FWFT mode the EFA and FFB functions are active in CY Standard mode quested to the output register no Read operation necessary it is not included in the FIFO memory count 11 BEis selected at Master Reset BM and SIZE must be static throughout device operation Document 38 06025 Rev C Page 13 of 37 7 CYPRESS Table 10 Data Size for Byte Writes to FIFO2 CY7C43644AV CY7C43664AV CY7C43684AV Size Model Write No Data Written to FIFO2 Data Read From FIFO2 BM SIZE BE Bo 8 A27 35 A18 26 Ag 47 Ao 8 H H H 1 A A B C D 2 B 3 C 4 D H H L 1 D A B C D 2 C 3 B 4 A Table 11 Data Size for FIFO Long Word Reads from FIFO1 Size Model Data Written to F
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CIRRUS LOGIC CY7C43644AV CY7C43664AV CY7C43684AV handbook