ANALOG DEVICES LC 2 MOS 8-Bit DAC with Output Amplifiers AD7224 handbook
Contents
1. gt y I H High State L Low State X Don t Care All control inputs are level triggered T he contents of both registers are reset by a low level on the RESET line With both registers transparent the RESET line functions like a zero override with the output brought to 0 V for the duration of the RESET pulse If both registers are latched a LOW pulse on RESET will latch all 05 into the registers and the output remains at 0 V after the RESET line has returned HIGH The RESET line can be used to ensure power up to 0 V on the AD 7224 output and is also useful when used as a zero override in system calibration cycles Figure 3 shows the input control logic for the AD 7224 LDAC T REGISTER INPUT DATA Figure 3 Input Control Logic cs ty ty WR t2 t2 ty t ty LDAC 1 tg gt 15 DATA DATA IN VALID NOTES 1 ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10 TO 90 OF Vpp t ty 20ns OVER Vpp RANGE Vinn Vine 2 TIMING MEASUREMENT REFERENCE LEVEL IS ar ae Figure 4 Write Cycle Timing Diagram SPECIFICATION RANGES For the DAC to maintain specified accuracy the reference volt age must be at least 4 V below the Vpp power supply voltage T his voltage differential is required for correct generation of bias voltages for the DAC switches With dual supply operation the AD 7224 has an extended Vpp range from 12 V 5 to 15 V2. T2240 Rr fS ANALOG DEVICES LC MOS 8 Bit DAC with Output Amplifiers AD7224 FEATURES 8 Bit CMOS DAC with Output Amplifiers Operates with Single or Dual Supplies Low Total Unadjusted Error Less Than 1 LSB Over Temperature Extended Temperature Range Operation p P Compatible with Double Buffered Inputs Standard 18 Pin DIPs and 20 Terminal Surface Mount Package and SOIC Package GENERAL DESCRIPTION The AD 7224 is a precision 8 bit voltage output digital to analog converter with output amplifier and double buffered interface logic on a monolithic CM OS chip N o external trims are required to achieve full specified performance for the part T he double buffered interface logic consists of two 8 bit regis ters an input register and a DAC register Only the data held in the DAC registers determines the analog output of the con verter T he double buffering allows simultaneous update in a system containing multiple AD 7224s Both registers may be made transparent under control of three external lines CS WR and LDAC With both registers transparent the RESET line functions like a zero override a useful function for system cali bration cycles All logic inputs are TTL and CMOS 5 V level compatible and the control logic is speed compatible with most 8 bit microprocessors Specified performance is guaranteed for input reference voltages from 2 V to 12 5 V when using dual supplies T he part is also speci
3. MSB DB7 7 Not to Scale 15 DBO LSB MSB DB7 Not to Scale DBO LSB DB6 8 14 DB1 DB6 DB1 9 10 11 12 13 0 m gt a NC NO CONNECT NC NO CONNECT REV B AD7224 TERMINOLOGY TOTAL UNADJUSTED ERROR T otal U nadjusted Error is a comprehensive specification which includes full scale error relative accuracy and zero code error M aximum output voltage is Var 1 LSB ideal where 1 LSB ideal is Vpef 256 The LSB size will vary over the Veer range H ence the zero code error relative to the LSB size will increase as Vref decreases Accordingly the total unadjusted error which includes the zero code error will also vary in terms of LSBs over the Vref range As a result total unadjusted error is specified for a fixed reference voltage of 10 V RELATIVE ACCURACY Relative Accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function It is measured after al lowing for zero code error and full scale error and is normally expressed in LSBs or as a percentage of full scale reading DIFFERENTIAL NONLINEARITY Differential N onlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity DIGITAL FEEDTHROUGH Digital Feedthrough is th
4. 0 0125 0 32 9 0 0040 0 10 127 0 0138 0 35 0 0091 0 23 L AA 0 0157 0 40 8 REV B 0 0500 1 27 xl m C836a 10 10 84 PRINTED IN U S A
5. 10 i e from 11 4 V to 16 5 V Operation is also specified for a single Vpp power supply of 15 V 5 Performance is specified over a wide range of reference voltages from 2 V to Vpp 4 V with dual supplies T his allows a range of standard reference generators to be used such as the AD 580 a 42 5 V bandgap reference and the AD 584 a precision 10 V reference N ote that in order to achieve an output voltage range of 0 V to 10 V a nominal 15 V 596 power supply voltage is required by the AD 7224 GROUND MANAGEMENT AC or transient voltages between AGND and DGND can cause noise at the analog output T his is especially true in micropro cessor systems where digital noise is prevalent T he simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGN D and DGND together at the AD 7224 In more complex systems where the AGND and DGND intertie is on the backplane it is recommended that two diodes be con nected in inverse parallel between the AD 7224 AGND and DGND pins IN 914 or equivalent Applying the AD7224 UNIPOLAR OUTPUT OPERATION T his is the basic mode of operation for the AD 7224 with the output voltage having the same positive polarity as Vagr T he AD 7224 can be operated single supply Vss AGN D or with positive negative supplies see op amp section which outlines the advantages of having negative Vss Connections for the uni polar output operation are shown in F igure 5 T he voltage
6. DIGITAL INPUTS nput High Voltage 2 4 2 4 V min nput Low Voltage Vint 0 8 0 8 V max nput Leakage C urrent 1 1 Vin 20V or Vpp nput C apacitance 8 8 pF max nput Coding Binary Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate 2 5 2 5 V us min Voltage O utput Settling T ime Positive ull 5cale C hange 5 5 us max Veer 10 V Settling Time to 1 2 LSB N egative F ull Scale C hange 7 7 us max Veer 10 V Settling Time to 1 2 LSB Digital F eedthrough 50 50 nV secs typ Veer 20V M inimum L oad Resistance 2 2 kQ min Vout 10 V POWER SUPPLIES Vpp Range 11 4 16 5 11 4 16 5 V min V max For Specified Performance Vss Range 4 5 5 5 4 5 5 5 V min V max For Specified Performance lop 25 C 4 4 mA max Outputs Unloaded Vin Vine Or Ving Tin to T max 6 6 mA max Outputs Unloaded Vin Vine Or Vina Iss 25 C 3 3 mA max Outputs Unloaded Vin Vine Or Ving Tin to T max 5 5 mA max Outputs Un oaded Vin Vine Or Ving SWITCHING CHARACTERISTICS 4 25 C 90 90 ns min Chip Select Load DAC Pulse Width Tin to Tmax 90 90 ns min b 25 C 90 90 ns min Write Reset Pulse Width Twin to T max 90 90 ns min ts 25 C 0 0 ns min Chip Select Load DAC to Write Setup Time Tin to T max 0 0 ns min ty 25 C 0 0 ns min Chip Select Load DAC to Write Hold Time Tmin to T max 0 0 ns min t5 25 C 90 90 ns min D ata Valid to Write Setup Time Tin to T max 90 90 ns min te 25 C 10 10 ns min Data Valid to Write Hold Time Tin to Tmax 10 10
7. at Veer must never be negative with respect to DGND Failure to observe this precaution may cause parasitic transistor action and possible device destruction T he code table for unipolar output operation is shown in T able Il Vpp VREF Figure 5 Unipolar Output Circuit Table Ill Unipolar Code Table DAC Register Contents MSB LSB Analog Output 255 1111 1111 W rer 256 129 1000 0001 V ger 256 128 _ V 1000 0000 127 0111 1111 H rer 355 1 0000 0001 W Rer 256 0000 0000 0v Note 1 LSB 028 V nee 355 REV BIPOLAR OUTPUT OPERATION The AD 7224 can be configured to provide bipolar output op eration using one external amplifier and two resistors F igure 6 shows a circuit used to implement offset binary coding In this Case Vo 23 V REF 32 v REF With R1 2R2 Vo 2D 1 where is a fractional representation of the digital word in the DAC register M ismatch between R 1 and R2 causes gain and offset errors therefore these resistors must match and track over tempera ture Once again the AD 7224 can be operated in single supply or from positive negative supplies T able 111 shows the digital code versus output voltage relationship for the circuit of Figure 6 with R1 R2 O Vour Vour 15V R1 R2 10kO 0 1 Figure 6 Bipolar Output Circuit Tablelll Bipolar Offset Binary Code Table Figure 7 AGND Bias
8. code and can vary from 0 to 255 256 OP AMP SECTION T he voltage mode D A converter output is buffered by a unity gain noninverting CM OS amplifier T his buffer amplifier is capable of developing 10 V across a 2 load and can drive capacitive loads of 3300 pF The AD 7224 can be operated single or dual supply resulting in different performance in some parameters from the output am plifier In single supply operation Vss 0 V AGN D the sink capability of the amplifier which is normally 400 pA is reduced as the output voltage nears AGND T he full sink capability of 400 pA is maintained over the full output voltage range by tying Vss to 5 V This is indicated in Figure 2 0 2 4 6 8 10 Vour Volts Figure 2 Variation of Ig with Vout Settling time for negative going output signals approaching AGN D is similarly affected by Vss N egative going settling time for single supply operation is longer than for dual supply opera tion Positive going settling time is not affected by Vss Additionally the negative Vss gives more headroom to the out put amplifier which results in better zero code performance and improved slew rate at the output than can be obtained in the single supply mode DIGITAL SECTION T he AD 7224 digital inputs are compatible with either TTL or 5 V CM OS levels All logic inputs are static protected M OS gates with typical input currents of less than 1 nA Internal in put prot
9. opera tion from a single power supply rail T he part can also be op erated with dual supplies giving enhanced performance for some parameters Versatile Interface Logic T he high speed logic allows direct interfacing to most micro processors Additionally the double buffered interface en ables simultaneous update of the AD 7224 in multiple DAC systems T he part also features a zero override function N C2 gt One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 AD7224 SPECIFICATIONS DUAL SUPPLY Vpp 11 4 V to 16 5 V Vss 5 V 10 AGND DGND O V 2 4 V unless otherwise noted All specifications Tmn to Tmax unless otherwise noted B T L C U Parameter Versions Versions Units Conditions Comments STATIC PERFORMANCE Resolution 8 8 Bits T otal Unadjusted Error 2 LSB max Vpp 15 V 5 10 V Relative Accuracy 1 1 2 LSB max Differential N onlinearity 1 1 LSB max Guaranteed M onotonic Full Scale Error 3 2 1 LSB max Full Scale T emperature C oefficient 20 20 ppm C max Vpp 14V to 16 5 V 10 V Zero Code Error 30 20 mV max Zero Code Error T emperature Coefficient 50 30 uv C typ REFERENCE INPUT Voltage Range 2 to Vpp 4 2 to Vpp 4 V min to V max nput Resistance 8 8 kQ min nput C apacitance 100 100 pF max Occurs when DAC is loaded with all 1s
10. to 85 C 2 max N 18 e Pr 0 3 E AD 7224LN 40 C to 85 C 1 max N 18 out t0 AG pO eene nnn nnn ss AD 7224K P 40 C to 85 C 2 max P 20A Power Dissipation Any Package to 75 450 mW AD 7224LP 40 C to 85 C 1 P 20A eis Ms DY ts Mad ath n 6 mW PC AD7224KR 1 40 C to 85 C 2 max R 20 o Dee E AD7224LR 1 40 C to 85 C 1 R 20 Commercial K L Versions 40 C to 85 C AD7224KR 18 40 C to 85 C 2 max R 18 Industrial B C Versions 40 C to 85 C AD7224LR 18 40 C to 85 C 1 max R 18 Extended T U Versions 55 C to 125 C AD 7224B0 40 C to 85 C 2 max 0 18 Storage Temperature 65 C to 150 C AD 7224CQ 40 C to 85 C 1 Q 18 L ead T emperature Soldering 10 secs 300 C AD 7224T Q 55 C to 125 C 2 max Q 18 NOTES AD 722400 55 C to 125 C 1 max Q 18 1Stresses above those listed under Absolute Maximum Ratings may cause AD 7224T E 559C to 125 C 2 max E 20A permanent damage to the device This is a stress rating only and functional 5 2 5 operation of the device at these or any other conditions above those indicated in AD 7224UE 55 to 125 C 1 E 20A the operational sections of this specification is not implied Exposure to absolute NOTES maximum rating conditions for extended periods may affect device reliability 2 he o
11. 5 0 381 0 203 ES 0 070 1 778 1 71 0 110 2 794 0 23 0 584 0 330 8 382 0 090 2 286 0 015 0 381 NOTES 1 LEAD NO 1 IDENTIFIED BY DOT OR NOTCH 2 CERAMIC DIP LEADS WILL BE EITHER GOLD OR TIN PLATED IN ACCORDANCE WITH MIL M 38510 REQUIREMENTS 18 Lead SOIC R 18 18 10 0 2992 7 60 0 2914 7 40 0 4193 10 65 0 3937 10 00 PIN 1 l v 0 4625 11 75 0 1043 2 65 0 0926 2 35 0 4469 11 35 0 0291 0 74 0 0098 0 25 45 0 0118 0 30 EN 0 0040 0 10 1 27 BSC E gt m ry 0 0500 1 27 0 0192 0 49 0 0125 0 32 0 0 0138 0 35 010091 0 23 20 Lead SOIC R 20 20 11 0 2992 7 60 0 2914 7 40 0 4193 10 65 0 3937 10 00 PIN 1 Lu 0 1043 2 65 0 0157 0 40 be 0 5118 13 00 0 0926 2 35 0 4961 12 60 A 0 0291 0 74 5 0 200 5 08 BSC 0 100 2 54 0 100 0 064 1 63 0 015 0 38 pa 4 0 095 2 41 0 358 9 09 t1 0 075 1 90 0 342 8 69 py 0 011 0 28 R 0 007 0 18 sa R TYP Y 0 075 Th 1 91 gt 0 088 2 24 0 054 1 37 0 055 1 40 0 045 1 14 BSC 2 54 0 028 0 71 0 022 0 56 E ue a 0098 0 25 0 0098 0 25 0 0118 0 30 0 0500 0 Aul 0 49
12. 5 2 67 0 045 1 9 045 1 15 0 015 0 381 0 095 2 42 NOTES 1 LEAD NO 1 IDENTIFIED BY DOT OR NOTCH 2 CERAMIC DIP LEADS WILL BE EITHER GOLD OR TIN PLATED ACCORDANCE WITH 32510 REQUIREMENTS 18 Pin Ceramic Suffix D 9 3 7 62 0 28 7 12 0 91 231 23 12 wo 0 12 3 05 28812261 0 06 1 53 0 17 32 E FE 0 175 ait 45 0 012 0 305 i aes 18 9 008 0 203 0 06 1 53 0 02 zi 508 ndm l5 0 306 rA 9 045 1 15 0 015 0 381 0 095 2 42 0 294 7 47 NOTES 1 LEAD NO 1 IDENTIFIED BY DOT OR NOTCH 2 CERAMIC DIP LEADS WILL BE EITHER GOLD OR TIN PLATED IN ACCORDANCE WITH MiL M 38510 REQUIREMENTS PLCC Package 0 048 1 21 0 180 4 57 0 042 1 07 0 056 1 42 0 165 Wu 19 0 042 1 07 0 025 0 63 Y 0 015 0 38 0 048 1 21 s 0 042 1 07 ry IDENTIFIER 0 050 Y TOP VIEW 1 27 BSC 4 9 008 70 008 0 203 203 Y 0 021 0 53 imei 0013 0 33 0 330 8 38 0 290 7 37 Y 0 032 0 81 0 026 0 66 e A e hoe 9 175 45 012 3 05 0 020 0 040 1 01 050 7 oase 9 04 gt 1 01 R 99 0 025 0 64 0 350 8 89 0 395 10 02 0 110 2 79 0 385 9 78 50 0 085 2 16 LCCC Package E 20A 18 Pin Cerdip Suffix Q Lh 7 874 ku 6 604 5 ime 24 13 MAX 0 060 1 524 0 015 10 389 0 320 8 128 0 290 2 366 0 180 4 572 0 140 3 556 0 200 5 080 8 125 1 199 0 01
13. Circuit MICROPROCESSOR INTERFACE ADDRESS BUS LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 8 AD7224 to 8085A 8088 Interface DAC Register Contents MSB LSB Analog Output LINEAR CIRCUITRY OMITTED FOR CLARITY 127 Li 1111 W REF GE Figure 9 AD7224 to 6809 6502 Interface 1 1000 0001 Neela 1000 0000 0v 1 0111 1111 127 0000 0001 17 128 V DATA BUS 0000 0000 V REF 128 REF LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 10 AD7224 to Z 80 Interface AGND BIAS TheAD7224 AGND pin can be biased above system GN D 72240 to provide an offset zero analog output voltage level Figure 7 shows a circuit configuration to achieve this The output voltage Vout is expressed as Vout Veias D Vin where D isa fractional representation of the digital word in DAC register and can vary from 0 to 255 256 oer DBO For a given Viy increasing above system GND will re DATABUS duce the effective Vpp Vae which must be at least 4 V to en sure specified operation N ote that Vpp and Vss for the AD 7224 must be referenced to DGND REV B 7 LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 11 AD7224 to 68008 Interface AD7224 OUTLINE DIMENSIONS Dimensions shown in inches and mm 18 Pin Plastic Suffix N 0 26 6 61 0 24 6 10 0 91 23 12 0 89 22 61 0 306 7 78 0 294 7 er a cde 0 12 20 12 0 305 305 0 065 1 66 0 02 0 508 0 10
14. UPPLIES Vpp Range 14 25 15 75 14 25 15 75 V min V max For Specified Performance lop 25 C 4 4 mA max Outputs Unloaded Vin Vine Or Ving Tin to T max 6 6 mA max Outputs U nloaded Viy Or Ving SWITCHING CHARACTERISTICS 4 t 25 C 90 90 ns min Chip Select L oad DAC Pulse Width Twin tO Tmax 90 90 ns min t2 25 C 90 90 ns min Write R eset Pulse Width Twin to T max 90 90 nsmin t3 25 C 0 0 ns min Chip Select L oad DAC to Write Setup Time T m n to T max 0 0 ns min ty 25 C 0 0 nsmin Chip Select Load DAC to Write Hold Time T m n to T max 0 0 ns min ts 25 C 90 90 nsmin Data Valid to Write Setup Time T m n to T max 90 90 ns min te 25 C 10 10 nsmin D ata Valid to Write H old Time Twin to T max 10 10 nsmin NOTES 1M aximum possible reference voltage 2 emperature ranges are as follows AD 7224K N LN 0 C to 70 C AD 7224BQ CQ 25 C to 85 C AD 7224TD UD 55 C to 125 C 3See T erminology Sample tested at 25 C by Product Assurance to ensure compliance Specifications subject to change without notice REV B 3 AD7224 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Vpp to AGND 0 3V 417 V Van tO DON Dress E ear Eben 0 3 V 17 V Total yo ERE 0 3 V 424 V Temperature Unadjusted Package AGND to DGND 0 3 V Vpp Moda Range Error LSB Option Digital Input VoltagetoDGND 0 3 V Vpp 0 3 V AD 7224K 40 C
15. e glitch impulse transferred to the out put due to a change in the digital input code It is specified in nV secs and is measured at 0 V FULL SCALE ERROR Full Scale Error is defined as M easured Value Zero Code Error Ideal Value CIRCUIT INFORMATION D A SECTION The AD 7224 contains an 8 bit voltage mode digital to analog converter T he output voltage from the converter has the same polarity as the reference voltage allowing single supply opera tion A novel DAC switch pair arrangement on the AD 7224 al lows a reference voltage range from 2 V to 12 5 V The DAC consists of a highly stable thin film R 2R ladder and eight high speed N M OS single pole double throw switches T he simplified circuit diagram for this DAC is shown in Figure 1 SHOWN FOR ALL 1 s ON DAC Figure 1 D A Simplified Circuit Diagram T he input impedance at the pin is code dependent and can vary from 8 kQ minimum to infinity T he lowest input imped ance occurs when the DAC isloaded with the digital code 01010101 T herefore it is important that the reference presents alow output impedance under changing load conditions T he nodal capacitance at the reference terminals is also code depen dent and typically varies from 25 pF to 50 pF The Voy pin can be considered as a digitally programmable voltage source with an output voltage of REV B Vout D Vaer where D is a fractional representation of the digital input
16. ection is achieved by an on chip distributed diode be tween DGND and each M OS gate T o minimize power supply currents it is recommended that the digital input voltages be driven as close to the supply rails Vpp and D GN D as practi cally possible INTERFACE LOGIC INFORMATION Table shows the truth table for AD 7224 operation T he part contains two registers an input register and a DAC register CS and WR control the loading of the input register while LDAC and WR control the transfer of information from the input regis ter to the DAC register Only the data held in the DAC register will determine the analog output of the converter All control signals are level triggered and therefore either or both registers may be made transparent the input register by keeping CS and WR LOW the DAC register by keeping LDAC and WR LOW Input data is latched on the rising edge of WR 5 AD7224 Tablel AD 7224 Truth Table o tm LDAC Function z cs Both Registers are T ransparent Both Registers are L atched Both Registers are L atched Input Register T ransparent Input Register L atched DAC Register T ransparent DAC Register 1 atched Both Registers L oaded With All Zeros Both Register Latched With All Zeros and Output Remains at Zero Both Registers are T ransparent and Output Follows Input D ata ae ae Se CE OE E lt x bQr lt T
17. fied for single supply operation using a reference of 10 V T he output amplifier is capable of developing 10 V across a 2 kQ load T he AD 7224 is fabricated in an all ion implanted high speed Linear Compatible CM OS 1 OS process which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM Vaer Voo WR 4 CONTROL UDAC LOGIC RESET PRODUCT HIGHLIGHTS 1 DAC and Amplifier on CM OS Chip T he single chip design of the 8 bit DAC and output amplifier is inherently more reliable than multi chip designs CM OS fabrication means low power consumption 35 mW typical with single supply Low T otal U nadjusted E rror T he fabrication of the AD 7224 on Analog D evices Linear Compatible CM OS 1 OS process coupled with a novel DAC switch pair arrangement enables an excellent total un adjusted error of less than 1 LSB over the full operating tem perature range Single or D ual Supply O peration T he voltage mode configuration of the AD 7224 allows
18. ns min NOTES 1M aximum possible reference voltage T emperature ranges are as follows K L Versions 40 C to 85 C B C Versions 40 C to 85 C T U Versions 55 C to 125 C 3Sample T ested at 25 by Product Assurance to ensure compliance 4Switching characteristics apply for single and dual supply operation Specifications subject to change without notice 2 REV B AD7224 15 V 5 Vss AGND DGND O V Vger 10 V unless otherwise noted NGLE SUPP LY All specifications Tmn to Tmax unless otherwise noted K B T L C U Parameter Versions Versions Units Conditions Comments STATIC PERFORMANCE Resolution 8 8 Bits T otal Unadjusted Error 2 2 LSB max Differential N onlinearity 1 1 LSB max Guaranteed M onotonic REFERENCE INPUT nput Resistance 8 8 kQ min nput C apacitance 100 100 pF max Occurs when DAC is loaded with all 1s DIGITAL INPUTS nput High Voltage 2 4 2 4 V min nput Low Voltage Vint 0 8 0 8 V max nput Leakage C urrent XT 1 Vin 20V or Vpp nput C apacitance 8 8 pF max nput Coding Binary Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate 2 2 V us min Voltage Output Settling T ime Positive ull 5cale C hange 5 5 us max Settling T ime to 1 2 LSB N egative F ull Scale C hange 20 20 us max Settling Time to 1 2 LSB Digital eedthrough 50 50 nV secs typ Veer 20V Minimum Load Resistance 2 2 kQ min Vour 10 V POWER S
19. utputs may be shorted to AGN D provided that the power dissipation of the package is not exceeded T ypically short circuit current to AGND is 60 mA To order MIL ST D 883 processed parts add 883B to part number Contact your local sales office for military data sheet E Leadless Ceramic Chip Carrier Plastic DIP P Plastic Leaded Chip Carrier Cerdip R SOIC CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD 7224 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING SERT Aa ESD SENSITIVE DEVICE PIN CONFIGURATIONS DIP and SOIC SOIC SOIC Vss VoD Vss VoD Vss Vpp Vour RESET Vour RESET Vout RESET VREF LDAC VREF LDAC Vngr LDAC AD7224 IL AD7224 AGND AD7224 WR AGND is WR AGND 72 WR DGND TOP VIEW cs DGND TOP VIEW cs DGND cs TOP VIEW MSB DB7 Not to Scale DBO LSB MSB DB7 Not to Scale DBO LSB MSB DB7 Not to Scale DBO LSB DB6 DB1 DB6 DB1 DB6 DB1 DB5 DB2 DB5 DB2 DB5 DB2 DB4 DB3 DB4 DB3 DB4 DB3 NC NC VREF 4 a 18 LDAC VREF DAG AGND 5 AD7224 17 WR AGND AD7224 ue DGND 6 TOP VIEW 16 CS DGND TOP VIEW cs
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