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ANALOG DEVICES AD7142/AD7142-1 Programmable Capacitance-to-Digital Converter with Environmental Compensation handbook

1. The decimation process on the AD7142 is an averaging process where a number of samples are taken and the averaged result is output The amount of samples taken is set equal to the decimation rate so 256 128 or 64 samples are averaged to obtain the CDC output The decimation process reduces the amount of noise present in the final CDC result However the higher the decimation rate the lower the sampling frequency thus a tradeoff is required between a noise free signal and speed of sampling CAPACITANCE SENSOR OFFSET CONTROL Apply the STAGE OFFSET registers to null any capacitance sensor offsets associated with printed circuit board parasitic capacitance or capacitance due to any other source such as connectors This is only required once during the initial capacitance sensor characterization A simplified block diagram in Figure 12 shows how to apply the STAGE OFFSET registers to null the offsets The 7 bit POS AFE OFFSET and AFE OFFSET registers provide 0 16 pF resolution offset adjustment over a range of 20 pF Apply the positive and negative offsets to either the positive or the negative CDC input using the NEG AFE OFFSET and POS AFE OFFSET registers DAC POS AFE OFFSET 20pF RANGE REGISTER POS AFE OFFSET SWAP REGISTER NEG AFE OFFSET SWAP REGISTER SENSOR DAC NEG AFE OFFSET 20pF RANGE REGISTER CIN CONNECTION SETUP REGISTER Figure 12 Analog Front End Offset Control 05702 011
2. 5 4 R W CIN9 CONNECTION SETUP CIN9 Connection Set Up 00 CIN9 not connected to CDC inputs 01 CIN9 connected to CDC negative input 10 2 CIN9 connected to CDC positive input 11 CIN9 connected to BIAS connect unused CIN inputs 7 6 R W CIN10 CONNECTION SETUP CIN10 Connection Setup 00 CIN10 not connected to CDC inputs 01 CIN10 connected to CDC negative input 10 2 CIN10 connected to CDC positive input 11 CIN10 connected BIAS connect unused CIN inputs 9 8 R W CIN11 CONNECTION SETUP CIN11 Connection Setup 00 CIN11 not connected to CDC inputs 01 CIN11 connected to CDC negative input 10 2 CIN11 connected to CDC positive input 11 CIN11 connected to BIAS connect unused CIN inputs 11 10 R W CIN12 CONNECTION SETUP CIN12 Connection Setup 00 CIN12 not connected to CDC inputs 01 CIN12 connected to CDC negative input 10 2 CIN12 connected to CDC positive input 11 CIN12 connected to BIAS connect unused CIN inputs 13 12 R W CIN13 CONNECTION SETUP CIN13 Connection Setup 00 CIN13 not connected to CDC inputs 01 CIN13 connected to CDC negative input 10 2 CIN13 connected to CDC positive input 11 CIN13 connected to BIAS connect unused CIN inputs 14 NEG AFE OFFSET DISABLE Negative AFE Offset Enable Control 0 enable 1 disable 15 POS AFE OFFSET DISABLE Positive AFE offset Enable Control 0 ena
3. 4 CONNECTION SETUP CIN4 Connection Set Up 00 CIN4 not connected to CDC inputs 01 CIN4 connected to CDC negative input 10 CIN4 connected to CDC positive input 11 2 CINA connected to BIAS connect unused CIN inputs 11 10 X R W CIN5 CONNECTION SETUP CIN5 Connection Setup 00 CIN5 not connected to CDC inputs 01 2 CIN5 connected to CDC negative input 10 2 CIN5 connected to CDC positive input 11 2 CIN5 connected to BIAS connect unused CIN inputs 13 12 X R W CIN6 CONNECTION SETUP CIN6 Connection Setup 00 CIN6 not connected to CDC inputs 01 CIN6 connected to CDC negative input 10 CIN6 connected to CDC positive input 11 CIN6 connected to BIAS connect unused CIN inputs 15 14 X Unused Rev PrD Page 59 of 64 AD7142 AD7142 1 Table 54 STAGEX Detailed CIN 7 13 Connection Setup Description X 0 to 11 Data Bit Content Default Value Type Name Description 1 0 X R W CIN7_CONNECTION_SETUP CIN7 Connection Setup 00 CIN7 not connected to CDC inputs 01 CIN7 connected to CDC negative input 10 CIN7 connected to CDC positive input 11 CIN7 connected to BIAS connect unused CIN inputs 3 2 R W CIN8_CONNECTION_SETUP CIN8 Connection Setup 00 CIN8 not connected to CDC inputs 01 CIN8 connected to CDC negative input 10 CIN8 connected to CDC positive input 11 connected to BIAS connect unused CIN inputs
4. CONVERSION SEQUENCER The AD7142 has an on chip sequencer to implement conversion control for the input channels Up to 12 conversion stages can be performed in sequence By using the Bank 2 registers each stage can be uniquely configured to support multiple capacitance sensor interface requirements For example a slider sensor can be assigned to STAGE with a button sensor assigned to STAGE2 The AD7142 on chip sequencer controller provides conversion control beginning with STAGEO Figure 13 shows a block diagram of the CDC conversion stages and CIN inputs A conversion sequence is defined as a sequence of CDC conversion starting at STAGEO and ending at the stage determined by the value pro grammed in the SEQUENCE_STAGE_NUM register In Figure 14 the conversion sequence is from STAGEO through STAGES Depending on the number and type of capacitance sensors that are used not all conversion stages are required Use the SEQUENCE STAGE NUM register to set the number of conversions in one sequence depending on the sensor interface requirements For example this register would be set to 5 if the CIN inputs were mapped to only six stages as shown in Figure 14 In addition set the STAGE CAL EN registers according to the number of stages that are used Rev PrD Page 12 of 64 AD7142 AD7142 1 Z A 16 BIT ADC 05702 012 Figure 13 AD7142 CDC Conversion Stages FF_SKIP_CNT SEQUENCE_CONV_NUM 5 1 SE
5. PIN CONFIGURATION ND FUNCTIONAL DESCRIPTIONS Wr J 222 222 E gt gt OZ CN N CIN3 1 cs CIN3 1 ADD1 PIN 2 INDICATOR Se CINE 5 INDICATOR pere CIN6 4 AD7142 SDO CIN6 4 AD7142 1 SDA CIN7 5 TOP VIEW VDRIVE CIN7 5 TOP VIEW VpRIVE CIN8 6 Not to Scale DGND2 CIN8 6 Not to Scale DGND2 7 DGND1 9 7 DGND1 CIN10 8 DVcc CIN10 8 DVcc Figure 5 AD7142 32 Lead LFCSP Pin Configuration Figure 6 AD7142 1 32 Lead LFCSP Pin Configuration Table 5 Pin Function Descriptions Pin No Name Description 1 CIN3 Capacitance Sensor Input 2 CIN4 Capacitance Sensor Input 3 CIN5 Capacitance Sensor Input 4 CIN6 Capacitance Sensor Input 5 CIN7 Capacitance Sensor Input 6 CIN8 Capacitance Sensor Input 7 CIN9 Capacitance Sensor Input 8 CIN10 Capacitance Sensor Input 9 CIN11 Capacitance Sensor Input 10 CIN12 Capacitance Sensor Input 11 CIN13 Capacitance Sensor Input 12 CDC Shield Potential Output Requires 10 nF capacitor to ground Connect to external shield 13 AVcc CDC Supply Voltage 14 AGND Analog Ground Reference Point for All CDC Circuitry Tie to analog ground plane 15 SRC CDC Excitation Source Output 16 SRC Inverted Excitation Source Output 17 DVcc Digital Core Supply Voltage 18 DGND1 Digital Ground 19 DGND2 Digital Ground 20 Vorive Serial Interface Operating Voltage Supply 21 SDO AD7142 SPI Serial Data Output SDA
6. 8 MIN WORD3 STAGE8 Minimum Value FIFO WORD3 220 15 0 X R W STAGE8 MIN AVG STAGES Average Minimum FIFO Value 221 15 0 X R W STAGE8 LOW THRESHOLD STAGE8 Low Threshold Value 222 15 0 X R W STAGE8 MIN TEMP STAGE7 Temporary Minimum Value 223 15 0 X R W Unused Rev PrD Page 55 of 64 AD7142 AD7142 1 Table 50 STAGE Results Register Map Data Bit Default Address Content Value Type Name Description 224 15 0 X RW STAGE9 CONV DATA STAGE CDC 16 Bit Conversion Data Copy of data in STAGE9 CONV DATA register 225 15 0 X R W STAGE9_FF_WORDO STAGE9 Fast FIFO WORDO 226 15 0 X R W STAGE9_FF_WORD1 STAGE9 Fast FIFO WORD1 227 15 0 X R W STAGE9_FF_WORD2 STAGE9 Fast FIFO WORD2 228 15 0 X R W STAGE9_FF_WORD3 STAGE9 Fast FIFO WORD3 229 15 0 X R W STAGE9_FF_WORD4 STAGE9 Fast FIFO WORD4 22A 15 0 X R W STAGE9_FF_WORD5 STAGE9 Fast FIFO WORD5 22B 15 0 X R W STAGE9_FF_WORD6 STAGE9 Fast FIFO WORD6 22C 15 0 X R W STAGE9_FF_WORD7 STAGE9 Fast FIFO WORD7 22D 15 0 X R W STAGE9 SF WORDO STAGE Slow FIFO WORDO 22b 15 0 X R W STAGE9 SF WORD1 STAGE Slow FIFO WORD1 22F 15 0 X R W STAGE9_SF_WORD2 STAGE9 Slow FIFO WORD2 230 15 0 X R W STAGE9_SF_WORD3 STAGE9 Slow FIFO WORD3 231 15 0 X R W STAGE9_SF_WORD4 STAGE9 Slow FIFO WORD4 232 15 0 X R W STAGE9_SF_WORD5 STAGE9 Slow FIFO WORD5 233 15 0 X R W STAGE9_SF_WORD6 STAGE9 Slow FIFO WORD6 234 15 0 X R W STAGE9_SF_WORD7 STAGE9 Slow FIFO WORD7 235 15 0
7. AD7142 1 ANALOG DEVICES Programmable Capacitance to Digital Converter with Environmental Compensation AD7142 AD7142 1 FEATURES Programmable capacitance to digital converter 30 Hz update rate maximum sequence length Better than one femto Farad resolution 14 capacitance sensor input channels No external RC tuning components required Automatic conversion sequencer On chip automatic calibration logic Automatic compensation for environmental changes Automatic adaptive threshold and sensitivity levels On chip RAM to store calibration data SPI or 12 AD7142 1 compatible serial interface Separate Vprive level for serial interface Interrupt output and GPIO 32 lead 5 mm x 5 mm LFCSP 2 7 V to 3 3 V supply voltage Low operating current Full power mode less than1 mA Low power mode 50 pA APPLICATIONS Personal music and multimedia players Cell phones Digital still cameras Smart hand held devices Television A V and remote controls Gaming consoles GENERAL DESCRIPTION The AD7142 and AD7142 1 are integrated capacitance to digital converters CDCs with on chip environmental calibration for use in systems requiring a novel user input method The AD7142 and AD7142 1 can interface to external capacitance sensors implementing functions such as capacitive buttons scroll bars or joypads The CDC has 14 inputs channeled through a switch matrix to a 16 bit 240 kHz sigma delta X A capacitance to digital
8. GPIO INPUT LOW WHEN REGISTER IS READBACK GPIO INPUT HIGH WHEN REGISTER IS READBACK I I GPIO GPIO INPUT INPUT i 1 INT INT OUTPUT OUTPUT 1 1 READ GPIO_STATUS REGISTER TO RESET INT OUTPUT 1 READ GPIO_STATUS REGISTER TO RESET INT OUTPUT 05702 028 Figure 29 INT Output Controlled by the GPIO Input Example Figure 31 INT Output Controlled by the GPIO Input Example GPIO SETUP 01 GPIO INPUT CONFIG 00 GPIO SETUP 01 GPIO INPUT CONFIG 10 11 SERIAL SERIAL READ BACK 3 READ BACK 34 1 1 1 1 1 1 GPIO INPUT HIGH WHEN REGISTER IS READBACK GPIO INPUT LOW WHEN REGISTER IS READBACK Nq gt GPIO GPIO INPUT INPUT I I 1 I I INT INT OUTPUT OUTPUT GPIO INPUT LOW WHEN REGISTER IS READBACK GPIO INPUT HIGH WHEN REGISTER IS READBACK i j l GPIO 5 GPIO I INPUT 1 I I INT INT OUTPUT OUTPUT NOTES NOTES 05702 031 1 READ GPIO STATUS REGISTER TO RESET INT OUTPUT 1 READ GPIO STATUS REGISTER TO RESET INT OUTPUT 05702 029 Figure 30 INT Output Controlled by the GPIO Input Example Figure 32 INT Output Controlled by the GPIO Input Example GPIO SETUP 01 GPIO INPUT CONFIG 01 GPIO SETUP 01 GPIO INPUT CONFIG 11 Rev PrD Page 23 of 64 AD7142 AD7142 1 OUTPUTS EXCITATION SOURCE The excitation source on board the AD7142 is
9. 249 15 0 X R W 5 10 WORDO 5 10 Fast FIFO WORDO 24A 15 0 X R W STAGE10 WORD1 STAGE10 Fast FIFO WORD1 24B 15 0 X R W 5 10 FF WORD2 STAGE10 Fast FIFO WORD2 24C 15 0 X R W 5 10 FF WORD3 5 10 Fast FIFO WORD3 24D 15 0 X R W STAGE10 FF WORD4 5 10 Fast FIFO WORDA 24E 15 0 X R W 5 10 FF WORD5 STAGE10 Fast FIFO WORD5 24F 15 0 X R W 5 10 FF WORD6 5 10 Fast FIFO WORD6 250 15 0 X R W 5 10 FF WORD7 5 10 Fast FIFO WORD7 251 15 0 X R W 5 10 SF WORDO STAGE10 Slow FIFO WORDO 252 15 0 X R W STAGE10 SF WORD1 STAGE10 Slow FIFO WORD1 253 15 0 X R W 5 10 SF WORD2 STAGE10 Slow FIFO WORD2 254 15 0 X R W 5 10 SF WORD3 5 10 Slow FIFO WORD3 255 15 0 X R W 5 10 SF WORDA STAGE10 Slow FIFO WORD4 256 15 0 X R W 5 10 SF WORD5 STAGE10 Slow FIFO WORD5 257 15 0 X R W 5 10 SF WORD6 STAGE10 Slow FIFO WORD6 258 15 0 X R W 5 10 SF WORD7 STAGE10 Slow FIFO WORD7 259 15 0 X R W 5 10 SF AMBIENT STAGE10 Slow FIFO Ambient Value 25A 15 0 X R W STAGE10_FF_AVG STAGE10 Fast FIFO Average Value 25B 15 0 X R W STAGE10 CDC WORDO STAGE10 CDC FIFO WORDO 25C 15 0 X R W STAGE10_CDC_WORD1 STAGE10 CDC FIFO WORD1 25D 15 0 X R W STAGE10 MAX WORDO STAGE10 Maximum Value FIFO WORDO 25E 15 0 X R W STAGE10_MAX_WORD1 STAGE10 Maximum Value FIFO WORD1 25F 15 0 X R W STAGE10 MAX WORD2 STAGE10 Maximum Value FIFO WORD2 260 15
10. 08B 15 0 X R W 1 SENSITIVITY STAGE1 Sensitivity Control See Table 56 08C 15 0 X R W STAGE1_OFFSET_LOW STAGE1 Initial Offset Low Value 08D 15 0 X R W STAGE1_OFFSET_HIGH STAGE1 Initial Offset High Value 08E 15 0 X R W STAGE1_OFFSET_HIGH_CLAMP STAGE1 Offset High Clamp Value O8F 15 0 X R W STAGE1_OFFSET_LOW_CLAMP STAGE1 Offset Low Clamp Value Table 31 STAGE2 Configuration Register Map Data Bit Default Address Content Value Type Name Description 090 15 0 X R W 5 2 CIN 0 6 SETUP STAGE2 CIN 0 6 Connection Setup See Table 53 091 15 0 X R W 5 2 7 13 SETUP STAGE2 7 13 Connection Setup See Table 54 092 15 0 X R W STAGE2 AFE OFFSET STAGE2 AFE Offset Control See Table 55 093 15 0 X R W STAGE2_SENSITIVITY STAGE2 Sensitivity Control See Table 56 094 15 0 X R W STAGE2 OFFSET LOW STAGE2 Initial Offset Low Value 095 15 0 X R W STAGE2 OFFSET HIGH STAGE2 Initial Offset High Value 096 15 0 X R W STAGE2_OFFSET_HIGH_CLAMP STAGE2 Offset High Clamp Value 097 15 0 X R W STAGE2 OFFSET LOW CLAMP STAGE2 Offset Low Clamp Value Table 32 STAGE3 Configuration Register Map Data Bit Default Address Content Value Type Name Description 098 15 0 X R W STAGE3_CIN 0 6 _ SETUP STAGE3 CIN 0 6 Connection Setup See Table 53 099 15 0 X R W 5 7 13 SETUP 5 CIN 7 13 Connection Setup See Table 54 09A 15 0 X R W STAGE3 AF
11. 16 H 05702 042 Figure 46 Typical Application Circuit with PC Interface Rev PrD Page 32 of 64 AD7142 AD7142 1 REGISTER MAP The AD7142 address space is divided into three different register banks referred to as Register Bank 1 Register Bank 2 and Register Bank 3 Figure 47 illustrates the division of these three banks Register Bank 1 contains setup and conversion control registers interrupt configuration registers and CDC conversion limit and completion registers Register Bank 1 also contains the 16 bit ADC raw data for all 12 conversion stages and the AD7142 device ID register Register Bank 2 contains the conversion stage configuration registers used for uniquely configuring the CIN inputs for each REGISTER BANK 1 ADDR 0x000 4 ADDR 0x080 ADROO 1 REGISTER ADDR 0x088 CALIBRATION AND SET UP 4 REGISTERS ADDR 0x090 ADDR 0x005 INTERRUPT CONFIGURATION 3 REGISTERS ADDR 0x098 ADDR 0x008 2 REGISTERS ADDR 0x00A CDC CONVERSION COMPLETION ADDR 0x0A8 1 REGISTER ADDR 0x00B CDC 16 BIT CONVERSION DATA ADDR 0x0B0 12 REGISTERS ADDR 0x017 ADDR 0x018 ADDR 0x042 PROXIMITY STATUS REGISTER INVALID DO NOT ACCESS ADDR 0x045 LOW POWER MODE SETTLING TIME REGISTER INVALID DO NOT ACCE ADDR 0x7F0 ener Y 96 REGISTERS ADDR 0x0B8 ADDR 0x0C0 24 REGISTERS _ gt ADDR 0x0C8 ADDR 0x0D0 ADDR 0x0D8 conversion s
12. Data Bit Default Address Content Value Type Name Description 0C8 15 0 X R W 5 9 CIN 0 6 SETUP STAGE CIN 0 6 Connection Setup See Table 53 0C9 15 0 X R W 5 9 CIN 7 13 SETUP STAGE CIN 7 13 Connection Setup See Table 54 OCA 15 0 X R W STAGE9 AFE OFFSET STAGES AFE Offset Control See Table 55 OCB 15 0 X R W STAGE9 SENSITIVITY STAGE9 Sensitivity Control See Table 56 occ 15 0 X R W STAGE9 OFFSET LOW STAGE Initial Offset LOW Value 0CD 15 0 X R W STAGE9 OFFSET HIGH STAGE Initial Offset HIGH Value OCE 15 0 X R W STAGE9 OFFSET HIGH CLAMP STAGE9 Offset High Clamp Value OCF 15 0 X R W STAGE9 OFFSET LOW CLAMP STAGE9 Offset Low Clamp Value Table 39 STAGE10 Configuration Register Map Data Bit Default Address Content Value Type Name Description ODO 15 0 X R W STAGE10_CIN 0 6 _ SETUP STAGE10 CIN 0 6 Connection Setup See Table 53 001 15 0 X R W 5 10 CIN 7 13 SETUP STAGE10 CIN 7 13 Connection Setup See Table 54 002 15 0 X R W STAGE10 AFE OFFSET STAGE10 AFE Offset Control See Table 55 003 15 0 X R W 5 10 SENSITIVITY STAGE10 Sensitivity Control See Table 56 0D4 15 0 X R W STAGE10 OFFSET LOW STAGE10 Initial Offset LOW Value 005 15 0 X R W STAGE10 OFFSET HIGH STAGE10 Initial Offset HIGH Value OD6 15 0 X R W 5 10 OFFSET HIGH CLAMP STAGE10 Offset High Clamp Value 0D7 15 0 X R W 5 10 OFFSET LOW CLAMP STAGE10 Offset Low Clamp Value Table 40 STAGE11 Configuration Register
13. OE8 15 0 X R W STAGEO FF WORD7 STAGEO Fast FIFO WORD7 OE9 15 0 X R W STAGEO SF WORDO STAGEO Slow FIFO WORDO OEA 15 0 X R W STAGEO SF WORD1 STAGEO Slow FIFO WORD1 OEB 15 0 X R W STAGEO SF WORD2 STAGEO Slow FIFO WORD2 OEC 15 0 X R W STAGEO_SF_WORD3 STAGEO Slow FIFO WORD3 OED 15 0 X R W STAGEO_SF_WORD4 STAGEO Slow FIFO WORD4 OEE 15 0 X R W 5 SF WORD5 STAGEO Slow FIFO WORD5 OEF 15 0 X R W STAGEO SF WORD6 STAGEO Slow FIFO WORD6 OFO 15 0 X R W STAGEO SF WORD7 STAGEO Slow FIFO WORD7 OF1 15 0 X R W STAGEO SF AMBIENT STAGEO Slow FIFO Ambient Value OF2 15 0 X R W STAGEO FF AVG STAGEO Fast FIFO Average Value OF3 15 0 X R W STAGEO PEAK DETECT WORDO STAGEO Peak FIFO WORDO Value OF4 15 0 X R W STAGEO PEAK DETECT STAGEO Peak FIFO WORD Value OF5 15 0 X R W STAGEO MAX WORDO STAGEO Maximum Value FIFO WORDO OF6 15 0 X R W STAGEO_MAX_WORD1 STAGEO Maximum Value FIFO WORD1 OF7 15 0 X R W STAGEO MAX WORD2 STAGEO Maximum Value FIFO WORD2 OF8 15 0 X R W STAGEO MAX WORD3 STAGEO Maximum Value FIFO WORD3 OF9 15 0 X R W STAGEO MAX AVG STAGEO Average Maximum FIFO Value OFA 15 0 X R W STAGEO_HIGH_THRESHOLD STAGEO High Threshold Value OFB 15 0 X R W STAGEO MAX TEMP STAGEO Temporary Maximum Value OFC 15 0 X R W STAGEO MIN WORDO STAGEO Minimum Value FIFO WORDO OFD 15 0 X R W STAGEO MIN WORD STAGEO Minimum Value FIFO WORD1 OFE 15 0 X R W STAGEO MIN WORD2 STAGEO Minimum Value FIFO WORD2 OFF 15 0 X R W 5 MIN
14. TEMP STAGE3 Temporary Minimum Value 16F 15 0 X R W Unused Rev PrD Page 50 of 64 Table 45 STAGEA Results Register Map AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 170 15 0 X R W STAGE4_CONV_DATA STAGE4 CDC 16 Bit Conversion Data Copy of data in STAGE4_CONV_DATA register 171 15 0 X R W 5 4 FF WORDO STAGEA Fast FIFO WORDO 172 15 0 X R W STAGE4_FF_WORD1 STAGE4 Fast FIFO WORD1 173 15 0 X R W STAGE4_FF_WORD2 STAGE4 Fast FIFO WORD2 174 15 0 X R W STAGE4_FF_WORD3 STAGE4 Fast FIFO WORD3 175 15 0 X R W STAGE4_FF_WORD4 STAGE4 Fast FIFO WORD4 176 15 0 X R W STAGE4_FF_WORD5 STAGE4 Fast FIFO WORD5 177 15 0 X R W STAGE4_FF_WORD6 STAGE4 Fast FIFO WORD6 178 15 0 X R W STAGE4_FF_WORD7 STAGE4 Fast FIFO WORD7 179 15 0 X R W STAGE4_SF_WORDO STAGE4 Slow FIFO WORDO 17A 15 0 X R W STAGE4_SF_WORD1 STAGE4 Slow FIFO WORD1 17B 15 0 X R W STAGE4_SF_WORD2 STAGE4 Slow FIFO WORD2 17C 15 0 X R W STAGE4_SF_WORD3 STAGE4 Slow FIFO WORD3 17D 15 0 X R W STAGE4_SF_WORD4 STAGE4 Slow FIFO WORD4 17E 15 0 X R W STAGE4_SF_WORD5 STAGE4 Slow FIFO WORD5 17F 15 0 X R W STAGE4_SF_WORD6 STAGE4 Slow FIFO WORD6 180 15 0 X R W STAGE4_SF_WORD7 STAGE4 Slow FIFO WORD7 181 15 0 X R W STAGE4_SF_AMBIENT STAGE4 Slow FIFO Ambient Value 182 15 0 X R W STAGE4_FF_AVG STAGE4 Fast FIFO Average Value 183 15 0 X R W STAGE4_CDC_WORDO STAGE4 CDC FIFO WORDO 184 15 0 X R W STAGE4_CDC_WORD1 S
15. skip 15 samples 11 skip 31 samples 15 14 0 AVG LP SKIP Low Power Mode Skip Control 00 use all samples 01 skip 1 sample 10 skip 2 samples 11 skip 3 samples Rev PrD Page 35 of 64 AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 002 3 0 0 R W FF_SKIP_CNT Fast Filter Skip Control N 1 0000 1 conversion skipped in each stage 0001 2 conversions skipped in each stage 1011 max value 12 conversions skipped in each stage 7 4 F FP_PROXIMITY_CNT Full Power Mode Proximity Period 11 8 F LP PROXIMITY CNT Low Power Mode Proximity Period 13 12 PWR DOWN TIMEOUT Power Down Time Out Control 00 2 1 25 x LP PROXIMITY CNT 0121 50 x LP PROXIMITY CNT 10 1 75 x LP PROXIMITY 11 2 00 x LP PROXIMITY 14 0 FORCED CAL Forced Calibration Control 0 normal operation 1 forces all conversion stages to recalibrate 15 0 CONV RESET Conversion Reset Control Self Clearing 0 normal operation 1 resets the conversion sequence back to STAGEO 003 7 0 64 R W PROXIMITY RECAL LVL Proximity Recalibration Level 13 8 1 PROXIMITY DETECTION RATE Proximity Detection Rate 15 14 0 SLOW FILTER UPDATE LVL Slow Filter Update Level 004 9 0 3FF R W PROXIMITY RECAL Full Power Mode Proximity Recalibration Time Control 15 10 3F LP PROXIMITY RECAL Low Power Mode Proximity Recalibration Time Control Tab
16. while the transmitter and receiver are constructed on a PCB that makes up the external sensor Registering a Sensor Activation When a sensor is approached the total capacitance associated with that sensor measured by the AD7142 changes When the capacitance changes to such an extent that a set threshold is exceeded the AD7142 registers this as a sensor touch For example consider the case of two button sensors that are connected to the AD7142 in a differential manner When one button is activated the AD7142 registers an increase in capacitance ifthe other button is activated the AD7142 registers a decrease in capacitance If neither of the buttons are activated the AD7142 measures the background or ambient capacitance level Rev PrD Page 9 of 64 AD7142 AD7142 1 Preprogrammed threshold levels are used to determine if a change in capacitance is due to a button being activated If the capacitance exceeds one of the threshold limits the AD7142 registers this as a true button activation The same thresholds principle is used to determine if other types of sensors such as sliders or joypads are activated Complete Solution for Capacitance Sensing Analog Devices provides a complete solution for capacitance sensing The two main elements to the solution are the sensor PCB and the AD7142 If the application requires sensors in the shape of a slider or joypad software is required that runs on the host processor No so
17. 0A9 15 0 X R W 5 5 CIN 7 13 SETUP STAGES CIN 7 13 Connection Setup See Table 54 15 0 X R W 5 5 AFE OFFSET STAGES AFE Offset Control See Table 55 OAB 15 0 X R W STAGE5 SENSITIVITY STAGES Sensitivity Control See Table 56 OAC 15 0 X R W STAGE5 OFFSET LOW STAGES Initial Offset Low Value OAD 15 0 X R W STAGE5_OFFSET_HIGH STAGES Initial Offset High Value OAE 15 0 X R W STAGE5_OFFSET_HIGH_CLAMP STAGES Offset High Clamp Value OAF 15 0 X R W STAGE5 OFFSET LOW CLAMP STAGES Offset Low Clamp Value Table 35 STAGE6 Configuration Register Map Data Bit Default Address Content Value Type Name Description OBO 15 0 X R W STAGE6_CIN 0 6 _ SETUP STAGE6 CIN 0 6 Connection Setup See Table 53 0B1 15 0 X R W STAGE6_CIN 7 13 _ SETUP STAGE6 CIN 7 13 Connection Setup See Table 54 0B2 15 0 X R W 5 6 AFE OFFSET STAGE6 AFE Offset Control See Table 55 0B3 15 0 X R W 5 6 SENSITIVITY STAGE6 Sensitivity Control See Table 56 0B4 15 0 X R W OFFSET LOW 5 Initial Offset Low Value 0 5 15 0 X R W STAGE6_OFFSET_HIGH STAGE6 Initial Offset High Value OB6 15 0 X R W STAGE6 OFFSET HIGH CLAMP STAGE6 Offset High Clamp Value 0B7 15 0 X R W 5 OFFSET LOW CLAMP STAGE6 Offset Low Clamp Value Table 36 STAGE7 Configuration Register Map Data Bit Default Address Content Value Type Name Description OB8 15 0 X R W STAGE7 CIN 0 6 SETUP STAGE7 CIN 0 6 Con
18. 1 BIT FOR R W AND 10 BITS FOR REGISTER ADDRESS THE REGISTER DATA WILL BE READ BACK ON THE SDO PIN X DENOTES DON T CARE XXX DENOTES HIGH IMPEDANCE TRISTATE OUTPUT CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK 16 BIT COMMAND WORD SETTINGS FOR SINGLE READ BACK OPERATION CW 15 11 11100 ENABLE WORD CW 10 1 RW CW 9 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO 10 MSB JUSTIFIED REGISTER ADDRESS NOoahowond 05702 035 Figure 36 Single Register Readback SPI Timing Reading Data The AD7142 continues to clock out data on the SDO line A read transaction begins when the master writes the command provided the master continues to supply the clock signal on word to the AD7142 with the read write bit set to 1 The master SCLK The read transaction finishes when the master takes then supplies 16 clock pulses per data word to be read and the CS high If the AD7142 address pointer reaches its maximum AD7142 clocks out data from the addressed register on the SDO value then the AD7142 repeatedly clocks out data from the line The first data word is clocked out on the first falling edge addressed register The address pointer does not wrap around of CS following the command word as shown in Figure 36 Rev PrD Page 26 of 64 AD7142 AD7142 1 m 16 BIT COMMAND WORD ENABLE WORD 1 REGISTER ADDRESS I E0060 6 GO 6980069 X86 88999 GC SCLK h al E
19. 10 0 R W CW 9 0 AD9 AD8 AD7 AD6 AD5 AD4 AD2 AD1 ADO 10 BIT MSB JUSTIFIED REGISTER ADDRESS 05702 033 Figure 34 Single Register Write SPI Timing Rev PrD Page 25 of 64 AD7142 AD7142 1 16 BIT COMMAND WORD ES y ENABLE WORD i RW STARTING REGISTER ADDRESS REGISTER ADDRESS REGISTER ADDRESS x s OOO DATA FOR STARTING DATA FOR NEXT SCLK 1 2 3 ALIS 6 7 8 9 ol 11 12 hsl hal hsi hel hzL s2 33 48 NOTES MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY THE FIRST LOWEST ADDRESS REGISTER ADDRESS IS WRITTEN FOLLOWED BY MULTIPLE 16 BIT DATA WORDS THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 16 BIT DATA WORD ALL 16 BITS MUST BE WRITTEN C8 IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED 16 BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION CW 15 11 11100 ENABLE WORD CW 10 0 R W CW 9 0 AD9 08 AD7 AD6 AD5 AD4 AD2 AD1 ADO STARTING MSB JUSTIFIED REGISTER ADDRESS 05702 034 Figure 35 Sequential Register Write SPI Timing 16 COMMAND WORD ENABLE WORD R W REGISTER ADDRESS DDD DDD DOOD t E 669696696 Qe 16 BIT READ BACK DATA NOTES 1 SDI BITS ARE LATCHED ON SCLK RISING EDGES SCLK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS THE 16 BIT CONTROL WORD MUST BE WRITTEN ON SDI 5 BITS FOR ENABLE WORD
20. 1C6 15 0 X R W SF WORD5 STAGE6 Slow FIFO WORD5 1C7 15 0 X R W STAGE6 SF WORD6 STAGE6 Slow FIFO WORD6 1C8 15 0 X R W STAGE6 SF WORD7 STAGE6 Slow FIFO WORD7 1C9 15 0 X R W 5 6 SF AMBIENT STAGE6 Slow FIFO Ambient Value 1CA 15 0 X R W STAGE6 FF AVG STAGE6 Fast FIFO Average Value 1CB 15 0 X R W STAGE6 CDC WORDO STAGEO CDC FIFO WORDO 1 15 0 X R W STAGE6 CDC WORD1 STAGE6 CDC FIFO WORD1 1CD 15 0 X R W STAGE6 MAX WORDO STAGE6 Maximum Value FIFO WORDO 1CE 15 0 X R W 5 6 MAX WORD STAGE6 Maximum Value FIFO WORD1 1CF 15 0 X R W STAGE6 MAX WORD2 STAGE6 Maximum Value FIFO WORD2 1DO 15 0 X R W STAGE6_MAX_WORD3 STAGE6 Maximum Value FIFO WORD3 1D1 15 0 X R W STAGE6 MAX AVG STAGE6 Average Maximum FIFO Value 1D2 15 0 X R W STAGE6_HIGH_THRESHOLD STAGE6 High Threshold Value 1D3 15 0 X R W STAGE6_MAX_TEMP STAGE6 Temporary Maximum Value 1D4 15 0 X R W STAGE6 MIN WORDO STAGE6 Minimum Value FIFO WORDO 1D5 15 0 X R W STAGE6 MIN WORD STAGE6 Minimum Value FIFO WORD1 1D6 15 0 X R W STAGE6 MIN WORD2 STAGE6 Minimum Value FIFO WORD2 1D7 15 0 X R W 5 6 MIN WORD3 STAGE6 Minimum Value FIFO WORD3 1D8 15 0 X R W STAGE6 MIN AVG STAGE6 Average Minimum FIFO Value 1D9 15 0 X R W STAGE6 LOW THRESHOLD STAGE6 Low Threshold Value 1DA 15 0 X R W STAGE6 MIN TEMP STAGE6 Temporary Minimum Value 1DB 15 0 X R W Unused Rev PrD Page 53 of 64 AD7142 AD7142 1 Table 48 STAGE7 Results Register
21. around the sensors on both layers of the PCB Figure 33 shows how the sensor traces are shielded by running traces connected to the shield potential around the sensor traces t o 2 o 05702 032 Figure 33 Shielding the Sensor Traces GPIO The AD7142 has one GPIO pin Pin 26 It can be configured as an input or an output The GPIO SETUP bits in the interrupt configuration register determine how the GPIO pin is configured Table 12 GPIO SETUP Bits GPIO SETUP GPIO Configuration 00 GPIO disabled 01 Input 10 Output low 11 Output high When the GPIO is configured as an output the voltage level on the pin is set to either a low level or a high level as defined by the GPIO SETUP bits shown in Table 12 When the GPIO is configured as an input the GPIO INPUT CONFIGURATON bits in the interrupt configuration register determine the response of the AD7142 to a signal on the GPIO pin The GPIO can be configured as either active high or active low as well as either edge triggered or level triggered as listed in Table 13 Table 13 GPIO INPUT CONFIGURATION Bits GPIO INPUT CONFIGURATION GPIO Configuration 00 Triggered on negative level active low 01 Triggered on positive edge active high 10 Triggered on negative edge active low 11 Triggered on positive level active high When GPIO is configured as an input it triggers the interrupt output on the AD7142
22. fel al fiol al fa E Ed ial al 5 m E il Me m feel ks ue I cs SD o NOTES 1 MULTIPLE REGISTERS MAY BE READ BACK CONTINUOUSLY 6969606369699 63696969669 696996969 6X 1 l READ BACK DATA FOR 1 READ BACK DATA FOR STARTING REGISTER ADDRESS NEXT REGISTER ADDRESS 2 THE 16 BIT CONTROL WORD MUST BE WRITTEN ON SDI 5 BITS FOR ENABLE WORD 1 BIT FOR R W AND 10 BITS FOR REGISTER ADDRESS 3 THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 16 BIT DATA WORD BEING READ BACK ON THE SDO PIN 4 CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK 5 X DENOTES DON T CARE 6 XXX DENOTES HIGH IMPEDANCE TRISTATE OUTPUT 7 16 BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READ BACK OPERATION CW 15 11 11100 ENABLE WORD CW 10 1 R W 05702 036 CW 9 0 9 AD8 07 AD6 AD5 AD4 AD2 AD1 ADO STARTING MSB JUSTIFIED REGISTER ADDRESS Figure 37 Sequential Register Readback SPI Timing PC INTERFACE The AD7142 1 supports the JEDEC industry standard 2 wire serial interface protocol The two wires associated with the timing are the SCLK and the SDA inputs The SDA is an I O pin that allows both register write and register readback operations The AD7142 1 is always a slave device on the PC serial interface bus It has a 7 bit device address Address 0101 1XX The lower two bits are set by tying the Add0 and Add1 pins hi
23. of 64 AD7142 AD7142 1 INTERRUPT OUTPUT The AD7142 has an interrupt output that triggers an interrupt service routine on the host processor The INT signal is on Pin 25 and is an open drain output There are three types of interrupt events on the AD7142 a CDC conversion complete interrupt a sensor threshold interrupt and a GPIO interrupt Each interrupt has enable and status registers The conversion complete and sensor threshold interrupts can be enabled on per conversion stage basis The status registers indicate what type of interrupt triggered the INT pin Status registers are cleared and the INT signal is reset high during a read operation The signal returns high as soon as the read address has been set up CDC CONVERSION COMPLETE INTERRUPT The AD7142 interrupt signal asserts low to indicate the completion of a conversion stage and new conversion result data is available in the registers The interrupt can be independently enabled for each conversion stage Each conversion stage complete interrupt can be enabled via the CDC Conversion Completion register Address 0x007 This register has a bit that corresponds to each conversion stage Setting this bit to 1 enables the interrupt for that stage Clearing this bit to 0 disables the conversion complete interrupt for that stage In normal operation the AD7142 is set up to interrupt enable the last stage only in a conversion sequence For example if there are five con
24. the CDC is defined as the CDC conversion time For optimal system per formance configure the AD7142 CDC conversion time within a range of 35 ms to 40 ms The SEQUENCE STAGE NUM FF 5 CNT and DECIMATION registers determine the conversion time as listed in Table 8 Rev PrD Page 13 of 64 AD7142 AD7142 1 Table 8 CDC Conversion Times for Full Power Mode DECIMATION 64 DECIMATION 128 DECIMATION 256 CDC Conversion CDC Conversion CDC Conversion SEQUENCE STAGE NUM FF_SKIP_CNT Time ms FF_SKIP_CNT Time ms FF_SKIP_CNT Time ms 0 11 9 2 11 18 4 11 36 5 1 11 18 4 11 36 8 5 36 5 2 11 27 6 7 36 8 3 36 5 3 11 36 8 5 36 8 2 36 5 4 9 38 4 4 38 4 2 46 0 5 7 36 8 3 36 8 1 36 8 6 6 37 6 2 32 2 1 43 0 7 5 36 8 2 36 8 1 49 1 8 4 34 5 2 41 4 0 27 6 9 4 38 4 1 30 7 0 30 7 10 3 33 8 1 33 8 0 33 7 11 3 36 8 1 36 8 0 36 8 For example while operating with a decimation rate of 128 if the SEQUENCE_STAGE_NUM register is set to 5 for the conversion of six stages in a sequence the FF_SKIP_CNT register should be set to 3 resulting in a conversion time of 36 8 ms This example is shown in Figure 14 Determining the FF_SKIP_CNT value is only required one time during the initial setup of the capacitance sensor interface This value determines which CDC samples are not used skipped in the proximity detection fast FIFO Full Power Mode CDC Conversion Time The full power mode CDC conversion time i
25. to account for changes in the ambient environment The calibration sequence is performed automatically and at continuous intervals while the sensors are not touched This ensures that there are no false or nonregistering touches on the external sensors due to a changing environment The AD7142 has an SPI compatible serial interface and the AD7142 1 has an PC compatible serial interface Both versions of AD7142 have an interrupt output as well as a general purpose input output GPIO The AD7142 and AD7142 1 are available in a 32 lead 5 mm x 5 mm LFCSP package and operate from a 2 7 V to 3 3 V supply The operating current consumption is less than 1 mA falling to 50 uA in low power mode conversion interval of 400 ms One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved AD7142 AD7142 1 TABLE OF CONTENTS Features cete uku eI EET REI 1 AP PLICALIONS rto em IHRER ER Reges 1 Functional Block Diagram sse 1 General Descriptio pnr r pE 1 REVISION OPY E 2 SPECI CATIONS e 3 SPI Timing Specifications AD7 142 4 PC Timing Specifications AD7142 1 sse 5 Absolute Maximum Ratings 000 6 ESD Cautions 6 Pin Configuration and Functional Descriptions 7 Typical Performance Characteristics sse 8
26. 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded 8 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded STAGE9 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded STAGE10 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded STAGE11 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded GPIO Setup 00 disable GPIO pin 01 configure GPIO as an input 10 2 configure GPIO as an active low output 11 2 configure GPIO as an active high output GPIO Input Configuration 00 triggered on negative level 01 triggered on positive edge 10 triggered on negative edge 11 triggered on positive level 006 0 1 2 3 4 5 6 7 R W STAGEO_HIGH_INT_EN STAGE1_HIGH_INT_EN STAGE2_HIGH_INT_EN STAGE3_HIGH_INT_EN STAGE4_HIGH_INT_EN STAGE5_HIGH_INT_EN STAGE6_HIGH_INT_EN STAGE7_HIGH_INT_EN STAGEO High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded STAGE1 High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded STAGE2 High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceed
27. 0 X R W STAGE10 MAX WORD3 STAGE10 Maximum Value FIFO WORD3 261 15 0 X R W STAGE10 MAX AVG STAGE10 Average Maximum FIFO Value 262 15 0 X R W STAGE10_HIGH_THRESHOLD STAGE10 High Threshold Value 263 15 0 X R W STAGE10_MAX_TEMP STAGE10 Temporary Maximum Value 264 15 0 X R W STAGE10_MIN_WORDO STAGE10 Minimum Value FIFO WORDO 265 15 0 X R W 5 10 MIN WORD1 STAGE10 Minimum Value FIFO WORD1 266 15 0 X R W STAGE10 MIN WORD2 STAGE10 Minimum Value FIFO WORD2 267 15 0 X R W STAGE10 MIN WORD3 STAGE10 Minimum Value FIFO WORD3 268 15 0 X R W 5 10 MIN STAGE10 Average Minimum FIFO Value 269 15 0 X R W STAGE10 LOW THRESHOLD STAGE10 Low Threshold Value 26A 15 0 X R W 5 10 MIN TEMP STAGE10 Temporary Minimum Value 26B 15 0 X R W Unused Rev PrD Page 57 of 64 AD7142 AD7142 1 Table 52 STAGE11 Results Register Map Data Bit Default Address Content Value Type Name Description 26C 15 0 X RW STAGE11 CONV DATA STAGE11 CDC 16 Bit Conversion Data Copy of data in STAGE11 CONV DATA register 26D 15 0 X R W 5 11 FF WORDO STAGE11 Fast FIFO WORDO 26E 15 0 X R W 5 11 FF WORD1 STAGE11 Fast FIFO WORD1 26F 15 0 X R W STAGE11_FF_WORD2 STAGE11 Fast FIFO WORD2 270 15 0 X R W STAGE11_FF_WORD3 STAGE11 Fast FIFO WORD3 271 15 0 X R W STAGE11_FF_WORD4 STAGE11 Fast FIFO WORD4 272 15 0 X R W STAGE11_FF_WORD5 STAGE11 Fast FIFO WORD5 273 15 0 X R W STAGE11_FF_WORD6 STAGE11 Fas
28. 0 X R W STAGE1_SF_AMBIENT STAGE1 Slow FIFO Ambient Value 116 15 0 X R W STAGE1 FF AVG STAGE Fast FIFO Average Value 117 15 0 X R W STAGE1_CDC_WORDO STAGE1 CDC FIFO WORDO 118 15 0 X R W STAGE1_CDC_WORD1 STAGE1 CDC FIFO WORD1 119 15 0 X R W STAGE1 MAX WORDO STAGE1 Maximum Value FIFO WORDO 11A 15 0 X R W STAGE1 MAX WORD STAGE1 Maximum Value FIFO WORD1 11B 15 0 X R W STAGE1 MAX WORD2 STAGE1 Maximum Value FIFO WORD2 11C 15 0 X R W STAGE1_MAX_WORD3 STAGE1 Maximum Value FIFO WORD3 11D 15 0 X R W STAGE1_MAX_AVG STAGE1 Average Maximum FIFO Value 11E 15 0 X R W STAGE1_HIGH_THRESHOLD STAGE1 High Threshold Value 11F 15 0 X R W STAGE1_MAX_TEMP STAGE1 Temporary Maximum Value 120 15 0 X R W STAGE1_MIN_WORDO STAGE1 Minimum Value FIFO WORDO 121 15 0 X R W STAGE1 MIN WORD STAGE1 Minimum Value FIFO WORD1 122 15 0 X R W 5 1 MIN WORD2 STAGE1 Minimum Value FIFO WORD2 123 15 0 X R W 5 1 MIN WORD3 STAGE1 Minimum Value FIFO WORD3 124 15 0 X R W 5 1 MIN AVG STAGE1 Average Minimum FIFO Value 125 15 0 X R W STAGE1 LOW THRESHOLD STAGE1 Low Threshold Value 126 15 0 X R W STAGE1 MIN TEMP STAGE1 Temporary Minimum Value 127 15 0 X R W Unused Rev PrD Page 48 of 64 Table 43 STAGE2 Results Register Map AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 128 15 0 X RW 5 2 CONV DATA STAGE2 CDC 16 Bit Conversion Data Copy of data in STAGE2 CONV DA
29. 0 X R W STAGE8_FF_WORD6 STAGES Fast FIFO WORD6 208 15 0 X R W STAGE8_FF_WORD7 STAGES Fast FIFO WORD7 209 15 0 X R W STAGE8 SF WORDO STAGES Slow FIFO WORDO 20A 15 0 X R W STAGE8_SF_WORD1 STAGE8 Slow FIFO WORD1 20B 15 0 X R W STAGE8_SF_WORD2 STAGE8 Slow FIFO WORD2 20C 15 0 X R W STAGE8_SF_WORD3 STAGES Slow FIFO WORD3 20D 15 0 X R W STAGE8_SF_WORD4 STAGE8 Slow FIFO WORD4 20E 15 0 X R W STAGE8_SF_WORD5 STAGE8 Slow FIFO WORD5 20F 15 0 X R W STAGE8_SF_WORD6 STAGE8 Slow FIFO WORD6 210 15 0 X R W STAGE8_SF_WORD7 STAGE8 Slow FIFO WORD7 211 15 0 X R W STAGE8_SF_AMBIENT STAGE8 Slow FIFO Ambient Value 212 15 0 X R W STAGE8_FF_AVG STAGE8 Fast FIFO Average Value 213 15 0 X R W STAGE8_CDC_WORDO STAGE8 CDC FIFO WORDO 214 15 0 X R W STAGE8_CDC_WORD1 STAGE8 CDC FIFO WORD1 215 15 0 X R W STAGE8 MAX WORDO STAGE8 Maximum Value FIFO WORDO 216 15 0 X R W STAGE8_MAX_WORD1 STAGE8 Maximum Value FIFO WORD1 217 15 0 X R W STAGE8 MAX WORD2 STAGE8 Maximum Value FIFO WORD2 218 15 0 X R W STAGE8 MAX WORD3 STAGE8 Maximum Value FIFO WORD3 219 15 0 X R W STAGE8 MAX AVG STAGE8 Average Maximum FIFO Value 21A 15 0 X R W STAGE8 HIGH THRESHOLD STAGES High Threshold Value 21B 15 0 X R W STAGE8 MAX TEMP STAGE8 Temporary Maximum Value 21C 15 0 X R W STAGE8 MIN WORDO STAGE8 Minimum Value FIFO WORDO 21D 15 0 X R W STAGE8 MIN WORD STAGE8 Minimum Value FIFO WORD1 21E 15 0 X R W 5 8 MIN WORD2 STAGE8 Minimum Value FIFO WORD2 21F 15 0 X R W 5
30. 0 R STAGE3 PROXIMITY STATUS STAGE3 Proximity Status Register 1 indicates proximity has been detected on STAGE3 4 0 R STAGE4 PROXIMITY STATUS STAGE4 Proximity Status Register 1 indicates proximity has been detected on STAGE4 5 0 R STAGES PROXIMITY STATUS STAGES Proximity Status Register 1 indicates proximity has been detected on STAGES 6 0 R STAGE6 PROXIMITY STATUS STAGE6 Proximity Status Register 1 indicates proximity has been detected on STAGE6 7 0 R STAGE7 PROXIMITY STATUS STAGE7 Proximity Status Register 1 indicates proximity has been detected on STAGE7 8 0 R STAGE8 PROXIMITY STATUS STAGES Proximity Status Register 1 indicates proximity has been detected on STAGE8 9 0 R STAGE9 PROXIMITY STATUS STAGE9 Proximity Status Register 1 indicates proximity has been detected on STAGE9 10 0 R STAGE10 PROXIMITY STATUS STAGE10 Proximity Status Register 1 indicates proximity has been detected on STAGE10 11 0 R 5 11 PROXIMITY STATUS STAGE11 Proximity Status Register 1 indicates proximity has been detected on STAGE11 15 0 Unused Set Unused Register Bits 0 Rev PrD Page 42 of 64 AD7142 AD7142 1 Table 28 Low Power Mode Settling Time Register Data Bit Default Address Content Value Type Name Description 045 1 0 0x3 R W Unused test bits Set Unused Register Bits 11 Binary Note that these bits always read back as 01 binary 14 2 0x240 R W Unused test bits Set Unused Register Bit
31. 00 ARE ALWAYS SEPERATED BY A LOW ACK BIT 05702 037 Figure 38 Example of PC Timing for Single Register Write Operation Writing Data over the PC Bus The process for writing to the AD7142 1 over the bus is shown in Figure 38 and Figure 40 The device address is sent over the bus followed by the R W bit set to 0 This is followed by two bytes of data that contain the 10 bit address of the internal data register to be written The upper and lower register address bytes are shown in Table 16 Note that Bit 7 to Bit 2 in the upper address byte are don t cares The address is contained in the 10 LSBs of the register address bytes Table 16 AD7142 1 Internal Register IC Addressing Register Address Upper Byte Any data written to the AD7142 1 after the address pointer has reached its maximum value is discarded All registers on the AD7142 1 are 16 bit Two consecutive 8 bit data bytes are combined and written to the 16 bit registers To avoid errors all writes to the device must contain an even number of data bytes To finish the transaction the master generates a stop condition on SDO or generates a repeat start condition if the master is to maintain control of the bus Reading Data over the C Bus To read from the AD7142 1 the address pointer must first be 7 6 5 4 3 2 1 0 X X X X X X Register Register Address Address Bit 9 Bit 8 set to the address of the required internal register Th
32. 2 019 Figure 20 Full Power Mode Proximity Detection with Forced Recalibration Example with FP PROXIMITY 1 and FP PROXIMITY RECAL 40 Rev PrD Page 16 of 64 AD7142 AD7142 1 USER APPROCHES USER LEAVES SENSOR SENSOR HERE AREA HERE Y CDC CONVERSION VALUES EXCEED USER IN CONTACT WITH SENSOR PROXIMITY RECALIBRATION LVL CDC CONVERSIONS TERNAL EEE RE torsca PROXIMITY DETECTION INTERNAL CC INTERNAL CALIBRATION DISABLED RECALIBRATION PERIOD X CALIBRATION ENABLED RECALIBRATION 4 itaca INTERNAL E Cee NOTES 1 CONVERSION TIME tconv_Hp LP_CONV_DELAY 2 tpiscaL tconv_tp x 16 x LP_PROXIMITY_CNT 3 treca x LP PROXIMITY RECAL x 4 05702 020 Figure 21 Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMITY 4 and LP PROXIMITY RECAL 10 Rev PrD Page 17 of 64 AD7142 AD7142 1 STAGE_MAX_WORDO STAGE_MAX_WORD1 STAGE_MAX_WORD2 STAGE_MAX_WORD3 BANK 3 REGISTERS X A 1 chor MAX LEVEL STAGE_MAX_AVG DETECTION BANK 3 REGISTERS LOGIC STAGE MAX TEMP BANK 3 REGISTERS STAGE HIGH THRESHOLD BANK 3 REGISTERS STAGE MIN WORDO STAGE MIN WORD1 STAGE MIN WORD2 STAGE MIN WORD3 BANK 3 REGISTERS MIN LEVEL STAGE MIN AVG DETECTION BANK 3 REGISTER3 LOGIC STAGE MIN TEMP CONTROL BANK 3 REGISTERS ad S
33. 7142 AD7142 1 CONVERSIONS STAGE 0 X STAGE 1 X STAGE 2 X STAGE X STAGE 4 X STAGE 5 X STAGE 6 X STAGE 7 X STAGE 8 K STAGE 9 X STAGE 10 X STAGE 11 1 3 2 4 SERIAL READS NOTES THIS EXAMPLE ASSUMES THAT SENSOR CONTACT FOR STAGEO EXCEEDED THE HIGH THRESHOLD LIMIT THIS EXAMPLE ASSUMES THAT SENSOR CONTACT FOR STAGE9 EXCEEDED THE LOW THRESHOLD LIMIT PROGRAMMING NOTES 1 STAGEO SENSOR HIGH INT 1 STAGEO SENSOR LOW INT STAGEO CONVERSION INT 0 2 READ BACK FROM STAGEO HIGH LIMIT REGISTER TO RESET INT OUTPUT 3 STAGE9 SENSOR HIGH INT 0 STAGES SENSOR LOW INT 1 STAGE5 CONVERSION INT 0 4 READ BACK FROM STAGEO LOW LIMIT REGISTER TO RESET INT OUTPUT 05702 027 STAGEx SENSOR HIGH INT STAGEx SENSOR LOW INT STAGEx CONVERSION INT 0 FOR ALL STAGES HIGHLIGHTED IN GRAY Figure 28 Example of Configuring the Registers for Sensor Interrupt Set Up Table 11 GPIO Interrupt Behavior GPIO INPUT CONFIG GPIO Pin GPIO STATUS INT INT Behavior 00 negative level triggered 1 0 1 Not triggered 00 negative level triggered 0 1 0 Asserted while signal on GPIO pin is low 01 positive edge triggered 1 1 0 Pulses low at low to high GPIO transition 01 positive edge triggered 0 0 1 Not triggered 10 negative edge triggered 1 0 1 Pulses low at high to low GPIO transition 10 negative edge triggered 0 1 0 Not triggered 11 positive level triggered 1 1 0 Asser
34. 7142EB 0 C to 85 C SPI Interface Evaluation Board Eval AD7142EB 1 0 C to 85 C Interface Evaluation Board 1Z Pb free part Rev PrD Page 62 of 64 AD7142 AD7142 1 NOTES Rev PrD Page 63 of 64 AD7142 AD7142 1 NOTES 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners PR05702 0 12 05 PrD DEVICES www analog com Rev PrD Page 64 of 64 WWW ZFA CN 23 MN PR Ph C WWW Zfa cm CA WALA PAK 710 1 041662 gl XA 26 XYI 0755 83278916 83278919 010 62632888 62636888 WWW ZFA CN 23 MN PR Ph C WWW Zfa cm CA WALA PAK 710 1 041662 gl XA 26 XYI 0755 83278916 83278919 010 62632888 62636888
35. AD7142 1 Serial Data Input Output SDA requires pull up resistor 22 SDI AD7142 SPI Serial Data Input ADDO AD7142 1 lC Address Bit 0 23 SCLK Clock Input for Serial Interface 24 cs AD7142 SPI Chip Select Signal ADD1 AD7142 1 12 Address Bit 1 25 INT General Purpose Interrupt Output Programmable polarity Requires pull up resistor 26 GPIO Programmable GPIO 27 TEST Factory Test Pin Tie to ground 28 Positive Reference Input Normally tied to analog power 29 VREF CDC Negative Reference Input Tie to analog ground 30 CINO Capacitance Sensor Input 31 CIN1 Capacitance Sensor Input 32 CIN2 Capacitance Sensor Input Rev PrD Page 7 of 64 AD7142 AD7142 1 TYPICAL PERFORMANCE CHARACTERISTICS Figure 7 Supply Current vs AVpp Rev PrD Page 8 of 64 AD7142 AD7142 1 THEORY OF OPERATION The AD7142 and AD7142 1 are capacitance to digital converters CDCs with on chip environmental compensation intended for use in portable systems requiring high resolution user input The internal circuitry consists of a 16 bit X A con verter that converts a capacitive input signal into a digital value There are 14 input pins on the AD7142 and AD7142 1 CINO to CIN 13 A switch matrix routes the input signals to the CDC The result of each capacitance to digital conversion is stored in on chip registers The host subsequently reads the results over the serial interface The AD7142 contains an SPI int
36. BIT IS SET TO A 1 TO INDICATE A READBACK OPERATION 1 2 3 4 5 6 7 8 WRITE 05702 038 Figure 39 Example of PC Timing for Single Register Readback Operation 6 BIT DEVICE REGISTER ADDR REGISTER ADDR WRITE DATA WRITE DATA WRITEDATA WRITEDATA ADDRESS lt 15 8 lt 7 0 HIGH BYTE 15 8 lt LOW BYTE 7 0 HIGH BYTE 15 8 LOW BYTE 7 0 6 READ USING REPEATED START 6 BIT DEVICE REGISTER ADDR 5 REGISTER ADDR 5 6 BIT DEVICE 5 READ DATA 5 READDATA READ DATA READ DATA ADDRESS HIGH BYTE lt LOW BYTE lt ADDRESS lt HIGH BYTE 15 8 lt LOW BYTE 7 0 HIGH BYTE 15 8 lt LOW BYTE 7 READ WRITE TRANSACITON SETS UP REGISTER ADDRESS NACK 6 BIT DEVICE REGISTER ADDR lt REGISTER ADDR 6 BITDEVICE 4 READDATA x READDATA READDATA READDATA ack ADDRESS lt HIGH BYTE LOWBYTE lt ADDRESS lt HIGH BYTE 15 8 lt LOW BYTE 7 0 HIGH BYTE 15 8 lt LOW BYTE 7 0 OUTPUT FROM MASTER S START BIT ACK ACKNOWLEDGE BIT 8 P STOP BIT NACK ACKNOWLEDGE BIT 8 OUTPUT FROM AD7142 SR REPEATED START BIT 5 Figure 40 Example of Sequential Write Readback Operation INPUT This allows the AD7142 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the AD7142 without the need for external level shifters The pin be conne
37. E OFFSET STAGE3 AFE Offset Control See Table 55 09B 15 0 X R W STAGE3 SENSITIVITY STAGE3 Sensitivity Control See Table 56 09C 15 0 X R W STAGE3 OFFSET LOW STAGE3 Initial Offset Low Value 09D 15 0 X R W STAGE3 OFFSET HIGH STAGE3 Initial Offset High Value 09 15 0 X R W STAGE3 OFFSET HIGH CLAMP STAGE3 Offset High Clamp Value 09F 15 0 X R W STAGE3 OFFSET LOW CLAMP STAGE3 Offset Low Clamp Value Rev PrD Page 44 of 64 Table 33 STAGE4 Configuration Register Map AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 0 0 15 0 X R W STAGE4_CIN 0 6 _ SETUP STAGE4 CIN 0 6 Connection Setup See Table 53 0A1 15 0 X R W STAGE4_CIN 7 13 _ SETUP STAGE4 CIN 7 13 Connection Setup See Table 54 0A2 15 0 X R W 5 4 AFE OFFSET STAGEA AFE Offset Control See Table 55 0A3 15 0 X R W STAGE4_ SENSITIVITY STAGEA Sensitivity Control See Table 56 0A4 15 0 X R W STAGEA OFFSET LOW STAGEA Initial Offset Low Value 0A5 15 0 X R W 5 4 OFFSET HIGH STAGEA Initial Offset High Value 0A6 15 0 X R W STAGEA4 OFFSET HIGH CLAMP STAGE4 Offset High Clamp Value 0A7 15 0 X R W STAGEA4 OFFSET LOW CLAMP STAGEA Offset Low Clamp Value Table 34 STAGES Configuration Register Map Data Bit Default Address Content Value Type Name Description 0A8 15 0 X R W STAGE5 CIN 0 6 SETUP STAGES CIN 0 6 Connection Setup See Table 53
38. E PROXIMITY RECAL LVL REGISTER 4 DESCRIPTION OF COMPARATOR FUNCTIONS COMPARATOR 1 USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR COMPARATOR 2 USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR OR APPROACHING A SENSOR VERY SLOWLY ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION FOR EXAMPLE HUMIDITY OR DIRT LEFT BEHIND ON SENSOR COMPARATOR 3 USED TO ENABLE THE SLOW FILTER UPDATE RATE THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND PROXIMITY IS NOT SET 05702 021 Figure 22 AD7142 Proximity Detection and Environmental Calibration Rev PrD Page 18 of 64 AD7142 AD7142 1 ENVIRONMENTAL CALIBRATION The AD7142 provides on chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the capacitance sensor ambient levels Capacitance sensor output levels are sensitive to temperature humidity and in some cases dirt The AD7142 achieves optimal and reliable sensor performance by continuously monitoring the CDC ambient levels and correcting for any changes by adjusting the initial STAGE OFFSET HIGH and STAGE OFFSET LOW register values The CDC ambient level is defined as the capacitance sensor output level during periods when the user is not approaching or in contact with the sensor The compensation logic runs automatically on every conversion after configuration when the AD7142 is not being touched This a
39. FF_WORD3 STAGES Fast FIFO WORD3 199 15 0 X R W STAGE5_FF_WORD4 STAGES Fast FIFO WORD4 19A 15 0 X R W STAGE5_FF_WORD5 STAGES Fast FIFO WORD5 19B 15 0 X R W STAGE5_FF_WORD6 STAGES Fast FIFO WORD6 19C 15 0 X R W STAGE5 FF WORD7 STAGES Fast FIFO WORD7 19D 15 0 X R W STAGE5 SF WORDO STAGES Slow FIFO WORDO 19E 15 0 X R W STAGE5 SF WORD1 STAGES Slow FIFO WORD1 19F 15 0 X R W STAGE5_SF_WORD2 STAGE5 Slow FIFO WORD2 1A0 15 0 X R W STAGE5_SF_WORD3 STAGE5 Slow FIFO WORD3 1A1 15 0 X R W STAGE5 SF WORD4 STAGES Slow FIFO WORD4 1A2 15 0 X R W STAGE5 SF WORD5 STAGES Slow FIFO WORD5 1A3 15 0 X R W STAGE5 SF WORD6 STAGES Slow FIFO WORD6 1A4 15 0 X R W STAGE5 SF WORD7 STAGES Slow FIFO WORD7 1A5 15 0 X R W STAGE5 SF AMBIENT STAGES Slow FIFO Ambient Value 1A6 15 0 X R W STAGE5 FF AVG STAGES Fast FIFO Average Value 1A7 15 0 X R W STAGE5 CDC WORDO STAGE5 CDC FIFO WORDO 1A8 15 0 X R W STAGE5 CDC WORD1 STAGES CDC FIFO WORD1 1A9 15 0 X R W 5 5 MAX WORDO STAGE5 Maximum Value FIFO WORDO 1AA 15 0 X R W 5 5 MAX WORD STAGE5 Maximum Value FIFO WORD1 1AB 15 0 X R W STAGE5_MAX_WORD2 STAGE5 Maximum Value FIFO WORD2 1AC 15 0 X R W STAGE5_MAX_WORD3 STAGE5 Maximum Value FIFO WORD3 1AD 15 0 X R W STAGE5_MAX_AVG STAGE5 Average Maximum FIFO Value 1AE 15 0 X R W STAGE5_HIGH_THRESHOLD STAGES High Threshold Value 1AF 15 0 X R W STAGE5 MAX TEMP STAGE5 Temporary Maximum Value 1 0 15 0 X R W STAGE5 MIN WORDO STAGE5 Minimum Value FIFO WO
40. FIFO WORD1 157 15 0 X R W STAGE3 SF WORD2 STAGE3 Slow FIFO WORD2 158 15 0 X R W STAGE3 SF WORD3 STAGE3 Slow FIFO WORD3 159 15 0 X R W STAGE3 SF WORD4 STAGE3 Slow FIFO WORD4 15A 15 0 X R W STAGE3 SF WORD5 STAGE3 Slow FIFO WORD5 15B 15 0 X R W STAGE3_SF_WORD6 STAGE3 Slow FIFO WORD6 15C 15 0 X R W STAGE3_SF_WORD7 STAGE3 Slow FIFO WORD7 15D 15 0 X R W STAGE3_SF_AMBIENT STAGE3 Slow FIFO Ambient Value 15E 15 0 X R W STAGE3 FF AVG STAGE3 Fast FIFO Average Value 15F 15 0 X R W STAGE3 CDC WORDO STAGE3 CDC FIFO WORDO 160 15 0 X R W STAGE3_CDC_WORD1 STAGE3 CDC FIFO WORD1 161 15 0 X R W STAGE3 MAX WORDO STAGE3 Maximum Value FIFO WORDO 162 15 0 X R W STAGE3_MAX_WORD1 STAGE3 Maximum Value FIFO WORD1 163 15 0 X R W STAGE3 MAX WORD2 STAGE3 Maximum Value FIFO WORD2 164 15 0 X R W STAGE3 MAX WORD3 STAGE3 Maximum Value FIFO WORD3 165 15 0 X R W STAGE3 MAX AVG STAGE3 Average Maximum FIFO Value 166 15 0 X R W STAGE3_HIGH_THRESHOLD STAGE3 High Threshold Value 167 15 0 X R W STAGE3 MAX TEMP STAGE3 Temporary Maximum Value 168 15 0 X R W STAGE3 MIN WORDO STAGE3 Minimum Value FIFO WORDO 169 15 0 X R W STAGE3 MIN WORD STAGE3 Minimum Value FIFO WORD1 16A 15 0 X R W STAGE3_MIN_WORD2 STAGE3 Minimum Value FIFO WORD2 16B 15 0 X R W STAGE3 MIN WORD3 STAGE3 Minimum Value FIFO WORD3 16C 15 0 X R W 5 MIN AVG STAGE3 Average Minimum FIFO Value 16D 15 0 X R W STAGE3 LOW THRESHOLD STAGE3 Low Threshold Value 16E 15 0 X R W STAGE3 MIN
41. FO Value 142 15 0 X R W STAGE2_HIGH_THRESHOLD STAGE2 High Threshold Value 143 15 0 X R W STAGE2_MAX_TEMP STAGE2 Temporary Maximum Value 144 15 0 X R W STAGE2 MIN WORDO STAGE2 Minimum Value FIFO WORDO 145 15 0 X R W STAGE2 MIN WORD STAGE2 Minimum Value FIFO WORD1 146 15 0 X R W STAGE2 MIN WORD2 STAGE2 Minimum Value FIFO WORD2 147 15 0 X R W STAGE2 MIN WORD3 STAGE2 Minimum Value FIFO WORD3 148 15 0 X R W 5 2 MIN AVG STAGE2 Average Minimum FIFO Value 149 15 0 X R W STAGE2 LOW THRESHOLD STAGE2 Low Threshold Value 14A 15 0 X R W STAGE2 MIN TEMP STAGE2 Temporary Minimum Value 14B 15 0 X R W Unused Rev PrD Page 49 of 64 AD7142 AD7142 1 Table 44 STAGE3 Results Register Map Data Bit Default Address Content Value Type Name Description 14C 15 0 X R W STAGE3 CONV DATA STAGE3 CDC 16 Bit Conversion Data Copy of data in STAGE3 CONV DATA register 14D 15 0 X R W STAGE3 FF WORDO STAGE3 Fast FIFO WORDO 14E 15 0 X R W STAGE3 FF WORD1 STAGE3 Fast FIFO WORD1 14F 15 0 X R W STAGE3 FF WORD2 STAGE3 Fast FIFO WORD2 150 15 0 X R W STAGE3 FF WORD3 STAGE3 Fast FIFO WORD3 151 15 0 X R W STAGE3 FF WORD4 STAGE3 Fast FIFO WORD4 152 15 0 X R W STAGE3 FF WORD5 STAGE3 Fast FIFO WORD5 153 15 0 X R W STAGE3_FF_WORD6 STAGE3 Fast FIFO WORD6 154 15 0 X R W STAGE3_FF_WORD7 STAGE3 Fast FIFO WORD7 155 15 0 X R W STAGE3 SF WORDO STAGE3 Slow FIFO WORDO 156 15 0 X R W STAGE3 SF WORD1 STAGE3 Slow
42. FO WORD2 28B 15 0 X R W STAGE11_MIN_WORD3 STAGE11 Minimum Value FIFO WORD3 28C 15 0 X R W STAGE11_MIN_AVG STAGE11 Average Minimum FIFO Value 28D 15 0 X R W STAGE11_LOW_THRESHOLD STAGE11 Low Threshold Value 28E 15 0 X R W STAGE11_MIN_TEMP STAGE11 Temporary Minimum Value 28F 15 0 X R W Unused Rev PrD Page 58 of 64 AD7142 AD7142 1 Table 53 STAGEX Detailed CIN 0 6 Connection Setup Description X 0 to 11 Data Bit Default Content Value Type Name Description 1 0 X R W CINO CONNECTION SETUP CINO Connection Setup 00 CINO not connected to CDC inputs 01 CINO connected to CDC negative input 10 2 CINO connected to CDC positive input 11 2 CINO connected to BIAS connect unused CIN inputs 3 2 X R W CIN1 CONNECTION SETUP CIN1 Connection Setup 00 CIN1 not connected to CDC inputs 01 CIN1 connected to CDC negative input 10 CIN1 connected to CDC positive input 11 CIN1 connected to BIAS connect unused CIN inputs 5 4 X R W CIN2 CONNECTION SETUP CIN2 Connection Setup 00 CIN2 not connected to CDC inputs 01 CIN2 connected to CDC negative input 10 2 CIN2 connected to CDC positive input 11 2 CIN2 connected to BIAS connect unused CIN inputs 7 6 X R W CIN3 CONNECTION SETUP CIN3 Connection Setup 00 CIN3 not connected to CDC inputs 01 CIN3 connected to CDC negative input 10 CIN3 connected to CDC positive input 11 CIN3 connected to BIAS connect unused CIN inputs 9 8 X R W
43. INTERNAL CALIBRATION CALIBRATION DISABLED INTERNAL Figure 18 Full Power Mode Proximity Detection Example with FP PROXIMITY 1 CALIBRATION ENABLED 05702 017 Rev PrD Page 15 of 64 AD7142 AD7142 1 USER APPROCHES USER LEAVES SENSOR SENSOR HERE AREA HERE t CDC CONVERSIONS 1 23 45 6 7 8 9 10111213141516 ERE EEE EE EH E tcaLpis PROXIMITY DETECTION INTERNAL CALIBRATION CALIBRATION DISABLED CALIBRATION ENABLED INTERNAL NOTES 1 CONVERSION TIME tconv_tp LP CONV DELAY 2 PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED 3 tcaLpis tconv_tp x LP PROXIMITY x 4 LP CONV DELAY 05702 018 Figure 19 Low Power Mode Proximity Detection with LP PROXIMITY 4 and LP CONV DELAY 0 USER APPROCHES USER LEAVES SENSOR SENSOR HERE AREA HERE Y CDC CONVERSION VALUES EXCEED USER IN CONTACT WITH SENSOR PROXIMITY RECALIBRATION _LVL t 16 30 70 CONVERSIONS MOS HHHHHHHHHHHHHHHH0HHHHHHHRHHHHHHHHHHHHHHHHHHHH lt tpisca PROXIMITY DETECTION INTERNAL STERNE CALIBRATION DISABLED RECALIBRATION PERIOD X CALIBRATION ENABLED RECALIBRATION INTERNAL MEME ef NOTES 1 CONVERSION TIME DETERMINED FROM TABLE 8 2 toiscat tcoNv_Fp FP PROXIMITY CNT 3 thEcAL tcov xFP PROXIMITY RECAL 0570
44. LK input is 40 60 to 60 40 SCLK t4 ts sb uss XX A A t gt t Figure 2 SPI Detailed Timing Diagram 05702 002 Rev PrD Page 4 of 64 AD7142 AD7142 1 TIMING SPECIFICATIONS AD7142 1 Ta 40 C to 105 C 1 8 V to 3 6 V AVcc DVcc 2 7 V to 3 6 V unless otherwise noted Sample tested at 25 C to ensure compliance All input signals timed from a voltage level of 1 6 V Table 3 PC Timing Specifications Parameter Limit Unit Description 400 kHz max ti 0 6 us min Start condition hold time tup sta t 1 3 us min Clock low period between 10 points tow ts 0 6 us min Clock high period between 90 points ta 100 ns min Data setup time tsu par ts 50 ns min Data hold time tup pat te 0 6 us min Stop condition setup time tsu sro t7 0 6 us min Start condition setup time tsu sta ts 1 3 us min Bus free time between stop and start conditions teur tr 300 ns max Clock data rise time tr 300 ns max Clock data fall time Guaranteed by design but not production tested SCLK SDATA STOP START Figure 3 lC Detailed Timing Diagram Rev PrD Page 5 of 64 05702 003 AD7142 AD7142 1 ABSOLUTE MAXIMUM RATINGS Table 4 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress AVcc to AGND DVc to 03Vto 3 6 V rating on
45. LTS 36 REGISTERS ADDR 0x0B8 STAGE 7 RESULTS 36 REGISTERS ADDR 0x0CO STAGE 8 RESULTS poorer aa REGISTERS STAGE 9 RESULTS 36 REGISTERS ADDR 0 000 STAGE 10 RESULTS 36 REGISTERS ADDR 0x28F STAGE 11 RESULTS 36 REGISTERS 05702 043 AD7142 AD7142 1 DETAILED REGISTER DESCRIPTIONS BANK 1 REGISTERS All addresses and default values are expressed in hexadecimal Table 19 Control Register Map Data Bit Default Address Content Value Type Name Description 000 1 0 0 R W POWER MODE Operating Modes 00 full power mode Normal operation CDC conversions approximately every 36 ms 01 full shutdown mode No CDC conversions 10 low power mode Automatic wake up operation 11 Full Shutdown Mode No CDC conversions 3 2 0 LP_CONV_DELAY Low Power Mode Conversion Delay 00 100 ms 01 200 ms 10 300 ms 11 400 ms 7 4 0 SEQUENCE_STAGE_NUM Number of Stages in Sequence N 1 0000 1 conversion stage in sequence 0001 2 conversion stages in sequence Maximum value 1011 12 conversion stages per sequence 9 8 0 DECIMATION ADC Decimation Factor 00 decimate by 256 01 decimate by 128 10 decimate by 64 11 decimate by 64 10 0 SW_RESET Software Reset Control Self Clearing 1 resets all registers to default values 11 0 INT POL Interrupt Polarity Control 0 active low 1 active high 12 0 SOURCE Excitation Source Control for Pin 15 0 enable
46. Map Data Bit Default Address Content Value Type Name Description 1DC 15 0 X R W STAGE7 CONV DATA STAGE7 CDC 16 Bit Conversion Data Copy of data in STAGE7 CONV DATA register 1DD 15 0 X R W STAGE7 FF WORDO STAGE7 Fast FIFO WORDO 1DE 15 0 X R W STAGE7 FF WORD1 STAGE7 Fast FIFO WORD1 1DF 15 0 X R W STAGE7 FF WORD2 STAGE7 Fast FIFO WORD2 15 0 X R W 5 7 FF WORD3 STAGE7 Fast FIFO WORD3 1E1 15 0 X R W STAGE7 WORD4 STAGE7 Fast FIFO WORD4 1E2 15 0 X R W 5 7 FF WORD5 STAGE7 Fast FIFO WORD5 1E3 15 0 X R W STAGE7 FF WORD6 STAGE7 Fast FIFO WORD6 1E4 15 0 X R W STAGE7 FF WORD7 STAGE7 Fast FIFO WORD7 1E5 15 0 X R W STAGE7 SF WORDO STAGE7 Slow FIFO WORDO 1E6 15 0 X R W STAGE7 SF WORD1 STAGE7 Slow FIFO WORD1 1E7 15 0 X R W STAGE7 SF WORD2 STAGE7 Slow FIFO WORD2 1E8 15 0 X R W STAGE7 SF WORD3 STAGE7 Slow FIFO WORD3 1E9 15 0 X R W STAGE7 SF WORD4 STAGE7 Slow FIFO WORD4 1EA 15 0 X R W STAGE7 SF WORD5 STAGE7 Slow FIFO WORD5 1EB 15 0 X R W STAGE7_SF_WORD6 STAGE7 Slow FIFO WORD6 1EC 15 0 X R W STAGE7_SF_WORD7 STAGE7 Slow FIFO WORD7 1ED 15 0 X R W STAGE7_SF_AMBIENT STAGE7 Slow FIFO Ambient Value 1EE 15 0 X R W STAGE7 FF AVG STAGE7 Fast FIFO Average Value 1EF 15 0 X R W STAGE7 CDC WORDO STAGE7 CDC FIFO WORDO 1 0 15 0 X R W STAGE7_CDC_WORD1 STAGE7 CDC FIFO WORD1 1F1 15 0 X R W STAGE7 MAX WORDO STAGE7 Maximum Value FIFO WORDO 1F2 15 0 X R W STAGE7_MAX_WORD1 STAGE7 Maximum Value FIFO
47. Map Data Bit Default Address Content Value Type Name Description OD8 15 0 X R W 5 11 0 6 SETUP 5 11 CIN 0 6 Connection Setup See Table 53 009 15 0 X R W 5 11 CIN 7 13 SETUP STAGE11 CIN 7 13 Connection Setup See Table 54 ODA 15 0 X R W 5 11 AFE OFFSET STAGE11 AFE Offset Control See Table 55 ODB 15 0 X R W 5 11 SENSITIVITY STAGE11 Sensitivity Control See Table 56 oDC 15 0 X R W STAGE11_OFFSET_LOW STAGE11 Initial Offset LOW Value ODD 15 0 X R W STAGE11_OFFSET_HIGH STAGE11 Initial Offset HIGH Value ODE 15 0 X R W STAGE11_OFFSET_HIGH_CLAMP STAGE11 Offset High Clamp Value ODF 15 0 X R W STAGE11_OFFSET_LOW_CLAMP STAGE11 Offset Low Clamp Value Rev PrD Page 46 of 64 BANK 3 REGISTERS All address values are expressed in hexadecimal Table 41 STAGEO Results Register Map AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description OEO 15 0 X R W STAGEO CONV DATA STAGEO CDC 16 Bit Conversion Data Copy of data in STAGEO CONV DATA register 1 15 0 X R W STAGEO FF WORDO STAGEO Fast FIFO WORDO OE2 15 0 X R W STAGEO FF WORD1 STAGEO Fast FIFO WORD1 OE3 15 0 X R W STAGEO FF WORD2 STAGEO Fast FIFO WORD2 OE4 15 0 X R W STAGEO FF WORD3 STAGEO Fast FIFO WORD3 OE5 15 0 X R W STAGEO FF WORD4 STAGEO Fast FIFO WORD4 OE6 15 0 X R W STAGEO FF WORD5 STAGEO Fast FIFO WORD5 7 15 0 X R W STAGEO FF WORD6 STAGEO Fast FIFO WORD6
48. QUENCE STAGE NUM 5 2 FF SKIP 3 VALUE SELECTED FROM TABLE 8 FOR DECIMATION 128 05702 013 Figure 14 Example Using SEQUENCE CON NUM and SKIP Registers The number of required conversion stages depends wholly on the number of sensors attached to the AD7142 Figure 15 shows how many conversion stages are required for each sensor and how many inputs to the AD7142 each sensor requires AD7142 SEQUENCER BUTTONS 05702 014 Figure 15 Sequencer Setup for Sensors A button sensor generally requires one sequencer stage however it is possible to configure two button sensors to operate differentially Only one button from the pair can be activated at a time pressing both buttons together results in neither button being activated This configuration requires one conversion stage A slider sensor requires two stages one stage for sensor activation the other stage for measuring positional data from the slider In Figure 15 the slider activation uses STAGE2 while the positional data uses STAGES The 8 way switch is made from two pairs of differential buttons It therefore requires two conversion stages one for each of the differential button pairs The buttons are orientated so that one pair makes up the top and bottom portions of the 8 way switch the other pair makes up the left and right portions of the 8 way switch CDC CONVERSION TIME The time required for one complete measurement by
49. RDO 1B1 15 0 X R W STAGE5_MIN_WORD1 STAGE5 Minimum Value FIFO WORD1 1B2 15 0 X R W STAGE5_MIN_WORD2 STAGE5 Minimum Value FIFO WORD2 1B3 15 0 X R W STAGE5_MIN_WORD3 STAGE5 Minimum Value FIFO WORD3 1B4 15 0 X R W 5 5 MIN AVG STAGE5 Average Minimum FIFO Value 1B5 15 0 X R W STAGE5_LOW_THRESHOLD STAGE5 Low Threshold Value 1B6 15 0 X R W STAGE5_MIN_TEMP STAGE5 Temporary Minimum Value 1B7 15 0 X R W Unused Rev PrD Page 52 of 64 Table 47 STAGE6 Results Register AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 1B8 15 0 X RW STAGEG6 CONV DATA STAGE6 CDC 16 Bit Conversion Data Copy of data in STAGE6 CONV DATA register 1B9 15 0 X R W 5 6 FF WORDO STAGE6 Fast FIFO WORDO 1BA 15 0 X R W STAGE6_FF_WORD1 STAGE6 Fast FIFO WORD1 1BB 15 0 X R W STAGE6_FF_WORD2 STAGE6 Fast FIFO WORD2 1BC 15 0 X R W STAGE6_FF_WORD3 STAGE6 Fast FIFO WORD3 1BD 15 0 X R W STAGE6_FF_WORD4 STAGE6 Fast FIFO WORD4 1BE 15 0 X R W STAGE6_FF_WORD5 STAGE6 Fast FIFO WORD5 1BF 15 0 X R W STAGE6_FF_WORD6 STAGE6 Fast FIFO WORD6 1 0 15 0 X R W 5 6 FF WORD7 STAGE6 Fast FIFO WORD7 1C1 15 0 X R W STAGE6 SF WORDO STAGE6 Slow FIFO WORDO 1C2 15 0 X R W SF WORD1 STAGE6 Slow FIFO WORD1 103 15 0 X R W SF WORD2 STAGE6 Slow FIFO WORD2 1 4 15 0 X R W STAGE6 SF WORD3 STAGE6 Slow FIFO WORD3 1C5 15 0 X R W STAGE6 SF WORD4 STAGE6 Slow FIFO WORD4
50. Specifications 30 Chip Scale Package uie ete eer 30 Power Up Sequence 31 Typical Application Circuits sss 32 R gister ET 33 Detailed Register Descriptions seen 34 Bank I Registers sisisi reri entre rp eiae cines 34 Bank 2 Registers a sas aqa aussi 44 Bank Registers qasqu 47 Outline Dimensions eene 62 Ordering Guide u oe ette 62 1 05 Preliminary Version A Rev PrD Page 2 of 64 AD7142 AD7142 1 SPECIFICATIONS Vcc 2 7 V to 3 3 V Ta 40 C to 85 C unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments CAPACITANCE TO DIGITAL CONVERTER Update Rate 30 Hz Maximum programmed sequence length Resolution 16 Bit Range 2 pF No Missing Codes 16 Bit Guaranteed by design but not production tested Total Unadjusted Error TBD fF Power Supply Rejection 500 aF V Output Noise Peak to Peak 10 aF VHz Parasitic Capacitance 60 pF Parasitic capacitance to ground guaranteed by characterization EXCITATION SOURCE Frequency TBD 240 TBD kHz Output Voltage AVcc V Short Circuit Current 10 mA Maximum Output Load 500 pF Capacitance load on source to ground Csuiip Output Drive 10 uA lt Bias Level AVcc 2 V LOGIC INPUTS SDI SCLK C SDA GPI TEST Vin Input High Voltage 0 7 x Vorive V Vi Input Low Voltage 0 3 xVorve V liu In
51. TA register 129 15 0 X R W STAGE2 FF WORDO STAGE2 Fast FIFO WORDO 12A 15 0 X R W STAGE2 FF WORD1 STAGE2 Fast FIFO WORD1 12B 15 0 X R W STAGE2 FF WORD2 STAGE2 Fast FIFO WORD2 12C 15 0 X R W STAGE2 FF WORD3 STAGE2 Fast FIFO WORD3 12D 15 0 X R W STAGE2 FF WORD4 STAGE2 Fast FIFO WORD4 12E 15 0 X R W STAGE2 FF WORD5 STAGE2 Fast FIFO WORD5 12F 15 0 X R W STAGE2 FF WORD6 STAGE2 Fast FIFO WORD6 130 15 0 X R W STAGE2 FF WORD7 STAGE2 Fast FIFO WORD7 131 15 0 X R W STAGE2 SF WORDO STAGE2 Slow FIFO WORDO 132 15 0 X R W STAGE2 SF WORD1 STAGE2 Slow FIFO WORD1 133 15 0 X R W STAGE2 SF WORD2 STAGE2 Slow FIFO WORD2 134 15 0 X R W STAGE2 SF WORD3 STAGE2 Slow FIFO WORD3 135 15 0 X R W STAGE2 SF WORD4 STAGE2 Slow FIFO WORD4 136 15 0 X R W STAGE2 SF WORD5 STAGE2 Slow FIFO WORD5 137 15 0 X R W STAGE2 SF WORD6 STAGE2 Slow FIFO WORD6 138 15 0 X R W STAGE2 SF WORD7 STAGE2 Slow FIFO WORD7 139 15 0 X R W 5 2 SF AMBIENT STAGE2 Slow FIFO Ambient Value 13A 15 0 X R W STAGE2 FF AVG STAGE2 Fast FIFO Average Value 13B 15 0 X R W STAGE2 CDC WORDO STAGE2 CDC FIFO WORDO 13C 15 0 X R W STAGE2_CDC_WORD1 STAGE2 CDC FIFO WORD1 13D 15 0 X R W STAGE2 MAX WORDO STAGE2 Maximum Value FIFO WORDO 13E 15 0 X R W STAGE2 MAX WORD STAGE2 Maximum Value FIFO WORD1 13F 15 0 X R W STAGE2_MAX_WORD2 STAGE2 Maximum Value FIFO WORD2 140 15 0 X R W STAGE2_MAX_WORD3 STAGE2 Maximum Value FIFO WORD3 141 15 0 X R W STAGE2_MAX_AVG STAGE2 Average Maximum FI
52. TAGE LOW THRESHOLD BANK 3 REGISTERS FP PROXIMITY CNT LP PROXIMITY CNT REGISTER 0x004 REGISTER 0X004 COMPARATOR 3 STAGE FF WORDO COMPARATOR 1 STAGE FF WORD1 PROXIMITY 1 STAGE FF WORD WORD 0 WORD PROXIMITY PROXIMITY TIMING a CONTROL LOGIC STAGE FF WORD3 STAGE FF WORD4 PROXIMITY DETECTION RATE FP PROXIMITY RECAL LP PROXIMITY RECAL REGISTER 0x003 REGISTER 0x004 REGISTER 0X004 STAGE FF WORD5 BANK 3 REGISTERS SLOW FILTER UPDATE LVL REGISTER 0x003 WORD 0 WORD 3 PROXIMITY 9 STAGE FF WORD6 STAGE WORD7 SLOW FILTER EN 7 gt wonp N N 0 8 PROXIMITY 2 swi o 0 t COMPARATOR 2 STAGE FF WORDX AVERAGE AMBIENT STAGE_FF_AVG STAGE SF WORDO BANK 3 REGISTERS STAGE SF WORD1 STAGE WORD2 PROXIMITY RECAL LVL STAGE SF WORD3 a a WORDX AMBIENT VALUE SSTAGE_SF_WORD4 SF WORD TAGE SF WORD TAGE SF WORD BANK 3 REGISTERS o a o OUTPUT CODE SENSOR CONTACT o STAGE SF AMBIENT BANK 3 REGISTERS NOTES 1 SLOW FILTER EN IS SET AND SW1 IS CLOSED WHEN WORD 0 WORD 3 EXCEEDS THE VALUE PROGRAMMED IN THE SLOW FILTER UPDATE REGISTER PROVIDING PROXIMITY IS NOT SET 2 PROXIMITY 11S SET WHEN WORD 0 WORD 3 EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY DETECTION RATE REGISTER 3 PROXIMITY 21S SET WHEN AVERAGE AMBIENT EXCEEDS THE VALUE PROGRAMMED IN TH
53. TAGE4 CDC FIFO WORD1 185 15 0 X R W STAGE4 MAX WORDO STAGE4 Maximum Value FIFO WORDO 186 15 0 X R W STAGE4_MAX_WORD1 STAGE4 Maximum Value FIFO WORD1 187 15 0 X R W STAGE4 MAX WORD2 STAGE4 Maximum Value FIFO WORD2 188 15 0 X R W STAGE4 MAX WORD3 STAGE4 Maximum Value FIFO WORD3 189 15 0 X R W STAGE4 MAX AVG STAGE4 Average Maximum FIFO Value 18A 15 0 X R W 5 4 HIGH THRESHOLD STAGEA High Threshold Value 18B 15 0 X R W STAGE4 MAX TEMP STAGE4 Temporary Maximum Value 18C 15 0 X R W STAGE4_MIN_WORDO STAGE4 Minimum Value FIFO WORDO 18D 15 0 X R W 5 4 MIN WORD STAGE4 Minimum Value FIFO WORD1 18E 15 0 X R W STAGE4 MIN WORD2 STAGE4 Minimum Value FIFO WORD2 18F 15 0 X R W STAGE4 MIN WORD3 STAGE4 Minimum Value FIFO WORD3 190 15 0 X R W 5 4 MIN AVG STAGE4 Average Minimum FIFO Value 191 15 0 X R W 5 4 LOW THRESHOLD STAGEA Low Threshold Value 192 15 0 X R W 5 4 MIN TEMP STAGE4 Temporary Minimum Value 193 15 0 X R W Unused Rev PrD Page 51 of 64 AD7142 AD7142 1 Table 46 STAGES Results Register Map Data Bit Default Address Content Value Type Name Description 194 15 0 X R W STAGE5 CONV DATA STAGES CDC 16 Bit Conversion Data Copy of data in STAGE5 CONV DATA register 195 15 0 X R W STAGE5 FF WORDO STAGES Fast FIFO WORDO 196 15 0 X R W STAGE5_FF_WORD1 STAGES Fast FIFO WORD1 197 15 0 X R W STAGE5_FF_WORD2 STAGES Fast FIFO WORD2 198 15 0 X R W STAGE5_
54. TE STATUS STAGE2 Conversion Completion Status 1 indicates STAGEO conversion completed 3 0 STAGE3 COMPLETE STATUS STAGE3 Conversion Completion Status 1 indicates STAGEO conversion completed 4 0 STAGE4 COMPLETE STATUS STAGE4 Conversion Completion Status 1 indicates STAGEO conversion completed 5 0 STAGE5 COMPLETE STATUS STAGES Conversion Completion Status 1 indicates STAGEO conversion completed 6 0 STAGE6 COMPLETE STATUS STAGE6 Conversion Completion Status 1 indicates STAGEO conversion completed 7 0 STAGE7_COMPLETE_STATUS STAGE7 Conversion Completion Status 1 indicates STAGEO conversion completed 8 0 STAGE8_COMPLETE_STATUS STAGE8 Conversion Completion Status 1 indicates STAGEO conversion completed 9 0 STAGE9 COMPLETE STATUS STAGE Conversion Completion Status 1 indicates STAGEO conversion completed 10 0 STAGE10 COMPLETE STATUS STAGE10 Conversion Completion Status 1 indicates STAGEO conversion completed 11 0 STAGE11 COMPLETE STATUS STAGE11 Conversion Completion Status 1 indicates STAGEO conversion completed 12 0 GPIO STATUS GPIO Input Pin Status 1 indicates level on GPIO pin has changed 15 13 Unused Set Unused Register Bits 0 Registers self clear to 0 after readback Rev PrD Page 41 of 64 AD7142 AD7142 1 Table 25 CDC 16 Bit Conversion Data Register Map Data Bit Default Address Content Value Type Nam
55. TIONS NOTES 1 INITIAL STAGE OFFSET HIGH REGISTER VALUE 2 POST CALIBRATED REGISTER STAGE OFFSET HIGH VALUE 3 POST CALIBRATED REGISTER STAGE OFFSET HIGH VALUE 4 INITIAL STAGE OFFSET LOW REGISTER VALUE 5 POST CALIBRATED REGISTER STAGE OFFSET LOW VALUE 6 POST CALIBRATED REGISTER STAGE OFFSET LOW VALUE 05702 024 Figure 25 Typical Sensor Behavior with Calibration Applied on the Data Path Rev PrD Page 19 of 64 AD7142 AD7142 1 ADAPTIVE THRESHOLD AND SENSITIVITY The AD7142 provides an on chip self learning adaptive threshold and sensitivity algorithm This algorithm continu ously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user As a result the AD7142 maintains optimal threshold and sensitivity levels for all types of users regardless of their finger sizes The threshold level is always referenced from the ambient level and is defined as the CDC converter output level that must be exceeded for a valid sensor contact The sensitivity level is defined as how sensitive the sensor is before a valid contact is registered Figure 26 provides an example of how the adaptive threshold and sensitivity algorithm works In a case where the adaptive threshold and sensitivity algorithm are disabled the positive and negative sensor threshold levels are set by the CDC OUTPUT CODES MAX VALUE 95 32 25 AVERAGE MAX VALUE
56. Table 11 lists the interrupt output behavior for each of the GPIO configuration setups Rev PrD Page 24 of 64 AD7142 AD7142 1 SERIAL INTERFACE The AD7142 is available with an SPI serial interface The AD7142 1 is available with an PC interface Both parts are exactly the same with the exception of the serial interface SPI INTERFACE The AD7142 has a 4 wire serial peripheral interface SPI The SPI has a data input pin SDI for inputting data to the device a data output pin SDO for reading data back from the device and a data clock pin SCLK for clocking data into and out of the device A chip select pin CS enables or disables the serial interface CS is required for correct operation of the SPI interface Data is clocked out of the AD7142 on the negative edge of SCLK and data is clocked into the device on the positive edge of SCLK SPI Command Word All data transactions on the SPI bus begin with the master taking CS low and sending out the command word This indicates to the AD7142 whether the transaction is a read or a write and gives the address of the register from which to begin the data transfer Table 14 SPI Command Word Bits 15 11 of the command word must be set to 11100 to successfully begin a bus transaction Bit 10 is the read write bit 1 indicates a read and 0 indicates a write Bits 9 0 contain the target register address When reading or writing to more t
57. Theory of Operation reete iet teles 9 Capacitance Sensing Theory sse 9 Operating Modes eet petente pei teet u g 10 Capacitance Sensor Input 11 CIN Input Multiplexer 11 Capacitiance to Digital Converter seen 12 Oversampling the CDC Output 12 Capacitance Sensor Offset Control sss 12 Conversion Sequencer esee 12 CDC Conversion Time seen 13 CDC Conversion Results sse 14 Non Contact Proximity Detection sse 15 Environmental Calibration seen 19 REVISION HISTORY 12 05 Preliminary Version D 7 05 Preliminary Version C 2 05 Preliminary Version B Adaptive Threshold and Sensitivity sss 20 Interrupt Output seen 21 CDC Conversion Complete Interrupt ses 21 Sensor Threshold Interrupt a 21 GPIO INT Output Control s 22 Q utp tlgk u M 24 EXCitatlOn SOUFCe es eee REIR RENE 24 tente e etre RR hasa 24 GPIO 24 Serial Interface ot t 25 SPIInterface coiere eene eee rie 25 PC iet ete ete ied 27 a u u ke sees 29 PCB Design Guidelines a a aa petits 30 Capacitive Sensor Board Mechanical
58. VERSION CONVERSION 1 05702 016 Figure 17 Low Power Mode CDC Conversion Time CDC Conversion Results CDC CONVERSION RESULTS Certain applications such as a slider function require reading back the CDC conversion results for host processing The registers required for host processing are located in Register Bank 3 The host processes the data read back from these registers to determine relative position information In addition to the results registers in Bank 3 the AD7142 provides the 16 bit CDC output data directly starting at Address 0x00B of Register Bank 1 Reading back the CDC 16 bit conversion data register allows for customer specific application data processing Rev PrD Page 14 of 64 AD7142 AD7142 1 NON CONTACT PROXIMITY DETECTION The AD7142 internal signal processing continuously monitors all capacitance sensors for non contact proximity detection This feature provides the ability to detect when a user is approaching a sensor at which time all internal calibration is immediately disabled while the AD7142 is automatically configured to detect a valid contact The proximity control register bits are described in Table 10 The FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register bits control how long the calibration disable period is after proximity is detected The calibration is disabled during this time and enabled again at the end of this period provided that the user is no longer approaching or in contact
59. WORD1 1F3 15 0 X R W STAGE7_MAX_WORD2 STAGE7 Maximum Value FIFO WORD2 1F4 15 0 X R W STAGE7_MAX_WORD3 STAGE7 Maximum Value FIFO WORD3 1F5 15 0 X R W STAGE7 AVG STAGE7 Average Maximum FIFO Value 1F6 15 0 X R W STAGE7_HIGH_THRESHOLD STAGE7 High Threshold Value 1F7 15 0 X R W STAGE7 MAX TEMP STAGE7 Temporary Maximum Value 1F8 15 0 X R W 5 7 MIN WORDO STAGE7 Minimum Value FIFO WORDO 1F9 15 0 X R W STAGE7 MIN WORD STAGE7 Minimum Value FIFO WORD1 1FA 15 0 X R W STAGE7_MIN_WORD2 STAGE7 Minimum Value FIFO WORD2 1FB 15 0 X R W STAGE7_MIN_WORD3 STAGE7 Minimum Value FIFO WORD3 1FC 15 0 X R W STAGE7 MIN AVG STAGE7 Average Minimum FIFO Value 1FD 15 0 X R W STAGE7 LOW THRESHOLD STAGE7 Low Threshold Value 1FE 15 0 X R W STAGE7 MIN TEMP STAGE7 Temporary Minimum Value 1FF 15 0 X R W Unused Rev PrD Page 54 of 64 Table 49 STAGES Results Register Map AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 200 15 0 X RW 5 8 CONV DATA STAGES CDC 16 Bit Conversion Data Copy of data in STAGE8 CONV DATA register 201 15 0 X R W STAGE8 FF WORDO STAGES Fast FIFO WORDO 202 15 0 X R W STAGE8_FF_WORD1 STAGES Fast FIFO WORD1 203 15 0 X R W STAGE8_FF_WORD2 STAGES Fast FIFO WORD2 204 15 0 X R W STAGE8_FF_WORD3 STAGES Fast FIFO WORD3 205 15 0 X R W STAGE8_FF_WORD4 STAGES Fast FIFO WORD4 206 15 0 X R W STAGE8_FF_WORD5 STAGES Fast FIFO WORD5 207 15
60. WORD3 STAGEO Minimum Value FIFO WORD3 100 15 0 X R W STAGEO MIN AVG STAGEO Average Minimum FIFO Value 101 15 0 X R W STAGEO LOW THRESHOLD STAGEO Low Threshold Value 102 15 0 X R W 5 MIN TEMP STAGEO Temporary Minimum Value 103 15 0 X R W Unused Rev PrD Page 47 of 64 AD7142 AD7142 1 Table 42 STAGE Results Register Data Bit Default Address Content Value Type Name Description 104 15 0 X R W 5 1 CONV DATA STAGE CDC 16 Bit Conversion Data Copy of data in STAGE1 CONV DATA register 105 15 0 X R W STAGE1_FF_WORDO STAGE1 Fast FIFO WORDO 106 15 0 X R W STAGE1_FF_WORD1 STAGE1 Fast FIFO WORD1 107 15 0 X R W STAGE1_FF_WORD2 STAGE1 Fast FIFO WORD2 108 15 0 X R W STAGE1_FF_WORD3 STAGE1 Fast FIFO WORD3 109 15 0 X R W STAGE1_FF_WORD4 STAGE1 Fast FIFO WORD4 10A 15 0 X R W STAGE1_FF_WORD5 STAGE1 Fast FIFO WORD5 10B 15 0 X R W STAGE1_FF_WORD6 STAGE1 Fast FIFO WORD6 10C 15 0 X R W STAGE1_FF_WORD7 STAGE1 Fast FIFO WORD7 10D 15 0 X R W STAGE1_SF_WORDO STAGE1 Slow FIFO WORDO 10E 15 0 X R W 5 1 SF WORD1 STAGE Slow FIFO WORD1 10F 15 0 X R W STAGE1_SF_WORD2 STAGE1 Slow FIFO WORD2 110 15 0 X R W STAGE1_SF_WORD3 STAGE1 Slow FIFO WORD3 111 15 0 X R W STAGE1_SF_WORD4 STAGE1 Slow FIFO WORD4 112 15 0 X R W STAGE1_SF_WORD5 STAGE1 Slow FIFO WORD5 113 15 0 X R W STAGE1_SF_WORD6 STAGE1 Slow FIFO WORD6 114 15 0 X R W STAGE1_SF_WORD7 STAGE1 Slow FIFO WORD7 115 15
61. X R W STAGE9_SF_AMBIENT STAGE9 Slow FIFO Ambient Value 236 15 0 X R W STAGE9_FF_AVG STAGE9 Fast FIFO Average Value 237 15 0 X R W STAGE9 CDC WORDO STAGE9 CDC FIFO WORDO 238 15 0 X R W STAGE9_CDC_WORD1 STAGE9 CDC FIFO WORD1 239 15 0 X R W STAGE9 MAX WORDO STAGE9 Maximum Value FIFO WORDO 23A 15 0 X R W STAGE9 MAX WORD STAGE9 Maximum Value FIFO WORD1 23B 15 0 X R W STAGE9 MAX WORD2 STAGE9 Maximum Value FIFO WORD2 23C 15 0 X R W STAGE9_MAX_WORD3 STAGE9 Maximum Value FIFO WORD3 23D 15 0 X R W STAGE9_MAX_AVG STAGE9 Average Maximum FIFO Value 23E 15 0 X R W STAGE9_HIGH_THRESHOLD STAGE9 High Threshold Value 23F 15 0 X R W STAGE9_MAX_TEMP STAGE9 Temporary Maximum Value 240 15 0 X R W STAGE9 MIN WORDO STAGE9 Minimum Value FIFO WORDO 241 15 0 X R W STAGE9 MIN WORD STAGE9 Minimum Value FIFO WORD1 242 15 0 X R W STAGE9 MIN WORD2 STAGE9 Minimum Value FIFO WORD2 243 15 0 X R W STAGE9 MIN WORD3 STAGE9 Minimum Value FIFO WORD3 244 15 0 X R W STAGE9 MIN AVG STAGE9 Average Minimum FIFO Value 245 15 0 X R W STAGE9 LOW THRESHOLD STAGE9 Low Threshold Value 246 15 0 X R W STAGE9 MIN TEMP STAGE9 Temporary Minimum Value 247 15 0 X R W Unused Rev PrD Page 56 of 64 Table 51 STAGEIO Results Register Map AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 248 15 0 X RW STAGE10 DATA STAGE10 CDC 16 Bit Conversion Data Copy of data in STAGE1TO0 CONV DATA register
62. also be internally connected to the signal to help prevent cross coupling If an input is not used always connect it to For each input pin CINO to CIN13 the multiplexer settings can be set on a per sequencer stage basis For example CINO is connected to the negative CDC input for conversion STAGEI left floating for sequencer STAGEL and so on for all twelve conversion stages Two bits in each register control the mux setting for the input pin CIN SETTING SETUP BITS CINX FLOATING CINX CONNECTED TO NEGATIVE CDC INPUT CINX CONNECTED TO POSITIVE CDC INPUT CINX CONNECTED TO CsHIELD 05702 010 Figure 11 Input Mux Configuration Options Rev PrD Page 11 of 64 AD7142 AD7142 1 CAPACITIANCE TO DIGITAL CONVERTER The capacitance to digital converter on the AD7142 has a sigma delta X A architecture with 16 bit resolution There are 14 possible inputs to the CDC that are connected to the input of the converter through a switch matrix The sampling frequency of the CDC is 240 kHz OVERSAMPLING THE CDC OUTPUT It is possible to sample the result of any CDC conversion at a rate less than 240 kHz The decimation rate or over sampling ratio is determined by Bits 9 8 of the control register as listed in Table 7 Table 7 CDC Decimation Rate Decimation Bit Value Decimation Rate CDC Sample Rate 00 256 312 5 Hz 01 128 625 Hz 10 64 1 25 kHz 11 64 1 25 kHz
63. as square wave source with a frequency of 240 kHz This excitation source forms the capacitance field between the transmitter and receiver in the external capacitance sensor PCB The source is output from the AD7142 on two pins the SRC pin and the SRC pin outputs an inverted version of the source square wave The SRC signal offsets large external sensor capacitances In current applications SRC is not used The source output can be disabled from both output pins separately by writing to the control register Address 0x000 Setting Bit 12 in this register to 1 disables the source output on the SRC pin Setting Bit 13 in this register to 1 disables the inverted source output on the SRC pin Csurip OUTPUT To prevent leakage from the external capacitance sensors the sensor traces are shielded The AD7142 has a voltage output that can be used as the potential for any shield traces Csur The Csui voltage is equal to Vp 2 The Csump potential is derived from the output of the AD7142 internal amplifier and is of equal potential to the CIN input lines Because the shield is at the same potential as the sensor traces no leakage to ground occurs To eliminate any ringing on the output connect a 10 nF capacitor between the pin and ground Csutetp is connected to layer three on a four layer sensor PCB to provide shielding for the sensors On a two layer PCB construc tion is used in place of a ground plane
64. ble 1 disable Rev PrD Page 60 of 64 AD7142 AD7142 1 Table 55 STAGEX Detailed Offset Control Description X 0 to 11 Data Bit Default Content Value Type Name Description 6 0 X R W NEG AFE OFFSET Negative AFE Offset Setting 20 pF Range 1 LSB value 0 16 pF of offset 7 X R W NEG AFE OFFSET SWAP Negative AFE Offset Swap Control 0 NEG AFE OFFSET applied to CDC negative input 1 2 NEG AFE OFFSET applied to CDC positive input 14 8 X R W POS AFE OFFSET Positive AFE Offset Setting 20 pF Range 1 LSB value 0 16 pF of offset 15 X R W POS AFE OFFSET SWAP Positive AFE Offset Swap Control 0 POS AFE OFFSET applied to CDC positive input 1 POS AFE OFFSET applied to CDC negative input Table 56 STAGEX Detailed Sensitivity Control Description X 0 to 11 Data Bit Content Default Value Type Name Description 3 0 X R W NEG_THRESHOLD_SENSITIVITY Negative Threshold Sensitivity Control 0000 25 0001 29 73 0010 34 40 0011 39 08 0100 43 79 0101 48 47 0110 53 15 0111 57 83 1000 62 51 1001 67 22 1010 71 90 1011 76 58 1100 81 28 1101 85 96 1110 90 64 1111 95 32 6 4 R W NEG_PEAK_DETECT Negative Peak Detect Setting 000 40 level 001 50 level 010 60 level 011 70 level 100 80 Level 101 90 level 7 R W Unused 11 8 R W POS_THRESHOLD_SENSITIVITY Posi
65. converter The CDC is capable of sensing changes in the capacitance of the external sensors and uses this information to register a sensor activation The external sensors can be arranged as a series of buttons as a scroll bar or wheel or asa combination of sensor types By programming the registers the user has full control over the CDC setup High resolution scroll bar sensors require software to run on the host processor Rev PrD Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM VREF VREF TEST CINO 0 POWER ON RESET 69 LOGIC 3 AVcc CIN5 3 14 AGND CALIBRATION ENGINE MATRIX 9 z SWITCH 7 12 DVcc CIN10 8 AD7142 CALIBRATION 18 DGND1 CONTROL 19 DGND2 AND DATA REGISTERS 240kHz EXCITATION SOURCE INTERRUPT AND GPIO LOGIC SERIAL INTERFACE GPIO AND CONTROL LOGIC MEE SDO sD 5 CS SDA ADDO ADD1 05702 001 Figure 1 The AD7142 and AD7142 1 have on chip calibration logic
66. cted to voltage supplies as low as 1 6 V and as high as Vcc The supply voltage to all pins associated with both the and SPI serial interfaces SDO SDI SCLK SDA and CS is separate from the main Vcc supply and is connected to the Vorive pin Rev PrD Page 29 of 64 AD7142 AD7142 1 PCB DESIGN GUIDELINES CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS Table 18 Parameter Symbol Min Typ Max Unit Distance from Edge of Any Sensor to Edge of Metal Object Di 1 0 mm Distance Between Sensor Edges D2 D4 0 mm Distance Between Bottom of Sensor Board and Controller Board or Metal Ds 1 0 mm Casing 4 Layer 2 Layer And Flex Circuit The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user s finger positioning and handling Adjacent sensors with 0 minimum space between them are implemented differentially The 1 0 mm specification is meant to prevent any direct sensor board contact with any conductive material This specification does not guarantee no EMI coupling from the controller board to the sensors Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main controller board as shown in Figure 43 CHIP SCALE PACKAGES The lands on the chip scale package CP 32 3 are rectangular The printed circuit board pad for these should be 0 1 mm mE longer than the packag
67. e Description 00B 15 0 0 R STAGEO CONV DATA STAGEO CDC 16 Bit Conversion Data 00 15 0 0 R STAGE1 DATA STAGE1 CDC 16 Bit Conversion Data 00D 15 0 0 R STAGE2 CONV DATA STAGE2 CDC 16 Bit Conversion Data 00E 15 0 0 R STAGE3_CONV_DATA STAGE3 CDC 16 Bit Conversion Data 00F 15 0 0 R STAGE4_CONV_DATA STAGE4 CDC 16 Bit Conversion Data 010 15 0 0 R STAGE5_CONV_DATA STAGE5 CDC 16 Bit Conversion Data 011 15 0 0 R STAGE6_CONV_DATA STAGE6 CDC 16 Bit Conversion Data 012 15 0 0 R STAGE7_CONV_DATA STAGE7 CDC 16 Bit Conversion Data 013 15 0 0 R STAGE8_CONV_DATA STAGE8 CDC 16 Bit Conversion Data 014 15 0 0 R STAGE9_CONV_DATA STAGE9 CDC 16 Bit Conversion Data 015 15 0 0 R STAGE10_CONV_DATA STAGE10 CDC 16 Bit Conversion Data 016 15 0 0 R STAGE11_CONV_DATA STAGE11 CDC 16 Bit Conversion Data Table 26 Device ID Register Map Data Bit Default Address Content Value Type Name Description 017 3 0 2 R REVISION_CODE AD7142 Revision Code 15 4 E62 R DEVICE ID AD7142 Device ID 110110100010 Table 27 Proximity Status Register Data Bit Default Address Content Value Type Name Description 042 0 0 R STAGEO PROXIMITY STATUS STAGEO Proximity Status Register 1 indicates proximity has been detected on STAGEO 1 0 R 5 1 PROXIMITY STATUS STAGE Proximity Status Register 1 indicates proximity has been detected on STAGE1 2 0 R STAGE2 PROXIMITY STATUS STAGE2 Proximity Status Register 1 indicates proximity has been detected on STAGE2 3
68. e detection range The Capacitance Sensor Behavior with Calibration section describes how the AD7142 adaptive calibration algorithm prevents errors such as this from occurring La SENSOR 1 INT ASSERTED STAGE OFFSET HIGH INITIAL REGISTER VALUE CDC AMBIENT VALUE DRIFTING CDC OUTPUT CODES STAGE OFFSET LOW INITIAL REGISTER VALUE SENSOR 2 INT NOT ASSERTED x 05702 023 CHANGING ENVIRONMENTALCONDITIONS Figure 24 Typical Sensor Behavior without Calibration Applied Capacitance Sensor Behavior with Calibration The AD7142 on chip adaptive calibration algorithm prevents sensor detection errors such the one shown in Figure 24 This is achieved by monitoring the CDC ambient levels and internally adjusting the initial offset level register values according to the amount of ambient drift measured on each sensor This closed loop routine ensures the reliability and repeatability operation of every sensor connected to the AD7142 under dynamic environmental conditions Figure 25 shows a simplified example of how the AD7142 applies the adaptive calibration process resulting in no interrupt errors under changing CDC ambient levels due to environmental conditions SENSOR 1 INT ASSERTED 2 3 STAGE OFFSET HIGH POST CALIBRATED REGISTER VALUE CDC AMBIENT VALUE DRIFTING STAGE OFFSET LOW POST CALIBRATED REGISTER VALUE CDC OUTPUT CODES SENSOR 2 INT ASSERTED CHANGING ENVIRONMENTALCONDI
69. e land length and 0 05 mm wider than PRINTED CIRCUIT the package land width Center the land on the pad to maximize 8 WAY ANE SWITCH the solder joint size METAL OBJECT The bottom of the chip scale package has a central thermal pad The thermal pad on the printed circuit board should be at least as large as this exposed pad To avoid shorting provide a clearance of at least 0 25 mm between the thermal pad and the inner edges of the land pattern on the printed circuit board SLIDER BUTTONS Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package If vias are used they should be incorporated in the thermal pad at a 1 2 mm pitch grid The via diameter should be between 0 3 mm and 0 33 mm and the via barrel should be plated with 1 oz copper to plug the via 05702 045 Connect the printed circuit board thermal pad to GND Figure 41 Capacitive Sensor Board Mechanicals Top View CAPACITIVE SENSOR BOARD Ds GROUNDED METAL SHIELD CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING Figure 42 Capacitive Sensor Board Mechanicals Side View 05702 046 CAPACITIVE SENSOR BOARD Ds CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING Figure 43 Capacitive Sensor Board with Grounded Shield 05702 047 Rev PrD Page 30 of 64 AD7142 AD7142 1 POWER UP SEQUENCE When the AD7142 is powered up the following sequence is 5 Set calibration enable bi
70. e master performs a write transaction and writes to the AD7142 1 to set Table 17 AD7142 1 Internal Register IC Addressing Register Address Lower Byte the address pointer The master then outputs a repeat start condition to keep control of the bus or if this is not possible ends the write transaction with a stop condition A read transaction is initiated with the R W bit set to 1 7 6 5 4 3 2 1 0 Reg Reg Reg Reg Reg Reg Reg Reg Add Add Add Add Add Add Add Add Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 The AD7142 1 supplies the upper eight bits of data from the addressed register in the first readback byte followed by the The third data byte contains the eight MSBs of the data to be written to the internal register The fourth byte of data contains the eight LSBs of data to be written to the internal register The AD7142 1 address pointer register automatically increments after each write This allows the master to sequentially write to all registers on the AD7142 1 in the same write transaction However the address pointer does not wrap around after the last address Rev lower eight bits in the next byte This is shown in Figure 39 and Figure 40 Because the address pointer automatically increases after each read the AD7142 1 continues to output readback data until the master puts a no acknowledge and stop condition on the bus If the address pointer reaches its maxi
71. ed STAGE3 High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded STAGEA High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded STAGES High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded STAGE6 High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded STAGE7 High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded Rev PrD Page 37 of 64 AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 8 0 STAGE8_HIGH_INT_EN STAGE8 High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded 9 0 STAGE9 HIGH INT EN STAGE9 Sensor Interrupt Low Limit Control 0 interrupt source disabled 1 INT asserted if STAGE10 LOW is exceeded 10 0 STAGE10 HIGH INT EN STAGE10 High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded 11 0 STAGE11 HIGH INT EN STAGE11 High Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO high reference is exceeded 15 12 Unused Set Unused Register Bits 0 007 0 0 R W STAGEO_COMPLETE_EN STAGEO Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGEO con
72. equired to implement buttons including 8 way button functionality The algorithms required for button sensors are implemented in digital logic on chip The AD7142 can be programmed to operate in either always powered mode or in an automatic wake up mode The auto wake up mode is particularly suited for portable devices that require low power operation giving the user significant power savings coupled with full functionality The AD7142 has a general interrupt output INT to indicate when new data has been placed into the registers INT is used to interrupt the host on sensor activation The AD7142 oper ates from a 2 7 V to 3 6 V supply and is available in a 32 lead 5mm x5 mm LFCSP CAPACITANCE SENSING THEORY The AD7142 uses a method of sensing capacitance known as the shunt method Using this method an excitation source is connected to a transmitter generating an electric field to a receiver The field lines measured at the receiver are translated into the digital domain by a X A converter When a finger or other grounded object interferes with the electric field some of the field lines are shunted to ground and do not reach the receiver see Figure 8 Therefore the total capacitance measured at the receiver decreases when an object comes close to the induced field EXCITATION SIGNAL 240KHz 05702 007 Figure 8 Sensing Capacitance Method In practice the excitation source and X A ADC are implemented on the AD7142
73. erface and the AD7142 1 has an interface ensuring that the parts are compatible with a wide range of host processors Because the AD7142 and AD7142 1 are identical parts with the exception of the serial interface AD7142 refers to both the AD7142 and AD7142 1 throughout this data sheet The AD7142 interfaces with to up to 14 external capacitance sensors These sensors can be arranged as buttons scroll bars joypads or as a combination of sensor types The external sensors consist of electrodes on a 2 or 4 layer PCB that interfaces directly to the AD7142 The AD7142 can be set up to implement any set of input sensors by programming the on chip registers The registers can also be programmed to control features such as averaging offsets and gains for each of the external sensors There is a sequencer on chip to control how each of the capacitance inputs is polled The AD7142 has on chip digital logic and 528 words of RAM that are used for environmental compensation The effects of humidity temperature and other environmental factors can effect the operation of capacitance sensors Transparent to the user the AD7142 performs continuous calibration to compensate for these effects allowing the AD7142 to give error free results at all times The AD7142 requires some minor companion software that runs on the host or other microcontroller to implement sensor functions such as a scroll bar or joypad However no companion software is r
74. ersion 11 0 STAGE11 COMPLETE EN STAGE11 Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGE11 conversion Rev PrD Page 38 of 64 AD7142 AD7142 1 Data Bit Default Address Content Value Type Name Description 12 0 GPIO INT EN Interrupt Control when GPIO Input Pin Changes Level 0 disabled 1 enabled 15 13 Unused Set Unused Register Bits 0 Table 22 CDC Low Limit Status Register Map Address Data Bit Content Default Value Type Name Description 008 0 2 3 4l 5 6 8 9 15 12 0 R STAGE0_LOW_LIMIT STAGE1_LOW_LIMIT STAGE2_LOW_LIMIT STAGE3_LOW_LIMIT STAGE4_LOW_LIMIT STAGE5_LOW_LIMIT STAGE6_LOW_LIMIT STAGE7_LOW_LIMIT STAGE8_LOW_LIMIT STAGE9_LOW_LIMIT STAGE10_LOW_LIMIT STAGE11_LOW_LIMIT Unused STAGEO CDC Conversion Low Limit Result 1 indicates STAGEO_OFFSET_LOW value was exceeded STAGE1 CDC Conversion Low Limit Result 1 indicates STAGE1_OFFSET_LOW value was exceeded STAGE2 CDC Conversion Low Limit Result 1 indicates STAGE2 OFFSET LOW value was exceeded STAGE3 CDC Conversion Low Limit Result 1 indicates STAGE3 OFFSET LOW value was exceeded STAGEA CDC Conversion Low Limit Result 1 indicates STAGE4 OFFSET LOW value was exceeded STAGES CDC Conversion Low Limit Result 1 indicate
75. es STAGE4 OFFSET HIGH value was exceeded 5 0 STAGE5 HIGH LIMIT 5 5 CDC Conversion High Limit Result 1 indicates STAGE5 OFFSET HIGH value was exceeded 6 0 5 6 HIGH LIMIT STAGE6 CDC Conversion High Limit Result 1 indicates STAGE6 OFFSET HIGH value was exceeded 7 0 STAGE7 HIGH LIMIT STAGE7 CDC Conversion Low Limit Result 1 indicates STAGE7 OFFSET HIGH value was exceeded 8 0 STAGE8 HIGH LIMIT 8 CDC Conversion High Limit Result 1 indicates STAGE8 OFFSET HIGH value was exceeded 9 0 STAGE9 HIGH LIMIT STAGE9 CDC Conversion High Limit Result 1 indicates STAGE9 OFFSET HIGH value was exceeded 10 0 STAGE10 HIGH LIMIT STAGE10 CDC Conversion High Limit Result 1 indicates STAGE10 OFFSET HIGH value was exceeded 11 0 5 11 HIGH LIMIT STAGE11 CDC Conversion High Limit Result 1 indicates STAGE11 OFFSET HIGH value was exceeded 15 12 Unused Set Unused Register Bits 0 Registers self clear to 0 after readback provided that the limits are not exceeded Rev PrD Page 40 of 64 AD7142 AD7142 1 Table 24 CDC Conversion Completion Register Map Data Bit Default Address Content Value Type Name Description 00A 0 0 R STAGEO COMPLETE STATUS STAGEO Conversion Completion Status 1 indicates STAGEO conversion completed 1 0 STAGE1 COMPLETE STATUS STAGE1 Conversion Completion Status 1 indicates STAGEO conversion completed 2 0 STAGE2 COMPLE
76. ftware is required for button sensors The software typically requires 3 kB of code and 500 bytes of data memory for a slider sensor AD7142 ra SENSOR PCB 2 HOST PROCESSOR SPI or 12C 1 MIPS 3kB ROM 500BYTES RAM 05702 008 Figure 9 3 Part Capacitance Sensing Solution Analog Devices supplies the sensor PCB design to the customer based on the customers specifications and supplies any necessary software on an open source basis Standard sensor designs are also available as PCB library components OPERATING MODES The AD7142 has three operating modes Full power mode where the device is always fully powered is suited for applications where power is not a concern for example game consoles that have an ac power supply Low power mode where the part automatically powers down is tailored to give significant power savings over full power mode and is suited for mobile applications where power must be conserved The AD7142 also has a com plete shutdown mode The POWER MODE bits Bit 0 and Bit 1 of the control register set the operating mode on the AD7142 The control register is at Address 0x000 Table 6 POWER MODE Settings POWER MODE Bits Operating Mode 00 Full power mode 01 Full shutdown mode 10 Low power mode 11 Full shutdown mode Table 6 shows the POWER MODE settings for each operating mode To put the AD7142 into shutdown mode set the POWER MODE bits to either 01 or 11 The power on defa
77. gh or low The AD7142 1 responds when the master device sends its device address over the bus The AD7142 1 cannot initiate data transfers on the bus Table 15 AD7142 1 PC Device Address ADD1 ADDO PC Address 0 0 0101 100 0 1 0101 101 1 0 0101 110 1 1 0101 111 Data Transfer 1 Data is transferred over the serial interface in 8 bit bytes The master initiates a data transfer by establishing a start con dition defined as a high to low transition on the serial data line SDA while the serial clock line SCLK remains high This indicates that an address data stream follows 2 All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits consisting of a 7 bit address MSB first plus an R W bit that determines the direction of the data transfer The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse This is known as the acknowledge bit All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it If the R W bit is a zero the master writes to the slave device If the R W bit is a one the master reads from the slave device Data is sent over the serial bus in a sequence of nine clock pulses eight bits of data followed by an acknowledge bit from the slave device Transitions on the data line must occur during the low pe
78. gs See the CDC Conversion Time section for more information AD7142 SETUP AND INITIALIZATION POWER MODE 10 CONVERSIONS EVERY 400ms UPDATE COMPENSATION LOGIC DATA PATH SEQUENCER CONTROLLED CONVERSIONS ON ALL SENSORS EVERY 40ms ANY SENSOR TOUCHED TOUCHED PROXIMITY TIMER COUNT DOWN TIMEOUT 05702 009 Figure 10 Low Power Mode Operation Rev PrD Page 10 of 64 AD7142 AD7142 1 CAPACITANCE SENSOR INPUT CONFIGURATION Each stage of the AD7142 capacitance sensors can be uniquely configured by using the registers in Table 53 and Table 54 These registers are used to configure input pin connection set ups sensor offsets sensor sensitivities and sensor limits for each stage Apply this feature to optimize the function of each sensor to the application For example a button sensor connected to STAGEO may require a different sensitivity and offset values than a button with a different function that is connected to a different stage CIN INPUT MULTIPLEXER SETUP The CIN CONNECTION SETUP registers in Table 53 list the different options that are provided for connecting the sensor input pin to the CDC converter CIN CONNECTION The AD7142 has an on chip multiplexer to route the input signals from each pin to the input of the converter Each input pin can be tied to either the negative or the positive input of the CDC or it can be left floating Each input can
79. gt 62 51 POS ADAPTIVE THRESHOLD LEVEL STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW initial values Reference A in Figure 26 shows that this results in an under sensitive threshold level for a small finger user demonstrating the disadvantages of a fixed threshold level By enabling the adaptive threshold and sensitivity algorithm the positive and negative threshold levels are determined by the POS_THRESHOLD_SENSI TIVITY and NEG_THRESHOLD_SENSITIVITY register values and the most recent average maximum sensor output value These registers can be used to select 16 different positive and negative sensitivity levels ranging between 25 and 95 32 of the most recent average maximum output level referenced from the ambient value Reference B shows that the positive adaptive threshold level is set at almost mid sensitivity with a 62 51 threshold level by setting POS_THRESHOLD_SENSITIVITY 1000 Figure 26 also provides a similar example for the negative threshold level with NEG_THRESHOLD_SENSITIVITY 0001 95 32 gt 62 51 POS ADAPTIVE THRESHOLD LEVEL STAGE OFFSET HIGH INITIAL VALUE 25 SENSOR CONTACTED BY SMALL FINGER SENSOR CONTACTED BY LARGE FINGER STAGE_OFFSET_LOW NEG ADAPTIVE THRESHOLD LEVEL 39 08 T INITIAL VALUE 95 32 L 05702 025 Figure 26 Threshold Sensitivity Example with POS THRESHOLD SENSITIVITY 1000 NEG THRESHOLD SENSITIVITY 0011 Rev PrD Page 20
80. han one register this address indicates the address of the first register to be written to or read from Writing Data Data is written to the AD7142 in 16 bit words The first word written to the device is the command word with the read write bit set to 0 The master then supplies the 16 bit input data word on the SDI line The AD7142 clocks the data into the register addressed in the command word If there is more than one word of data to be clocked in the AD7142 automatically incre ments the address pointer and clock the next data word into the next register The AD7142 continues to clock in data on the SDI line until either the master finishes the write transition by pulling CS high or until the address pointer reaches its maximum value The AD7142 address pointer does not wrap around When it reaches its maximum value any data provided by the master on the SDI ine is ignored by the AD7142 15 10 9 0 1 1 11 0 0 RW Register Address 16 BIT COMMAND WORD ENABLE WORD RAV ja tof bl NOTES REGISTER ADDRESS se ODDO OAK KOO 16 DATA fisel Jie i9 eo __ t H 1 SDI BITS ARE LATCHED ON SCLK RISING EDGES SCLK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS 2 ALL 32 BITS MUST BE WRITTEN 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA 3 16 BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION CW 15 11 11100 ENABLE WORD CW
81. le 21 Interrupt Configuration Register Map Data Bit Default Address Content Value Type Name Description 005 0 0 R W STAGEO LOW INT EN STAGEO Low Interrupt Enable 0 interrupt source disabled 1 asserted if STAGEO low reference is exceeded 1 0 STAGE1_LOW_INT_EN STAGE1 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded 2 0 STAGE2 LOW INT EN STAGE2 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded 3 0 STAGE3 LOW INT EN STAGE3 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded 4 0 STAGE4_LOW_INT_EN STAGE4 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded 5 0 STAGE5 LOW INT EN STAGES Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded 6 0 STAGE6 LOW INT EN STAGE6 Low Interrupt Enable 0 interrupt source disabled 1 INT asserted if STAGEO low reference is exceeded Rev PrD Page 36 of 64 AD7142 AD7142 1 Address Data Bit Content Default Value Type Name Description 7 8 9 10 11 13 12 15 14 0 STAGE7 LOW INT EN STAGE8 LOW INT EN STAGE9 LOW INT EN STAGE10 LOW INT EN STAGE11 LOW INT EN GPIO SETUP GPIO INPUT CONFIG STAGE7 Low Interrupt Enable
82. llows the AD7142 to account for rapidly changing environ mental conditions The ambient compensation control registers give the host access to general setup and controls for the compensation algorithm The RAM stores the compensation data for each conversion stage as well as setup information specific to each stage Figure 23 shows an example of an ideal capacitance sensor behavior where the CDC ambient level remains constant regardless of the environmental conditions In this example the initial settings programmed in the STAGE OFFSET HIGH and STAGE OFFSET LOW registers are sufficient to detect a sensor contact resulting with the AD7142 asserting the INT output when the offset levels are exceeded SENSOR 1 INT 4 ASSERTED STAGE_OFFSET_HIGH INITIAL REGISTER VALUE a E 5 CDC AMBIENT VALUE 5 o o a o STAGE OFFSET LOW INITIAL REGISTER VALUE SENSOR 2 INT ASSERTED CHANGING ENVIRONMENTALCONDITIONS Figure 23 Ideal Sensor Behavior with a Constant Ambient Level Capacitance Sensor Behavior Without Calibration Figure 24 shows the typical behavior of a capacitance sensor with no applied calibration This figure shows ambient levels drifting over time as environmental conditions change The ambient level drift has resulted in the detection of a missed user contact on Sensor 2 This is a result of the initial low offset level remaining constant while the ambient levels drifted upward beyond th
83. ly functional operation of the device at these or any Analog Input Voltage to AGND 0 3 V to AVcc 0 3 V other conditions above those indicated in the operational Digital Input Voltage to DGND 03V to Vorne 0 3 V section of this specification is not implied Exposure to absolute Digital Output Voltage to DGND 0 3V to Vorve 0 3 V maximum rating conditions for extended periods may affect Input Current to Any Pin Except 10 mA device reliability Supplies ESD Rating 2 5 kV Operating Temperature Range 40 C to 105 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C TO QUTRUT LFCSP Package Power Dissipation 450 mW Osa Thermal Impedance 135 7 C W IR Reflow Peak Temperature 260 C 0 5 C Figure 4 Load Circuit for Digital Output Timing Specifications Lead Temperature Soldering 10 sec 300 C Transient currents of up to 100 mA do not cause SCR latch up ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Spr electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance ESD SENSITIVE DEVICE degradation or loss of functionality Rev PrD Page 6 of 64 AD7142 AD7142 1
84. mum value and the master continues to read from the part the AD7142 1 repeatedly sends data from the last register addressed rD Page 28 of 64 AD7142 AD7142 1 START 1 AD7142 DEVICE ADDRESS REGISTER ADDRESS A15 A8 i REGISTER ADDRESS A7 A0 I LENS EN REX Aen ACK oS HO 2 1 1 sR AD7142 DEVICE ADDRESS REGISTER DATA D7 D0 te gt AD7142 DEVICE ADDRESS l 1 1 1 1 REPEATED START Luc 4 0 gt lt t 1 1 AD7142 DEVICE ADDRESS REGISTER DATA D7 D0 I I 1 1 1 I SEPERATE READ AND 40 at 1 1 WRITE TRANSACTIONS 1 pod 1 woe ERI b eee 34 35 se 7 38 oo 4 jl fae 1 peu NOTES A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH TO LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH A STOP CONDITION AT THE END IS DEFINED AS A LOW TO HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH THE MASTER GENERATES THE NACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WNAT ADDITIONAL DATA 7 BIT DEVICE ADDRESS DEV A6 DEV AQ 0 1 0 1 1 X X WHERE THE TWO LSB X s ARE DON T CARES 16 BIT REGISTER ADDRESS A15 A0 X X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 WHERE THE UPPER LSB X s ARE DON T CARES REGISTER ADDRESS A15 A8 AND REGISTER ADDRESS A7 A0 ARE AWAYS SEPERATED BY A LOW ACK BIT REGISTER DATA D15 D8 AND REGISTER DATA D7 D0 ARE ALWAYS SEPERATED BY A LOW ACK BIT THE R W
85. nection Setup See Table 53 0 9 15 0 X R W STAGE7_CIN 7 13 _ SETUP STAGE7 CIN 7 13 Connection Setup See Table 54 OBA 15 0 X R W STAGE7 AFE OFFSET STAGE7 AFE Offset Control See Table 55 OBB 15 0 X R W STAGE7 SENSITIVITY STAGE7 Sensitivity Control See Table 56 OBC 15 0 X R W STAGE7 OFFSET LOW STAGE7 Initial Offset Low Value OBD 15 0 X R W STAGE7 OFFSET HIGH STAGE7 Initial Offset High Value OBE 15 0 X R W STAGE7 OFFSET HIGH CLAMP STAGE7 Offset High Clamp Value OBF 15 0 X R W STAGE7 OFFSET LOW CLAMP STAGE7 Offset Low Clamp Value Rev PrD Page 45 of 64 AD7142 AD7142 1 Table 37 STAGES Configuration Register Map Data Bit Default Address Content Value Type Name Description oco 15 0 X R W STAGES8 CIN 0 6 SETUP 5 8 CIN 0 6 Connection Setup See Table 53 0C1 15 0 X R W STAGES 7 13 SETUP 8 CIN 7 13 Connection Setup See Table 54 0C2 15 0 X R W STAGE8 AFE OFFSET STAGES AFE Offset Control See Table 55 0C3 15 0 X R W STAGE8_ SENSITIVITY STAGES Sensitivity Control See Table 56 OCA 15 0 X R W STAGE8_OFFSET_LOW STAGES Initial Offset Low Value 0C5 15 0 X R W STAGE8 OFFSET HIGH STAGES Initial Offset High Value 0C6 15 0 X R W STAGE8 OFFSET HIGH CLAMP STAGES Offset High Clamp Value 0C7 15 0 X R W STAGE8 OFFSET LOW CLAMP STAGES Offset Low Clamp Value Table 38 STAGE Configuration Register
86. output 1 disable output 13 0 SRC Excitation Source Control for Pin 16 0 enable output 1 disable output 15 14 0 BIAS CDC Bias Current Control 00 normal operation 01 normal operation 2096 10 normal operation 3596 11 2 normal operation 5096 Rev PrD Page 34 of 64 AD7142 AD7142 1 Table 20 CDC Conversion Control Register Map Data Bit Default Address Content Value Type Name Description 001 0 0 R W STAGEO_CAL_EN STAGEO Calibration Enable 0 disable 1 enable 1 0 5 1 CAL EN STAGE Calibration Enable 0 disable 1 enable 2 0 5 2 CAL EN STAGE2 Calibration Enable 0 disable 1 enable 3 0 STAGE3 CAL EN STAGE3 Calibration Enable 0 disable 1 enable 4 0 5 4 CAL EN STAGEA Calibration Enable 0 disable 1 enable 5 0 STAGE5 CAL EN STAGES Calibration Enable 0 disable 1 enable 6 0 5 6 CAL EN STAGE6 Calibration Enable 0 disable 1 enable 7 0 STAGE7 CAL EN STAGE7 Calibration Enable 0 disable 1 enable 8 0 8 CAL EN STAGES Calibration Enable 0 disable 1 enable 9 0 STAGE9 CAL EN STAGE Calibration Enable 0 disable 1 enable 10 0 STAGE10 CAL EN STAGE10 Calibration Enable 0 disable 1 enable 11 0 5 11 CAL EN STAGE11 Calibration Enable 0 disable 1 enable 13 12 0 AVG FP SKIP Full Power Mode Skip Control 00 skip 3 samples 01 skip 7 samples 10
87. put High Voltage 1 l Input Low Voltage 1 HA Hysteresis 150 mV OPEN DRAIN OUTPUTS SDO SDA INT Vo Output Low Voltage 0 4 V Isink 1 mA lou Output High Leakage Current 0 1 1 Vour Vorive LOGIC OUTPUTS Vo Output Low Voltage 0 4 V Isink 1 mA Vorive 1 6 V to DVcc 0 3 V Output High Voltage Vorive 0 6 V Isource 1 mA Floating State Leakage Current 10 Pin tri stated POWER AVcc DVcc 2 7 3 6 V 1 65 DVcc 0 3 V Serial interface operating voltage 1 TBD mA Full power mode 50 TBD HA Low power mode conversion delay 400 ms 2 TBD uA Full shutdown Rev PrD Page 3 of 64 AD7142 AD7142 1 SPI TIMING SPECIFICATIONS AD7142 Ta 40 C to 105 C Vorwe 1 8 V to 3 6 V AVcc DVcc 2 7 V to 3 6 V unless otherwise noted Sample tested at 25 C to ensure compliance All input signals are specified with tr tr 5 ns 10 to 90 of Vcc and timed from a voltage level of 1 6 V Table 2 SPI Timing Specifications Parameter Limit at Tmn Tmax Unit Description 10 2 10 2 ti 5 ns min CS falling edge to first SCLK falling edge t 20 ns min SCLK high pulse width ts 20 ns min SCLK low pulse width ta 15 ns min SDI set up time ts 15 ns min SDI hold time te 20 ns max SDO access time after SCLK falling edge t 16 ns max CS rising edge to SDO high impedance ts TBD ns SCLK rising edge to CS high Mark space ratio duty cycle for the DC
88. riod ofthe clock signal and remain stable during the high period since a low to high transition when the clock is high can be interpreted as a stop signal The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle When all data bytes are read or written a stop condition is established A stop condition is defined by a low to high transition on SDA while SCLK remains high If the AD7142 encounters a stop condition it returns to its idle condition and the address pointer resets to Address 0x00 Rev PrD Page 27 of 64 AD7142 AD7142 1 START AD7142 DEVICE ADDRESS i REGISTER ADDRESS A15 A8 REGISTER ADDRESS A7 A0 1 1 1 1 1 1 _ KODAK OE REGISTER DATA D7 D0 AD7142 DEVICE ADDRESS OD I I REGISTER DATA D15 D8 I NOTES 1 ASTART CONDITION AT THE BEGINNING IS DEFINED AS A HIGH TO LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH 2 ASTOP CONDITION AT THE END IS DEFINED AS A LOW TO HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH 3 7 BIT DEVICE ADDRESS DEV A6 DEV A0 0 1 0 1 1 X X WHERE X ARE DON T CARES 4 16 BIT REGISTER ADDRESS A15 A0 X X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 WHERE X ARE DON T CARES 5 REGISTER ADDRESS A15 A8 AND REGISTER ADDRESS 7 0 ARE AWAYS SEPERATED BY A LOW ACK BIT 6 REGISTER DATA D15 D8 AND REGISTER DATA 07
89. s 0x240 15 13 0x0 R W Low power mode settling time These bits control the settling time of the ADC in low power mode Each unit of delay is equivalent to one conversion time Set to 0x2 Rev PrD Page 43 of 64 AD7142 AD7142 1 BANK 2 REGISTERS All address values are expressed in hexadecimal Table 29 STAGEO Configuration Register Map Data Bit Default Address Content Value Type Name Description 080 15 0 X R W STAGEO CIN 0 6 SETUP STAGEO CIN 0 6 Connection Set Up See Table 53 081 15 0 X R W STAGEO CIN 7 13 SETUP STAGEO CIN 7 13 Connection Set Up See Table 54 082 15 0 X R W STAGEO AFE OFFSET STAGEO AFE Offset Control See Table 55 083 15 0 X R W STAGEO SENSITIVITY STAGEO Sensitivity Control See Table 56 084 15 0 X R W STAGEO OFFSET LOW STAGEO Initial Offset Low Value 085 15 0 X R W STAGEO OFFSET HIGH STAGEO Initial Offset High Value 086 15 0 X R W STAGEO OFFSET HIGH CLAMP STAGEO Offset High Clamp Value 087 15 0 X R W STAGEO OFFSET LOW CLAMP STAGEO Offset Low Clamp Value Table 30 STAGEI Configuration Register Map Data Bit Default Address Content Value Type Name Description 088 15 0 X R W STAGE1_CIN 0 6 _ SETUP STAGE1 CIN 0 6 Connection Setup See Table 53 089 15 0 X R W STAGE1_CIN 7 13 _ SETUP STAGE1 CIN 7 13 Connection Setup See Table 54 08A 15 0 X R W 5 1 AFE OFFSET STAGE AFE Offset Control See Table 55
90. s STAGE5 OFFSET LOW value was exceeded STAGE6 CDC Conversion Low Limit Result 1 indicates STAGE6 OFFSET LOW value was exceeded STAGE7 CDC Conversion Low Limit Result 1 indicates STAGE7 OFFSET LOW value was exceeded STAGE8 CDC Conversion Low Limit Result 1 indicates 8 OFFSET LOW value was exceeded STAGE9 CDC Conversion Low Limit Result 1 indicates STAGE9 OFFSET LOW value was exceeded STAGE10 CDC Conversion Low Limit Result 1 indicates STAGE10 OFFSET LOW value was exceeded STAGE11 CDC Conversion Low Limit Result 1 indicates STAGE11 OFFSET LOW value was exceeded Set Unused Register Bits 0 1 Registers self clear to 0 after readback provided that the limits are not exceeded Rev PrD Page 39 of 64 AD7142 AD7142 1 Table 23 CDC High Limit Status Data Bit Default Address Content Value Type Name Description 009 0 0 R STAGEO HIGH LIMIT STAGEO CDC Conversion High Limit Result 1 indicates STAGEO OFFSET HIGH value was exceeded 1 0 5 1 HIGH LIMIT STAGE1 CDC Conversion High Limit Result 1 indicates STAGE1 OFFSET HIGH value was exceeded 2 0 STAGE2 HIGH LIMIT Stage2 CDC Conversion High Limit Result 1 indicates STAGE2 OFFSET HIGH value was exceeded 3 0 5 HIGH LIMIT STAGE3 CDC Conversion High Limit Result 1 indicates STAGE3 OFFSET HIGH value was exceeded 4 0 5 4 HIGH LIMIT STAGE4 CDC Conversion High Limit Result 1 indicat
91. s set by configuring the SEQUENCE STAGE NUM FF_SKIP_CNT and DECIMATION registers as outlined in Table 8 Figure 16 shows a simplified timing diagram of the full power CDC conversion time The full power mode CDC conversion time tcoxv rr is set using Table 8 CDC CONVERSION CONVERSION N NOTES 1 VALUE SET FROM TABLE 8 CONVERSION V CONVERSION N 1 N 2 05702 015 Figure 16 Full Power Mode CDC Conversion Time Low Power Mode CDC Conversion Time with Delay The frequency of each CDC conversion while operating in the low power automatic wake up mode is controlled by using the LP CONV DELAY register bits Bits 3 2 in Register 0x00 in addition to the registers listed in Table 8 This feature provides some flexibility for optimizing the conversion time to meet system requirements vs AD7142 power consumption For example maximum power savings is achieved when the LP CONV DELAY is set to 3 With a setting of 3 the AD7142 automatically wakes up performing a conversion every 400 ms Table9 LP CONV DELAY Settings LP CONV DELAY BITS Delay Between Conversions 00 100 ms 01 200 ms 10 300 ms 11 400 ms Figure 17 shows a simplified timing example of the low power CDC conversion time As shown the low power CDC conversion time is set by tconv_rp and the CONV DELAY register tconv LP CONVERSION N NOTES 1 Lp tcoNv_Fp LP CONV DELAY CDC CON
92. stage Clearing a bit to 0 disables the interrupt for that stage When a conversion result exceeds a low threshold the status bit corresponding to that conversion stage is set in the CDC low limit status register at Address 0x008 For a detailed register description see Table 22 If a conversion stage result exceeds a high limit the status bit corresponding to that stage is set in the CDC high limit status register at Address 0x009 For a detailed register description see Table 23 All bits in the status registers are cleared on read back if all conversion results are within the threshold limits CONVERSIONS STAGE 0 X STAGE 1 X STAGE 2 X STAGE 3 X STAGE 4 STAGE 5 X STAGE 6 X STAGE 7 X STAGE 8 STAGE 9 XSTAGE10X STAGE 11 SERIAL READS PROGRAMMINGE NOTES 1 STAGEO SENSOR HIGH INT STAGEO SENSOR LOW INT 0 STAGEO CONVERSION INT 1 2 READ BACK FROM STAGEO CONVERSION REGISTER TO RESET INT OUTPUT 3 STAGES SENSOR HIGH INT STAGES SENSOR LOW INT 0 STAGE5 CONVERSION INT 1 4 READ BACK FROM STAGE5 CONVERSION REGISTER TO RESET INT OUTPUT 5 STAGE9 SENSOR HIGH INT STAGE9 SENSOR LOW INT 0 STAGE9 CONVERSION INT 1 6 READ BACK FROM STAGE9 CONVERSION REGISTER TO RESET INT OUTPUT STAGEx SENSOR HIGH INT STAGEx SENSOR LOW INT STAGEx CONVERSION NT 0 FOR ALL STAGES HIGHLIGHTED IN GRAY 05702 026 Figure 27 Example of Configuring the Registers for End of Conversion Interrupt Set Up Rev PrD Page 21 of 64 AD
93. t FIFO WORD6 274 15 0 X R W STAGE11_FF_WORD7 STAGE11 Fast FIFO WORD7 275 15 0 X R W 5 11 SF WORDO STAGE11 Slow FIFO WORDO 276 15 0 X R W 5 11 SF WORD1 STAGE11 Slow FIFO WORD1 277 15 0 X R W 5 11 SF WORD2 STAGE11 Slow FIFO WORD2 278 15 0 X R W 5 11 SF WORD3 STAGE11 Slow FIFO WORD3 279 15 0 X R W 5 11 SF WORDA STAGE11 Slow FIFO WORD4 27A 15 0 X R W 5 11 SF WORD5 STAGE11 Slow FIFO WORD5 27B 15 0 X R W STAGE11_SF_WORD6 STAGE11 Slow FIFO WORD6 27C 15 0 X R W STAGE11_SF_WORD7 STAGE11 Slow FIFO WORD7 27D 15 0 X R W STAGE11_SF_AMBIENT STAGE11 Slow FIFO Ambient Value 27E 15 0 X R W STAGE11 FF AVG STAGE11 Fast FIFO Average Value 27F 15 0 X R W STAGE11_CDC_WORDO STAGE11 CDC FIFO WORDO 280 15 0 X R W STAGE11_CDC_WORD1 STAGE11 CDC FIFO WORD1 281 15 0 X R W STAGE11_MAX_WORDO STAGE11 Maximum Value FIFO WORDO 282 15 0 X R W STAGE11_MAX_WORD1 STAGE11 Maximum Value FIFO WORD1 283 15 0 X R W STAGE11_MAX_WORD2 STAGE11 Maximum Value FIFO WORD2 284 15 0 X R W STAGE11_MAX_WORD3 STAGE11 Maximum Value FIFO WORD3 285 15 0 X R W STAGE11_MAX_AVG STAGE11 Average Maximum FIFO Value 286 15 0 X R W STAGE11_HIGH_THRESHOLD STAGE11 High Threshold Value 287 15 0 X R W STAGE11_MAX_TEMP STAGE11 Temporary Maximum Value 288 15 0 X R W STAGE11_MIN_WORDO STAGE11 Minimum Value FIFO WORDO 289 15 0 X R W STAGE11_MIN_WORD1 STAGE11 Minimum Value FIFO WORD1 28A 15 0 X R W STAGE11_MIN_WORD2 STAGE11 Minimum Value FI
94. tage Initialize the Bank 2 configuration registers immediately after power up to obtain valid CDC conversion result data Register Bank 3 contains the results of each conversion stage These registers automatically update at the end of each conversion sequence Although these registers are primarily used by the AD7142 internal data processing they are accessible by the host processor for additional external data processing if desired Default values are undefined for Register Bank 2 and Register Bank 3 until after power up and configuration of Register Bank 2 REGISTER BANK 2 STAGE 0 CONFIGURATION 8 REGISTERS STAGE 1 CONFIGURATION 8 REGISTERS STAGE 2 CONFIGURATION 8 REGISTERS STAGE 3 CONFIGURATION 8 REGISTERS STAGE 4 CONFIGURATION 8 REGISTERS STAGE 5 CONFIGURATION 8 REGISTERS STAGE 6 CONFIGURATION 8 REGISTERS STAGE 7 CONFIGURATION 8 REGISTERS STAGE 8 CONFIGURATION 8 REGISTERS STAGE 9 CONFIGURATION 8 REGISTERS STAGE 10 CONFIGURATION 8 REGISTERS STAGE 11 CONFIGURATION 8 REGISTERS 432 REGISTERS P v N Figure 47 Layout of Bank 1 Bank 2 and Bank 3 Registers Rev PrD Page 33 of 64 REGISTER BANK 3 ADDR 0x0E0 STAGE 0 RESULTS 36 REGISTERS ADDR 0x088 STAGE 1 RESULTS 36 REGISTERS STAGE 2 RESULTS 36 REGISTERS STAGE 3 RESULTS 36 REGISTERS STAGE 4 RESULTS 36 REGISTERS STAGE 5 RESULTS mr 36 REGISTERS 0x0BO STAGE 6 RESU
95. ted while signal on GPIO pin is high 11 positive level triggered 0 0 1 Not triggered GPIO INT OUTPUT CONTROL The INT output signal can be controlled by the GPIO pin when back from the register provided the condition that caused the the GPIO is configured as an input The GPIO is configured as interrupt has gone away an input by setting the GPIO_SETUP bits in the interrupt configuration register to 01 See GPIO section for more information on how to configure the GPIO The GPIO interrupt can be set to trigger on a rising edge falling edge high level or low level at the GPIO input pin Table 11 shows how the settings of the GPIO INPUT CONFIG bits in Enable the GPIO interrupt by setting the GPIO INT EN bit in the interrupt configuration register affect the behavior of INT Register 0x007 to 1 or disable by clearing this bit to 0 The GPIO status bit in the CDC conversion completion register Figure 29 to Figure 32 show how the interrupt output is cleared reflects the status of the GPIO interrupt This bit is set to 1 on a read from the CDC conversion completion register when the GPIO has triggered INT The bit is cleared on read Rev PrD Page 22 of 64 AD7142 AD7142 1 SERIAL SERIAL READ T READ BACK I I I I GPIO INPUT HIGH WHEN REGISTER IS READBACK I GPIO INPUT LOW WHEN REGISTER IS READBACK GPIO GPIO INPUT I INPUT I 1 n I I I I INT 1 INT 1 OUTPUT OUTPUT RN
96. ternal proximity detection signal as described in Figure 22 with Comparator 1 and Comparator 2 Comparator 1 detects when a user is approaching a sensor The sensitivity of Comparator 1 is controlled by PROXIMITY_DETECTION_RATE For example if PROXIMITY_DETECTION_RATE is set to 4 the Proximity 1 signal is set when the absolute difference between WORD1 and WORD3 exceed four LSB codes Comparator 2 detects when a user is hovering over a sensor or approaches a sensor very slowly The sensitivity of Comparator 2 is controlled by the PROXIMITY RECAL LVL in Register 0x003 For example if PROXIMITY RECAL is set to 75 the Proximity 2 signal is set when the absolute difference between the fast filter average value and the ambient value exceeds 75 LSB codes Length Register Bits Register Address Description FP PROXIMITY 4 0x002 Full power mode proximity control PROXIMITY CNT 4 0x002 Low power mode proximity control FP PROXIMITY RECAL 8 0x004 Full power mode proximity recalibration control LP PROXIMITY RECAL 6 0x004 Low power mode proximity recalibration control PROXIMITY LVL 8 0x003 Proximity recalibration level PROXIMITY DETECTION RATE 6 0x003 Proximity detection rate USER APPROCHES USER LEAVES SENSOR SENSOR HERE AREA HERE Y S re CONVERSIONS 123456 7 8 9 1011 1213 141516 INTERNAL tH EA A 4 teans PROXIMITY DETECTION 2
97. tive Threshold Sensitivity Control 0000 25 0001 29 73 0010 34 40 0011 39 08 0100 43 79 0101 48 47 0110 53 15 0111 57 83 1000 62 51 1001 67 22 1010 71 90 1011 76 58 1100 81 28 1101 85 96 1110 90 64 1111 95 32 14 12 R W POS_PEAK_DETECT Positive Peak Detect Setting 000 40 level 001 50 level 010 60 level 011 70 level 100 80 level 101 90 level 15 R W Unused Rev PrD Page 61 of 64 AD7142 AD7142 1 OUTLINE DIMENSIONS 0 60 ned i dd PIN 1 U INDICATOR PIN 1 INDICATOR 0 50 BSC 7 EXPOSED 3 25 PAD 1050 F BOTTOM VIEW 2 95 0 50 0 40 0 30 0 25 MIN ANNANN 3 50 REF 0 80 MAX 12 MAX t 0 65 0 05 E TI 4 0 02 NOM 0 85 N 4 T COPLANARITY 0 20 REF 080 SEATING 0 23 0 08 PLANE 0 18 COMPLIANT TO JEDEC STANDARDS MO 220 VHHD 2 Figure 48 32 Lead Frame Chip Scale Package LFCSP VQ 5mm x 5 mm Very Thin Quad CP 32 3 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Serial Interface Description Package Description Package Option AD7142ACPZ REEL 40 C to 85 C SPI Interface 32 Lead LFCSP CP 32 3 AD7142ACPZ REEL 7 40 C to 85 C SPI Interface 32 Lead LFCSP CP 32 3 AD7142 1ACPZ REEL 40 C to 85 C Interface 32 Lead LFCSP CP 32 3 AD7142 1ACPZ REEL7 40 C to 85 C Interface 32 Lead LFCSP CP 32 3 Eval AD
98. ts for each conversion stage recommended Register Address 0x001 Bits 11 0 Wait for three interrupt cycles After the third interrupt valid data is available in 1 Turn the power supplies to the AD7142 the AD7142 registers 2 Load all of the required Bank 2 configuration registers 6 Read back either the CDC conversion 3 Load Bank 1 registers at Address 0x000 through conversion completion registers to reset the INT output as Address 0x004 except Register Address 0x001 Bits 11 0 explained in the Interrupt Output section and Register Address 0x045 to configure the AD7142 AE a Step every time INT is asserted 4 Load Bank 1 registers at Address 0x005 through Address 0x007 This enables the interrupt operation DVCC AVCC VDRIVE 3V 1 POWER SUPPLIES OV 1 1 I 2 3 4 5 6 SERIAL WRITES lt tcoNv gt INT OUTPUT FIRST CONVERSION SECOND CONVERSION 05702 040 Figure 44 Recommended Start Up Sequence Rev PrD Page 31 of 64 AD7142 AD7142 1 TYPICAL APPLICATION CIRCUITS HOST WITH SPI INTERFACE AD7142 SENSOR PCB LAYER 1 SENSOR PCB LAYER 2 Voc 2 7V 3 6V QTuF 10uF 0 1uF OPTIONAL 05702 041 Figure 45 Typical Application Circuit with SPI Interface HOST WITH 12C INTERFACE AD7142 1 SENSOR PCB LAYER 2 2 7 3 6 TuF 10uF OPTIONAL 12 CSHIELD SENSOR PCB LAYER 1 8 N 1H Eus p 15
99. ult setting of the POWER MODE bits is 00 full power mode Full Power Mode In full power mode all sections of the AD7142 remain fully powered at all times While a sensor is being touched the AD7142 processes the sensor data If no sensor is touched the AD7142 measures the ambient capacitance level and uses this data for the on chip compensation routines In full power mode the AD7142 converts at a constant rate See the CDC Conversion Time section for more information Low Power Mode When in low power mode the AD7142 POWER MODE bits are set to 10 upon device initialization If the external sensors are not touched the AD7142 reduces its conversion frequency thereby greatly reducing its power consumption The part remains in a low power state while the sensors are not touched Every 400 ms the AD7142 performs a conversion and uses this data to update the compensation logic When an external sensor is touched the AD7142 begins a conversion sequence every 40 ms to read back data from the sensors In low power mode the total current consumption of the AD7142 is an average of the current used during a conversion and the current used while the AD7142 is waiting for the next conversion to begin For example when the low power mode conversion interval is 400 ms the AD7142 uses typically 0 9 mA current for 40 ms and 15 A for 360 ms of the conversion interval Note that these conversion timings can be altered through the register settin
100. version 1 0 STAGE1 COMPLETE EN STAGE1 Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGE1 conversion 2 0 STAGE2 COMPLETE EN STAGE2 Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGE2 conversion 3 0 STAGE3 COMPLETE EN STAGE3 Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGE3 conversion 4 0 STAGE4 COMPLETE EN STAGEA Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGE4 conversion 5 0 STAGE5 COMPLETE EN STAGES Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGES conversion 6 0 STAGE6 COMPLETE STAGE6 Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGE6 conversion 7 0 STAGE7 COMPLETE STAGE7 Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGE7 conversion 8 0 STAGE8 COMPLETE EN STAGE8 Conversion Complete Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGEB8 conversion 9 0 STAGE9 COMPLETE EN STAGE Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGES conversion 10 0 STAGE10 COMPLETE EN STAGE10 Conversion Interrupt Control 0 interrupt source disabled 1 INT asserted at completion of STAGE10 conv
101. version stages the conversion complete interrupt for STAGE4 is enabled INT only asserts when all five conversion stages are complete and the host can read new data from all five result registers The interrupt is cleared by reading the status register tconv_FP Register 0x00A is the conversion completion status register Each bit in this register corresponds to a conversion stage If a bit is set it means that the conversion complete interrupt for the corresponding stage was triggered This register is cleared on a read provided the underlying condition that triggered the interrupt has gone away For a detailed register description see Table 24 SENSOR THRESHOLD INTERRUPT The AD7142 interrupt signal asserts low to indicate that a conversion result exceeds either the high or low threshold limits for that sensor When a conversion result from a sensor exceeds the threshold limits it indicates the sensor has been touched The sensor threshold interrupt can be enabled independently for each conversion stage via the interrupt configuration regis ters Register 0x05 is the low threshold interrupt enable register Each bit in the register corresponds to the threshold low interrupt for conversion STAGEO to STAGE11 Register 0x006 is the high threshold enable register Each bit in this register corresponds to the high threshold interrupt enable for conversion STAGEO to STAGE11 Setting a bit to 1 enables the interrupt for that
102. with the sensor Figure 18 and Figure 19 show examples of how these registers are used to set the full and low power mode calibration disable periods Recalibration In the event of a very long proximity detection event such as a user hovering over a sensor for a long period of time the FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL bits in register 0x004 can be applied to force a recalibration This feature ensures that the ambient values are recalibrated regardless of how long the user may be hovering over a sensor A recalibration ensures maximum AD7142 sensor performance Figure 20 and Figure 21 show examples of using the FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL Table 10 Proximity Control Registers Refer to Figure 22 register bits to force a recalibration while operating in the full and low power modes These figures show a user approaching a sensor followed by the user leaving the sensor while the proximity detection remained active after the user left the sensor This situation could occur if the user interaction created some moisture on the sensor for example thus causing the new sensor value to be different from the expected value In this case the internal recalibration would be applied to automatically recalibrate the sensor The force calibration event takes two interrupt cycles nothing should be read from or written to the AD7142 during the recalibration period Proximity Sensitivity There are two conditions that set the in

ANALOG DEVICES AD7142/AD7142-1 Programmable Capacitance-to-Digital Converter with Environmental Compensation handbook

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